1060a96d2184c1e2123f50a8d2c12d3b77ac6e4e
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/device.h>
31 #include <drm/drmP.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45                 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54                 "-1=force lid closed, -2=force lid open)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69                 "Enable power-saving render C-state 6. "
70                 "Different stages can be selected via bitmask values "
71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73                 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78                 "Enable frame buffer compression for power savings "
79                 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84                 "Use panel (LVDS/eDP) downclocking for power savings "
85                 "(default: false)");
86
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90                  "Specify LVDS channel mode "
91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97                 "(default: auto from VBT)");
98
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102                 "Override/Ignore selection of SDVO panel mode in the VBT "
103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112                 "Periodically check GPU activity for detecting hangs. "
113                 "WARNING: Disabling this can cause system wide hangs. "
114                 "(default: true)");
115
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119                 "Enable PPGTT (default: true)");
120
121 int i915_enable_psr __read_mostly = 0;
122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
124
125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
127 MODULE_PARM_DESC(preliminary_hw_support,
128                 "Enable preliminary hardware support.");
129
130 int i915_disable_power_well __read_mostly = 1;
131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
132 MODULE_PARM_DESC(disable_power_well,
133                  "Disable the power well when possible (default: true)");
134
135 int i915_enable_ips __read_mostly = 1;
136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
138
139 bool i915_fastboot __read_mostly = 0;
140 module_param_named(fastboot, i915_fastboot, bool, 0600);
141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
142                  "(default: false)");
143
144 int i915_enable_pc8 __read_mostly = 1;
145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
147
148 int i915_pc8_timeout __read_mostly = 5000;
149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
151
152 bool i915_prefault_disable __read_mostly;
153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
154 MODULE_PARM_DESC(prefault_disable,
155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
156
157 static struct drm_driver driver;
158 extern int intel_agp_enabled;
159
160 static const struct intel_device_info intel_i830_info = {
161         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
162         .has_overlay = 1, .overlay_needs_physical = 1,
163         .ring_mask = RENDER_RING,
164 };
165
166 static const struct intel_device_info intel_845g_info = {
167         .gen = 2, .num_pipes = 1,
168         .has_overlay = 1, .overlay_needs_physical = 1,
169         .ring_mask = RENDER_RING,
170 };
171
172 static const struct intel_device_info intel_i85x_info = {
173         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
174         .cursor_needs_physical = 1,
175         .has_overlay = 1, .overlay_needs_physical = 1,
176         .ring_mask = RENDER_RING,
177 };
178
179 static const struct intel_device_info intel_i865g_info = {
180         .gen = 2, .num_pipes = 1,
181         .has_overlay = 1, .overlay_needs_physical = 1,
182         .ring_mask = RENDER_RING,
183 };
184
185 static const struct intel_device_info intel_i915g_info = {
186         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
187         .has_overlay = 1, .overlay_needs_physical = 1,
188         .ring_mask = RENDER_RING,
189 };
190 static const struct intel_device_info intel_i915gm_info = {
191         .gen = 3, .is_mobile = 1, .num_pipes = 2,
192         .cursor_needs_physical = 1,
193         .has_overlay = 1, .overlay_needs_physical = 1,
194         .supports_tv = 1,
195         .ring_mask = RENDER_RING,
196 };
197 static const struct intel_device_info intel_i945g_info = {
198         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
199         .has_overlay = 1, .overlay_needs_physical = 1,
200         .ring_mask = RENDER_RING,
201 };
202 static const struct intel_device_info intel_i945gm_info = {
203         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
204         .has_hotplug = 1, .cursor_needs_physical = 1,
205         .has_overlay = 1, .overlay_needs_physical = 1,
206         .supports_tv = 1,
207         .ring_mask = RENDER_RING,
208 };
209
210 static const struct intel_device_info intel_i965g_info = {
211         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
212         .has_hotplug = 1,
213         .has_overlay = 1,
214         .ring_mask = RENDER_RING,
215 };
216
217 static const struct intel_device_info intel_i965gm_info = {
218         .gen = 4, .is_crestline = 1, .num_pipes = 2,
219         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
220         .has_overlay = 1,
221         .supports_tv = 1,
222         .ring_mask = RENDER_RING,
223 };
224
225 static const struct intel_device_info intel_g33_info = {
226         .gen = 3, .is_g33 = 1, .num_pipes = 2,
227         .need_gfx_hws = 1, .has_hotplug = 1,
228         .has_overlay = 1,
229         .ring_mask = RENDER_RING,
230 };
231
232 static const struct intel_device_info intel_g45_info = {
233         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
234         .has_pipe_cxsr = 1, .has_hotplug = 1,
235         .ring_mask = RENDER_RING | BSD_RING,
236 };
237
238 static const struct intel_device_info intel_gm45_info = {
239         .gen = 4, .is_g4x = 1, .num_pipes = 2,
240         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
241         .has_pipe_cxsr = 1, .has_hotplug = 1,
242         .supports_tv = 1,
243         .ring_mask = RENDER_RING | BSD_RING,
244 };
245
246 static const struct intel_device_info intel_pineview_info = {
247         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
248         .need_gfx_hws = 1, .has_hotplug = 1,
249         .has_overlay = 1,
250 };
251
252 static const struct intel_device_info intel_ironlake_d_info = {
253         .gen = 5, .num_pipes = 2,
254         .need_gfx_hws = 1, .has_hotplug = 1,
255         .ring_mask = RENDER_RING | BSD_RING,
256 };
257
258 static const struct intel_device_info intel_ironlake_m_info = {
259         .gen = 5, .is_mobile = 1, .num_pipes = 2,
260         .need_gfx_hws = 1, .has_hotplug = 1,
261         .has_fbc = 1,
262         .ring_mask = RENDER_RING | BSD_RING,
263 };
264
265 static const struct intel_device_info intel_sandybridge_d_info = {
266         .gen = 6, .num_pipes = 2,
267         .need_gfx_hws = 1, .has_hotplug = 1,
268         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
269         .has_llc = 1,
270 };
271
272 static const struct intel_device_info intel_sandybridge_m_info = {
273         .gen = 6, .is_mobile = 1, .num_pipes = 2,
274         .need_gfx_hws = 1, .has_hotplug = 1,
275         .has_fbc = 1,
276         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
277         .has_llc = 1,
278 };
279
280 #define GEN7_FEATURES  \
281         .gen = 7, .num_pipes = 3, \
282         .need_gfx_hws = 1, .has_hotplug = 1, \
283         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
284         .has_llc = 1
285
286 static const struct intel_device_info intel_ivybridge_d_info = {
287         GEN7_FEATURES,
288         .is_ivybridge = 1,
289 };
290
291 static const struct intel_device_info intel_ivybridge_m_info = {
292         GEN7_FEATURES,
293         .is_ivybridge = 1,
294         .is_mobile = 1,
295         .has_fbc = 1,
296 };
297
298 static const struct intel_device_info intel_ivybridge_q_info = {
299         GEN7_FEATURES,
300         .is_ivybridge = 1,
301         .num_pipes = 0, /* legal, last one wins */
302 };
303
304 static const struct intel_device_info intel_valleyview_m_info = {
305         GEN7_FEATURES,
306         .is_mobile = 1,
307         .num_pipes = 2,
308         .is_valleyview = 1,
309         .display_mmio_offset = VLV_DISPLAY_BASE,
310         .has_llc = 0, /* legal, last one wins */
311 };
312
313 static const struct intel_device_info intel_valleyview_d_info = {
314         GEN7_FEATURES,
315         .num_pipes = 2,
316         .is_valleyview = 1,
317         .display_mmio_offset = VLV_DISPLAY_BASE,
318         .has_llc = 0, /* legal, last one wins */
319 };
320
321 static const struct intel_device_info intel_haswell_d_info = {
322         GEN7_FEATURES,
323         .is_haswell = 1,
324         .has_ddi = 1,
325         .has_fpga_dbg = 1,
326         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
327 };
328
329 static const struct intel_device_info intel_haswell_m_info = {
330         GEN7_FEATURES,
331         .is_haswell = 1,
332         .is_mobile = 1,
333         .has_ddi = 1,
334         .has_fpga_dbg = 1,
335         .has_fbc = 1,
336         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
337 };
338
339 /*
340  * Make sure any device matches here are from most specific to most
341  * general.  For example, since the Quanta match is based on the subsystem
342  * and subvendor IDs, we need it to come before the more general IVB
343  * PCI ID matches, otherwise we'll use the wrong info struct above.
344  */
345 #define INTEL_PCI_IDS \
346         INTEL_I830_IDS(&intel_i830_info),       \
347         INTEL_I845G_IDS(&intel_845g_info),      \
348         INTEL_I85X_IDS(&intel_i85x_info),       \
349         INTEL_I865G_IDS(&intel_i865g_info),     \
350         INTEL_I915G_IDS(&intel_i915g_info),     \
351         INTEL_I915GM_IDS(&intel_i915gm_info),   \
352         INTEL_I945G_IDS(&intel_i945g_info),     \
353         INTEL_I945GM_IDS(&intel_i945gm_info),   \
354         INTEL_I965G_IDS(&intel_i965g_info),     \
355         INTEL_G33_IDS(&intel_g33_info),         \
356         INTEL_I965GM_IDS(&intel_i965gm_info),   \
357         INTEL_GM45_IDS(&intel_gm45_info),       \
358         INTEL_G45_IDS(&intel_g45_info),         \
359         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
360         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
361         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
362         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
363         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
364         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
365         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
366         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
367         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
368         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
369         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
370         INTEL_VLV_D_IDS(&intel_valleyview_d_info)
371
372 static const struct pci_device_id pciidlist[] = {               /* aka */
373         INTEL_PCI_IDS,
374         {0, 0, 0}
375 };
376
377 #if defined(CONFIG_DRM_I915_KMS)
378 MODULE_DEVICE_TABLE(pci, pciidlist);
379 #endif
380
381 void intel_detect_pch(struct drm_device *dev)
382 {
383         struct drm_i915_private *dev_priv = dev->dev_private;
384         struct pci_dev *pch;
385
386         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
387          * (which really amounts to a PCH but no South Display).
388          */
389         if (INTEL_INFO(dev)->num_pipes == 0) {
390                 dev_priv->pch_type = PCH_NOP;
391                 return;
392         }
393
394         /*
395          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
396          * make graphics device passthrough work easy for VMM, that only
397          * need to expose ISA bridge to let driver know the real hardware
398          * underneath. This is a requirement from virtualization team.
399          *
400          * In some virtualized environments (e.g. XEN), there is irrelevant
401          * ISA bridge in the system. To work reliably, we should scan trhough
402          * all the ISA bridge devices and check for the first match, instead
403          * of only checking the first one.
404          */
405         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
406         while (pch) {
407                 struct pci_dev *curr = pch;
408                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
409                         unsigned short id;
410                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
411                         dev_priv->pch_id = id;
412
413                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
414                                 dev_priv->pch_type = PCH_IBX;
415                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
416                                 WARN_ON(!IS_GEN5(dev));
417                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
418                                 dev_priv->pch_type = PCH_CPT;
419                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
420                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
421                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
422                                 /* PantherPoint is CPT compatible */
423                                 dev_priv->pch_type = PCH_CPT;
424                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
425                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
426                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
427                                 dev_priv->pch_type = PCH_LPT;
428                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
429                                 WARN_ON(!IS_HASWELL(dev));
430                                 WARN_ON(IS_ULT(dev));
431                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
432                                 dev_priv->pch_type = PCH_LPT;
433                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
434                                 WARN_ON(!IS_HASWELL(dev));
435                                 WARN_ON(!IS_ULT(dev));
436                         } else {
437                                 goto check_next;
438                         }
439                         pci_dev_put(pch);
440                         break;
441                 }
442 check_next:
443                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
444                 pci_dev_put(curr);
445         }
446         if (!pch)
447                 DRM_DEBUG_KMS("No PCH found?\n");
448 }
449
450 bool i915_semaphore_is_enabled(struct drm_device *dev)
451 {
452         if (INTEL_INFO(dev)->gen < 6)
453                 return 0;
454
455         if (i915_semaphores >= 0)
456                 return i915_semaphores;
457
458 #ifdef CONFIG_INTEL_IOMMU
459         /* Enable semaphores on SNB when IO remapping is off */
460         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
461                 return false;
462 #endif
463
464         return 1;
465 }
466
467 static int i915_drm_freeze(struct drm_device *dev)
468 {
469         struct drm_i915_private *dev_priv = dev->dev_private;
470         struct drm_crtc *crtc;
471
472         /* ignore lid events during suspend */
473         mutex_lock(&dev_priv->modeset_restore_lock);
474         dev_priv->modeset_restore = MODESET_SUSPENDED;
475         mutex_unlock(&dev_priv->modeset_restore_lock);
476
477         /* We do a lot of poking in a lot of registers, make sure they work
478          * properly. */
479         hsw_disable_package_c8(dev_priv);
480         intel_set_power_well(dev, true);
481
482         drm_kms_helper_poll_disable(dev);
483
484         pci_save_state(dev->pdev);
485
486         /* If KMS is active, we do the leavevt stuff here */
487         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
488                 int error;
489
490                 error = i915_gem_suspend(dev);
491                 if (error) {
492                         dev_err(&dev->pdev->dev,
493                                 "GEM idle failed, resume might fail\n");
494                         return error;
495                 }
496
497                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
498
499                 drm_irq_uninstall(dev);
500                 dev_priv->enable_hotplug_processing = false;
501                 /*
502                  * Disable CRTCs directly since we want to preserve sw state
503                  * for _thaw.
504                  */
505                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
506                         dev_priv->display.crtc_disable(crtc);
507
508                 intel_modeset_suspend_hw(dev);
509         }
510
511         i915_save_state(dev);
512
513         intel_opregion_fini(dev);
514
515         console_lock();
516         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
517         console_unlock();
518
519         return 0;
520 }
521
522 int i915_suspend(struct drm_device *dev, pm_message_t state)
523 {
524         int error;
525
526         if (!dev || !dev->dev_private) {
527                 DRM_ERROR("dev: %p\n", dev);
528                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
529                 return -ENODEV;
530         }
531
532         if (state.event == PM_EVENT_PRETHAW)
533                 return 0;
534
535
536         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
537                 return 0;
538
539         error = i915_drm_freeze(dev);
540         if (error)
541                 return error;
542
543         if (state.event == PM_EVENT_SUSPEND) {
544                 /* Shut down the device */
545                 pci_disable_device(dev->pdev);
546                 pci_set_power_state(dev->pdev, PCI_D3hot);
547         }
548
549         return 0;
550 }
551
552 void intel_console_resume(struct work_struct *work)
553 {
554         struct drm_i915_private *dev_priv =
555                 container_of(work, struct drm_i915_private,
556                              console_resume_work);
557         struct drm_device *dev = dev_priv->dev;
558
559         console_lock();
560         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
561         console_unlock();
562 }
563
564 static void intel_resume_hotplug(struct drm_device *dev)
565 {
566         struct drm_mode_config *mode_config = &dev->mode_config;
567         struct intel_encoder *encoder;
568
569         mutex_lock(&mode_config->mutex);
570         DRM_DEBUG_KMS("running encoder hotplug functions\n");
571
572         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
573                 if (encoder->hot_plug)
574                         encoder->hot_plug(encoder);
575
576         mutex_unlock(&mode_config->mutex);
577
578         /* Just fire off a uevent and let userspace tell us what to do */
579         drm_helper_hpd_irq_event(dev);
580 }
581
582 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
583 {
584         struct drm_i915_private *dev_priv = dev->dev_private;
585         int error = 0;
586
587         intel_uncore_early_sanitize(dev);
588
589         intel_uncore_sanitize(dev);
590
591         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
592             restore_gtt_mappings) {
593                 mutex_lock(&dev->struct_mutex);
594                 i915_gem_restore_gtt_mappings(dev);
595                 mutex_unlock(&dev->struct_mutex);
596         }
597
598         intel_init_power_well(dev);
599
600         i915_restore_state(dev);
601         intel_opregion_setup(dev);
602
603         /* KMS EnterVT equivalent */
604         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
605                 intel_init_pch_refclk(dev);
606
607                 mutex_lock(&dev->struct_mutex);
608
609                 error = i915_gem_init_hw(dev);
610                 mutex_unlock(&dev->struct_mutex);
611
612                 /* We need working interrupts for modeset enabling ... */
613                 drm_irq_install(dev);
614
615                 intel_modeset_init_hw(dev);
616
617                 drm_modeset_lock_all(dev);
618                 intel_modeset_setup_hw_state(dev, true);
619                 drm_modeset_unlock_all(dev);
620
621                 /*
622                  * ... but also need to make sure that hotplug processing
623                  * doesn't cause havoc. Like in the driver load code we don't
624                  * bother with the tiny race here where we might loose hotplug
625                  * notifications.
626                  * */
627                 intel_hpd_init(dev);
628                 dev_priv->enable_hotplug_processing = true;
629                 /* Config may have changed between suspend and resume */
630                 intel_resume_hotplug(dev);
631         }
632
633         intel_opregion_init(dev);
634
635         /*
636          * The console lock can be pretty contented on resume due
637          * to all the printk activity.  Try to keep it out of the hot
638          * path of resume if possible.
639          */
640         if (console_trylock()) {
641                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
642                 console_unlock();
643         } else {
644                 schedule_work(&dev_priv->console_resume_work);
645         }
646
647         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
648          * expected level. */
649         hsw_enable_package_c8(dev_priv);
650
651         mutex_lock(&dev_priv->modeset_restore_lock);
652         dev_priv->modeset_restore = MODESET_DONE;
653         mutex_unlock(&dev_priv->modeset_restore_lock);
654         return error;
655 }
656
657 static int i915_drm_thaw(struct drm_device *dev)
658 {
659         return __i915_drm_thaw(dev, true);
660 }
661
662 int i915_resume(struct drm_device *dev)
663 {
664         struct drm_i915_private *dev_priv = dev->dev_private;
665         int ret;
666
667         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
668                 return 0;
669
670         if (pci_enable_device(dev->pdev))
671                 return -EIO;
672
673         pci_set_master(dev->pdev);
674
675         /*
676          * Platforms with opregion should have sane BIOS, older ones (gen3 and
677          * earlier) need to restore the GTT mappings since the BIOS might clear
678          * all our scratch PTEs.
679          */
680         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
681         if (ret)
682                 return ret;
683
684         drm_kms_helper_poll_enable(dev);
685         return 0;
686 }
687
688 /**
689  * i915_reset - reset chip after a hang
690  * @dev: drm device to reset
691  *
692  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
693  * reset or otherwise an error code.
694  *
695  * Procedure is fairly simple:
696  *   - reset the chip using the reset reg
697  *   - re-init context state
698  *   - re-init hardware status page
699  *   - re-init ring buffer
700  *   - re-init interrupt state
701  *   - re-init display
702  */
703 int i915_reset(struct drm_device *dev)
704 {
705         drm_i915_private_t *dev_priv = dev->dev_private;
706         bool simulated;
707         int ret;
708
709         if (!i915_try_reset)
710                 return 0;
711
712         mutex_lock(&dev->struct_mutex);
713
714         i915_gem_reset(dev);
715
716         simulated = dev_priv->gpu_error.stop_rings != 0;
717
718         ret = intel_gpu_reset(dev);
719
720         /* Also reset the gpu hangman. */
721         if (simulated) {
722                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
723                 dev_priv->gpu_error.stop_rings = 0;
724                 if (ret == -ENODEV) {
725                         DRM_ERROR("Reset not implemented, but ignoring "
726                                   "error for simulated gpu hangs\n");
727                         ret = 0;
728                 }
729         }
730
731         if (ret) {
732                 DRM_ERROR("Failed to reset chip.\n");
733                 mutex_unlock(&dev->struct_mutex);
734                 return ret;
735         }
736
737         /* Ok, now get things going again... */
738
739         /*
740          * Everything depends on having the GTT running, so we need to start
741          * there.  Fortunately we don't need to do this unless we reset the
742          * chip at a PCI level.
743          *
744          * Next we need to restore the context, but we don't use those
745          * yet either...
746          *
747          * Ring buffer needs to be re-initialized in the KMS case, or if X
748          * was running at the time of the reset (i.e. we weren't VT
749          * switched away).
750          */
751         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
752                         !dev_priv->ums.mm_suspended) {
753                 bool hw_contexts_disabled = dev_priv->hw_contexts_disabled;
754                 dev_priv->ums.mm_suspended = 0;
755
756                 ret = i915_gem_init_hw(dev);
757                 if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled)
758                         DRM_ERROR("HW contexts didn't survive reset\n");
759                 mutex_unlock(&dev->struct_mutex);
760                 if (ret) {
761                         DRM_ERROR("Failed hw init on reset %d\n", ret);
762                         return ret;
763                 }
764
765                 drm_irq_uninstall(dev);
766                 drm_irq_install(dev);
767                 intel_hpd_init(dev);
768         } else {
769                 mutex_unlock(&dev->struct_mutex);
770         }
771
772         return 0;
773 }
774
775 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
776 {
777         struct intel_device_info *intel_info =
778                 (struct intel_device_info *) ent->driver_data;
779
780         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
781                 DRM_INFO("This hardware requires preliminary hardware support.\n"
782                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
783                 return -ENODEV;
784         }
785
786         /* Only bind to function 0 of the device. Early generations
787          * used function 1 as a placeholder for multi-head. This causes
788          * us confusion instead, especially on the systems where both
789          * functions have the same PCI-ID!
790          */
791         if (PCI_FUNC(pdev->devfn))
792                 return -ENODEV;
793
794         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
795          * implementation for gen3 (and only gen3) that used legacy drm maps
796          * (gasp!) to share buffers between X and the client. Hence we need to
797          * keep around the fake agp stuff for gen3, even when kms is enabled. */
798         if (intel_info->gen != 3) {
799                 driver.driver_features &=
800                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
801         } else if (!intel_agp_enabled) {
802                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
803                 return -ENODEV;
804         }
805
806         return drm_get_pci_dev(pdev, ent, &driver);
807 }
808
809 static void
810 i915_pci_remove(struct pci_dev *pdev)
811 {
812         struct drm_device *dev = pci_get_drvdata(pdev);
813
814         drm_put_dev(dev);
815 }
816
817 static int i915_pm_suspend(struct device *dev)
818 {
819         struct pci_dev *pdev = to_pci_dev(dev);
820         struct drm_device *drm_dev = pci_get_drvdata(pdev);
821         int error;
822
823         if (!drm_dev || !drm_dev->dev_private) {
824                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
825                 return -ENODEV;
826         }
827
828         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
829                 return 0;
830
831         error = i915_drm_freeze(drm_dev);
832         if (error)
833                 return error;
834
835         pci_disable_device(pdev);
836         pci_set_power_state(pdev, PCI_D3hot);
837
838         return 0;
839 }
840
841 static int i915_pm_resume(struct device *dev)
842 {
843         struct pci_dev *pdev = to_pci_dev(dev);
844         struct drm_device *drm_dev = pci_get_drvdata(pdev);
845
846         return i915_resume(drm_dev);
847 }
848
849 static int i915_pm_freeze(struct device *dev)
850 {
851         struct pci_dev *pdev = to_pci_dev(dev);
852         struct drm_device *drm_dev = pci_get_drvdata(pdev);
853
854         if (!drm_dev || !drm_dev->dev_private) {
855                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
856                 return -ENODEV;
857         }
858
859         return i915_drm_freeze(drm_dev);
860 }
861
862 static int i915_pm_thaw(struct device *dev)
863 {
864         struct pci_dev *pdev = to_pci_dev(dev);
865         struct drm_device *drm_dev = pci_get_drvdata(pdev);
866
867         return i915_drm_thaw(drm_dev);
868 }
869
870 static int i915_pm_poweroff(struct device *dev)
871 {
872         struct pci_dev *pdev = to_pci_dev(dev);
873         struct drm_device *drm_dev = pci_get_drvdata(pdev);
874
875         return i915_drm_freeze(drm_dev);
876 }
877
878 static const struct dev_pm_ops i915_pm_ops = {
879         .suspend = i915_pm_suspend,
880         .resume = i915_pm_resume,
881         .freeze = i915_pm_freeze,
882         .thaw = i915_pm_thaw,
883         .poweroff = i915_pm_poweroff,
884         .restore = i915_pm_resume,
885 };
886
887 static const struct vm_operations_struct i915_gem_vm_ops = {
888         .fault = i915_gem_fault,
889         .open = drm_gem_vm_open,
890         .close = drm_gem_vm_close,
891 };
892
893 static const struct file_operations i915_driver_fops = {
894         .owner = THIS_MODULE,
895         .open = drm_open,
896         .release = drm_release,
897         .unlocked_ioctl = drm_ioctl,
898         .mmap = drm_gem_mmap,
899         .poll = drm_poll,
900         .read = drm_read,
901 #ifdef CONFIG_COMPAT
902         .compat_ioctl = i915_compat_ioctl,
903 #endif
904         .llseek = noop_llseek,
905 };
906
907 static struct drm_driver driver = {
908         /* Don't use MTRRs here; the Xserver or userspace app should
909          * deal with them for Intel hardware.
910          */
911         .driver_features =
912             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
913             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
914             DRIVER_RENDER,
915         .load = i915_driver_load,
916         .unload = i915_driver_unload,
917         .open = i915_driver_open,
918         .lastclose = i915_driver_lastclose,
919         .preclose = i915_driver_preclose,
920         .postclose = i915_driver_postclose,
921
922         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
923         .suspend = i915_suspend,
924         .resume = i915_resume,
925
926         .device_is_agp = i915_driver_device_is_agp,
927         .master_create = i915_master_create,
928         .master_destroy = i915_master_destroy,
929 #if defined(CONFIG_DEBUG_FS)
930         .debugfs_init = i915_debugfs_init,
931         .debugfs_cleanup = i915_debugfs_cleanup,
932 #endif
933         .gem_free_object = i915_gem_free_object,
934         .gem_vm_ops = &i915_gem_vm_ops,
935
936         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
937         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
938         .gem_prime_export = i915_gem_prime_export,
939         .gem_prime_import = i915_gem_prime_import,
940
941         .dumb_create = i915_gem_dumb_create,
942         .dumb_map_offset = i915_gem_mmap_gtt,
943         .dumb_destroy = drm_gem_dumb_destroy,
944         .ioctls = i915_ioctls,
945         .fops = &i915_driver_fops,
946         .name = DRIVER_NAME,
947         .desc = DRIVER_DESC,
948         .date = DRIVER_DATE,
949         .major = DRIVER_MAJOR,
950         .minor = DRIVER_MINOR,
951         .patchlevel = DRIVER_PATCHLEVEL,
952 };
953
954 static struct pci_driver i915_pci_driver = {
955         .name = DRIVER_NAME,
956         .id_table = pciidlist,
957         .probe = i915_pci_probe,
958         .remove = i915_pci_remove,
959         .driver.pm = &i915_pm_ops,
960 };
961
962 static int __init i915_init(void)
963 {
964         driver.num_ioctls = i915_max_ioctl;
965
966         /*
967          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
968          * explicitly disabled with the module pararmeter.
969          *
970          * Otherwise, just follow the parameter (defaulting to off).
971          *
972          * Allow optional vga_text_mode_force boot option to override
973          * the default behavior.
974          */
975 #if defined(CONFIG_DRM_I915_KMS)
976         if (i915_modeset != 0)
977                 driver.driver_features |= DRIVER_MODESET;
978 #endif
979         if (i915_modeset == 1)
980                 driver.driver_features |= DRIVER_MODESET;
981
982 #ifdef CONFIG_VGA_CONSOLE
983         if (vgacon_text_force() && i915_modeset == -1)
984                 driver.driver_features &= ~DRIVER_MODESET;
985 #endif
986
987         if (!(driver.driver_features & DRIVER_MODESET))
988                 driver.get_vblank_timestamp = NULL;
989
990         return drm_pci_init(&driver, &i915_pci_driver);
991 }
992
993 static void __exit i915_exit(void)
994 {
995         drm_pci_exit(&driver, &i915_pci_driver);
996 }
997
998 module_init(i915_init);
999 module_exit(i915_exit);
1000
1001 MODULE_AUTHOR(DRIVER_AUTHOR);
1002 MODULE_DESCRIPTION(DRIVER_DESC);
1003 MODULE_LICENSE("GPL and additional rights");