drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
  51         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
  52         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  53
  54 #define GEN_CHV_PIPEOFFSETS \
  55         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  56                           CHV_PIPE_C_OFFSET }, \
  57         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  58                            CHV_TRANSCODER_C_OFFSET, }, \
  59         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
  60                           CHV_DPLL_C_OFFSET }, \
  61         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
  62                              CHV_DPLL_C_MD_OFFSET }, \
  63         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  64                              CHV_PALETTE_C_OFFSET }
  65
  66 #define CURSOR_OFFSETS \
  67         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  68
  69 #define IVB_CURSOR_OFFSETS \
  70         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  71
  72 static const struct intel_device_info intel_i830_info = {
  73         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  74         .has_overlay = 1, .overlay_needs_physical = 1,
  75         .ring_mask = RENDER_RING,
  76         GEN_DEFAULT_PIPEOFFSETS,
  77         CURSOR_OFFSETS,
  78 };
  79
  80 static const struct intel_device_info intel_845g_info = {
  81         .gen = 2, .num_pipes = 1,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83         .ring_mask = RENDER_RING,
  84         GEN_DEFAULT_PIPEOFFSETS,
  85         CURSOR_OFFSETS,
  86 };
  87
  88 static const struct intel_device_info intel_i85x_info = {
  89         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  90         .cursor_needs_physical = 1,
  91         .has_overlay = 1, .overlay_needs_physical = 1,
  92         .has_fbc = 1,
  93         .ring_mask = RENDER_RING,
  94         GEN_DEFAULT_PIPEOFFSETS,
  95         CURSOR_OFFSETS,
  96 };
  97
  98 static const struct intel_device_info intel_i865g_info = {
  99         .gen = 2, .num_pipes = 1,
 100         .has_overlay = 1, .overlay_needs_physical = 1,
 101         .ring_mask = RENDER_RING,
 102         GEN_DEFAULT_PIPEOFFSETS,
 103         CURSOR_OFFSETS,
 104 };
 105
 106 static const struct intel_device_info intel_i915g_info = {
 107         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 108         .has_overlay = 1, .overlay_needs_physical = 1,
 109         .ring_mask = RENDER_RING,
 110         GEN_DEFAULT_PIPEOFFSETS,
 111         CURSOR_OFFSETS,
 112 };
 113 static const struct intel_device_info intel_i915gm_info = {
 114         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 115         .cursor_needs_physical = 1,
 116         .has_overlay = 1, .overlay_needs_physical = 1,
 117         .supports_tv = 1,
 118         .has_fbc = 1,
 119         .ring_mask = RENDER_RING,
 120         GEN_DEFAULT_PIPEOFFSETS,
 121         CURSOR_OFFSETS,
 122 };
 123 static const struct intel_device_info intel_i945g_info = {
 124         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 125         .has_overlay = 1, .overlay_needs_physical = 1,
 126         .ring_mask = RENDER_RING,
 127         GEN_DEFAULT_PIPEOFFSETS,
 128         CURSOR_OFFSETS,
 129 };
 130 static const struct intel_device_info intel_i945gm_info = {
 131         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 132         .has_hotplug = 1, .cursor_needs_physical = 1,
 133         .has_overlay = 1, .overlay_needs_physical = 1,
 134         .supports_tv = 1,
 135         .has_fbc = 1,
 136         .ring_mask = RENDER_RING,
 137         GEN_DEFAULT_PIPEOFFSETS,
 138         CURSOR_OFFSETS,
 139 };
 140
 141 static const struct intel_device_info intel_i965g_info = {
 142         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 143         .has_hotplug = 1,
 144         .has_overlay = 1,
 145         .ring_mask = RENDER_RING,
 146         GEN_DEFAULT_PIPEOFFSETS,
 147         CURSOR_OFFSETS,
 148 };
 149
 150 static const struct intel_device_info intel_i965gm_info = {
 151         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 152         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 153         .has_overlay = 1,
 154         .supports_tv = 1,
 155         .ring_mask = RENDER_RING,
 156         GEN_DEFAULT_PIPEOFFSETS,
 157         CURSOR_OFFSETS,
 158 };
 159
 160 static const struct intel_device_info intel_g33_info = {
 161         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 162         .need_gfx_hws = 1, .has_hotplug = 1,
 163         .has_overlay = 1,
 164         .ring_mask = RENDER_RING,
 165         GEN_DEFAULT_PIPEOFFSETS,
 166         CURSOR_OFFSETS,
 167 };
 168
 169 static const struct intel_device_info intel_g45_info = {
 170         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 171         .has_pipe_cxsr = 1, .has_hotplug = 1,
 172         .ring_mask = RENDER_RING | BSD_RING,
 173         GEN_DEFAULT_PIPEOFFSETS,
 174         CURSOR_OFFSETS,
 175 };
 176
 177 static const struct intel_device_info intel_gm45_info = {
 178         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 179         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 180         .has_pipe_cxsr = 1, .has_hotplug = 1,
 181         .supports_tv = 1,
 182         .ring_mask = RENDER_RING | BSD_RING,
 183         GEN_DEFAULT_PIPEOFFSETS,
 184         CURSOR_OFFSETS,
 185 };
 186
 187 static const struct intel_device_info intel_pineview_info = {
 188         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 189         .need_gfx_hws = 1, .has_hotplug = 1,
 190         .has_overlay = 1,
 191         GEN_DEFAULT_PIPEOFFSETS,
 192         CURSOR_OFFSETS,
 193 };
 194
 195 static const struct intel_device_info intel_ironlake_d_info = {
 196         .gen = 5, .num_pipes = 2,
 197         .need_gfx_hws = 1, .has_hotplug = 1,
 198         .ring_mask = RENDER_RING | BSD_RING,
 199         GEN_DEFAULT_PIPEOFFSETS,
 200         CURSOR_OFFSETS,
 201 };
 202
 203 static const struct intel_device_info intel_ironlake_m_info = {
 204         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 205         .need_gfx_hws = 1, .has_hotplug = 1,
 206         .has_fbc = 1,
 207         .ring_mask = RENDER_RING | BSD_RING,
 208         GEN_DEFAULT_PIPEOFFSETS,
 209         CURSOR_OFFSETS,
 210 };
 211
 212 static const struct intel_device_info intel_sandybridge_d_info = {
 213         .gen = 6, .num_pipes = 2,
 214         .need_gfx_hws = 1, .has_hotplug = 1,
 215         .has_fbc = 1,
 216         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 217         .has_llc = 1,
 218         GEN_DEFAULT_PIPEOFFSETS,
 219         CURSOR_OFFSETS,
 220 };
 221
 222 static const struct intel_device_info intel_sandybridge_m_info = {
 223         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 224         .need_gfx_hws = 1, .has_hotplug = 1,
 225         .has_fbc = 1,
 226         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 227         .has_llc = 1,
 228         GEN_DEFAULT_PIPEOFFSETS,
 229         CURSOR_OFFSETS,
 230 };
 231
 232 #define GEN7_FEATURES  \
 233         .gen = 7, .num_pipes = 3, \
 234         .need_gfx_hws = 1, .has_hotplug = 1, \
 235         .has_fbc = 1, \
 236         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 237         .has_llc = 1
 238
 239 static const struct intel_device_info intel_ivybridge_d_info = {
 240         GEN7_FEATURES,
 241         .is_ivybridge = 1,
 242         GEN_DEFAULT_PIPEOFFSETS,
 243         IVB_CURSOR_OFFSETS,
 244 };
 245
 246 static const struct intel_device_info intel_ivybridge_m_info = {
 247         GEN7_FEATURES,
 248         .is_ivybridge = 1,
 249         .is_mobile = 1,
 250         GEN_DEFAULT_PIPEOFFSETS,
 251         IVB_CURSOR_OFFSETS,
 252 };
 253
 254 static const struct intel_device_info intel_ivybridge_q_info = {
 255         GEN7_FEATURES,
 256         .is_ivybridge = 1,
 257         .num_pipes = 0, /* legal, last one wins */
 258         GEN_DEFAULT_PIPEOFFSETS,
 259         IVB_CURSOR_OFFSETS,
 260 };
 261
 262 static const struct intel_device_info intel_valleyview_m_info = {
 263         GEN7_FEATURES,
 264         .is_mobile = 1,
 265         .num_pipes = 2,
 266         .is_valleyview = 1,
 267         .display_mmio_offset = VLV_DISPLAY_BASE,
 268         .has_fbc = 0, /* legal, last one wins */
 269         .has_llc = 0, /* legal, last one wins */
 270         GEN_DEFAULT_PIPEOFFSETS,
 271         CURSOR_OFFSETS,
 272 };
 273
 274 static const struct intel_device_info intel_valleyview_d_info = {
 275         GEN7_FEATURES,
 276         .num_pipes = 2,
 277         .is_valleyview = 1,
 278         .display_mmio_offset = VLV_DISPLAY_BASE,
 279         .has_fbc = 0, /* legal, last one wins */
 280         .has_llc = 0, /* legal, last one wins */
 281         GEN_DEFAULT_PIPEOFFSETS,
 282         CURSOR_OFFSETS,
 283 };
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         GEN7_FEATURES,
 287         .is_haswell = 1,
 288         .has_ddi = 1,
 289         .has_fpga_dbg = 1,
 290         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 291         GEN_DEFAULT_PIPEOFFSETS,
 292         IVB_CURSOR_OFFSETS,
 293 };
 294
 295 static const struct intel_device_info intel_haswell_m_info = {
 296         GEN7_FEATURES,
 297         .is_haswell = 1,
 298         .is_mobile = 1,
 299         .has_ddi = 1,
 300         .has_fpga_dbg = 1,
 301         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 302         GEN_DEFAULT_PIPEOFFSETS,
 303         IVB_CURSOR_OFFSETS,
 304 };
 305
 306 static const struct intel_device_info intel_broadwell_d_info = {
 307         .gen = 8, .num_pipes = 3,
 308         .need_gfx_hws = 1, .has_hotplug = 1,
 309         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 310         .has_llc = 1,
 311         .has_ddi = 1,
 312         .has_fbc = 1,
 313         GEN_DEFAULT_PIPEOFFSETS,
 314         IVB_CURSOR_OFFSETS,
 315 };
 316
 317 static const struct intel_device_info intel_broadwell_m_info = {
 318         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 319         .need_gfx_hws = 1, .has_hotplug = 1,
 320         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 321         .has_llc = 1,
 322         .has_ddi = 1,
 323         .has_fbc = 1,
 324         GEN_DEFAULT_PIPEOFFSETS,
 325         IVB_CURSOR_OFFSETS,
 326 };
 327
 328 static const struct intel_device_info intel_broadwell_gt3d_info = {
 329         .gen = 8, .num_pipes = 3,
 330         .need_gfx_hws = 1, .has_hotplug = 1,
 331         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 332         .has_llc = 1,
 333         .has_ddi = 1,
 334         .has_fbc = 1,
 335         GEN_DEFAULT_PIPEOFFSETS,
 336         IVB_CURSOR_OFFSETS,
 337 };
 338
 339 static const struct intel_device_info intel_broadwell_gt3m_info = {
 340         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 341         .need_gfx_hws = 1, .has_hotplug = 1,
 342         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 343         .has_llc = 1,
 344         .has_ddi = 1,
 345         .has_fbc = 1,
 346         GEN_DEFAULT_PIPEOFFSETS,
 347         IVB_CURSOR_OFFSETS,
 348 };
 349
 350 static const struct intel_device_info intel_cherryview_info = {
 351         .is_preliminary = 1,
 352         .gen = 8, .num_pipes = 3,
 353         .need_gfx_hws = 1, .has_hotplug = 1,
 354         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 355         .is_valleyview = 1,
 356         .display_mmio_offset = VLV_DISPLAY_BASE,
 357         GEN_CHV_PIPEOFFSETS,
 358         CURSOR_OFFSETS,
 359 };
 360
 361 /*
 362  * Make sure any device matches here are from most specific to most
 363  * general.  For example, since the Quanta match is based on the subsystem
 364  * and subvendor IDs, we need it to come before the more general IVB
 365  * PCI ID matches, otherwise we'll use the wrong info struct above.
 366  */
 367 #define INTEL_PCI_IDS \
 368         INTEL_I830_IDS(&intel_i830_info),       \
 369         INTEL_I845G_IDS(&intel_845g_info),      \
 370         INTEL_I85X_IDS(&intel_i85x_info),       \
 371         INTEL_I865G_IDS(&intel_i865g_info),     \
 372         INTEL_I915G_IDS(&intel_i915g_info),     \
 373         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 374         INTEL_I945G_IDS(&intel_i945g_info),     \
 375         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 376         INTEL_I965G_IDS(&intel_i965g_info),     \
 377         INTEL_G33_IDS(&intel_g33_info),         \
 378         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 379         INTEL_GM45_IDS(&intel_gm45_info),       \
 380         INTEL_G45_IDS(&intel_g45_info),         \
 381         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 382         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 383         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 384         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 385         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 386         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 387         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 388         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 389         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 390         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 391         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 392         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 393         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 394         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 395         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 396         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 397         INTEL_CHV_IDS(&intel_cherryview_info)
 398
 399 static const struct pci_device_id pciidlist[] = {               /* aka */
 400         INTEL_PCI_IDS,
 401         {0, 0, 0}
 402 };
 403
 404 #if defined(CONFIG_DRM_I915_KMS)
 405 MODULE_DEVICE_TABLE(pci, pciidlist);
 406 #endif
 407
 408 void intel_detect_pch(struct drm_device *dev)
 409 {
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411         struct pci_dev *pch = NULL;
 412
 413         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 414          * (which really amounts to a PCH but no South Display).
 415          */
 416         if (INTEL_INFO(dev)->num_pipes == 0) {
 417                 dev_priv->pch_type = PCH_NOP;
 418                 return;
 419         }
 420
 421         /*
 422          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 423          * make graphics device passthrough work easy for VMM, that only
 424          * need to expose ISA bridge to let driver know the real hardware
 425          * underneath. This is a requirement from virtualization team.
 426          *
 427          * In some virtualized environments (e.g. XEN), there is irrelevant
 428          * ISA bridge in the system. To work reliably, we should scan trhough
 429          * all the ISA bridge devices and check for the first match, instead
 430          * of only checking the first one.
 431          */
 432         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 433                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 434                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 435                         dev_priv->pch_id = id;
 436
 437                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 438                                 dev_priv->pch_type = PCH_IBX;
 439                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 440                                 WARN_ON(!IS_GEN5(dev));
 441                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 442                                 dev_priv->pch_type = PCH_CPT;
 443                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 444                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 445                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 446                                 /* PantherPoint is CPT compatible */
 447                                 dev_priv->pch_type = PCH_CPT;
 448                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 449                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 450                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 451                                 dev_priv->pch_type = PCH_LPT;
 452                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 453                                 WARN_ON(!IS_HASWELL(dev));
 454                                 WARN_ON(IS_ULT(dev));
 455                         } else if (IS_BROADWELL(dev)) {
 456                                 dev_priv->pch_type = PCH_LPT;
 457                                 dev_priv->pch_id =
 458                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 459                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 460                                               "LynxPoint LP PCH\n");
 461                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 462                                 dev_priv->pch_type = PCH_LPT;
 463                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 464                                 WARN_ON(!IS_HASWELL(dev));
 465                                 WARN_ON(!IS_ULT(dev));
 466                         } else
 467                                 continue;
 468
 469                         break;
 470                 }
 471         }
 472         if (!pch)
 473                 DRM_DEBUG_KMS("No PCH found.\n");
 474
 475         pci_dev_put(pch);
 476 }
 477
 478 bool i915_semaphore_is_enabled(struct drm_device *dev)
 479 {
 480         if (INTEL_INFO(dev)->gen < 6)
 481                 return false;
 482
 483         if (i915.semaphores >= 0)
 484                 return i915.semaphores;
 485
 486         /* Until we get further testing... */
 487         if (IS_GEN8(dev))
 488                 return false;
 489
 490 #ifdef CONFIG_INTEL_IOMMU
 491         /* Enable semaphores on SNB when IO remapping is off */
 492         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 493                 return false;
 494 #endif
 495
 496         return true;
 497 }
 498
 499 static int i915_drm_freeze(struct drm_device *dev)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         struct drm_crtc *crtc;
 503         pci_power_t opregion_target_state;
 504
 505         intel_runtime_pm_get(dev_priv);
 506
 507         /* ignore lid events during suspend */
 508         mutex_lock(&dev_priv->modeset_restore_lock);
 509         dev_priv->modeset_restore = MODESET_SUSPENDED;
 510         mutex_unlock(&dev_priv->modeset_restore_lock);
 511
 512         /* We do a lot of poking in a lot of registers, make sure they work
 513          * properly. */
 514         intel_display_set_init_power(dev_priv, true);
 515
 516         drm_kms_helper_poll_disable(dev);
 517
 518         pci_save_state(dev->pdev);
 519
 520         /* If KMS is active, we do the leavevt stuff here */
 521         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 522                 int error;
 523
 524                 error = i915_gem_suspend(dev);
 525                 if (error) {
 526                         dev_err(&dev->pdev->dev,
 527                                 "GEM idle failed, resume might fail\n");
 528                         return error;
 529                 }
 530
 531                 drm_irq_uninstall(dev);
 532                 dev_priv->enable_hotplug_processing = false;
 533
 534                 intel_suspend_gt_powersave(dev);
 535
 536                 /*
 537                  * Disable CRTCs directly since we want to preserve sw state
 538                  * for _thaw.
 539                  */
 540                 drm_modeset_lock_all(dev);
 541                 for_each_crtc(dev, crtc) {
 542                         dev_priv->display.crtc_disable(crtc);
 543                 }
 544                 drm_modeset_unlock_all(dev);
 545
 546                 intel_modeset_suspend_hw(dev);
 547         }
 548
 549         i915_gem_suspend_gtt_mappings(dev);
 550
 551         i915_save_state(dev);
 552
 553         if (acpi_target_system_state() >= ACPI_STATE_S3)
 554                 opregion_target_state = PCI_D3cold;
 555         else
 556                 opregion_target_state = PCI_D1;
 557         intel_opregion_notify_adapter(dev, opregion_target_state);
 558
 559         intel_uncore_forcewake_reset(dev, false);
 560         intel_opregion_fini(dev);
 561
 562         console_lock();
 563         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 564         console_unlock();
 565
 566         dev_priv->suspend_count++;
 567
 568         intel_display_set_init_power(dev_priv, false);
 569
 570         return 0;
 571 }
 572
 573 int i915_suspend(struct drm_device *dev, pm_message_t state)
 574 {
 575         int error;
 576
 577         if (!dev || !dev->dev_private) {
 578                 DRM_ERROR("dev: %p\n", dev);
 579                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 580                 return -ENODEV;
 581         }
 582
 583         if (state.event == PM_EVENT_PRETHAW)
 584                 return 0;
 585
 586
 587         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 588                 return 0;
 589
 590         error = i915_drm_freeze(dev);
 591         if (error)
 592                 return error;
 593
 594         if (state.event == PM_EVENT_SUSPEND) {
 595                 /* Shut down the device */
 596                 pci_disable_device(dev->pdev);
 597                 pci_set_power_state(dev->pdev, PCI_D3hot);
 598         }
 599
 600         return 0;
 601 }
 602
 603 void intel_console_resume(struct work_struct *work)
 604 {
 605         struct drm_i915_private *dev_priv =
 606                 container_of(work, struct drm_i915_private,
 607                              console_resume_work);
 608         struct drm_device *dev = dev_priv->dev;
 609
 610         console_lock();
 611         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 612         console_unlock();
 613 }
 614
 615 static int i915_drm_thaw_early(struct drm_device *dev)
 616 {
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618
 619         intel_uncore_early_sanitize(dev);
 620         intel_uncore_sanitize(dev);
 621         intel_power_domains_init_hw(dev_priv);
 622
 623         return 0;
 624 }
 625
 626 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 627 {
 628         struct drm_i915_private *dev_priv = dev->dev_private;
 629
 630         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 631             restore_gtt_mappings) {
 632                 mutex_lock(&dev->struct_mutex);
 633                 i915_gem_restore_gtt_mappings(dev);
 634                 mutex_unlock(&dev->struct_mutex);
 635         }
 636
 637         i915_restore_state(dev);
 638         intel_opregion_setup(dev);
 639
 640         /* KMS EnterVT equivalent */
 641         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 642                 intel_init_pch_refclk(dev);
 643                 drm_mode_config_reset(dev);
 644
 645                 mutex_lock(&dev->struct_mutex);
 646                 if (i915_gem_init_hw(dev)) {
 647                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 648                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 649                 }
 650                 mutex_unlock(&dev->struct_mutex);
 651
 652                 /* We need working interrupts for modeset enabling ... */
 653                 drm_irq_install(dev, dev->pdev->irq);
 654
 655                 intel_modeset_init_hw(dev);
 656
 657                 drm_modeset_lock_all(dev);
 658                 intel_modeset_setup_hw_state(dev, true);
 659                 drm_modeset_unlock_all(dev);
 660
 661                 /*
 662                  * ... but also need to make sure that hotplug processing
 663                  * doesn't cause havoc. Like in the driver load code we don't
 664                  * bother with the tiny race here where we might loose hotplug
 665                  * notifications.
 666                  * */
 667                 intel_hpd_init(dev);
 668                 dev_priv->enable_hotplug_processing = true;
 669                 /* Config may have changed between suspend and resume */
 670                 drm_helper_hpd_irq_event(dev);
 671         }
 672
 673         intel_opregion_init(dev);
 674
 675         /*
 676          * The console lock can be pretty contented on resume due
 677          * to all the printk activity.  Try to keep it out of the hot
 678          * path of resume if possible.
 679          */
 680         if (console_trylock()) {
 681                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 682                 console_unlock();
 683         } else {
 684                 schedule_work(&dev_priv->console_resume_work);
 685         }
 686
 687         mutex_lock(&dev_priv->modeset_restore_lock);
 688         dev_priv->modeset_restore = MODESET_DONE;
 689         mutex_unlock(&dev_priv->modeset_restore_lock);
 690
 691         intel_opregion_notify_adapter(dev, PCI_D0);
 692
 693         intel_runtime_pm_put(dev_priv);
 694         return 0;
 695 }
 696
 697 static int i915_drm_thaw(struct drm_device *dev)
 698 {
 699         if (drm_core_check_feature(dev, DRIVER_MODESET))
 700                 i915_check_and_clear_faults(dev);
 701
 702         return __i915_drm_thaw(dev, true);
 703 }
 704
 705 static int i915_resume_early(struct drm_device *dev)
 706 {
 707         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 708                 return 0;
 709
 710         /*
 711          * We have a resume ordering issue with the snd-hda driver also
 712          * requiring our device to be power up. Due to the lack of a
 713          * parent/child relationship we currently solve this with an early
 714          * resume hook.
 715          *
 716          * FIXME: This should be solved with a special hdmi sink device or
 717          * similar so that power domains can be employed.
 718          */
 719         if (pci_enable_device(dev->pdev))
 720                 return -EIO;
 721
 722         pci_set_master(dev->pdev);
 723
 724         return i915_drm_thaw_early(dev);
 725 }
 726
 727 int i915_resume(struct drm_device *dev)
 728 {
 729         struct drm_i915_private *dev_priv = dev->dev_private;
 730         int ret;
 731
 732         /*
 733          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 734          * earlier) need to restore the GTT mappings since the BIOS might clear
 735          * all our scratch PTEs.
 736          */
 737         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 738         if (ret)
 739                 return ret;
 740
 741         drm_kms_helper_poll_enable(dev);
 742         return 0;
 743 }
 744
 745 static int i915_resume_legacy(struct drm_device *dev)
 746 {
 747         i915_resume_early(dev);
 748         i915_resume(dev);
 749
 750         return 0;
 751 }
 752
 753 /**
 754  * i915_reset - reset chip after a hang
 755  * @dev: drm device to reset
 756  *
 757  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 758  * reset or otherwise an error code.
 759  *
 760  * Procedure is fairly simple:
 761  *   - reset the chip using the reset reg
 762  *   - re-init context state
 763  *   - re-init hardware status page
 764  *   - re-init ring buffer
 765  *   - re-init interrupt state
 766  *   - re-init display
 767  */
 768 int i915_reset(struct drm_device *dev)
 769 {
 770         struct drm_i915_private *dev_priv = dev->dev_private;
 771         bool simulated;
 772         int ret;
 773
 774         if (!i915.reset)
 775                 return 0;
 776
 777         mutex_lock(&dev->struct_mutex);
 778
 779         i915_gem_reset(dev);
 780
 781         simulated = dev_priv->gpu_error.stop_rings != 0;
 782
 783         ret = intel_gpu_reset(dev);
 784
 785         /* Also reset the gpu hangman. */
 786         if (simulated) {
 787                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 788                 dev_priv->gpu_error.stop_rings = 0;
 789                 if (ret == -ENODEV) {
 790                         DRM_INFO("Reset not implemented, but ignoring "
 791                                  "error for simulated gpu hangs\n");
 792                         ret = 0;
 793                 }
 794         }
 795
 796         if (ret) {
 797                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 798                 mutex_unlock(&dev->struct_mutex);
 799                 return ret;
 800         }
 801
 802         /* Ok, now get things going again... */
 803
 804         /*
 805          * Everything depends on having the GTT running, so we need to start
 806          * there.  Fortunately we don't need to do this unless we reset the
 807          * chip at a PCI level.
 808          *
 809          * Next we need to restore the context, but we don't use those
 810          * yet either...
 811          *
 812          * Ring buffer needs to be re-initialized in the KMS case, or if X
 813          * was running at the time of the reset (i.e. we weren't VT
 814          * switched away).
 815          */
 816         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 817                         !dev_priv->ums.mm_suspended) {
 818                 dev_priv->ums.mm_suspended = 0;
 819
 820                 ret = i915_gem_init_hw(dev);
 821                 mutex_unlock(&dev->struct_mutex);
 822                 if (ret) {
 823                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 824                         return ret;
 825                 }
 826
 827                 /*
 828                  * FIXME: This races pretty badly against concurrent holders of
 829                  * ring interrupts. This is possible since we've started to drop
 830                  * dev->struct_mutex in select places when waiting for the gpu.
 831                  */
 832
 833                 /*
 834                  * rps/rc6 re-init is necessary to restore state lost after the
 835                  * reset and the re-install of gt irqs. Skip for ironlake per
 836                  * previous concerns that it doesn't respond well to some forms
 837                  * of re-init after reset.
 838                  */
 839                 if (INTEL_INFO(dev)->gen > 5)
 840                         intel_reset_gt_powersave(dev);
 841
 842                 intel_hpd_init(dev);
 843         } else {
 844                 mutex_unlock(&dev->struct_mutex);
 845         }
 846
 847         return 0;
 848 }
 849
 850 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 851 {
 852         struct intel_device_info *intel_info =
 853                 (struct intel_device_info *) ent->driver_data;
 854
 855         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 856                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 857                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 858                 return -ENODEV;
 859         }
 860
 861         /* Only bind to function 0 of the device. Early generations
 862          * used function 1 as a placeholder for multi-head. This causes
 863          * us confusion instead, especially on the systems where both
 864          * functions have the same PCI-ID!
 865          */
 866         if (PCI_FUNC(pdev->devfn))
 867                 return -ENODEV;
 868
 869         driver.driver_features &= ~(DRIVER_USE_AGP);
 870
 871         return drm_get_pci_dev(pdev, ent, &driver);
 872 }
 873
 874 static void
 875 i915_pci_remove(struct pci_dev *pdev)
 876 {
 877         struct drm_device *dev = pci_get_drvdata(pdev);
 878
 879         drm_put_dev(dev);
 880 }
 881
 882 static int i915_pm_suspend(struct device *dev)
 883 {
 884         struct pci_dev *pdev = to_pci_dev(dev);
 885         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 886
 887         if (!drm_dev || !drm_dev->dev_private) {
 888                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 889                 return -ENODEV;
 890         }
 891
 892         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 893                 return 0;
 894
 895         return i915_drm_freeze(drm_dev);
 896 }
 897
 898 static int i915_pm_suspend_late(struct device *dev)
 899 {
 900         struct pci_dev *pdev = to_pci_dev(dev);
 901         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 902
 903         /*
 904          * We have a suspedn ordering issue with the snd-hda driver also
 905          * requiring our device to be power up. Due to the lack of a
 906          * parent/child relationship we currently solve this with an late
 907          * suspend hook.
 908          *
 909          * FIXME: This should be solved with a special hdmi sink device or
 910          * similar so that power domains can be employed.
 911          */
 912         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 913                 return 0;
 914
 915         pci_disable_device(pdev);
 916         pci_set_power_state(pdev, PCI_D3hot);
 917
 918         return 0;
 919 }
 920
 921 static int i915_pm_resume_early(struct device *dev)
 922 {
 923         struct pci_dev *pdev = to_pci_dev(dev);
 924         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 925
 926         return i915_resume_early(drm_dev);
 927 }
 928
 929 static int i915_pm_resume(struct device *dev)
 930 {
 931         struct pci_dev *pdev = to_pci_dev(dev);
 932         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 933
 934         return i915_resume(drm_dev);
 935 }
 936
 937 static int i915_pm_freeze(struct device *dev)
 938 {
 939         struct pci_dev *pdev = to_pci_dev(dev);
 940         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 941
 942         if (!drm_dev || !drm_dev->dev_private) {
 943                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 944                 return -ENODEV;
 945         }
 946
 947         return i915_drm_freeze(drm_dev);
 948 }
 949
 950 static int i915_pm_thaw_early(struct device *dev)
 951 {
 952         struct pci_dev *pdev = to_pci_dev(dev);
 953         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 954
 955         return i915_drm_thaw_early(drm_dev);
 956 }
 957
 958 static int i915_pm_thaw(struct device *dev)
 959 {
 960         struct pci_dev *pdev = to_pci_dev(dev);
 961         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 962
 963         return i915_drm_thaw(drm_dev);
 964 }
 965
 966 static int i915_pm_poweroff(struct device *dev)
 967 {
 968         struct pci_dev *pdev = to_pci_dev(dev);
 969         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 970
 971         return i915_drm_freeze(drm_dev);
 972 }
 973
 974 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 975 {
 976         hsw_enable_pc8(dev_priv);
 977
 978         return 0;
 979 }
 980
 981 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
 982 {
 983         struct drm_device *dev = dev_priv->dev;
 984
 985         intel_init_pch_refclk(dev);
 986
 987         return 0;
 988 }
 989
 990 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
 991 {
 992         hsw_disable_pc8(dev_priv);
 993
 994         return 0;
 995 }
 996
 997 /*
 998  * Save all Gunit registers that may be lost after a D3 and a subsequent
 999  * S0i[R123] transition. The list of registers needing a save/restore is
1000  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1001  * registers in the following way:
1002  * - Driver: saved/restored by the driver
1003  * - Punit : saved/restored by the Punit firmware
1004  * - No, w/o marking: no need to save/restore, since the register is R/O or
1005  *                    used internally by the HW in a way that doesn't depend
1006  *                    keeping the content across a suspend/resume.
1007  * - Debug : used for debugging
1008  *
1009  * We save/restore all registers marked with 'Driver', with the following
1010  * exceptions:
1011  * - Registers out of use, including also registers marked with 'Debug'.
1012  *   These have no effect on the driver's operation, so we don't save/restore
1013  *   them to reduce the overhead.
1014  * - Registers that are fully setup by an initialization function called from
1015  *   the resume path. For example many clock gating and RPS/RC6 registers.
1016  * - Registers that provide the right functionality with their reset defaults.
1017  *
1018  * TODO: Except for registers that based on the above 3 criteria can be safely
1019  * ignored, we save/restore all others, practically treating the HW context as
1020  * a black-box for the driver. Further investigation is needed to reduce the
1021  * saved/restored registers even further, by following the same 3 criteria.
1022  */
1023 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1024 {
1025         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1026         int i;
1027
1028         /* GAM 0x4000-0x4770 */
1029         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1030         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1031         s->arb_mode             = I915_READ(ARB_MODE);
1032         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1033         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1034
1035         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1036                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1037
1038         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1039         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1040
1041         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1042         s->ecochk               = I915_READ(GAM_ECOCHK);
1043         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1044         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1045
1046         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1047
1048         /* MBC 0x9024-0x91D0, 0x8500 */
1049         s->g3dctl               = I915_READ(VLV_G3DCTL);
1050         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1051         s->mbctl                = I915_READ(GEN6_MBCTL);
1052
1053         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1054         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1055         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1056         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1057         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1058         s->rstctl               = I915_READ(GEN6_RSTCTL);
1059         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1060
1061         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1062         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1063         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1064         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1065         s->ecobus               = I915_READ(ECOBUS);
1066         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1067         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1068         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1069         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1070         s->rcedata              = I915_READ(VLV_RCEDATA);
1071         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1072
1073         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1074         s->gt_imr               = I915_READ(GTIMR);
1075         s->gt_ier               = I915_READ(GTIER);
1076         s->pm_imr               = I915_READ(GEN6_PMIMR);
1077         s->pm_ier               = I915_READ(GEN6_PMIER);
1078
1079         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1080                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1081
1082         /* GT SA CZ domain, 0x100000-0x138124 */
1083         s->tilectl              = I915_READ(TILECTL);
1084         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1085         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1086         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1087         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1088
1089         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1090         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1091         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1092         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1093
1094         /*
1095          * Not saving any of:
1096          * DFT,         0x9800-0x9EC0
1097          * SARB,        0xB000-0xB1FC
1098          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1099          * PCI CFG
1100          */
1101 }
1102
1103 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1104 {
1105         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1106         u32 val;
1107         int i;
1108
1109         /* GAM 0x4000-0x4770 */
1110         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1111         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1112         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1113         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1114         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1115
1116         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1117                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1118
1119         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1120         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1121
1122         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1123         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1124         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1125         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1126
1127         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1128
1129         /* MBC 0x9024-0x91D0, 0x8500 */
1130         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1131         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1132         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1133
1134         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1135         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1136         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1137         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1138         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1139         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1140         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1141
1142         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1143         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1144         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1145         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1146         I915_WRITE(ECOBUS,              s->ecobus);
1147         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1148         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1149         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1150         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1151         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1152         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1153
1154         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1155         I915_WRITE(GTIMR,               s->gt_imr);
1156         I915_WRITE(GTIER,               s->gt_ier);
1157         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1158         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1159
1160         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1161                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1162
1163         /* GT SA CZ domain, 0x100000-0x138124 */
1164         I915_WRITE(TILECTL,                     s->tilectl);
1165         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1166         /*
1167          * Preserve the GT allow wake and GFX force clock bit, they are not
1168          * be restored, as they are used to control the s0ix suspend/resume
1169          * sequence by the caller.
1170          */
1171         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1172         val &= VLV_GTLC_ALLOWWAKEREQ;
1173         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1174         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1175
1176         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1177         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1178         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1179         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1180
1181         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1182
1183         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1184         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1185         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1186         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1187 }
1188
1189 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1190 {
1191         u32 val;
1192         int err;
1193
1194         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1195         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1196
1197 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1198         /* Wait for a previous force-off to settle */
1199         if (force_on) {
1200                 err = wait_for(!COND, 20);
1201                 if (err) {
1202                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1203                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1204                         return err;
1205                 }
1206         }
1207
1208         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1209         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1210         if (force_on)
1211                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1212         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1213
1214         if (!force_on)
1215                 return 0;
1216
1217         err = wait_for(COND, 20);
1218         if (err)
1219                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1220                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1221
1222         return err;
1223 #undef COND
1224 }
1225
1226 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1227 {
1228         u32 val;
1229         int err = 0;
1230
1231         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1232         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1233         if (allow)
1234                 val |= VLV_GTLC_ALLOWWAKEREQ;
1235         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1236         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1237
1238 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1239               allow)
1240         err = wait_for(COND, 1);
1241         if (err)
1242                 DRM_ERROR("timeout disabling GT waking\n");
1243         return err;
1244 #undef COND
1245 }
1246
1247 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1248                                  bool wait_for_on)
1249 {
1250         u32 mask;
1251         u32 val;
1252         int err;
1253
1254         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1255         val = wait_for_on ? mask : 0;
1256 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1257         if (COND)
1258                 return 0;
1259
1260         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1261                         wait_for_on ? "on" : "off",
1262                         I915_READ(VLV_GTLC_PW_STATUS));
1263
1264         /*
1265          * RC6 transitioning can be delayed up to 2 msec (see
1266          * valleyview_enable_rps), use 3 msec for safety.
1267          */
1268         err = wait_for(COND, 3);
1269         if (err)
1270                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1271                           wait_for_on ? "on" : "off");
1272
1273         return err;
1274 #undef COND
1275 }
1276
1277 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1278 {
1279         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1280                 return;
1281
1282         DRM_ERROR("GT register access while GT waking disabled\n");
1283         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1284 }
1285
1286 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1287 {
1288         u32 mask;
1289         int err;
1290
1291         /*
1292          * Bspec defines the following GT well on flags as debug only, so
1293          * don't treat them as hard failures.
1294          */
1295         (void)vlv_wait_for_gt_wells(dev_priv, false);
1296
1297         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1298         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1299
1300         vlv_check_no_gt_access(dev_priv);
1301
1302         err = vlv_force_gfx_clock(dev_priv, true);
1303         if (err)
1304                 goto err1;
1305
1306         err = vlv_allow_gt_wake(dev_priv, false);
1307         if (err)
1308                 goto err2;
1309         vlv_save_gunit_s0ix_state(dev_priv);
1310
1311         err = vlv_force_gfx_clock(dev_priv, false);
1312         if (err)
1313                 goto err2;
1314
1315         return 0;
1316
1317 err2:
1318         /* For safety always re-enable waking and disable gfx clock forcing */
1319         vlv_allow_gt_wake(dev_priv, true);
1320 err1:
1321         vlv_force_gfx_clock(dev_priv, false);
1322
1323         return err;
1324 }
1325
1326 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1327 {
1328         struct drm_device *dev = dev_priv->dev;
1329         int err;
1330         int ret;
1331
1332         /*
1333          * If any of the steps fail just try to continue, that's the best we
1334          * can do at this point. Return the first error code (which will also
1335          * leave RPM permanently disabled).
1336          */
1337         ret = vlv_force_gfx_clock(dev_priv, true);
1338
1339         vlv_restore_gunit_s0ix_state(dev_priv);
1340
1341         err = vlv_allow_gt_wake(dev_priv, true);
1342         if (!ret)
1343                 ret = err;
1344
1345         err = vlv_force_gfx_clock(dev_priv, false);
1346         if (!ret)
1347                 ret = err;
1348
1349         vlv_check_no_gt_access(dev_priv);
1350
1351         intel_init_clock_gating(dev);
1352         i915_gem_restore_fences(dev);
1353
1354         return ret;
1355 }
1356
1357 static int intel_runtime_suspend(struct device *device)
1358 {
1359         struct pci_dev *pdev = to_pci_dev(device);
1360         struct drm_device *dev = pci_get_drvdata(pdev);
1361         struct drm_i915_private *dev_priv = dev->dev_private;
1362         int ret;
1363
1364         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1365                 return -ENODEV;
1366
1367         WARN_ON(!HAS_RUNTIME_PM(dev));
1368         assert_force_wake_inactive(dev_priv);
1369
1370         DRM_DEBUG_KMS("Suspending device\n");
1371
1372         /*
1373          * We could deadlock here in case another thread holding struct_mutex
1374          * calls RPM suspend concurrently, since the RPM suspend will wait
1375          * first for this RPM suspend to finish. In this case the concurrent
1376          * RPM resume will be followed by its RPM suspend counterpart. Still
1377          * for consistency return -EAGAIN, which will reschedule this suspend.
1378          */
1379         if (!mutex_trylock(&dev->struct_mutex)) {
1380                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1381                 /*
1382                  * Bump the expiration timestamp, otherwise the suspend won't
1383                  * be rescheduled.
1384                  */
1385                 pm_runtime_mark_last_busy(device);
1386
1387                 return -EAGAIN;
1388         }
1389         /*
1390          * We are safe here against re-faults, since the fault handler takes
1391          * an RPM reference.
1392          */
1393         i915_gem_release_all_mmaps(dev_priv);
1394         mutex_unlock(&dev->struct_mutex);
1395
1396         /*
1397          * rps.work can't be rearmed here, since we get here only after making
1398          * sure the GPU is idle and the RPS freq is set to the minimum. See
1399          * intel_mark_idle().
1400          */
1401         cancel_work_sync(&dev_priv->rps.work);
1402         intel_runtime_pm_disable_interrupts(dev);
1403
1404         if (IS_GEN6(dev)) {
1405                 ret = 0;
1406         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1407                 ret = hsw_runtime_suspend(dev_priv);
1408         } else if (IS_VALLEYVIEW(dev)) {
1409                 ret = vlv_runtime_suspend(dev_priv);
1410         } else {
1411                 ret = -ENODEV;
1412                 WARN_ON(1);
1413         }
1414
1415         if (ret) {
1416                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1417                 intel_runtime_pm_restore_interrupts(dev);
1418
1419                 return ret;
1420         }
1421
1422         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1423         dev_priv->pm.suspended = true;
1424
1425         /*
1426          * current versions of firmware which depend on this opregion
1427          * notification have repurposed the D1 definition to mean
1428          * "runtime suspended" vs. what you would normally expect (D3)
1429          * to distinguish it from notifications that might be sent
1430          * via the suspend path.
1431          */
1432         intel_opregion_notify_adapter(dev, PCI_D1);
1433
1434         DRM_DEBUG_KMS("Device suspended\n");
1435         return 0;
1436 }
1437
1438 static int intel_runtime_resume(struct device *device)
1439 {
1440         struct pci_dev *pdev = to_pci_dev(device);
1441         struct drm_device *dev = pci_get_drvdata(pdev);
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int ret;
1444
1445         WARN_ON(!HAS_RUNTIME_PM(dev));
1446
1447         DRM_DEBUG_KMS("Resuming device\n");
1448
1449         intel_opregion_notify_adapter(dev, PCI_D0);
1450         dev_priv->pm.suspended = false;
1451
1452         if (IS_GEN6(dev)) {
1453                 ret = snb_runtime_resume(dev_priv);
1454         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1455                 ret = hsw_runtime_resume(dev_priv);
1456         } else if (IS_VALLEYVIEW(dev)) {
1457                 ret = vlv_runtime_resume(dev_priv);
1458         } else {
1459                 WARN_ON(1);
1460                 ret = -ENODEV;
1461         }
1462
1463         /*
1464          * No point of rolling back things in case of an error, as the best
1465          * we can do is to hope that things will still work (and disable RPM).
1466          */
1467         i915_gem_init_swizzling(dev);
1468         gen6_update_ring_freq(dev);
1469
1470         intel_runtime_pm_restore_interrupts(dev);
1471         intel_reset_gt_powersave(dev);
1472
1473         if (ret)
1474                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1475         else
1476                 DRM_DEBUG_KMS("Device resumed\n");
1477
1478         return ret;
1479 }
1480
1481 static const struct dev_pm_ops i915_pm_ops = {
1482         .suspend = i915_pm_suspend,
1483         .suspend_late = i915_pm_suspend_late,
1484         .resume_early = i915_pm_resume_early,
1485         .resume = i915_pm_resume,
1486         .freeze = i915_pm_freeze,
1487         .thaw_early = i915_pm_thaw_early,
1488         .thaw = i915_pm_thaw,
1489         .poweroff = i915_pm_poweroff,
1490         .restore_early = i915_pm_resume_early,
1491         .restore = i915_pm_resume,
1492         .runtime_suspend = intel_runtime_suspend,
1493         .runtime_resume = intel_runtime_resume,
1494 };
1495
1496 static const struct vm_operations_struct i915_gem_vm_ops = {
1497         .fault = i915_gem_fault,
1498         .open = drm_gem_vm_open,
1499         .close = drm_gem_vm_close,
1500 };
1501
1502 static const struct file_operations i915_driver_fops = {
1503         .owner = THIS_MODULE,
1504         .open = drm_open,
1505         .release = drm_release,
1506         .unlocked_ioctl = drm_ioctl,
1507         .mmap = drm_gem_mmap,
1508         .poll = drm_poll,
1509         .read = drm_read,
1510 #ifdef CONFIG_COMPAT
1511         .compat_ioctl = i915_compat_ioctl,
1512 #endif
1513         .llseek = noop_llseek,
1514 };
1515
1516 static struct drm_driver driver = {
1517         /* Don't use MTRRs here; the Xserver or userspace app should
1518          * deal with them for Intel hardware.
1519          */
1520         .driver_features =
1521             DRIVER_USE_AGP |
1522             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1523             DRIVER_RENDER,
1524         .load = i915_driver_load,
1525         .unload = i915_driver_unload,
1526         .open = i915_driver_open,
1527         .lastclose = i915_driver_lastclose,
1528         .preclose = i915_driver_preclose,
1529         .postclose = i915_driver_postclose,
1530
1531         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1532         .suspend = i915_suspend,
1533         .resume = i915_resume_legacy,
1534
1535         .device_is_agp = i915_driver_device_is_agp,
1536         .master_create = i915_master_create,
1537         .master_destroy = i915_master_destroy,
1538 #if defined(CONFIG_DEBUG_FS)
1539         .debugfs_init = i915_debugfs_init,
1540         .debugfs_cleanup = i915_debugfs_cleanup,
1541 #endif
1542         .gem_free_object = i915_gem_free_object,
1543         .gem_vm_ops = &i915_gem_vm_ops,
1544
1545         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1546         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1547         .gem_prime_export = i915_gem_prime_export,
1548         .gem_prime_import = i915_gem_prime_import,
1549
1550         .dumb_create = i915_gem_dumb_create,
1551         .dumb_map_offset = i915_gem_mmap_gtt,
1552         .dumb_destroy = drm_gem_dumb_destroy,
1553         .ioctls = i915_ioctls,
1554         .fops = &i915_driver_fops,
1555         .name = DRIVER_NAME,
1556         .desc = DRIVER_DESC,
1557         .date = DRIVER_DATE,
1558         .major = DRIVER_MAJOR,
1559         .minor = DRIVER_MINOR,
1560         .patchlevel = DRIVER_PATCHLEVEL,
1561 };
1562
1563 static struct pci_driver i915_pci_driver = {
1564         .name = DRIVER_NAME,
1565         .id_table = pciidlist,
1566         .probe = i915_pci_probe,
1567         .remove = i915_pci_remove,
1568         .driver.pm = &i915_pm_ops,
1569 };
1570
1571 static int __init i915_init(void)
1572 {
1573         driver.num_ioctls = i915_max_ioctl;
1574
1575         /*
1576          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1577          * explicitly disabled with the module pararmeter.
1578          *
1579          * Otherwise, just follow the parameter (defaulting to off).
1580          *
1581          * Allow optional vga_text_mode_force boot option to override
1582          * the default behavior.
1583          */
1584 #if defined(CONFIG_DRM_I915_KMS)
1585         if (i915.modeset != 0)
1586                 driver.driver_features |= DRIVER_MODESET;
1587 #endif
1588         if (i915.modeset == 1)
1589                 driver.driver_features |= DRIVER_MODESET;
1590
1591 #ifdef CONFIG_VGA_CONSOLE
1592         if (vgacon_text_force() && i915.modeset == -1)
1593                 driver.driver_features &= ~DRIVER_MODESET;
1594 #endif
1595
1596         if (!(driver.driver_features & DRIVER_MODESET)) {
1597                 driver.get_vblank_timestamp = NULL;
1598 #ifndef CONFIG_DRM_I915_UMS
1599                 /* Silently fail loading to not upset userspace. */
1600                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1601                 return 0;
1602 #endif
1603         }
1604
1605         return drm_pci_init(&driver, &i915_pci_driver);
1606 }
1607
1608 static void __exit i915_exit(void)
1609 {
1610 #ifndef CONFIG_DRM_I915_UMS
1611         if (!(driver.driver_features & DRIVER_MODESET))
1612                 return; /* Never loaded a driver. */
1613 #endif
1614
1615         drm_pci_exit(&driver, &i915_pci_driver);
1616 }
1617
1618 module_init(i915_init);
1619 module_exit(i915_exit);
1620
1621 MODULE_AUTHOR(DRIVER_AUTHOR);
1622 MODULE_DESCRIPTION(DRIVER_DESC);
1623 MODULE_LICENSE("GPL and additional rights");