drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 int i915_panel_ignore_lid = 0;
  47 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  48
  49 unsigned int i915_powersave = 1;
  50 module_param_named(powersave, i915_powersave, int, 0600);
  51
  52 unsigned int i915_semaphores = 1;
  53 module_param_named(semaphores, i915_semaphores, int, 0600);
  54
  55 unsigned int i915_enable_rc6 = 0;
  56 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  57
  58 unsigned int i915_lvds_downclock = 0;
  59 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  60
  61 unsigned int i915_panel_use_ssc = 1;
  62 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  63
  64 int i915_vbt_sdvo_panel_type = -1;
  65 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  66
  67 static bool i915_try_reset = true;
  68 module_param_named(reset, i915_try_reset, bool, 0600);
  69
  70 static struct drm_driver driver;
  71 extern int intel_agp_enabled;
  72
  73 #define INTEL_VGA_DEVICE(id, info) {            \
  74         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  75         .class_mask = 0xff0000,                 \
  76         .vendor = 0x8086,                       \
  77         .device = id,                           \
  78         .subvendor = PCI_ANY_ID,                \
  79         .subdevice = PCI_ANY_ID,                \
  80         .driver_data = (unsigned long) info }
  81
  82 static const struct intel_device_info intel_i830_info = {
  83         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  84         .has_overlay = 1, .overlay_needs_physical = 1,
  85 };
  86
  87 static const struct intel_device_info intel_845g_info = {
  88         .gen = 2,
  89         .has_overlay = 1, .overlay_needs_physical = 1,
  90 };
  91
  92 static const struct intel_device_info intel_i85x_info = {
  93         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  94         .cursor_needs_physical = 1,
  95         .has_overlay = 1, .overlay_needs_physical = 1,
  96 };
  97
  98 static const struct intel_device_info intel_i865g_info = {
  99         .gen = 2,
 100         .has_overlay = 1, .overlay_needs_physical = 1,
 101 };
 102
 103 static const struct intel_device_info intel_i915g_info = {
 104         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 105         .has_overlay = 1, .overlay_needs_physical = 1,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112 };
 113 static const struct intel_device_info intel_i945g_info = {
 114         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 115         .has_overlay = 1, .overlay_needs_physical = 1,
 116 };
 117 static const struct intel_device_info intel_i945gm_info = {
 118         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 119         .has_hotplug = 1, .cursor_needs_physical = 1,
 120         .has_overlay = 1, .overlay_needs_physical = 1,
 121         .supports_tv = 1,
 122 };
 123
 124 static const struct intel_device_info intel_i965g_info = {
 125         .gen = 4, .is_broadwater = 1,
 126         .has_hotplug = 1,
 127         .has_overlay = 1,
 128 };
 129
 130 static const struct intel_device_info intel_i965gm_info = {
 131         .gen = 4, .is_crestline = 1,
 132         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 133         .has_overlay = 1,
 134         .supports_tv = 1,
 135 };
 136
 137 static const struct intel_device_info intel_g33_info = {
 138         .gen = 3, .is_g33 = 1,
 139         .need_gfx_hws = 1, .has_hotplug = 1,
 140         .has_overlay = 1,
 141 };
 142
 143 static const struct intel_device_info intel_g45_info = {
 144         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 145         .has_pipe_cxsr = 1, .has_hotplug = 1,
 146         .has_bsd_ring = 1,
 147 };
 148
 149 static const struct intel_device_info intel_gm45_info = {
 150         .gen = 4, .is_g4x = 1,
 151         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 152         .has_pipe_cxsr = 1, .has_hotplug = 1,
 153         .supports_tv = 1,
 154         .has_bsd_ring = 1,
 155 };
 156
 157 static const struct intel_device_info intel_pineview_info = {
 158         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 159         .need_gfx_hws = 1, .has_hotplug = 1,
 160         .has_overlay = 1,
 161 };
 162
 163 static const struct intel_device_info intel_ironlake_d_info = {
 164         .gen = 5,
 165         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .has_bsd_ring = 1,
 167 };
 168
 169 static const struct intel_device_info intel_ironlake_m_info = {
 170         .gen = 5, .is_mobile = 1,
 171         .need_gfx_hws = 1, .has_hotplug = 1,
 172         .has_fbc = 0, /* disabled due to buggy hardware */
 173         .has_bsd_ring = 1,
 174 };
 175
 176 static const struct intel_device_info intel_sandybridge_d_info = {
 177         .gen = 6,
 178         .need_gfx_hws = 1, .has_hotplug = 1,
 179         .has_bsd_ring = 1,
 180         .has_blt_ring = 1,
 181 };
 182
 183 static const struct intel_device_info intel_sandybridge_m_info = {
 184         .gen = 6, .is_mobile = 1,
 185         .need_gfx_hws = 1, .has_hotplug = 1,
 186         .has_fbc = 1,
 187         .has_bsd_ring = 1,
 188         .has_blt_ring = 1,
 189 };
 190
 191 static const struct intel_device_info intel_ivybridge_d_info = {
 192         .is_ivybridge = 1, .gen = 7,
 193         .need_gfx_hws = 1, .has_hotplug = 1,
 194         .has_bsd_ring = 1,
 195         .has_blt_ring = 1,
 196 };
 197
 198 static const struct intel_device_info intel_ivybridge_m_info = {
 199         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 200         .need_gfx_hws = 1, .has_hotplug = 1,
 201         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 202         .has_bsd_ring = 1,
 203         .has_blt_ring = 1,
 204 };
 205
 206 static const struct pci_device_id pciidlist[] = {               /* aka */
 207         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 208         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 209         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 210         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 211         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 212         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 213         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 214         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 215         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 216         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 217         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 218         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 219         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 220         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 221         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 222         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 223         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 224         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 225         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 226         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 227         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 228         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 229         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 230         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 231         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 232         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 233         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 234         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 235         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 236         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 237         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 238         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 239         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 240         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 241         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 242         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 243         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 244         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 245         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 246         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 247         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 248         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 249         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 250         {0, 0, 0}
 251 };
 252
 253 #if defined(CONFIG_DRM_I915_KMS)
 254 MODULE_DEVICE_TABLE(pci, pciidlist);
 255 #endif
 256
 257 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 258 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 259 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 260 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 261
 262 void intel_detect_pch (struct drm_device *dev)
 263 {
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         struct pci_dev *pch;
 266
 267         /*
 268          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 269          * make graphics device passthrough work easy for VMM, that only
 270          * need to expose ISA bridge to let driver know the real hardware
 271          * underneath. This is a requirement from virtualization team.
 272          */
 273         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 274         if (pch) {
 275                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 276                         int id;
 277                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 278
 279                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 280                                 dev_priv->pch_type = PCH_IBX;
 281                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 282                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 283                                 dev_priv->pch_type = PCH_CPT;
 284                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 285                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 286                                 /* PantherPoint is CPT compatible */
 287                                 dev_priv->pch_type = PCH_CPT;
 288                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 289                         }
 290                 }
 291                 pci_dev_put(pch);
 292         }
 293 }
 294
 295 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 296 {
 297         int count;
 298
 299         count = 0;
 300         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 301                 udelay(10);
 302
 303         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 304         POSTING_READ(FORCEWAKE);
 305
 306         count = 0;
 307         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 308                 udelay(10);
 309 }
 310
 311 /*
 312  * Generally this is called implicitly by the register read function. However,
 313  * if some sequence requires the GT to not power down then this function should
 314  * be called at the beginning of the sequence followed by a call to
 315  * gen6_gt_force_wake_put() at the end of the sequence.
 316  */
 317 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 318 {
 319         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 320
 321         /* Forcewake is atomic in case we get in here without the lock */
 322         if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
 323                 __gen6_gt_force_wake_get(dev_priv);
 324 }
 325
 326 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 327 {
 328         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 329         POSTING_READ(FORCEWAKE);
 330 }
 331
 332 /*
 333  * see gen6_gt_force_wake_get()
 334  */
 335 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 336 {
 337         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 338
 339         if (atomic_dec_and_test(&dev_priv->forcewake_count))
 340                 __gen6_gt_force_wake_put(dev_priv);
 341 }
 342
 343 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 344 {
 345         int loop = 500;
 346         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 347         while (fifo < 20 && loop--) {
 348                 udelay(10);
 349                 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 350         }
 351 }
 352
 353 static int i915_drm_freeze(struct drm_device *dev)
 354 {
 355         struct drm_i915_private *dev_priv = dev->dev_private;
 356
 357         drm_kms_helper_poll_disable(dev);
 358
 359         pci_save_state(dev->pdev);
 360
 361         /* If KMS is active, we do the leavevt stuff here */
 362         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 363                 int error = i915_gem_idle(dev);
 364                 if (error) {
 365                         dev_err(&dev->pdev->dev,
 366                                 "GEM idle failed, resume might fail\n");
 367                         return error;
 368                 }
 369                 drm_irq_uninstall(dev);
 370         }
 371
 372         i915_save_state(dev);
 373
 374         intel_opregion_fini(dev);
 375
 376         /* Modeset on resume, not lid events */
 377         dev_priv->modeset_on_lid = 0;
 378
 379         return 0;
 380 }
 381
 382 int i915_suspend(struct drm_device *dev, pm_message_t state)
 383 {
 384         int error;
 385
 386         if (!dev || !dev->dev_private) {
 387                 DRM_ERROR("dev: %p\n", dev);
 388                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 389                 return -ENODEV;
 390         }
 391
 392         if (state.event == PM_EVENT_PRETHAW)
 393                 return 0;
 394
 395
 396         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 397                 return 0;
 398
 399         error = i915_drm_freeze(dev);
 400         if (error)
 401                 return error;
 402
 403         if (state.event == PM_EVENT_SUSPEND) {
 404                 /* Shut down the device */
 405                 pci_disable_device(dev->pdev);
 406                 pci_set_power_state(dev->pdev, PCI_D3hot);
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int i915_drm_thaw(struct drm_device *dev)
 413 {
 414         struct drm_i915_private *dev_priv = dev->dev_private;
 415         int error = 0;
 416
 417         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 418                 mutex_lock(&dev->struct_mutex);
 419                 i915_gem_restore_gtt_mappings(dev);
 420                 mutex_unlock(&dev->struct_mutex);
 421         }
 422
 423         i915_restore_state(dev);
 424         intel_opregion_setup(dev);
 425
 426         /* KMS EnterVT equivalent */
 427         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 428                 mutex_lock(&dev->struct_mutex);
 429                 dev_priv->mm.suspended = 0;
 430
 431                 error = i915_gem_init_ringbuffer(dev);
 432                 mutex_unlock(&dev->struct_mutex);
 433
 434                 drm_mode_config_reset(dev);
 435                 drm_irq_install(dev);
 436
 437                 /* Resume the modeset for every activated CRTC */
 438                 drm_helper_resume_force_mode(dev);
 439
 440                 if (IS_IRONLAKE_M(dev))
 441                         ironlake_enable_rc6(dev);
 442         }
 443
 444         intel_opregion_init(dev);
 445
 446         dev_priv->modeset_on_lid = 0;
 447
 448         return error;
 449 }
 450
 451 int i915_resume(struct drm_device *dev)
 452 {
 453         int ret;
 454
 455         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 456                 return 0;
 457
 458         if (pci_enable_device(dev->pdev))
 459                 return -EIO;
 460
 461         pci_set_master(dev->pdev);
 462
 463         ret = i915_drm_thaw(dev);
 464         if (ret)
 465                 return ret;
 466
 467         drm_kms_helper_poll_enable(dev);
 468         return 0;
 469 }
 470
 471 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474
 475         if (IS_I85X(dev))
 476                 return -ENODEV;
 477
 478         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 479         POSTING_READ(D_STATE);
 480
 481         if (IS_I830(dev) || IS_845G(dev)) {
 482                 I915_WRITE(DEBUG_RESET_I830,
 483                            DEBUG_RESET_DISPLAY |
 484                            DEBUG_RESET_RENDER |
 485                            DEBUG_RESET_FULL);
 486                 POSTING_READ(DEBUG_RESET_I830);
 487                 msleep(1);
 488
 489                 I915_WRITE(DEBUG_RESET_I830, 0);
 490                 POSTING_READ(DEBUG_RESET_I830);
 491         }
 492
 493         msleep(1);
 494
 495         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 496         POSTING_READ(D_STATE);
 497
 498         return 0;
 499 }
 500
 501 static int i965_reset_complete(struct drm_device *dev)
 502 {
 503         u8 gdrst;
 504         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 505         return gdrst & 0x1;
 506 }
 507
 508 static int i965_do_reset(struct drm_device *dev, u8 flags)
 509 {
 510         u8 gdrst;
 511
 512         /*
 513          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 514          * well as the reset bit (GR/bit 0).  Setting the GR bit
 515          * triggers the reset; when done, the hardware will clear it.
 516          */
 517         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 518         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 519
 520         return wait_for(i965_reset_complete(dev), 500);
 521 }
 522
 523 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 524 {
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 527         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 528         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 529 }
 530
 531 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 532 {
 533         struct drm_i915_private *dev_priv = dev->dev_private;
 534
 535         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 536         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 537 }
 538
 539 /**
 540  * i965_reset - reset chip after a hang
 541  * @dev: drm device to reset
 542  * @flags: reset domains
 543  *
 544  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 545  * reset or otherwise an error code.
 546  *
 547  * Procedure is fairly simple:
 548  *   - reset the chip using the reset reg
 549  *   - re-init context state
 550  *   - re-init hardware status page
 551  *   - re-init ring buffer
 552  *   - re-init interrupt state
 553  *   - re-init display
 554  */
 555 int i915_reset(struct drm_device *dev, u8 flags)
 556 {
 557         drm_i915_private_t *dev_priv = dev->dev_private;
 558         /*
 559          * We really should only reset the display subsystem if we actually
 560          * need to
 561          */
 562         bool need_display = true;
 563         int ret;
 564
 565         if (!i915_try_reset)
 566                 return 0;
 567
 568         if (!mutex_trylock(&dev->struct_mutex))
 569                 return -EBUSY;
 570
 571         i915_gem_reset(dev);
 572
 573         ret = -ENODEV;
 574         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 575                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 576         } else switch (INTEL_INFO(dev)->gen) {
 577         case 6:
 578                 ret = gen6_do_reset(dev, flags);
 579                 break;
 580         case 5:
 581                 ret = ironlake_do_reset(dev, flags);
 582                 break;
 583         case 4:
 584                 ret = i965_do_reset(dev, flags);
 585                 break;
 586         case 2:
 587                 ret = i8xx_do_reset(dev, flags);
 588                 break;
 589         }
 590         dev_priv->last_gpu_reset = get_seconds();
 591         if (ret) {
 592                 DRM_ERROR("Failed to reset chip.\n");
 593                 mutex_unlock(&dev->struct_mutex);
 594                 return ret;
 595         }
 596
 597         /* Ok, now get things going again... */
 598
 599         /*
 600          * Everything depends on having the GTT running, so we need to start
 601          * there.  Fortunately we don't need to do this unless we reset the
 602          * chip at a PCI level.
 603          *
 604          * Next we need to restore the context, but we don't use those
 605          * yet either...
 606          *
 607          * Ring buffer needs to be re-initialized in the KMS case, or if X
 608          * was running at the time of the reset (i.e. we weren't VT
 609          * switched away).
 610          */
 611         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 612                         !dev_priv->mm.suspended) {
 613                 dev_priv->mm.suspended = 0;
 614
 615                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 616                 if (HAS_BSD(dev))
 617                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 618                 if (HAS_BLT(dev))
 619                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 620
 621                 mutex_unlock(&dev->struct_mutex);
 622                 drm_irq_uninstall(dev);
 623                 drm_mode_config_reset(dev);
 624                 drm_irq_install(dev);
 625                 mutex_lock(&dev->struct_mutex);
 626         }
 627
 628         mutex_unlock(&dev->struct_mutex);
 629
 630         /*
 631          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 632          * need to retrain the display link and cannot just restore the register
 633          * values.
 634          */
 635         if (need_display) {
 636                 mutex_lock(&dev->mode_config.mutex);
 637                 drm_helper_resume_force_mode(dev);
 638                 mutex_unlock(&dev->mode_config.mutex);
 639         }
 640
 641         return 0;
 642 }
 643
 644
 645 static int __devinit
 646 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 647 {
 648         /* Only bind to function 0 of the device. Early generations
 649          * used function 1 as a placeholder for multi-head. This causes
 650          * us confusion instead, especially on the systems where both
 651          * functions have the same PCI-ID!
 652          */
 653         if (PCI_FUNC(pdev->devfn))
 654                 return -ENODEV;
 655
 656         return drm_get_pci_dev(pdev, ent, &driver);
 657 }
 658
 659 static void
 660 i915_pci_remove(struct pci_dev *pdev)
 661 {
 662         struct drm_device *dev = pci_get_drvdata(pdev);
 663
 664         drm_put_dev(dev);
 665 }
 666
 667 static int i915_pm_suspend(struct device *dev)
 668 {
 669         struct pci_dev *pdev = to_pci_dev(dev);
 670         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 671         int error;
 672
 673         if (!drm_dev || !drm_dev->dev_private) {
 674                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 675                 return -ENODEV;
 676         }
 677
 678         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 679                 return 0;
 680
 681         error = i915_drm_freeze(drm_dev);
 682         if (error)
 683                 return error;
 684
 685         pci_disable_device(pdev);
 686         pci_set_power_state(pdev, PCI_D3hot);
 687
 688         return 0;
 689 }
 690
 691 static int i915_pm_resume(struct device *dev)
 692 {
 693         struct pci_dev *pdev = to_pci_dev(dev);
 694         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 695
 696         return i915_resume(drm_dev);
 697 }
 698
 699 static int i915_pm_freeze(struct device *dev)
 700 {
 701         struct pci_dev *pdev = to_pci_dev(dev);
 702         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 703
 704         if (!drm_dev || !drm_dev->dev_private) {
 705                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 706                 return -ENODEV;
 707         }
 708
 709         return i915_drm_freeze(drm_dev);
 710 }
 711
 712 static int i915_pm_thaw(struct device *dev)
 713 {
 714         struct pci_dev *pdev = to_pci_dev(dev);
 715         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 716
 717         return i915_drm_thaw(drm_dev);
 718 }
 719
 720 static int i915_pm_poweroff(struct device *dev)
 721 {
 722         struct pci_dev *pdev = to_pci_dev(dev);
 723         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 724
 725         return i915_drm_freeze(drm_dev);
 726 }
 727
 728 static const struct dev_pm_ops i915_pm_ops = {
 729      .suspend = i915_pm_suspend,
 730      .resume = i915_pm_resume,
 731      .freeze = i915_pm_freeze,
 732      .thaw = i915_pm_thaw,
 733      .poweroff = i915_pm_poweroff,
 734      .restore = i915_pm_resume,
 735 };
 736
 737 static struct vm_operations_struct i915_gem_vm_ops = {
 738         .fault = i915_gem_fault,
 739         .open = drm_gem_vm_open,
 740         .close = drm_gem_vm_close,
 741 };
 742
 743 static struct drm_driver driver = {
 744         /* don't use mtrr's here, the Xserver or user space app should
 745          * deal with them for intel hardware.
 746          */
 747         .driver_features =
 748             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 749             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 750         .load = i915_driver_load,
 751         .unload = i915_driver_unload,
 752         .open = i915_driver_open,
 753         .lastclose = i915_driver_lastclose,
 754         .preclose = i915_driver_preclose,
 755         .postclose = i915_driver_postclose,
 756
 757         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 758         .suspend = i915_suspend,
 759         .resume = i915_resume,
 760
 761         .device_is_agp = i915_driver_device_is_agp,
 762         .enable_vblank = i915_enable_vblank,
 763         .disable_vblank = i915_disable_vblank,
 764         .get_vblank_timestamp = i915_get_vblank_timestamp,
 765         .get_scanout_position = i915_get_crtc_scanoutpos,
 766         .irq_preinstall = i915_driver_irq_preinstall,
 767         .irq_postinstall = i915_driver_irq_postinstall,
 768         .irq_uninstall = i915_driver_irq_uninstall,
 769         .irq_handler = i915_driver_irq_handler,
 770         .reclaim_buffers = drm_core_reclaim_buffers,
 771         .master_create = i915_master_create,
 772         .master_destroy = i915_master_destroy,
 773 #if defined(CONFIG_DEBUG_FS)
 774         .debugfs_init = i915_debugfs_init,
 775         .debugfs_cleanup = i915_debugfs_cleanup,
 776 #endif
 777         .gem_init_object = i915_gem_init_object,
 778         .gem_free_object = i915_gem_free_object,
 779         .gem_vm_ops = &i915_gem_vm_ops,
 780         .dumb_create = i915_gem_dumb_create,
 781         .dumb_map_offset = i915_gem_mmap_gtt,
 782         .dumb_destroy = i915_gem_dumb_destroy,
 783         .ioctls = i915_ioctls,
 784         .fops = {
 785                  .owner = THIS_MODULE,
 786                  .open = drm_open,
 787                  .release = drm_release,
 788                  .unlocked_ioctl = drm_ioctl,
 789                  .mmap = drm_gem_mmap,
 790                  .poll = drm_poll,
 791                  .fasync = drm_fasync,
 792                  .read = drm_read,
 793 #ifdef CONFIG_COMPAT
 794                  .compat_ioctl = i915_compat_ioctl,
 795 #endif
 796                  .llseek = noop_llseek,
 797         },
 798
 799         .name = DRIVER_NAME,
 800         .desc = DRIVER_DESC,
 801         .date = DRIVER_DATE,
 802         .major = DRIVER_MAJOR,
 803         .minor = DRIVER_MINOR,
 804         .patchlevel = DRIVER_PATCHLEVEL,
 805 };
 806
 807 static struct pci_driver i915_pci_driver = {
 808         .name = DRIVER_NAME,
 809         .id_table = pciidlist,
 810         .probe = i915_pci_probe,
 811         .remove = i915_pci_remove,
 812         .driver.pm = &i915_pm_ops,
 813 };
 814
 815 static int __init i915_init(void)
 816 {
 817         if (!intel_agp_enabled) {
 818                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 819                 return -ENODEV;
 820         }
 821
 822         driver.num_ioctls = i915_max_ioctl;
 823
 824         /*
 825          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 826          * explicitly disabled with the module pararmeter.
 827          *
 828          * Otherwise, just follow the parameter (defaulting to off).
 829          *
 830          * Allow optional vga_text_mode_force boot option to override
 831          * the default behavior.
 832          */
 833 #if defined(CONFIG_DRM_I915_KMS)
 834         if (i915_modeset != 0)
 835                 driver.driver_features |= DRIVER_MODESET;
 836 #endif
 837         if (i915_modeset == 1)
 838                 driver.driver_features |= DRIVER_MODESET;
 839
 840 #ifdef CONFIG_VGA_CONSOLE
 841         if (vgacon_text_force() && i915_modeset == -1)
 842                 driver.driver_features &= ~DRIVER_MODESET;
 843 #endif
 844
 845         if (!(driver.driver_features & DRIVER_MODESET))
 846                 driver.get_vblank_timestamp = NULL;
 847
 848         return drm_pci_init(&driver, &i915_pci_driver);
 849 }
 850
 851 static void __exit i915_exit(void)
 852 {
 853         drm_pci_exit(&driver, &i915_pci_driver);
 854 }
 855
 856 module_init(i915_init);
 857 module_exit(i915_exit);
 858
 859 MODULE_AUTHOR(DRIVER_AUTHOR);
 860 MODULE_DESCRIPTION(DRIVER_DESC);
 861 MODULE_LICENSE("GPL and additional rights");