1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include "drm_crtc_helper.h"
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
71 int i915_enable_fbc __read_mostly = -1;
72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
73 MODULE_PARM_DESC(i915_enable_fbc,
74 "Enable frame buffer compression for power savings "
75 "(default: -1 (use per-chip default))");
77 unsigned int i915_lvds_downclock __read_mostly = 0;
78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
79 MODULE_PARM_DESC(lvds_downclock,
80 "Use panel (LVDS/eDP) downclocking for power savings "
83 int i915_panel_use_ssc __read_mostly = -1;
84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
85 MODULE_PARM_DESC(lvds_use_ssc,
86 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
87 "(default: auto from VBT)");
89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
92 "Override selection of SDVO panel mode in the VBT "
95 static bool i915_try_reset __read_mostly = true;
96 module_param_named(reset, i915_try_reset, bool, 0600);
97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
99 bool i915_enable_hangcheck __read_mostly = true;
100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
101 MODULE_PARM_DESC(enable_hangcheck,
102 "Periodically check GPU activity for detecting hangs. "
103 "WARNING: Disabling this can cause system wide hangs. "
106 static struct drm_driver driver;
107 extern int intel_agp_enabled;
109 #define INTEL_VGA_DEVICE(id, info) { \
110 .class = PCI_BASE_CLASS_DISPLAY << 16, \
111 .class_mask = 0xff0000, \
114 .subvendor = PCI_ANY_ID, \
115 .subdevice = PCI_ANY_ID, \
116 .driver_data = (unsigned long) info }
118 static const struct intel_device_info intel_i830_info = {
119 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
120 .has_overlay = 1, .overlay_needs_physical = 1,
123 static const struct intel_device_info intel_845g_info = {
125 .has_overlay = 1, .overlay_needs_physical = 1,
128 static const struct intel_device_info intel_i85x_info = {
129 .gen = 2, .is_i85x = 1, .is_mobile = 1,
130 .cursor_needs_physical = 1,
131 .has_overlay = 1, .overlay_needs_physical = 1,
134 static const struct intel_device_info intel_i865g_info = {
136 .has_overlay = 1, .overlay_needs_physical = 1,
139 static const struct intel_device_info intel_i915g_info = {
140 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
141 .has_overlay = 1, .overlay_needs_physical = 1,
143 static const struct intel_device_info intel_i915gm_info = {
144 .gen = 3, .is_mobile = 1,
145 .cursor_needs_physical = 1,
146 .has_overlay = 1, .overlay_needs_physical = 1,
149 static const struct intel_device_info intel_i945g_info = {
150 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
151 .has_overlay = 1, .overlay_needs_physical = 1,
153 static const struct intel_device_info intel_i945gm_info = {
154 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
155 .has_hotplug = 1, .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
160 static const struct intel_device_info intel_i965g_info = {
161 .gen = 4, .is_broadwater = 1,
166 static const struct intel_device_info intel_i965gm_info = {
167 .gen = 4, .is_crestline = 1,
168 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
173 static const struct intel_device_info intel_g33_info = {
174 .gen = 3, .is_g33 = 1,
175 .need_gfx_hws = 1, .has_hotplug = 1,
179 static const struct intel_device_info intel_g45_info = {
180 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
181 .has_pipe_cxsr = 1, .has_hotplug = 1,
185 static const struct intel_device_info intel_gm45_info = {
186 .gen = 4, .is_g4x = 1,
187 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
188 .has_pipe_cxsr = 1, .has_hotplug = 1,
193 static const struct intel_device_info intel_pineview_info = {
194 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
195 .need_gfx_hws = 1, .has_hotplug = 1,
199 static const struct intel_device_info intel_ironlake_d_info = {
201 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
205 static const struct intel_device_info intel_ironlake_m_info = {
206 .gen = 5, .is_mobile = 1,
207 .need_gfx_hws = 1, .has_hotplug = 1,
212 static const struct intel_device_info intel_sandybridge_d_info = {
214 .need_gfx_hws = 1, .has_hotplug = 1,
219 static const struct intel_device_info intel_sandybridge_m_info = {
220 .gen = 6, .is_mobile = 1,
221 .need_gfx_hws = 1, .has_hotplug = 1,
227 static const struct intel_device_info intel_ivybridge_d_info = {
228 .is_ivybridge = 1, .gen = 7,
229 .need_gfx_hws = 1, .has_hotplug = 1,
234 static const struct intel_device_info intel_ivybridge_m_info = {
235 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
236 .need_gfx_hws = 1, .has_hotplug = 1,
237 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
242 static const struct pci_device_id pciidlist[] = { /* aka */
243 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
244 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
245 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
246 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
247 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
248 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
249 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
250 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
251 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
252 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
253 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
254 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
255 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
256 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
257 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
258 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
259 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
260 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
261 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
262 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
263 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
264 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
265 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
266 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
267 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
268 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
269 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
270 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
271 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
272 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
273 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
274 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
275 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
276 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
277 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
278 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
279 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
280 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
281 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
282 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
283 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
284 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
285 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
289 #if defined(CONFIG_DRM_I915_KMS)
290 MODULE_DEVICE_TABLE(pci, pciidlist);
293 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
294 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
295 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
296 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
298 void intel_detect_pch(struct drm_device *dev)
300 struct drm_i915_private *dev_priv = dev->dev_private;
304 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
305 * make graphics device passthrough work easy for VMM, that only
306 * need to expose ISA bridge to let driver know the real hardware
307 * underneath. This is a requirement from virtualization team.
309 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
311 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
313 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
315 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
316 dev_priv->pch_type = PCH_IBX;
317 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
318 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
319 dev_priv->pch_type = PCH_CPT;
320 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
321 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
322 /* PantherPoint is CPT compatible */
323 dev_priv->pch_type = PCH_CPT;
324 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
331 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
336 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
339 I915_WRITE_NOTRACE(FORCEWAKE, 1);
340 POSTING_READ(FORCEWAKE);
343 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
347 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
352 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
355 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
356 POSTING_READ(FORCEWAKE_MT);
359 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
364 * Generally this is called implicitly by the register read function. However,
365 * if some sequence requires the GT to not power down then this function should
366 * be called at the beginning of the sequence followed by a call to
367 * gen6_gt_force_wake_put() at the end of the sequence.
369 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
371 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
373 /* Forcewake is atomic in case we get in here without the lock */
374 if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
375 dev_priv->display.force_wake_get(dev_priv);
378 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
380 I915_WRITE_NOTRACE(FORCEWAKE, 0);
381 POSTING_READ(FORCEWAKE);
384 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
386 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
387 POSTING_READ(FORCEWAKE_MT);
391 * see gen6_gt_force_wake_get()
393 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
395 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
397 if (atomic_dec_and_test(&dev_priv->forcewake_count))
398 dev_priv->display.force_wake_put(dev_priv);
401 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
403 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
405 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
406 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
408 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
410 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
411 dev_priv->gt_fifo_count = fifo;
413 dev_priv->gt_fifo_count--;
416 static int i915_drm_freeze(struct drm_device *dev)
418 struct drm_i915_private *dev_priv = dev->dev_private;
420 drm_kms_helper_poll_disable(dev);
422 pci_save_state(dev->pdev);
424 /* If KMS is active, we do the leavevt stuff here */
425 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
426 int error = i915_gem_idle(dev);
428 dev_err(&dev->pdev->dev,
429 "GEM idle failed, resume might fail\n");
432 drm_irq_uninstall(dev);
435 i915_save_state(dev);
437 intel_opregion_fini(dev);
439 /* Modeset on resume, not lid events */
440 dev_priv->modeset_on_lid = 0;
445 int i915_suspend(struct drm_device *dev, pm_message_t state)
449 if (!dev || !dev->dev_private) {
450 DRM_ERROR("dev: %p\n", dev);
451 DRM_ERROR("DRM not initialized, aborting suspend.\n");
455 if (state.event == PM_EVENT_PRETHAW)
459 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
462 error = i915_drm_freeze(dev);
466 if (state.event == PM_EVENT_SUSPEND) {
467 /* Shut down the device */
468 pci_disable_device(dev->pdev);
469 pci_set_power_state(dev->pdev, PCI_D3hot);
475 static int i915_drm_thaw(struct drm_device *dev)
477 struct drm_i915_private *dev_priv = dev->dev_private;
480 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
481 mutex_lock(&dev->struct_mutex);
482 i915_gem_restore_gtt_mappings(dev);
483 mutex_unlock(&dev->struct_mutex);
486 i915_restore_state(dev);
487 intel_opregion_setup(dev);
489 /* KMS EnterVT equivalent */
490 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
491 mutex_lock(&dev->struct_mutex);
492 dev_priv->mm.suspended = 0;
494 error = i915_gem_init_ringbuffer(dev);
495 mutex_unlock(&dev->struct_mutex);
497 if (HAS_PCH_SPLIT(dev))
498 ironlake_init_pch_refclk(dev);
500 drm_mode_config_reset(dev);
501 drm_irq_install(dev);
503 /* Resume the modeset for every activated CRTC */
504 drm_helper_resume_force_mode(dev);
506 if (IS_IRONLAKE_M(dev))
507 ironlake_enable_rc6(dev);
510 intel_opregion_init(dev);
512 dev_priv->modeset_on_lid = 0;
517 int i915_resume(struct drm_device *dev)
521 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
524 if (pci_enable_device(dev->pdev))
527 pci_set_master(dev->pdev);
529 ret = i915_drm_thaw(dev);
533 drm_kms_helper_poll_enable(dev);
537 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
539 struct drm_i915_private *dev_priv = dev->dev_private;
544 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
545 POSTING_READ(D_STATE);
547 if (IS_I830(dev) || IS_845G(dev)) {
548 I915_WRITE(DEBUG_RESET_I830,
549 DEBUG_RESET_DISPLAY |
552 POSTING_READ(DEBUG_RESET_I830);
555 I915_WRITE(DEBUG_RESET_I830, 0);
556 POSTING_READ(DEBUG_RESET_I830);
561 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
562 POSTING_READ(D_STATE);
567 static int i965_reset_complete(struct drm_device *dev)
570 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
574 static int i965_do_reset(struct drm_device *dev, u8 flags)
579 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
580 * well as the reset bit (GR/bit 0). Setting the GR bit
581 * triggers the reset; when done, the hardware will clear it.
583 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
584 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
586 return wait_for(i965_reset_complete(dev), 500);
589 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
591 struct drm_i915_private *dev_priv = dev->dev_private;
592 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
593 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
594 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
597 static int gen6_do_reset(struct drm_device *dev, u8 flags)
599 struct drm_i915_private *dev_priv = dev->dev_private;
601 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
602 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
606 * i965_reset - reset chip after a hang
607 * @dev: drm device to reset
608 * @flags: reset domains
610 * Reset the chip. Useful if a hang is detected. Returns zero on successful
611 * reset or otherwise an error code.
613 * Procedure is fairly simple:
614 * - reset the chip using the reset reg
615 * - re-init context state
616 * - re-init hardware status page
617 * - re-init ring buffer
618 * - re-init interrupt state
621 int i915_reset(struct drm_device *dev, u8 flags)
623 drm_i915_private_t *dev_priv = dev->dev_private;
625 * We really should only reset the display subsystem if we actually
628 bool need_display = true;
634 if (!mutex_trylock(&dev->struct_mutex))
640 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
641 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
642 } else switch (INTEL_INFO(dev)->gen) {
645 ret = gen6_do_reset(dev, flags);
646 /* If reset with a user forcewake, try to restore */
647 if (atomic_read(&dev_priv->forcewake_count))
648 __gen6_gt_force_wake_get(dev_priv);
651 ret = ironlake_do_reset(dev, flags);
654 ret = i965_do_reset(dev, flags);
657 ret = i8xx_do_reset(dev, flags);
660 dev_priv->last_gpu_reset = get_seconds();
662 DRM_ERROR("Failed to reset chip.\n");
663 mutex_unlock(&dev->struct_mutex);
667 /* Ok, now get things going again... */
670 * Everything depends on having the GTT running, so we need to start
671 * there. Fortunately we don't need to do this unless we reset the
672 * chip at a PCI level.
674 * Next we need to restore the context, but we don't use those
677 * Ring buffer needs to be re-initialized in the KMS case, or if X
678 * was running at the time of the reset (i.e. we weren't VT
681 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
682 !dev_priv->mm.suspended) {
683 dev_priv->mm.suspended = 0;
685 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
687 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
689 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
691 mutex_unlock(&dev->struct_mutex);
692 drm_irq_uninstall(dev);
693 drm_mode_config_reset(dev);
694 drm_irq_install(dev);
695 mutex_lock(&dev->struct_mutex);
698 mutex_unlock(&dev->struct_mutex);
701 * Perform a full modeset as on later generations, e.g. Ironlake, we may
702 * need to retrain the display link and cannot just restore the register
706 mutex_lock(&dev->mode_config.mutex);
707 drm_helper_resume_force_mode(dev);
708 mutex_unlock(&dev->mode_config.mutex);
716 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
718 /* Only bind to function 0 of the device. Early generations
719 * used function 1 as a placeholder for multi-head. This causes
720 * us confusion instead, especially on the systems where both
721 * functions have the same PCI-ID!
723 if (PCI_FUNC(pdev->devfn))
726 return drm_get_pci_dev(pdev, ent, &driver);
730 i915_pci_remove(struct pci_dev *pdev)
732 struct drm_device *dev = pci_get_drvdata(pdev);
737 static int i915_pm_suspend(struct device *dev)
739 struct pci_dev *pdev = to_pci_dev(dev);
740 struct drm_device *drm_dev = pci_get_drvdata(pdev);
743 if (!drm_dev || !drm_dev->dev_private) {
744 dev_err(dev, "DRM not initialized, aborting suspend.\n");
748 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
751 error = i915_drm_freeze(drm_dev);
755 pci_disable_device(pdev);
756 pci_set_power_state(pdev, PCI_D3hot);
761 static int i915_pm_resume(struct device *dev)
763 struct pci_dev *pdev = to_pci_dev(dev);
764 struct drm_device *drm_dev = pci_get_drvdata(pdev);
766 return i915_resume(drm_dev);
769 static int i915_pm_freeze(struct device *dev)
771 struct pci_dev *pdev = to_pci_dev(dev);
772 struct drm_device *drm_dev = pci_get_drvdata(pdev);
774 if (!drm_dev || !drm_dev->dev_private) {
775 dev_err(dev, "DRM not initialized, aborting suspend.\n");
779 return i915_drm_freeze(drm_dev);
782 static int i915_pm_thaw(struct device *dev)
784 struct pci_dev *pdev = to_pci_dev(dev);
785 struct drm_device *drm_dev = pci_get_drvdata(pdev);
787 return i915_drm_thaw(drm_dev);
790 static int i915_pm_poweroff(struct device *dev)
792 struct pci_dev *pdev = to_pci_dev(dev);
793 struct drm_device *drm_dev = pci_get_drvdata(pdev);
795 return i915_drm_freeze(drm_dev);
798 static const struct dev_pm_ops i915_pm_ops = {
799 .suspend = i915_pm_suspend,
800 .resume = i915_pm_resume,
801 .freeze = i915_pm_freeze,
802 .thaw = i915_pm_thaw,
803 .poweroff = i915_pm_poweroff,
804 .restore = i915_pm_resume,
807 static struct vm_operations_struct i915_gem_vm_ops = {
808 .fault = i915_gem_fault,
809 .open = drm_gem_vm_open,
810 .close = drm_gem_vm_close,
813 static const struct file_operations i915_driver_fops = {
814 .owner = THIS_MODULE,
816 .release = drm_release,
817 .unlocked_ioctl = drm_ioctl,
818 .mmap = drm_gem_mmap,
820 .fasync = drm_fasync,
823 .compat_ioctl = i915_compat_ioctl,
825 .llseek = noop_llseek,
828 static struct drm_driver driver = {
829 /* Don't use MTRRs here; the Xserver or userspace app should
830 * deal with them for Intel hardware.
833 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
834 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
835 .load = i915_driver_load,
836 .unload = i915_driver_unload,
837 .open = i915_driver_open,
838 .lastclose = i915_driver_lastclose,
839 .preclose = i915_driver_preclose,
840 .postclose = i915_driver_postclose,
842 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
843 .suspend = i915_suspend,
844 .resume = i915_resume,
846 .device_is_agp = i915_driver_device_is_agp,
847 .reclaim_buffers = drm_core_reclaim_buffers,
848 .master_create = i915_master_create,
849 .master_destroy = i915_master_destroy,
850 #if defined(CONFIG_DEBUG_FS)
851 .debugfs_init = i915_debugfs_init,
852 .debugfs_cleanup = i915_debugfs_cleanup,
854 .gem_init_object = i915_gem_init_object,
855 .gem_free_object = i915_gem_free_object,
856 .gem_vm_ops = &i915_gem_vm_ops,
857 .dumb_create = i915_gem_dumb_create,
858 .dumb_map_offset = i915_gem_mmap_gtt,
859 .dumb_destroy = i915_gem_dumb_destroy,
860 .ioctls = i915_ioctls,
861 .fops = &i915_driver_fops,
865 .major = DRIVER_MAJOR,
866 .minor = DRIVER_MINOR,
867 .patchlevel = DRIVER_PATCHLEVEL,
870 static struct pci_driver i915_pci_driver = {
872 .id_table = pciidlist,
873 .probe = i915_pci_probe,
874 .remove = i915_pci_remove,
875 .driver.pm = &i915_pm_ops,
878 static int __init i915_init(void)
880 if (!intel_agp_enabled) {
881 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
885 driver.num_ioctls = i915_max_ioctl;
888 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
889 * explicitly disabled with the module pararmeter.
891 * Otherwise, just follow the parameter (defaulting to off).
893 * Allow optional vga_text_mode_force boot option to override
894 * the default behavior.
896 #if defined(CONFIG_DRM_I915_KMS)
897 if (i915_modeset != 0)
898 driver.driver_features |= DRIVER_MODESET;
900 if (i915_modeset == 1)
901 driver.driver_features |= DRIVER_MODESET;
903 #ifdef CONFIG_VGA_CONSOLE
904 if (vgacon_text_force() && i915_modeset == -1)
905 driver.driver_features &= ~DRIVER_MODESET;
908 if (!(driver.driver_features & DRIVER_MODESET))
909 driver.get_vblank_timestamp = NULL;
911 return drm_pci_init(&driver, &i915_pci_driver);
914 static void __exit i915_exit(void)
916 drm_pci_exit(&driver, &i915_pci_driver);
919 module_init(i915_init);
920 module_exit(i915_exit);
922 MODULE_AUTHOR(DRIVER_AUTHOR);
923 MODULE_DESCRIPTION(DRIVER_DESC);
924 MODULE_LICENSE("GPL and additional rights");
926 #define __i915_read(x, y) \
927 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
929 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
930 gen6_gt_force_wake_get(dev_priv); \
931 val = read##y(dev_priv->regs + reg); \
932 gen6_gt_force_wake_put(dev_priv); \
934 val = read##y(dev_priv->regs + reg); \
936 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
946 #define __i915_write(x, y) \
947 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
948 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
949 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
950 __gen6_gt_wait_for_fifo(dev_priv); \
952 write##y(val, dev_priv->regs + reg); \