drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fbc = 1,
 307         GEN_DEFAULT_PIPEOFFSETS,
 308         IVB_CURSOR_OFFSETS,
 309 };
 310
 311 static const struct intel_device_info intel_broadwell_m_info = {
 312         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 313         .need_gfx_hws = 1, .has_hotplug = 1,
 314         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 315         .has_llc = 1,
 316         .has_ddi = 1,
 317         .has_fbc = 1,
 318         GEN_DEFAULT_PIPEOFFSETS,
 319         IVB_CURSOR_OFFSETS,
 320 };
 321
 322 static const struct intel_device_info intel_broadwell_gt3d_info = {
 323         .gen = 8, .num_pipes = 3,
 324         .need_gfx_hws = 1, .has_hotplug = 1,
 325         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 326         .has_llc = 1,
 327         .has_ddi = 1,
 328         .has_fbc = 1,
 329         GEN_DEFAULT_PIPEOFFSETS,
 330         IVB_CURSOR_OFFSETS,
 331 };
 332
 333 static const struct intel_device_info intel_broadwell_gt3m_info = {
 334         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 335         .need_gfx_hws = 1, .has_hotplug = 1,
 336         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 337         .has_llc = 1,
 338         .has_ddi = 1,
 339         .has_fbc = 1,
 340         GEN_DEFAULT_PIPEOFFSETS,
 341         IVB_CURSOR_OFFSETS,
 342 };
 343
 344 static const struct intel_device_info intel_cherryview_info = {
 345         .is_preliminary = 1,
 346         .gen = 8, .num_pipes = 3,
 347         .need_gfx_hws = 1, .has_hotplug = 1,
 348         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 349         .is_valleyview = 1,
 350         .display_mmio_offset = VLV_DISPLAY_BASE,
 351         GEN_CHV_PIPEOFFSETS,
 352         CURSOR_OFFSETS,
 353 };
 354
 355 /*
 356  * Make sure any device matches here are from most specific to most
 357  * general.  For example, since the Quanta match is based on the subsystem
 358  * and subvendor IDs, we need it to come before the more general IVB
 359  * PCI ID matches, otherwise we'll use the wrong info struct above.
 360  */
 361 #define INTEL_PCI_IDS \
 362         INTEL_I830_IDS(&intel_i830_info),       \
 363         INTEL_I845G_IDS(&intel_845g_info),      \
 364         INTEL_I85X_IDS(&intel_i85x_info),       \
 365         INTEL_I865G_IDS(&intel_i865g_info),     \
 366         INTEL_I915G_IDS(&intel_i915g_info),     \
 367         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 368         INTEL_I945G_IDS(&intel_i945g_info),     \
 369         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 370         INTEL_I965G_IDS(&intel_i965g_info),     \
 371         INTEL_G33_IDS(&intel_g33_info),         \
 372         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 373         INTEL_GM45_IDS(&intel_gm45_info),       \
 374         INTEL_G45_IDS(&intel_g45_info),         \
 375         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 376         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 377         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 378         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 379         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 380         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 381         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 382         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 383         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 384         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 385         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 386         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 387         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 388         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 389         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 390         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 391         INTEL_CHV_IDS(&intel_cherryview_info)
 392
 393 static const struct pci_device_id pciidlist[] = {               /* aka */
 394         INTEL_PCI_IDS,
 395         {0, 0, 0}
 396 };
 397
 398 #if defined(CONFIG_DRM_I915_KMS)
 399 MODULE_DEVICE_TABLE(pci, pciidlist);
 400 #endif
 401
 402 void intel_detect_pch(struct drm_device *dev)
 403 {
 404         struct drm_i915_private *dev_priv = dev->dev_private;
 405         struct pci_dev *pch = NULL;
 406
 407         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 408          * (which really amounts to a PCH but no South Display).
 409          */
 410         if (INTEL_INFO(dev)->num_pipes == 0) {
 411                 dev_priv->pch_type = PCH_NOP;
 412                 return;
 413         }
 414
 415         /*
 416          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 417          * make graphics device passthrough work easy for VMM, that only
 418          * need to expose ISA bridge to let driver know the real hardware
 419          * underneath. This is a requirement from virtualization team.
 420          *
 421          * In some virtualized environments (e.g. XEN), there is irrelevant
 422          * ISA bridge in the system. To work reliably, we should scan trhough
 423          * all the ISA bridge devices and check for the first match, instead
 424          * of only checking the first one.
 425          */
 426         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 427                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 428                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 429                         dev_priv->pch_id = id;
 430
 431                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 432                                 dev_priv->pch_type = PCH_IBX;
 433                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 434                                 WARN_ON(!IS_GEN5(dev));
 435                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_CPT;
 437                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 438                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 439                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 440                                 /* PantherPoint is CPT compatible */
 441                                 dev_priv->pch_type = PCH_CPT;
 442                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 443                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 444                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 445                                 dev_priv->pch_type = PCH_LPT;
 446                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 447                                 WARN_ON(!IS_HASWELL(dev));
 448                                 WARN_ON(IS_ULT(dev));
 449                         } else if (IS_BROADWELL(dev)) {
 450                                 dev_priv->pch_type = PCH_LPT;
 451                                 dev_priv->pch_id =
 452                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 453                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 454                                               "LynxPoint LP PCH\n");
 455                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 456                                 dev_priv->pch_type = PCH_LPT;
 457                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 458                                 WARN_ON(!IS_HASWELL(dev));
 459                                 WARN_ON(!IS_ULT(dev));
 460                         } else
 461                                 continue;
 462
 463                         break;
 464                 }
 465         }
 466         if (!pch)
 467                 DRM_DEBUG_KMS("No PCH found.\n");
 468
 469         pci_dev_put(pch);
 470 }
 471
 472 bool i915_semaphore_is_enabled(struct drm_device *dev)
 473 {
 474         if (INTEL_INFO(dev)->gen < 6)
 475                 return false;
 476
 477         if (i915.semaphores >= 0)
 478                 return i915.semaphores;
 479
 480         /* Until we get further testing... */
 481         if (IS_GEN8(dev))
 482                 return false;
 483
 484 #ifdef CONFIG_INTEL_IOMMU
 485         /* Enable semaphores on SNB when IO remapping is off */
 486         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 487                 return false;
 488 #endif
 489
 490         return true;
 491 }
 492
 493 static int i915_drm_freeze(struct drm_device *dev)
 494 {
 495         struct drm_i915_private *dev_priv = dev->dev_private;
 496         struct drm_crtc *crtc;
 497         pci_power_t opregion_target_state;
 498
 499         intel_runtime_pm_get(dev_priv);
 500
 501         /* ignore lid events during suspend */
 502         mutex_lock(&dev_priv->modeset_restore_lock);
 503         dev_priv->modeset_restore = MODESET_SUSPENDED;
 504         mutex_unlock(&dev_priv->modeset_restore_lock);
 505
 506         /* We do a lot of poking in a lot of registers, make sure they work
 507          * properly. */
 508         intel_display_set_init_power(dev_priv, true);
 509
 510         drm_kms_helper_poll_disable(dev);
 511
 512         pci_save_state(dev->pdev);
 513
 514         /* If KMS is active, we do the leavevt stuff here */
 515         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 516                 int error;
 517
 518                 error = i915_gem_suspend(dev);
 519                 if (error) {
 520                         dev_err(&dev->pdev->dev,
 521                                 "GEM idle failed, resume might fail\n");
 522                         return error;
 523                 }
 524
 525                 intel_runtime_pm_disable_interrupts(dev);
 526                 dev_priv->enable_hotplug_processing = false;
 527
 528                 intel_suspend_gt_powersave(dev);
 529
 530                 /*
 531                  * Disable CRTCs directly since we want to preserve sw state
 532                  * for _thaw.
 533                  */
 534                 drm_modeset_lock_all(dev);
 535                 for_each_crtc(dev, crtc) {
 536                         dev_priv->display.crtc_disable(crtc);
 537                 }
 538                 drm_modeset_unlock_all(dev);
 539
 540                 intel_modeset_suspend_hw(dev);
 541         }
 542
 543         i915_gem_suspend_gtt_mappings(dev);
 544
 545         i915_save_state(dev);
 546
 547         if (acpi_target_system_state() >= ACPI_STATE_S3)
 548                 opregion_target_state = PCI_D3cold;
 549         else
 550                 opregion_target_state = PCI_D1;
 551         intel_opregion_notify_adapter(dev, opregion_target_state);
 552
 553         intel_uncore_forcewake_reset(dev, false);
 554         intel_opregion_fini(dev);
 555
 556         console_lock();
 557         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 558         console_unlock();
 559
 560         dev_priv->suspend_count++;
 561
 562         intel_display_set_init_power(dev_priv, false);
 563
 564         return 0;
 565 }
 566
 567 int i915_suspend(struct drm_device *dev, pm_message_t state)
 568 {
 569         int error;
 570
 571         if (!dev || !dev->dev_private) {
 572                 DRM_ERROR("dev: %p\n", dev);
 573                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 574                 return -ENODEV;
 575         }
 576
 577         if (state.event == PM_EVENT_PRETHAW)
 578                 return 0;
 579
 580
 581         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 582                 return 0;
 583
 584         error = i915_drm_freeze(dev);
 585         if (error)
 586                 return error;
 587
 588         if (state.event == PM_EVENT_SUSPEND) {
 589                 /* Shut down the device */
 590                 pci_disable_device(dev->pdev);
 591                 pci_set_power_state(dev->pdev, PCI_D3hot);
 592         }
 593
 594         return 0;
 595 }
 596
 597 void intel_console_resume(struct work_struct *work)
 598 {
 599         struct drm_i915_private *dev_priv =
 600                 container_of(work, struct drm_i915_private,
 601                              console_resume_work);
 602         struct drm_device *dev = dev_priv->dev;
 603
 604         console_lock();
 605         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 606         console_unlock();
 607 }
 608
 609 static int i915_drm_thaw_early(struct drm_device *dev)
 610 {
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612
 613         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 614                 hsw_disable_pc8(dev_priv);
 615
 616         intel_uncore_early_sanitize(dev, true);
 617         intel_uncore_sanitize(dev);
 618         intel_power_domains_init_hw(dev_priv);
 619
 620         return 0;
 621 }
 622
 623 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 624 {
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626
 627         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 628             restore_gtt_mappings) {
 629                 mutex_lock(&dev->struct_mutex);
 630                 i915_gem_restore_gtt_mappings(dev);
 631                 mutex_unlock(&dev->struct_mutex);
 632         }
 633
 634         i915_restore_state(dev);
 635         intel_opregion_setup(dev);
 636
 637         /* KMS EnterVT equivalent */
 638         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 639                 intel_init_pch_refclk(dev);
 640                 drm_mode_config_reset(dev);
 641
 642                 mutex_lock(&dev->struct_mutex);
 643                 if (i915_gem_init_hw(dev)) {
 644                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 645                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 646                 }
 647                 mutex_unlock(&dev->struct_mutex);
 648
 649                 intel_runtime_pm_restore_interrupts(dev);
 650
 651                 intel_modeset_init_hw(dev);
 652
 653                 drm_modeset_lock_all(dev);
 654                 intel_modeset_setup_hw_state(dev, true);
 655                 drm_modeset_unlock_all(dev);
 656
 657                 /*
 658                  * ... but also need to make sure that hotplug processing
 659                  * doesn't cause havoc. Like in the driver load code we don't
 660                  * bother with the tiny race here where we might loose hotplug
 661                  * notifications.
 662                  * */
 663                 intel_hpd_init(dev);
 664                 dev_priv->enable_hotplug_processing = true;
 665                 /* Config may have changed between suspend and resume */
 666                 drm_helper_hpd_irq_event(dev);
 667         }
 668
 669         intel_opregion_init(dev);
 670
 671         /*
 672          * The console lock can be pretty contented on resume due
 673          * to all the printk activity.  Try to keep it out of the hot
 674          * path of resume if possible.
 675          */
 676         if (console_trylock()) {
 677                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 678                 console_unlock();
 679         } else {
 680                 schedule_work(&dev_priv->console_resume_work);
 681         }
 682
 683         mutex_lock(&dev_priv->modeset_restore_lock);
 684         dev_priv->modeset_restore = MODESET_DONE;
 685         mutex_unlock(&dev_priv->modeset_restore_lock);
 686
 687         intel_opregion_notify_adapter(dev, PCI_D0);
 688
 689         intel_runtime_pm_put(dev_priv);
 690         return 0;
 691 }
 692
 693 static int i915_drm_thaw(struct drm_device *dev)
 694 {
 695         if (drm_core_check_feature(dev, DRIVER_MODESET))
 696                 i915_check_and_clear_faults(dev);
 697
 698         return __i915_drm_thaw(dev, true);
 699 }
 700
 701 static int i915_resume_early(struct drm_device *dev)
 702 {
 703         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 704                 return 0;
 705
 706         /*
 707          * We have a resume ordering issue with the snd-hda driver also
 708          * requiring our device to be power up. Due to the lack of a
 709          * parent/child relationship we currently solve this with an early
 710          * resume hook.
 711          *
 712          * FIXME: This should be solved with a special hdmi sink device or
 713          * similar so that power domains can be employed.
 714          */
 715         if (pci_enable_device(dev->pdev))
 716                 return -EIO;
 717
 718         pci_set_master(dev->pdev);
 719
 720         return i915_drm_thaw_early(dev);
 721 }
 722
 723 int i915_resume(struct drm_device *dev)
 724 {
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         int ret;
 727
 728         /*
 729          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 730          * earlier) need to restore the GTT mappings since the BIOS might clear
 731          * all our scratch PTEs.
 732          */
 733         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 734         if (ret)
 735                 return ret;
 736
 737         drm_kms_helper_poll_enable(dev);
 738         return 0;
 739 }
 740
 741 static int i915_resume_legacy(struct drm_device *dev)
 742 {
 743         i915_resume_early(dev);
 744         i915_resume(dev);
 745
 746         return 0;
 747 }
 748
 749 /**
 750  * i915_reset - reset chip after a hang
 751  * @dev: drm device to reset
 752  *
 753  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 754  * reset or otherwise an error code.
 755  *
 756  * Procedure is fairly simple:
 757  *   - reset the chip using the reset reg
 758  *   - re-init context state
 759  *   - re-init hardware status page
 760  *   - re-init ring buffer
 761  *   - re-init interrupt state
 762  *   - re-init display
 763  */
 764 int i915_reset(struct drm_device *dev)
 765 {
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         bool simulated;
 768         int ret;
 769
 770         if (!i915.reset)
 771                 return 0;
 772
 773         mutex_lock(&dev->struct_mutex);
 774
 775         i915_gem_reset(dev);
 776
 777         simulated = dev_priv->gpu_error.stop_rings != 0;
 778
 779         ret = intel_gpu_reset(dev);
 780
 781         /* Also reset the gpu hangman. */
 782         if (simulated) {
 783                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 784                 dev_priv->gpu_error.stop_rings = 0;
 785                 if (ret == -ENODEV) {
 786                         DRM_INFO("Reset not implemented, but ignoring "
 787                                  "error for simulated gpu hangs\n");
 788                         ret = 0;
 789                 }
 790         }
 791
 792         if (ret) {
 793                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 794                 mutex_unlock(&dev->struct_mutex);
 795                 return ret;
 796         }
 797
 798         /* Ok, now get things going again... */
 799
 800         /*
 801          * Everything depends on having the GTT running, so we need to start
 802          * there.  Fortunately we don't need to do this unless we reset the
 803          * chip at a PCI level.
 804          *
 805          * Next we need to restore the context, but we don't use those
 806          * yet either...
 807          *
 808          * Ring buffer needs to be re-initialized in the KMS case, or if X
 809          * was running at the time of the reset (i.e. we weren't VT
 810          * switched away).
 811          */
 812         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 813                         !dev_priv->ums.mm_suspended) {
 814                 dev_priv->ums.mm_suspended = 0;
 815
 816                 ret = i915_gem_init_hw(dev);
 817                 mutex_unlock(&dev->struct_mutex);
 818                 if (ret) {
 819                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 820                         return ret;
 821                 }
 822
 823                 /*
 824                  * FIXME: This races pretty badly against concurrent holders of
 825                  * ring interrupts. This is possible since we've started to drop
 826                  * dev->struct_mutex in select places when waiting for the gpu.
 827                  */
 828
 829                 /*
 830                  * rps/rc6 re-init is necessary to restore state lost after the
 831                  * reset and the re-install of gt irqs. Skip for ironlake per
 832                  * previous concerns that it doesn't respond well to some forms
 833                  * of re-init after reset.
 834                  */
 835                 if (INTEL_INFO(dev)->gen > 5)
 836                         intel_reset_gt_powersave(dev);
 837
 838                 intel_hpd_init(dev);
 839         } else {
 840                 mutex_unlock(&dev->struct_mutex);
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 847 {
 848         struct intel_device_info *intel_info =
 849                 (struct intel_device_info *) ent->driver_data;
 850
 851         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 852                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 853                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 854                 return -ENODEV;
 855         }
 856
 857         /* Only bind to function 0 of the device. Early generations
 858          * used function 1 as a placeholder for multi-head. This causes
 859          * us confusion instead, especially on the systems where both
 860          * functions have the same PCI-ID!
 861          */
 862         if (PCI_FUNC(pdev->devfn))
 863                 return -ENODEV;
 864
 865         driver.driver_features &= ~(DRIVER_USE_AGP);
 866
 867         return drm_get_pci_dev(pdev, ent, &driver);
 868 }
 869
 870 static void
 871 i915_pci_remove(struct pci_dev *pdev)
 872 {
 873         struct drm_device *dev = pci_get_drvdata(pdev);
 874
 875         drm_put_dev(dev);
 876 }
 877
 878 static int i915_pm_suspend(struct device *dev)
 879 {
 880         struct pci_dev *pdev = to_pci_dev(dev);
 881         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 882
 883         if (!drm_dev || !drm_dev->dev_private) {
 884                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 885                 return -ENODEV;
 886         }
 887
 888         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 889                 return 0;
 890
 891         return i915_drm_freeze(drm_dev);
 892 }
 893
 894 static int i915_pm_suspend_late(struct device *dev)
 895 {
 896         struct pci_dev *pdev = to_pci_dev(dev);
 897         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 898         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 899
 900         /*
 901          * We have a suspedn ordering issue with the snd-hda driver also
 902          * requiring our device to be power up. Due to the lack of a
 903          * parent/child relationship we currently solve this with an late
 904          * suspend hook.
 905          *
 906          * FIXME: This should be solved with a special hdmi sink device or
 907          * similar so that power domains can be employed.
 908          */
 909         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 910                 return 0;
 911
 912         if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
 913                 hsw_enable_pc8(dev_priv);
 914
 915         pci_disable_device(pdev);
 916         pci_set_power_state(pdev, PCI_D3hot);
 917
 918         return 0;
 919 }
 920
 921 static int i915_pm_resume_early(struct device *dev)
 922 {
 923         struct pci_dev *pdev = to_pci_dev(dev);
 924         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 925
 926         return i915_resume_early(drm_dev);
 927 }
 928
 929 static int i915_pm_resume(struct device *dev)
 930 {
 931         struct pci_dev *pdev = to_pci_dev(dev);
 932         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 933
 934         return i915_resume(drm_dev);
 935 }
 936
 937 static int i915_pm_freeze(struct device *dev)
 938 {
 939         struct pci_dev *pdev = to_pci_dev(dev);
 940         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 941
 942         if (!drm_dev || !drm_dev->dev_private) {
 943                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 944                 return -ENODEV;
 945         }
 946
 947         return i915_drm_freeze(drm_dev);
 948 }
 949
 950 static int i915_pm_thaw_early(struct device *dev)
 951 {
 952         struct pci_dev *pdev = to_pci_dev(dev);
 953         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 954
 955         return i915_drm_thaw_early(drm_dev);
 956 }
 957
 958 static int i915_pm_thaw(struct device *dev)
 959 {
 960         struct pci_dev *pdev = to_pci_dev(dev);
 961         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 962
 963         return i915_drm_thaw(drm_dev);
 964 }
 965
 966 static int i915_pm_poweroff(struct device *dev)
 967 {
 968         struct pci_dev *pdev = to_pci_dev(dev);
 969         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 970
 971         return i915_drm_freeze(drm_dev);
 972 }
 973
 974 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 975 {
 976         hsw_enable_pc8(dev_priv);
 977
 978         return 0;
 979 }
 980
 981 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
 982 {
 983         struct drm_device *dev = dev_priv->dev;
 984
 985         intel_init_pch_refclk(dev);
 986
 987         return 0;
 988 }
 989
 990 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
 991 {
 992         hsw_disable_pc8(dev_priv);
 993
 994         return 0;
 995 }
 996
 997 /*
 998  * Save all Gunit registers that may be lost after a D3 and a subsequent
 999  * S0i[R123] transition. The list of registers needing a save/restore is
1000  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1001  * registers in the following way:
1002  * - Driver: saved/restored by the driver
1003  * - Punit : saved/restored by the Punit firmware
1004  * - No, w/o marking: no need to save/restore, since the register is R/O or
1005  *                    used internally by the HW in a way that doesn't depend
1006  *                    keeping the content across a suspend/resume.
1007  * - Debug : used for debugging
1008  *
1009  * We save/restore all registers marked with 'Driver', with the following
1010  * exceptions:
1011  * - Registers out of use, including also registers marked with 'Debug'.
1012  *   These have no effect on the driver's operation, so we don't save/restore
1013  *   them to reduce the overhead.
1014  * - Registers that are fully setup by an initialization function called from
1015  *   the resume path. For example many clock gating and RPS/RC6 registers.
1016  * - Registers that provide the right functionality with their reset defaults.
1017  *
1018  * TODO: Except for registers that based on the above 3 criteria can be safely
1019  * ignored, we save/restore all others, practically treating the HW context as
1020  * a black-box for the driver. Further investigation is needed to reduce the
1021  * saved/restored registers even further, by following the same 3 criteria.
1022  */
1023 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1024 {
1025         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1026         int i;
1027
1028         /* GAM 0x4000-0x4770 */
1029         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1030         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1031         s->arb_mode             = I915_READ(ARB_MODE);
1032         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1033         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1034
1035         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1036                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1037
1038         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1039         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1040
1041         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1042         s->ecochk               = I915_READ(GAM_ECOCHK);
1043         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1044         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1045
1046         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1047
1048         /* MBC 0x9024-0x91D0, 0x8500 */
1049         s->g3dctl               = I915_READ(VLV_G3DCTL);
1050         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1051         s->mbctl                = I915_READ(GEN6_MBCTL);
1052
1053         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1054         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1055         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1056         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1057         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1058         s->rstctl               = I915_READ(GEN6_RSTCTL);
1059         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1060
1061         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1062         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1063         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1064         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1065         s->ecobus               = I915_READ(ECOBUS);
1066         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1067         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1068         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1069         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1070         s->rcedata              = I915_READ(VLV_RCEDATA);
1071         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1072
1073         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1074         s->gt_imr               = I915_READ(GTIMR);
1075         s->gt_ier               = I915_READ(GTIER);
1076         s->pm_imr               = I915_READ(GEN6_PMIMR);
1077         s->pm_ier               = I915_READ(GEN6_PMIER);
1078
1079         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1080                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1081
1082         /* GT SA CZ domain, 0x100000-0x138124 */
1083         s->tilectl              = I915_READ(TILECTL);
1084         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1085         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1086         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1087         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1088
1089         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1090         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1091         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1092         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1093
1094         /*
1095          * Not saving any of:
1096          * DFT,         0x9800-0x9EC0
1097          * SARB,        0xB000-0xB1FC
1098          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1099          * PCI CFG
1100          */
1101 }
1102
1103 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1104 {
1105         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1106         u32 val;
1107         int i;
1108
1109         /* GAM 0x4000-0x4770 */
1110         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1111         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1112         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1113         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1114         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1115
1116         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1117                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1118
1119         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1120         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1121
1122         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1123         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1124         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1125         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1126
1127         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1128
1129         /* MBC 0x9024-0x91D0, 0x8500 */
1130         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1131         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1132         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1133
1134         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1135         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1136         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1137         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1138         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1139         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1140         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1141
1142         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1143         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1144         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1145         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1146         I915_WRITE(ECOBUS,              s->ecobus);
1147         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1148         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1149         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1150         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1151         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1152         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1153
1154         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1155         I915_WRITE(GTIMR,               s->gt_imr);
1156         I915_WRITE(GTIER,               s->gt_ier);
1157         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1158         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1159
1160         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1161                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1162
1163         /* GT SA CZ domain, 0x100000-0x138124 */
1164         I915_WRITE(TILECTL,                     s->tilectl);
1165         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1166         /*
1167          * Preserve the GT allow wake and GFX force clock bit, they are not
1168          * be restored, as they are used to control the s0ix suspend/resume
1169          * sequence by the caller.
1170          */
1171         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1172         val &= VLV_GTLC_ALLOWWAKEREQ;
1173         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1174         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1175
1176         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1177         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1178         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1179         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1180
1181         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1182
1183         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1184         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1185         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1186         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1187 }
1188
1189 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1190 {
1191         u32 val;
1192         int err;
1193
1194         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1195         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1196
1197 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1198         /* Wait for a previous force-off to settle */
1199         if (force_on) {
1200                 err = wait_for(!COND, 20);
1201                 if (err) {
1202                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1203                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1204                         return err;
1205                 }
1206         }
1207
1208         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1209         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1210         if (force_on)
1211                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1212         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1213
1214         if (!force_on)
1215                 return 0;
1216
1217         err = wait_for(COND, 20);
1218         if (err)
1219                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1220                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1221
1222         return err;
1223 #undef COND
1224 }
1225
1226 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1227 {
1228         u32 val;
1229         int err = 0;
1230
1231         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1232         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1233         if (allow)
1234                 val |= VLV_GTLC_ALLOWWAKEREQ;
1235         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1236         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1237
1238 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1239               allow)
1240         err = wait_for(COND, 1);
1241         if (err)
1242                 DRM_ERROR("timeout disabling GT waking\n");
1243         return err;
1244 #undef COND
1245 }
1246
1247 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1248                                  bool wait_for_on)
1249 {
1250         u32 mask;
1251         u32 val;
1252         int err;
1253
1254         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1255         val = wait_for_on ? mask : 0;
1256 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1257         if (COND)
1258                 return 0;
1259
1260         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1261                         wait_for_on ? "on" : "off",
1262                         I915_READ(VLV_GTLC_PW_STATUS));
1263
1264         /*
1265          * RC6 transitioning can be delayed up to 2 msec (see
1266          * valleyview_enable_rps), use 3 msec for safety.
1267          */
1268         err = wait_for(COND, 3);
1269         if (err)
1270                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1271                           wait_for_on ? "on" : "off");
1272
1273         return err;
1274 #undef COND
1275 }
1276
1277 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1278 {
1279         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1280                 return;
1281
1282         DRM_ERROR("GT register access while GT waking disabled\n");
1283         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1284 }
1285
1286 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1287 {
1288         u32 mask;
1289         int err;
1290
1291         /*
1292          * Bspec defines the following GT well on flags as debug only, so
1293          * don't treat them as hard failures.
1294          */
1295         (void)vlv_wait_for_gt_wells(dev_priv, false);
1296
1297         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1298         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1299
1300         vlv_check_no_gt_access(dev_priv);
1301
1302         err = vlv_force_gfx_clock(dev_priv, true);
1303         if (err)
1304                 goto err1;
1305
1306         err = vlv_allow_gt_wake(dev_priv, false);
1307         if (err)
1308                 goto err2;
1309         vlv_save_gunit_s0ix_state(dev_priv);
1310
1311         err = vlv_force_gfx_clock(dev_priv, false);
1312         if (err)
1313                 goto err2;
1314
1315         return 0;
1316
1317 err2:
1318         /* For safety always re-enable waking and disable gfx clock forcing */
1319         vlv_allow_gt_wake(dev_priv, true);
1320 err1:
1321         vlv_force_gfx_clock(dev_priv, false);
1322
1323         return err;
1324 }
1325
1326 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1327 {
1328         struct drm_device *dev = dev_priv->dev;
1329         int err;
1330         int ret;
1331
1332         /*
1333          * If any of the steps fail just try to continue, that's the best we
1334          * can do at this point. Return the first error code (which will also
1335          * leave RPM permanently disabled).
1336          */
1337         ret = vlv_force_gfx_clock(dev_priv, true);
1338
1339         vlv_restore_gunit_s0ix_state(dev_priv);
1340
1341         err = vlv_allow_gt_wake(dev_priv, true);
1342         if (!ret)
1343                 ret = err;
1344
1345         err = vlv_force_gfx_clock(dev_priv, false);
1346         if (!ret)
1347                 ret = err;
1348
1349         vlv_check_no_gt_access(dev_priv);
1350
1351         intel_init_clock_gating(dev);
1352         i915_gem_restore_fences(dev);
1353
1354         return ret;
1355 }
1356
1357 static int intel_runtime_suspend(struct device *device)
1358 {
1359         struct pci_dev *pdev = to_pci_dev(device);
1360         struct drm_device *dev = pci_get_drvdata(pdev);
1361         struct drm_i915_private *dev_priv = dev->dev_private;
1362         int ret;
1363
1364         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1365                 return -ENODEV;
1366
1367         WARN_ON(!HAS_RUNTIME_PM(dev));
1368         assert_force_wake_inactive(dev_priv);
1369
1370         DRM_DEBUG_KMS("Suspending device\n");
1371
1372         /*
1373          * We could deadlock here in case another thread holding struct_mutex
1374          * calls RPM suspend concurrently, since the RPM suspend will wait
1375          * first for this RPM suspend to finish. In this case the concurrent
1376          * RPM resume will be followed by its RPM suspend counterpart. Still
1377          * for consistency return -EAGAIN, which will reschedule this suspend.
1378          */
1379         if (!mutex_trylock(&dev->struct_mutex)) {
1380                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1381                 /*
1382                  * Bump the expiration timestamp, otherwise the suspend won't
1383                  * be rescheduled.
1384                  */
1385                 pm_runtime_mark_last_busy(device);
1386
1387                 return -EAGAIN;
1388         }
1389         /*
1390          * We are safe here against re-faults, since the fault handler takes
1391          * an RPM reference.
1392          */
1393         i915_gem_release_all_mmaps(dev_priv);
1394         mutex_unlock(&dev->struct_mutex);
1395
1396         /*
1397          * rps.work can't be rearmed here, since we get here only after making
1398          * sure the GPU is idle and the RPS freq is set to the minimum. See
1399          * intel_mark_idle().
1400          */
1401         cancel_work_sync(&dev_priv->rps.work);
1402         intel_runtime_pm_disable_interrupts(dev);
1403
1404         if (IS_GEN6(dev)) {
1405                 ret = 0;
1406         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1407                 ret = hsw_runtime_suspend(dev_priv);
1408         } else if (IS_VALLEYVIEW(dev)) {
1409                 ret = vlv_runtime_suspend(dev_priv);
1410         } else {
1411                 ret = -ENODEV;
1412                 WARN_ON(1);
1413         }
1414
1415         if (ret) {
1416                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1417                 intel_runtime_pm_restore_interrupts(dev);
1418
1419                 return ret;
1420         }
1421
1422         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1423         dev_priv->pm.suspended = true;
1424
1425         /*
1426          * current versions of firmware which depend on this opregion
1427          * notification have repurposed the D1 definition to mean
1428          * "runtime suspended" vs. what you would normally expect (D3)
1429          * to distinguish it from notifications that might be sent
1430          * via the suspend path.
1431          */
1432         intel_opregion_notify_adapter(dev, PCI_D1);
1433
1434         DRM_DEBUG_KMS("Device suspended\n");
1435         return 0;
1436 }
1437
1438 static int intel_runtime_resume(struct device *device)
1439 {
1440         struct pci_dev *pdev = to_pci_dev(device);
1441         struct drm_device *dev = pci_get_drvdata(pdev);
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int ret;
1444
1445         WARN_ON(!HAS_RUNTIME_PM(dev));
1446
1447         DRM_DEBUG_KMS("Resuming device\n");
1448
1449         intel_opregion_notify_adapter(dev, PCI_D0);
1450         dev_priv->pm.suspended = false;
1451
1452         if (IS_GEN6(dev)) {
1453                 ret = snb_runtime_resume(dev_priv);
1454         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1455                 ret = hsw_runtime_resume(dev_priv);
1456         } else if (IS_VALLEYVIEW(dev)) {
1457                 ret = vlv_runtime_resume(dev_priv);
1458         } else {
1459                 WARN_ON(1);
1460                 ret = -ENODEV;
1461         }
1462
1463         /*
1464          * No point of rolling back things in case of an error, as the best
1465          * we can do is to hope that things will still work (and disable RPM).
1466          */
1467         i915_gem_init_swizzling(dev);
1468         gen6_update_ring_freq(dev);
1469
1470         intel_runtime_pm_restore_interrupts(dev);
1471         intel_reset_gt_powersave(dev);
1472
1473         if (ret)
1474                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1475         else
1476                 DRM_DEBUG_KMS("Device resumed\n");
1477
1478         return ret;
1479 }
1480
1481 static const struct dev_pm_ops i915_pm_ops = {
1482         .suspend = i915_pm_suspend,
1483         .suspend_late = i915_pm_suspend_late,
1484         .resume_early = i915_pm_resume_early,
1485         .resume = i915_pm_resume,
1486         .freeze = i915_pm_freeze,
1487         .thaw_early = i915_pm_thaw_early,
1488         .thaw = i915_pm_thaw,
1489         .poweroff = i915_pm_poweroff,
1490         .restore_early = i915_pm_resume_early,
1491         .restore = i915_pm_resume,
1492         .runtime_suspend = intel_runtime_suspend,
1493         .runtime_resume = intel_runtime_resume,
1494 };
1495
1496 static const struct vm_operations_struct i915_gem_vm_ops = {
1497         .fault = i915_gem_fault,
1498         .open = drm_gem_vm_open,
1499         .close = drm_gem_vm_close,
1500 };
1501
1502 static const struct file_operations i915_driver_fops = {
1503         .owner = THIS_MODULE,
1504         .open = drm_open,
1505         .release = drm_release,
1506         .unlocked_ioctl = drm_ioctl,
1507         .mmap = drm_gem_mmap,
1508         .poll = drm_poll,
1509         .read = drm_read,
1510 #ifdef CONFIG_COMPAT
1511         .compat_ioctl = i915_compat_ioctl,
1512 #endif
1513         .llseek = noop_llseek,
1514 };
1515
1516 static struct drm_driver driver = {
1517         /* Don't use MTRRs here; the Xserver or userspace app should
1518          * deal with them for Intel hardware.
1519          */
1520         .driver_features =
1521             DRIVER_USE_AGP |
1522             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1523             DRIVER_RENDER,
1524         .load = i915_driver_load,
1525         .unload = i915_driver_unload,
1526         .open = i915_driver_open,
1527         .lastclose = i915_driver_lastclose,
1528         .preclose = i915_driver_preclose,
1529         .postclose = i915_driver_postclose,
1530
1531         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1532         .suspend = i915_suspend,
1533         .resume = i915_resume_legacy,
1534
1535         .device_is_agp = i915_driver_device_is_agp,
1536         .master_create = i915_master_create,
1537         .master_destroy = i915_master_destroy,
1538 #if defined(CONFIG_DEBUG_FS)
1539         .debugfs_init = i915_debugfs_init,
1540         .debugfs_cleanup = i915_debugfs_cleanup,
1541 #endif
1542         .gem_free_object = i915_gem_free_object,
1543         .gem_vm_ops = &i915_gem_vm_ops,
1544
1545         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1546         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1547         .gem_prime_export = i915_gem_prime_export,
1548         .gem_prime_import = i915_gem_prime_import,
1549
1550         .dumb_create = i915_gem_dumb_create,
1551         .dumb_map_offset = i915_gem_mmap_gtt,
1552         .dumb_destroy = drm_gem_dumb_destroy,
1553         .ioctls = i915_ioctls,
1554         .fops = &i915_driver_fops,
1555         .name = DRIVER_NAME,
1556         .desc = DRIVER_DESC,
1557         .date = DRIVER_DATE,
1558         .major = DRIVER_MAJOR,
1559         .minor = DRIVER_MINOR,
1560         .patchlevel = DRIVER_PATCHLEVEL,
1561 };
1562
1563 static struct pci_driver i915_pci_driver = {
1564         .name = DRIVER_NAME,
1565         .id_table = pciidlist,
1566         .probe = i915_pci_probe,
1567         .remove = i915_pci_remove,
1568         .driver.pm = &i915_pm_ops,
1569 };
1570
1571 static int __init i915_init(void)
1572 {
1573         driver.num_ioctls = i915_max_ioctl;
1574
1575         /*
1576          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1577          * explicitly disabled with the module pararmeter.
1578          *
1579          * Otherwise, just follow the parameter (defaulting to off).
1580          *
1581          * Allow optional vga_text_mode_force boot option to override
1582          * the default behavior.
1583          */
1584 #if defined(CONFIG_DRM_I915_KMS)
1585         if (i915.modeset != 0)
1586                 driver.driver_features |= DRIVER_MODESET;
1587 #endif
1588         if (i915.modeset == 1)
1589                 driver.driver_features |= DRIVER_MODESET;
1590
1591 #ifdef CONFIG_VGA_CONSOLE
1592         if (vgacon_text_force() && i915.modeset == -1)
1593                 driver.driver_features &= ~DRIVER_MODESET;
1594 #endif
1595
1596         if (!(driver.driver_features & DRIVER_MODESET)) {
1597                 driver.get_vblank_timestamp = NULL;
1598 #ifndef CONFIG_DRM_I915_UMS
1599                 /* Silently fail loading to not upset userspace. */
1600                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1601                 return 0;
1602 #endif
1603         }
1604
1605         return drm_pci_init(&driver, &i915_pci_driver);
1606 }
1607
1608 static void __exit i915_exit(void)
1609 {
1610 #ifndef CONFIG_DRM_I915_UMS
1611         if (!(driver.driver_features & DRIVER_MODESET))
1612                 return; /* Never loaded a driver. */
1613 #endif
1614
1615         drm_pci_exit(&driver, &i915_pci_driver);
1616 }
1617
1618 module_init(i915_init);
1619 module_exit(i915_exit);
1620
1621 MODULE_AUTHOR(DRIVER_AUTHOR);
1622 MODULE_DESCRIPTION(DRIVER_DESC);
1623 MODULE_LICENSE("GPL and additional rights");