drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 unsigned int i915_powersave = 1;
  47 module_param_named(powersave, i915_powersave, int, 0600);
  48
  49 unsigned int i915_lvds_downclock = 0;
  50 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  51
  52 static struct drm_driver driver;
  53 extern int intel_agp_enabled;
  54
  55 #define INTEL_VGA_DEVICE(id, info) {            \
  56         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  57         .class_mask = 0xffff00,                 \
  58         .vendor = 0x8086,                       \
  59         .device = id,                           \
  60         .subvendor = PCI_ANY_ID,                \
  61         .subdevice = PCI_ANY_ID,                \
  62         .driver_data = (unsigned long) info }
  63
  64 static const struct intel_device_info intel_i830_info = {
  65         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  66         .has_overlay = 1, .overlay_needs_physical = 1,
  67 };
  68
  69 static const struct intel_device_info intel_845g_info = {
  70         .gen = 2,
  71         .has_overlay = 1, .overlay_needs_physical = 1,
  72 };
  73
  74 static const struct intel_device_info intel_i85x_info = {
  75         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  76         .cursor_needs_physical = 1,
  77         .has_overlay = 1, .overlay_needs_physical = 1,
  78 };
  79
  80 static const struct intel_device_info intel_i865g_info = {
  81         .gen = 2,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83 };
  84
  85 static const struct intel_device_info intel_i915g_info = {
  86         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88 };
  89 static const struct intel_device_info intel_i915gm_info = {
  90         .gen = 3, .is_mobile = 1,
  91         .cursor_needs_physical = 1,
  92         .has_overlay = 1, .overlay_needs_physical = 1,
  93         .supports_tv = 1,
  94 };
  95 static const struct intel_device_info intel_i945g_info = {
  96         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  97         .has_overlay = 1, .overlay_needs_physical = 1,
  98 };
  99 static const struct intel_device_info intel_i945gm_info = {
 100         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 101         .has_hotplug = 1, .cursor_needs_physical = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .supports_tv = 1,
 104 };
 105
 106 static const struct intel_device_info intel_i965g_info = {
 107         .gen = 4, .is_broadwater = 1,
 108         .has_hotplug = 1,
 109         .has_overlay = 1,
 110 };
 111
 112 static const struct intel_device_info intel_i965gm_info = {
 113         .gen = 4, .is_crestline = 1,
 114         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 115         .has_overlay = 1,
 116         .supports_tv = 1,
 117 };
 118
 119 static const struct intel_device_info intel_g33_info = {
 120         .gen = 3, .is_g33 = 1,
 121         .need_gfx_hws = 1, .has_hotplug = 1,
 122         .has_overlay = 1,
 123 };
 124
 125 static const struct intel_device_info intel_g45_info = {
 126         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 127         .has_pipe_cxsr = 1, .has_hotplug = 1,
 128         .has_bsd_ring = 1,
 129 };
 130
 131 static const struct intel_device_info intel_gm45_info = {
 132         .gen = 4, .is_g4x = 1,
 133         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 134         .has_pipe_cxsr = 1, .has_hotplug = 1,
 135         .supports_tv = 1,
 136         .has_bsd_ring = 1,
 137 };
 138
 139 static const struct intel_device_info intel_pineview_info = {
 140         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 141         .need_gfx_hws = 1, .has_hotplug = 1,
 142         .has_overlay = 1,
 143 };
 144
 145 static const struct intel_device_info intel_ironlake_d_info = {
 146         .gen = 5,
 147         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 148         .has_bsd_ring = 1,
 149 };
 150
 151 static const struct intel_device_info intel_ironlake_m_info = {
 152         .gen = 5, .is_mobile = 1,
 153         .need_gfx_hws = 1, .has_hotplug = 1,
 154         .has_fbc = 0, /* disabled due to buggy hardware */
 155         .has_bsd_ring = 1,
 156 };
 157
 158 static const struct intel_device_info intel_sandybridge_d_info = {
 159         .gen = 6,
 160         .need_gfx_hws = 1, .has_hotplug = 1,
 161         .has_bsd_ring = 1,
 162         .has_blt_ring = 1,
 163 };
 164
 165 static const struct intel_device_info intel_sandybridge_m_info = {
 166         .gen = 6, .is_mobile = 1,
 167         .need_gfx_hws = 1, .has_hotplug = 1,
 168         .has_fbc = 1,
 169         .has_bsd_ring = 1,
 170         .has_blt_ring = 1,
 171 };
 172
 173 static const struct pci_device_id pciidlist[] = {               /* aka */
 174         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 175         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 176         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 177         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 178         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 179         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 180         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 181         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 182         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 183         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 184         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 185         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 186         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 187         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 188         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 189         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 190         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 191         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 192         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 193         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 194         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 195         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 196         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 197         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 198         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 199         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 200         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 201         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 202         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 203         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 204         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 205         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 206         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 207         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 208         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 209         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 210         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 211         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 212         {0, 0, 0}
 213 };
 214
 215 #if defined(CONFIG_DRM_I915_KMS)
 216 MODULE_DEVICE_TABLE(pci, pciidlist);
 217 #endif
 218
 219 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 220 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 221
 222 void intel_detect_pch (struct drm_device *dev)
 223 {
 224         struct drm_i915_private *dev_priv = dev->dev_private;
 225         struct pci_dev *pch;
 226
 227         /*
 228          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 229          * make graphics device passthrough work easy for VMM, that only
 230          * need to expose ISA bridge to let driver know the real hardware
 231          * underneath. This is a requirement from virtualization team.
 232          */
 233         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 234         if (pch) {
 235                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 236                         int id;
 237                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 238
 239                         if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 240                                 dev_priv->pch_type = PCH_CPT;
 241                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 242                         }
 243                 }
 244                 pci_dev_put(pch);
 245         }
 246 }
 247
 248 void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
 249 {
 250         int count;
 251
 252         count = 0;
 253         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 254                 udelay(10);
 255
 256         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 257         POSTING_READ(FORCEWAKE);
 258
 259         count = 0;
 260         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 261                 udelay(10);
 262 }
 263
 264 void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
 265 {
 266         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 267         POSTING_READ(FORCEWAKE);
 268 }
 269
 270 static int i915_drm_freeze(struct drm_device *dev)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         drm_kms_helper_poll_disable(dev);
 275
 276         pci_save_state(dev->pdev);
 277
 278         /* If KMS is active, we do the leavevt stuff here */
 279         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 280                 int error = i915_gem_idle(dev);
 281                 if (error) {
 282                         dev_err(&dev->pdev->dev,
 283                                 "GEM idle failed, resume might fail\n");
 284                         return error;
 285                 }
 286                 drm_irq_uninstall(dev);
 287         }
 288
 289         i915_save_state(dev);
 290
 291         intel_opregion_fini(dev);
 292
 293         /* Modeset on resume, not lid events */
 294         dev_priv->modeset_on_lid = 0;
 295
 296         return 0;
 297 }
 298
 299 int i915_suspend(struct drm_device *dev, pm_message_t state)
 300 {
 301         int error;
 302
 303         if (!dev || !dev->dev_private) {
 304                 DRM_ERROR("dev: %p\n", dev);
 305                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 306                 return -ENODEV;
 307         }
 308
 309         if (state.event == PM_EVENT_PRETHAW)
 310                 return 0;
 311
 312
 313         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 314                 return 0;
 315
 316         error = i915_drm_freeze(dev);
 317         if (error)
 318                 return error;
 319
 320         if (state.event == PM_EVENT_SUSPEND) {
 321                 /* Shut down the device */
 322                 pci_disable_device(dev->pdev);
 323                 pci_set_power_state(dev->pdev, PCI_D3hot);
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int i915_drm_thaw(struct drm_device *dev)
 330 {
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332         int error = 0;
 333
 334         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 335                 mutex_lock(&dev->struct_mutex);
 336                 i915_gem_restore_gtt_mappings(dev);
 337                 mutex_unlock(&dev->struct_mutex);
 338         }
 339
 340         i915_restore_state(dev);
 341         intel_opregion_setup(dev);
 342
 343         /* KMS EnterVT equivalent */
 344         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 345                 mutex_lock(&dev->struct_mutex);
 346                 dev_priv->mm.suspended = 0;
 347
 348                 error = i915_gem_init_ringbuffer(dev);
 349                 mutex_unlock(&dev->struct_mutex);
 350
 351                 drm_irq_install(dev);
 352
 353                 /* Resume the modeset for every activated CRTC */
 354                 drm_helper_resume_force_mode(dev);
 355         }
 356
 357         intel_opregion_init(dev);
 358
 359         dev_priv->modeset_on_lid = 0;
 360
 361         return error;
 362 }
 363
 364 int i915_resume(struct drm_device *dev)
 365 {
 366         int ret;
 367
 368         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 369                 return 0;
 370
 371         if (pci_enable_device(dev->pdev))
 372                 return -EIO;
 373
 374         pci_set_master(dev->pdev);
 375
 376         ret = i915_drm_thaw(dev);
 377         if (ret)
 378                 return ret;
 379
 380         drm_kms_helper_poll_enable(dev);
 381         return 0;
 382 }
 383
 384 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 385 {
 386         struct drm_i915_private *dev_priv = dev->dev_private;
 387
 388         if (IS_I85X(dev))
 389                 return -ENODEV;
 390
 391         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 392         POSTING_READ(D_STATE);
 393
 394         if (IS_I830(dev) || IS_845G(dev)) {
 395                 I915_WRITE(DEBUG_RESET_I830,
 396                            DEBUG_RESET_DISPLAY |
 397                            DEBUG_RESET_RENDER |
 398                            DEBUG_RESET_FULL);
 399                 POSTING_READ(DEBUG_RESET_I830);
 400                 msleep(1);
 401
 402                 I915_WRITE(DEBUG_RESET_I830, 0);
 403                 POSTING_READ(DEBUG_RESET_I830);
 404         }
 405
 406         msleep(1);
 407
 408         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 409         POSTING_READ(D_STATE);
 410
 411         return 0;
 412 }
 413
 414 static int i965_reset_complete(struct drm_device *dev)
 415 {
 416         u8 gdrst;
 417         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 418         return gdrst & 0x1;
 419 }
 420
 421 static int i965_do_reset(struct drm_device *dev, u8 flags)
 422 {
 423         u8 gdrst;
 424
 425         /*
 426          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 427          * well as the reset bit (GR/bit 0).  Setting the GR bit
 428          * triggers the reset; when done, the hardware will clear it.
 429          */
 430         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 431         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 432
 433         return wait_for(i965_reset_complete(dev), 500);
 434 }
 435
 436 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 437 {
 438         struct drm_i915_private *dev_priv = dev->dev_private;
 439         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 440         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 441         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 442 }
 443
 444 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 445 {
 446         struct drm_i915_private *dev_priv = dev->dev_private;
 447
 448         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 449         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 450 }
 451
 452 /**
 453  * i965_reset - reset chip after a hang
 454  * @dev: drm device to reset
 455  * @flags: reset domains
 456  *
 457  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 458  * reset or otherwise an error code.
 459  *
 460  * Procedure is fairly simple:
 461  *   - reset the chip using the reset reg
 462  *   - re-init context state
 463  *   - re-init hardware status page
 464  *   - re-init ring buffer
 465  *   - re-init interrupt state
 466  *   - re-init display
 467  */
 468 int i915_reset(struct drm_device *dev, u8 flags)
 469 {
 470         drm_i915_private_t *dev_priv = dev->dev_private;
 471         /*
 472          * We really should only reset the display subsystem if we actually
 473          * need to
 474          */
 475         bool need_display = true;
 476         int ret;
 477
 478         if (!mutex_trylock(&dev->struct_mutex))
 479                 return -EBUSY;
 480
 481         i915_gem_reset(dev);
 482
 483         ret = -ENODEV;
 484         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 485                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 486         } else switch (INTEL_INFO(dev)->gen) {
 487         case 6:
 488                 ret = gen6_do_reset(dev, flags);
 489                 break;
 490         case 5:
 491                 ret = ironlake_do_reset(dev, flags);
 492                 break;
 493         case 4:
 494                 ret = i965_do_reset(dev, flags);
 495                 break;
 496         case 2:
 497                 ret = i8xx_do_reset(dev, flags);
 498                 break;
 499         }
 500         dev_priv->last_gpu_reset = get_seconds();
 501         if (ret) {
 502                 DRM_ERROR("Failed to reset chip.\n");
 503                 mutex_unlock(&dev->struct_mutex);
 504                 return ret;
 505         }
 506
 507         /* Ok, now get things going again... */
 508
 509         /*
 510          * Everything depends on having the GTT running, so we need to start
 511          * there.  Fortunately we don't need to do this unless we reset the
 512          * chip at a PCI level.
 513          *
 514          * Next we need to restore the context, but we don't use those
 515          * yet either...
 516          *
 517          * Ring buffer needs to be re-initialized in the KMS case, or if X
 518          * was running at the time of the reset (i.e. we weren't VT
 519          * switched away).
 520          */
 521         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 522                         !dev_priv->mm.suspended) {
 523                 dev_priv->mm.suspended = 0;
 524
 525                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 526                 if (HAS_BSD(dev))
 527                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 528                 if (HAS_BLT(dev))
 529                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 530
 531                 mutex_unlock(&dev->struct_mutex);
 532                 drm_irq_uninstall(dev);
 533                 drm_irq_install(dev);
 534                 mutex_lock(&dev->struct_mutex);
 535         }
 536
 537         mutex_unlock(&dev->struct_mutex);
 538
 539         /*
 540          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 541          * need to retrain the display link and cannot just restore the register
 542          * values.
 543          */
 544         if (need_display) {
 545                 mutex_lock(&dev->mode_config.mutex);
 546                 drm_helper_resume_force_mode(dev);
 547                 mutex_unlock(&dev->mode_config.mutex);
 548         }
 549
 550         return 0;
 551 }
 552
 553
 554 static int __devinit
 555 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 556 {
 557         return drm_get_pci_dev(pdev, ent, &driver);
 558 }
 559
 560 static void
 561 i915_pci_remove(struct pci_dev *pdev)
 562 {
 563         struct drm_device *dev = pci_get_drvdata(pdev);
 564
 565         drm_put_dev(dev);
 566 }
 567
 568 static int i915_pm_suspend(struct device *dev)
 569 {
 570         struct pci_dev *pdev = to_pci_dev(dev);
 571         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 572         int error;
 573
 574         if (!drm_dev || !drm_dev->dev_private) {
 575                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 576                 return -ENODEV;
 577         }
 578
 579         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 580                 return 0;
 581
 582         error = i915_drm_freeze(drm_dev);
 583         if (error)
 584                 return error;
 585
 586         pci_disable_device(pdev);
 587         pci_set_power_state(pdev, PCI_D3hot);
 588
 589         return 0;
 590 }
 591
 592 static int i915_pm_resume(struct device *dev)
 593 {
 594         struct pci_dev *pdev = to_pci_dev(dev);
 595         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 596
 597         return i915_resume(drm_dev);
 598 }
 599
 600 static int i915_pm_freeze(struct device *dev)
 601 {
 602         struct pci_dev *pdev = to_pci_dev(dev);
 603         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 604
 605         if (!drm_dev || !drm_dev->dev_private) {
 606                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 607                 return -ENODEV;
 608         }
 609
 610         return i915_drm_freeze(drm_dev);
 611 }
 612
 613 static int i915_pm_thaw(struct device *dev)
 614 {
 615         struct pci_dev *pdev = to_pci_dev(dev);
 616         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 617
 618         return i915_drm_thaw(drm_dev);
 619 }
 620
 621 static int i915_pm_poweroff(struct device *dev)
 622 {
 623         struct pci_dev *pdev = to_pci_dev(dev);
 624         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 625
 626         return i915_drm_freeze(drm_dev);
 627 }
 628
 629 static const struct dev_pm_ops i915_pm_ops = {
 630      .suspend = i915_pm_suspend,
 631      .resume = i915_pm_resume,
 632      .freeze = i915_pm_freeze,
 633      .thaw = i915_pm_thaw,
 634      .poweroff = i915_pm_poweroff,
 635      .restore = i915_pm_resume,
 636 };
 637
 638 static struct vm_operations_struct i915_gem_vm_ops = {
 639         .fault = i915_gem_fault,
 640         .open = drm_gem_vm_open,
 641         .close = drm_gem_vm_close,
 642 };
 643
 644 static struct drm_driver driver = {
 645         /* don't use mtrr's here, the Xserver or user space app should
 646          * deal with them for intel hardware.
 647          */
 648         .driver_features =
 649             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 650             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 651         .load = i915_driver_load,
 652         .unload = i915_driver_unload,
 653         .open = i915_driver_open,
 654         .lastclose = i915_driver_lastclose,
 655         .preclose = i915_driver_preclose,
 656         .postclose = i915_driver_postclose,
 657
 658         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 659         .suspend = i915_suspend,
 660         .resume = i915_resume,
 661
 662         .device_is_agp = i915_driver_device_is_agp,
 663         .enable_vblank = i915_enable_vblank,
 664         .disable_vblank = i915_disable_vblank,
 665         .get_vblank_timestamp = i915_get_vblank_timestamp,
 666         .get_scanout_position = i915_get_crtc_scanoutpos,
 667         .irq_preinstall = i915_driver_irq_preinstall,
 668         .irq_postinstall = i915_driver_irq_postinstall,
 669         .irq_uninstall = i915_driver_irq_uninstall,
 670         .irq_handler = i915_driver_irq_handler,
 671         .reclaim_buffers = drm_core_reclaim_buffers,
 672         .master_create = i915_master_create,
 673         .master_destroy = i915_master_destroy,
 674 #if defined(CONFIG_DEBUG_FS)
 675         .debugfs_init = i915_debugfs_init,
 676         .debugfs_cleanup = i915_debugfs_cleanup,
 677 #endif
 678         .gem_init_object = i915_gem_init_object,
 679         .gem_free_object = i915_gem_free_object,
 680         .gem_vm_ops = &i915_gem_vm_ops,
 681         .ioctls = i915_ioctls,
 682         .fops = {
 683                  .owner = THIS_MODULE,
 684                  .open = drm_open,
 685                  .release = drm_release,
 686                  .unlocked_ioctl = drm_ioctl,
 687                  .mmap = drm_gem_mmap,
 688                  .poll = drm_poll,
 689                  .fasync = drm_fasync,
 690                  .read = drm_read,
 691 #ifdef CONFIG_COMPAT
 692                  .compat_ioctl = i915_compat_ioctl,
 693 #endif
 694                  .llseek = noop_llseek,
 695         },
 696
 697         .pci_driver = {
 698                  .name = DRIVER_NAME,
 699                  .id_table = pciidlist,
 700                  .probe = i915_pci_probe,
 701                  .remove = i915_pci_remove,
 702                  .driver.pm = &i915_pm_ops,
 703         },
 704
 705         .name = DRIVER_NAME,
 706         .desc = DRIVER_DESC,
 707         .date = DRIVER_DATE,
 708         .major = DRIVER_MAJOR,
 709         .minor = DRIVER_MINOR,
 710         .patchlevel = DRIVER_PATCHLEVEL,
 711 };
 712
 713 static int __init i915_init(void)
 714 {
 715         if (!intel_agp_enabled) {
 716                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 717                 return -ENODEV;
 718         }
 719
 720         driver.num_ioctls = i915_max_ioctl;
 721
 722         /*
 723          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 724          * explicitly disabled with the module pararmeter.
 725          *
 726          * Otherwise, just follow the parameter (defaulting to off).
 727          *
 728          * Allow optional vga_text_mode_force boot option to override
 729          * the default behavior.
 730          */
 731 #if defined(CONFIG_DRM_I915_KMS)
 732         if (i915_modeset != 0)
 733                 driver.driver_features |= DRIVER_MODESET;
 734 #endif
 735         if (i915_modeset == 1)
 736                 driver.driver_features |= DRIVER_MODESET;
 737
 738 #ifdef CONFIG_VGA_CONSOLE
 739         if (vgacon_text_force() && i915_modeset == -1)
 740                 driver.driver_features &= ~DRIVER_MODESET;
 741 #endif
 742
 743         return drm_init(&driver);
 744 }
 745
 746 static void __exit i915_exit(void)
 747 {
 748         drm_exit(&driver);
 749 }
 750
 751 module_init(i915_init);
 752 module_exit(i915_exit);
 753
 754 MODULE_AUTHOR(DRIVER_AUTHOR);
 755 MODULE_DESCRIPTION(DRIVER_DESC);
 756 MODULE_LICENSE("GPL and additional rights");