drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 unsigned int i915_powersave = 1;
  47 module_param_named(powersave, i915_powersave, int, 0600);
  48
  49 unsigned int i915_lvds_downclock = 0;
  50 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  51
  52 static struct drm_driver driver;
  53 extern int intel_agp_enabled;
  54
  55 #define INTEL_VGA_DEVICE(id, info) {            \
  56         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  57         .class_mask = 0xffff00,                 \
  58         .vendor = 0x8086,                       \
  59         .device = id,                           \
  60         .subvendor = PCI_ANY_ID,                \
  61         .subdevice = PCI_ANY_ID,                \
  62         .driver_data = (unsigned long) info }
  63
  64 static const struct intel_device_info intel_i830_info = {
  65         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  66         .has_overlay = 1, .overlay_needs_physical = 1,
  67 };
  68
  69 static const struct intel_device_info intel_845g_info = {
  70         .gen = 2,
  71         .has_overlay = 1, .overlay_needs_physical = 1,
  72 };
  73
  74 static const struct intel_device_info intel_i85x_info = {
  75         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  76         .cursor_needs_physical = 1,
  77         .has_overlay = 1, .overlay_needs_physical = 1,
  78 };
  79
  80 static const struct intel_device_info intel_i865g_info = {
  81         .gen = 2,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83 };
  84
  85 static const struct intel_device_info intel_i915g_info = {
  86         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88 };
  89 static const struct intel_device_info intel_i915gm_info = {
  90         .gen = 3, .is_mobile = 1,
  91         .cursor_needs_physical = 1,
  92         .has_overlay = 1, .overlay_needs_physical = 1,
  93         .supports_tv = 1,
  94 };
  95 static const struct intel_device_info intel_i945g_info = {
  96         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  97         .has_overlay = 1, .overlay_needs_physical = 1,
  98 };
  99 static const struct intel_device_info intel_i945gm_info = {
 100         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 101         .has_hotplug = 1, .cursor_needs_physical = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .supports_tv = 1,
 104 };
 105
 106 static const struct intel_device_info intel_i965g_info = {
 107         .gen = 4, .is_broadwater = 1,
 108         .has_hotplug = 1,
 109         .has_overlay = 1,
 110 };
 111
 112 static const struct intel_device_info intel_i965gm_info = {
 113         .gen = 4, .is_crestline = 1,
 114         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 115         .has_overlay = 1,
 116         .supports_tv = 1,
 117 };
 118
 119 static const struct intel_device_info intel_g33_info = {
 120         .gen = 3, .is_g33 = 1,
 121         .need_gfx_hws = 1, .has_hotplug = 1,
 122         .has_overlay = 1,
 123 };
 124
 125 static const struct intel_device_info intel_g45_info = {
 126         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 127         .has_pipe_cxsr = 1, .has_hotplug = 1,
 128         .has_bsd_ring = 1,
 129 };
 130
 131 static const struct intel_device_info intel_gm45_info = {
 132         .gen = 4, .is_g4x = 1,
 133         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 134         .has_pipe_cxsr = 1, .has_hotplug = 1,
 135         .supports_tv = 1,
 136         .has_bsd_ring = 1,
 137 };
 138
 139 static const struct intel_device_info intel_pineview_info = {
 140         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 141         .need_gfx_hws = 1, .has_hotplug = 1,
 142         .has_overlay = 1,
 143 };
 144
 145 static const struct intel_device_info intel_ironlake_d_info = {
 146         .gen = 5,
 147         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 148         .has_bsd_ring = 1,
 149 };
 150
 151 static const struct intel_device_info intel_ironlake_m_info = {
 152         .gen = 5, .is_mobile = 1,
 153         .need_gfx_hws = 1, .has_hotplug = 1,
 154         .has_fbc = 0, /* disabled due to buggy hardware */
 155         .has_bsd_ring = 1,
 156 };
 157
 158 static const struct intel_device_info intel_sandybridge_d_info = {
 159         .gen = 6,
 160         .need_gfx_hws = 1, .has_hotplug = 1,
 161         .has_bsd_ring = 1,
 162         .has_blt_ring = 1,
 163 };
 164
 165 static const struct intel_device_info intel_sandybridge_m_info = {
 166         .gen = 6, .is_mobile = 1,
 167         .need_gfx_hws = 1, .has_hotplug = 1,
 168         .has_bsd_ring = 1,
 169         .has_blt_ring = 1,
 170 };
 171
 172 static const struct pci_device_id pciidlist[] = {               /* aka */
 173         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 174         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 175         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 176         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 177         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 178         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 179         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 180         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 181         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 182         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 183         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 184         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 185         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 186         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 187         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 188         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 189         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 190         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 191         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 192         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 193         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 194         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 195         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 196         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 197         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 198         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 199         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 200         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 201         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 202         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 203         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 204         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 205         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 206         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 207         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 208         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 209         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 210         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 211         {0, 0, 0}
 212 };
 213
 214 #if defined(CONFIG_DRM_I915_KMS)
 215 MODULE_DEVICE_TABLE(pci, pciidlist);
 216 #endif
 217
 218 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 219 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 220
 221 void intel_detect_pch (struct drm_device *dev)
 222 {
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct pci_dev *pch;
 225
 226         /*
 227          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 228          * make graphics device passthrough work easy for VMM, that only
 229          * need to expose ISA bridge to let driver know the real hardware
 230          * underneath. This is a requirement from virtualization team.
 231          */
 232         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 233         if (pch) {
 234                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 235                         int id;
 236                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 237
 238                         if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 239                                 dev_priv->pch_type = PCH_CPT;
 240                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 241                         }
 242                 }
 243                 pci_dev_put(pch);
 244         }
 245 }
 246
 247 void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
 248 {
 249         int count;
 250
 251         count = 0;
 252         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 253                 udelay(10);
 254
 255         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 256         POSTING_READ(FORCEWAKE);
 257
 258         count = 0;
 259         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 260                 udelay(10);
 261 }
 262
 263 void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
 264 {
 265         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 266         POSTING_READ(FORCEWAKE);
 267 }
 268
 269 static int i915_drm_freeze(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         pci_save_state(dev->pdev);
 274
 275         /* If KMS is active, we do the leavevt stuff here */
 276         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 277                 int error = i915_gem_idle(dev);
 278                 if (error) {
 279                         dev_err(&dev->pdev->dev,
 280                                 "GEM idle failed, resume might fail\n");
 281                         return error;
 282                 }
 283                 drm_irq_uninstall(dev);
 284         }
 285
 286         i915_save_state(dev);
 287
 288         intel_opregion_fini(dev);
 289
 290         /* Modeset on resume, not lid events */
 291         dev_priv->modeset_on_lid = 0;
 292
 293         return 0;
 294 }
 295
 296 int i915_suspend(struct drm_device *dev, pm_message_t state)
 297 {
 298         int error;
 299
 300         if (!dev || !dev->dev_private) {
 301                 DRM_ERROR("dev: %p\n", dev);
 302                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 303                 return -ENODEV;
 304         }
 305
 306         if (state.event == PM_EVENT_PRETHAW)
 307                 return 0;
 308
 309         drm_kms_helper_poll_disable(dev);
 310
 311         error = i915_drm_freeze(dev);
 312         if (error)
 313                 return error;
 314
 315         if (state.event == PM_EVENT_SUSPEND) {
 316                 /* Shut down the device */
 317                 pci_disable_device(dev->pdev);
 318                 pci_set_power_state(dev->pdev, PCI_D3hot);
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int i915_drm_thaw(struct drm_device *dev)
 325 {
 326         struct drm_i915_private *dev_priv = dev->dev_private;
 327         int error = 0;
 328
 329         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 330                 mutex_lock(&dev->struct_mutex);
 331                 i915_gem_restore_gtt_mappings(dev);
 332                 mutex_unlock(&dev->struct_mutex);
 333         }
 334
 335         i915_restore_state(dev);
 336         intel_opregion_setup(dev);
 337
 338         /* KMS EnterVT equivalent */
 339         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 340                 mutex_lock(&dev->struct_mutex);
 341                 dev_priv->mm.suspended = 0;
 342
 343                 error = i915_gem_init_ringbuffer(dev);
 344                 mutex_unlock(&dev->struct_mutex);
 345
 346                 drm_irq_install(dev);
 347
 348                 /* Resume the modeset for every activated CRTC */
 349                 drm_helper_resume_force_mode(dev);
 350         }
 351
 352         intel_opregion_init(dev);
 353
 354         dev_priv->modeset_on_lid = 0;
 355
 356         return error;
 357 }
 358
 359 int i915_resume(struct drm_device *dev)
 360 {
 361         int ret;
 362
 363         if (pci_enable_device(dev->pdev))
 364                 return -EIO;
 365
 366         pci_set_master(dev->pdev);
 367
 368         ret = i915_drm_thaw(dev);
 369         if (ret)
 370                 return ret;
 371
 372         drm_kms_helper_poll_enable(dev);
 373         return 0;
 374 }
 375
 376 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 377 {
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379
 380         if (IS_I85X(dev))
 381                 return -ENODEV;
 382
 383         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 384         POSTING_READ(D_STATE);
 385
 386         if (IS_I830(dev) || IS_845G(dev)) {
 387                 I915_WRITE(DEBUG_RESET_I830,
 388                            DEBUG_RESET_DISPLAY |
 389                            DEBUG_RESET_RENDER |
 390                            DEBUG_RESET_FULL);
 391                 POSTING_READ(DEBUG_RESET_I830);
 392                 msleep(1);
 393
 394                 I915_WRITE(DEBUG_RESET_I830, 0);
 395                 POSTING_READ(DEBUG_RESET_I830);
 396         }
 397
 398         msleep(1);
 399
 400         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 401         POSTING_READ(D_STATE);
 402
 403         return 0;
 404 }
 405
 406 static int i965_reset_complete(struct drm_device *dev)
 407 {
 408         u8 gdrst;
 409         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 410         return gdrst & 0x1;
 411 }
 412
 413 static int i965_do_reset(struct drm_device *dev, u8 flags)
 414 {
 415         u8 gdrst;
 416
 417         /*
 418          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 419          * well as the reset bit (GR/bit 0).  Setting the GR bit
 420          * triggers the reset; when done, the hardware will clear it.
 421          */
 422         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 423         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 424
 425         return wait_for(i965_reset_complete(dev), 500);
 426 }
 427
 428 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 429 {
 430         struct drm_i915_private *dev_priv = dev->dev_private;
 431         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 432         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 433         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 434 }
 435
 436 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 437 {
 438         struct drm_i915_private *dev_priv = dev->dev_private;
 439
 440         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 441         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 442 }
 443
 444 /**
 445  * i965_reset - reset chip after a hang
 446  * @dev: drm device to reset
 447  * @flags: reset domains
 448  *
 449  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 450  * reset or otherwise an error code.
 451  *
 452  * Procedure is fairly simple:
 453  *   - reset the chip using the reset reg
 454  *   - re-init context state
 455  *   - re-init hardware status page
 456  *   - re-init ring buffer
 457  *   - re-init interrupt state
 458  *   - re-init display
 459  */
 460 int i915_reset(struct drm_device *dev, u8 flags)
 461 {
 462         drm_i915_private_t *dev_priv = dev->dev_private;
 463         /*
 464          * We really should only reset the display subsystem if we actually
 465          * need to
 466          */
 467         bool need_display = true;
 468         int ret;
 469
 470         if (!mutex_trylock(&dev->struct_mutex))
 471                 return -EBUSY;
 472
 473         i915_gem_reset(dev);
 474
 475         ret = -ENODEV;
 476         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 477                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 478         } else switch (INTEL_INFO(dev)->gen) {
 479         case 6:
 480                 ret = gen6_do_reset(dev, flags);
 481                 break;
 482         case 5:
 483                 ret = ironlake_do_reset(dev, flags);
 484                 break;
 485         case 4:
 486                 ret = i965_do_reset(dev, flags);
 487                 break;
 488         case 2:
 489                 ret = i8xx_do_reset(dev, flags);
 490                 break;
 491         }
 492         dev_priv->last_gpu_reset = get_seconds();
 493         if (ret) {
 494                 DRM_ERROR("Failed to reset chip.\n");
 495                 mutex_unlock(&dev->struct_mutex);
 496                 return ret;
 497         }
 498
 499         /* Ok, now get things going again... */
 500
 501         /*
 502          * Everything depends on having the GTT running, so we need to start
 503          * there.  Fortunately we don't need to do this unless we reset the
 504          * chip at a PCI level.
 505          *
 506          * Next we need to restore the context, but we don't use those
 507          * yet either...
 508          *
 509          * Ring buffer needs to be re-initialized in the KMS case, or if X
 510          * was running at the time of the reset (i.e. we weren't VT
 511          * switched away).
 512          */
 513         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 514                         !dev_priv->mm.suspended) {
 515                 dev_priv->mm.suspended = 0;
 516
 517                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 518                 if (HAS_BSD(dev))
 519                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 520                 if (HAS_BLT(dev))
 521                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 522
 523                 mutex_unlock(&dev->struct_mutex);
 524                 drm_irq_uninstall(dev);
 525                 drm_irq_install(dev);
 526                 mutex_lock(&dev->struct_mutex);
 527         }
 528
 529         mutex_unlock(&dev->struct_mutex);
 530
 531         /*
 532          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 533          * need to retrain the display link and cannot just restore the register
 534          * values.
 535          */
 536         if (need_display) {
 537                 mutex_lock(&dev->mode_config.mutex);
 538                 drm_helper_resume_force_mode(dev);
 539                 mutex_unlock(&dev->mode_config.mutex);
 540         }
 541
 542         return 0;
 543 }
 544
 545
 546 static int __devinit
 547 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 548 {
 549         return drm_get_pci_dev(pdev, ent, &driver);
 550 }
 551
 552 static void
 553 i915_pci_remove(struct pci_dev *pdev)
 554 {
 555         struct drm_device *dev = pci_get_drvdata(pdev);
 556
 557         drm_put_dev(dev);
 558 }
 559
 560 static int i915_pm_suspend(struct device *dev)
 561 {
 562         struct pci_dev *pdev = to_pci_dev(dev);
 563         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 564         int error;
 565
 566         if (!drm_dev || !drm_dev->dev_private) {
 567                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 568                 return -ENODEV;
 569         }
 570
 571         error = i915_drm_freeze(drm_dev);
 572         if (error)
 573                 return error;
 574
 575         pci_disable_device(pdev);
 576         pci_set_power_state(pdev, PCI_D3hot);
 577
 578         return 0;
 579 }
 580
 581 static int i915_pm_resume(struct device *dev)
 582 {
 583         struct pci_dev *pdev = to_pci_dev(dev);
 584         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 585
 586         return i915_resume(drm_dev);
 587 }
 588
 589 static int i915_pm_freeze(struct device *dev)
 590 {
 591         struct pci_dev *pdev = to_pci_dev(dev);
 592         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 593
 594         if (!drm_dev || !drm_dev->dev_private) {
 595                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 596                 return -ENODEV;
 597         }
 598
 599         return i915_drm_freeze(drm_dev);
 600 }
 601
 602 static int i915_pm_thaw(struct device *dev)
 603 {
 604         struct pci_dev *pdev = to_pci_dev(dev);
 605         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 606
 607         return i915_drm_thaw(drm_dev);
 608 }
 609
 610 static int i915_pm_poweroff(struct device *dev)
 611 {
 612         struct pci_dev *pdev = to_pci_dev(dev);
 613         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 614
 615         return i915_drm_freeze(drm_dev);
 616 }
 617
 618 static const struct dev_pm_ops i915_pm_ops = {
 619      .suspend = i915_pm_suspend,
 620      .resume = i915_pm_resume,
 621      .freeze = i915_pm_freeze,
 622      .thaw = i915_pm_thaw,
 623      .poweroff = i915_pm_poweroff,
 624      .restore = i915_pm_resume,
 625 };
 626
 627 static struct vm_operations_struct i915_gem_vm_ops = {
 628         .fault = i915_gem_fault,
 629         .open = drm_gem_vm_open,
 630         .close = drm_gem_vm_close,
 631 };
 632
 633 static struct drm_driver driver = {
 634         /* don't use mtrr's here, the Xserver or user space app should
 635          * deal with them for intel hardware.
 636          */
 637         .driver_features =
 638             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 639             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 640         .load = i915_driver_load,
 641         .unload = i915_driver_unload,
 642         .open = i915_driver_open,
 643         .lastclose = i915_driver_lastclose,
 644         .preclose = i915_driver_preclose,
 645         .postclose = i915_driver_postclose,
 646
 647         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 648         .suspend = i915_suspend,
 649         .resume = i915_resume,
 650
 651         .device_is_agp = i915_driver_device_is_agp,
 652         .enable_vblank = i915_enable_vblank,
 653         .disable_vblank = i915_disable_vblank,
 654         .irq_preinstall = i915_driver_irq_preinstall,
 655         .irq_postinstall = i915_driver_irq_postinstall,
 656         .irq_uninstall = i915_driver_irq_uninstall,
 657         .irq_handler = i915_driver_irq_handler,
 658         .reclaim_buffers = drm_core_reclaim_buffers,
 659         .master_create = i915_master_create,
 660         .master_destroy = i915_master_destroy,
 661 #if defined(CONFIG_DEBUG_FS)
 662         .debugfs_init = i915_debugfs_init,
 663         .debugfs_cleanup = i915_debugfs_cleanup,
 664 #endif
 665         .gem_init_object = i915_gem_init_object,
 666         .gem_free_object = i915_gem_free_object,
 667         .gem_vm_ops = &i915_gem_vm_ops,
 668         .ioctls = i915_ioctls,
 669         .fops = {
 670                  .owner = THIS_MODULE,
 671                  .open = drm_open,
 672                  .release = drm_release,
 673                  .unlocked_ioctl = drm_ioctl,
 674                  .mmap = drm_gem_mmap,
 675                  .poll = drm_poll,
 676                  .fasync = drm_fasync,
 677                  .read = drm_read,
 678 #ifdef CONFIG_COMPAT
 679                  .compat_ioctl = i915_compat_ioctl,
 680 #endif
 681                  .llseek = noop_llseek,
 682         },
 683
 684         .pci_driver = {
 685                  .name = DRIVER_NAME,
 686                  .id_table = pciidlist,
 687                  .probe = i915_pci_probe,
 688                  .remove = i915_pci_remove,
 689                  .driver.pm = &i915_pm_ops,
 690         },
 691
 692         .name = DRIVER_NAME,
 693         .desc = DRIVER_DESC,
 694         .date = DRIVER_DATE,
 695         .major = DRIVER_MAJOR,
 696         .minor = DRIVER_MINOR,
 697         .patchlevel = DRIVER_PATCHLEVEL,
 698 };
 699
 700 static int __init i915_init(void)
 701 {
 702         if (!intel_agp_enabled) {
 703                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 704                 return -ENODEV;
 705         }
 706
 707         driver.num_ioctls = i915_max_ioctl;
 708
 709         /*
 710          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 711          * explicitly disabled with the module pararmeter.
 712          *
 713          * Otherwise, just follow the parameter (defaulting to off).
 714          *
 715          * Allow optional vga_text_mode_force boot option to override
 716          * the default behavior.
 717          */
 718 #if defined(CONFIG_DRM_I915_KMS)
 719         if (i915_modeset != 0)
 720                 driver.driver_features |= DRIVER_MODESET;
 721 #endif
 722         if (i915_modeset == 1)
 723                 driver.driver_features |= DRIVER_MODESET;
 724
 725 #ifdef CONFIG_VGA_CONSOLE
 726         if (vgacon_text_force() && i915_modeset == -1)
 727                 driver.driver_features &= ~DRIVER_MODESET;
 728 #endif
 729
 730         return drm_init(&driver);
 731 }
 732
 733 static void __exit i915_exit(void)
 734 {
 735         drm_exit(&driver);
 736 }
 737
 738 module_init(i915_init);
 739 module_exit(i915_exit);
 740
 741 MODULE_AUTHOR(DRIVER_AUTHOR);
 742 MODULE_DESCRIPTION(DRIVER_DESC);
 743 MODULE_LICENSE("GPL and additional rights");