1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include "drm_crtc_helper.h"
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
71 int i915_enable_fbc __read_mostly = -1;
72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
73 MODULE_PARM_DESC(i915_enable_fbc,
74 "Enable frame buffer compression for power savings "
75 "(default: -1 (use per-chip default))");
77 unsigned int i915_lvds_downclock __read_mostly = 0;
78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
79 MODULE_PARM_DESC(lvds_downclock,
80 "Use panel (LVDS/eDP) downclocking for power savings "
83 int i915_panel_use_ssc __read_mostly = -1;
84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
85 MODULE_PARM_DESC(lvds_use_ssc,
86 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
87 "(default: auto from VBT)");
89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
92 "Override selection of SDVO panel mode in the VBT "
95 static bool i915_try_reset __read_mostly = true;
96 module_param_named(reset, i915_try_reset, bool, 0600);
97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
99 bool i915_enable_hangcheck __read_mostly = true;
100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
101 MODULE_PARM_DESC(enable_hangcheck,
102 "Periodically check GPU activity for detecting hangs. "
103 "WARNING: Disabling this can cause system wide hangs. "
106 bool i915_enable_ppgtt __read_mostly = 1;
107 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
108 MODULE_PARM_DESC(i915_enable_ppgtt,
109 "Enable PPGTT (default: true)");
111 static struct drm_driver driver;
112 extern int intel_agp_enabled;
114 #define INTEL_VGA_DEVICE(id, info) { \
115 .class = PCI_BASE_CLASS_DISPLAY << 16, \
116 .class_mask = 0xff0000, \
119 .subvendor = PCI_ANY_ID, \
120 .subdevice = PCI_ANY_ID, \
121 .driver_data = (unsigned long) info }
123 static const struct intel_device_info intel_i830_info = {
124 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
125 .has_overlay = 1, .overlay_needs_physical = 1,
128 static const struct intel_device_info intel_845g_info = {
130 .has_overlay = 1, .overlay_needs_physical = 1,
133 static const struct intel_device_info intel_i85x_info = {
134 .gen = 2, .is_i85x = 1, .is_mobile = 1,
135 .cursor_needs_physical = 1,
136 .has_overlay = 1, .overlay_needs_physical = 1,
139 static const struct intel_device_info intel_i865g_info = {
141 .has_overlay = 1, .overlay_needs_physical = 1,
144 static const struct intel_device_info intel_i915g_info = {
145 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
146 .has_overlay = 1, .overlay_needs_physical = 1,
148 static const struct intel_device_info intel_i915gm_info = {
149 .gen = 3, .is_mobile = 1,
150 .cursor_needs_physical = 1,
151 .has_overlay = 1, .overlay_needs_physical = 1,
154 static const struct intel_device_info intel_i945g_info = {
155 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
158 static const struct intel_device_info intel_i945gm_info = {
159 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
160 .has_hotplug = 1, .cursor_needs_physical = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
165 static const struct intel_device_info intel_i965g_info = {
166 .gen = 4, .is_broadwater = 1,
171 static const struct intel_device_info intel_i965gm_info = {
172 .gen = 4, .is_crestline = 1,
173 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
178 static const struct intel_device_info intel_g33_info = {
179 .gen = 3, .is_g33 = 1,
180 .need_gfx_hws = 1, .has_hotplug = 1,
184 static const struct intel_device_info intel_g45_info = {
185 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
186 .has_pipe_cxsr = 1, .has_hotplug = 1,
190 static const struct intel_device_info intel_gm45_info = {
191 .gen = 4, .is_g4x = 1,
192 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
193 .has_pipe_cxsr = 1, .has_hotplug = 1,
198 static const struct intel_device_info intel_pineview_info = {
199 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
200 .need_gfx_hws = 1, .has_hotplug = 1,
204 static const struct intel_device_info intel_ironlake_d_info = {
206 .need_gfx_hws = 1, .has_hotplug = 1,
210 static const struct intel_device_info intel_ironlake_m_info = {
211 .gen = 5, .is_mobile = 1,
212 .need_gfx_hws = 1, .has_hotplug = 1,
217 static const struct intel_device_info intel_sandybridge_d_info = {
219 .need_gfx_hws = 1, .has_hotplug = 1,
225 static const struct intel_device_info intel_sandybridge_m_info = {
226 .gen = 6, .is_mobile = 1,
227 .need_gfx_hws = 1, .has_hotplug = 1,
234 static const struct intel_device_info intel_ivybridge_d_info = {
235 .is_ivybridge = 1, .gen = 7,
236 .need_gfx_hws = 1, .has_hotplug = 1,
242 static const struct intel_device_info intel_ivybridge_m_info = {
243 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
244 .need_gfx_hws = 1, .has_hotplug = 1,
245 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
251 static const struct pci_device_id pciidlist[] = { /* aka */
252 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
253 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
254 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
255 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
256 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
257 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
258 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
259 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
260 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
261 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
262 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
263 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
264 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
265 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
266 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
267 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
268 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
269 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
270 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
271 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
272 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
273 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
274 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
275 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
276 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
277 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
278 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
279 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
280 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
281 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
282 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
283 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
284 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
285 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
286 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
287 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
288 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
289 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
290 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
291 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
292 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
293 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
294 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
298 #if defined(CONFIG_DRM_I915_KMS)
299 MODULE_DEVICE_TABLE(pci, pciidlist);
302 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
303 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
304 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
305 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
307 void intel_detect_pch(struct drm_device *dev)
309 struct drm_i915_private *dev_priv = dev->dev_private;
313 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
314 * make graphics device passthrough work easy for VMM, that only
315 * need to expose ISA bridge to let driver know the real hardware
316 * underneath. This is a requirement from virtualization team.
318 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
320 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
322 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
324 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
325 dev_priv->pch_type = PCH_IBX;
326 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
327 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
328 dev_priv->pch_type = PCH_CPT;
329 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
330 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
331 /* PantherPoint is CPT compatible */
332 dev_priv->pch_type = PCH_CPT;
333 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
340 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
345 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
348 I915_WRITE_NOTRACE(FORCEWAKE, 1);
349 POSTING_READ(FORCEWAKE);
352 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
356 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
361 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
364 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
365 POSTING_READ(FORCEWAKE_MT);
368 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
373 * Generally this is called implicitly by the register read function. However,
374 * if some sequence requires the GT to not power down then this function should
375 * be called at the beginning of the sequence followed by a call to
376 * gen6_gt_force_wake_put() at the end of the sequence.
378 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
380 unsigned long irqflags;
382 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
383 if (dev_priv->forcewake_count++ == 0)
384 dev_priv->display.force_wake_get(dev_priv);
385 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
388 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
391 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
392 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
393 "MMIO read or write has been dropped %x\n", gtfifodbg))
394 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
397 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
399 I915_WRITE_NOTRACE(FORCEWAKE, 0);
400 /* The below doubles as a POSTING_READ */
401 gen6_gt_check_fifodbg(dev_priv);
404 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
406 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
407 /* The below doubles as a POSTING_READ */
408 gen6_gt_check_fifodbg(dev_priv);
412 * see gen6_gt_force_wake_get()
414 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
416 unsigned long irqflags;
418 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
419 if (--dev_priv->forcewake_count == 0)
420 dev_priv->display.force_wake_put(dev_priv);
421 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
424 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
428 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
430 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
431 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
433 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
435 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
437 dev_priv->gt_fifo_count = fifo;
439 dev_priv->gt_fifo_count--;
444 static int i915_drm_freeze(struct drm_device *dev)
446 struct drm_i915_private *dev_priv = dev->dev_private;
448 drm_kms_helper_poll_disable(dev);
450 pci_save_state(dev->pdev);
452 /* If KMS is active, we do the leavevt stuff here */
453 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
454 int error = i915_gem_idle(dev);
456 dev_err(&dev->pdev->dev,
457 "GEM idle failed, resume might fail\n");
460 drm_irq_uninstall(dev);
463 i915_save_state(dev);
465 intel_opregion_fini(dev);
467 /* Modeset on resume, not lid events */
468 dev_priv->modeset_on_lid = 0;
473 int i915_suspend(struct drm_device *dev, pm_message_t state)
477 if (!dev || !dev->dev_private) {
478 DRM_ERROR("dev: %p\n", dev);
479 DRM_ERROR("DRM not initialized, aborting suspend.\n");
483 if (state.event == PM_EVENT_PRETHAW)
487 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
490 error = i915_drm_freeze(dev);
494 if (state.event == PM_EVENT_SUSPEND) {
495 /* Shut down the device */
496 pci_disable_device(dev->pdev);
497 pci_set_power_state(dev->pdev, PCI_D3hot);
503 static int i915_drm_thaw(struct drm_device *dev)
505 struct drm_i915_private *dev_priv = dev->dev_private;
508 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
509 mutex_lock(&dev->struct_mutex);
510 i915_gem_restore_gtt_mappings(dev);
511 mutex_unlock(&dev->struct_mutex);
514 i915_restore_state(dev);
515 intel_opregion_setup(dev);
517 /* KMS EnterVT equivalent */
518 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
519 mutex_lock(&dev->struct_mutex);
520 dev_priv->mm.suspended = 0;
522 error = i915_gem_init_hw(dev);
523 mutex_unlock(&dev->struct_mutex);
525 if (HAS_PCH_SPLIT(dev))
526 ironlake_init_pch_refclk(dev);
528 drm_mode_config_reset(dev);
529 drm_irq_install(dev);
531 /* Resume the modeset for every activated CRTC */
532 drm_helper_resume_force_mode(dev);
534 if (IS_IRONLAKE_M(dev))
535 ironlake_enable_rc6(dev);
538 intel_opregion_init(dev);
540 dev_priv->modeset_on_lid = 0;
545 int i915_resume(struct drm_device *dev)
549 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
552 if (pci_enable_device(dev->pdev))
555 pci_set_master(dev->pdev);
557 ret = i915_drm_thaw(dev);
561 drm_kms_helper_poll_enable(dev);
565 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
567 struct drm_i915_private *dev_priv = dev->dev_private;
572 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
573 POSTING_READ(D_STATE);
575 if (IS_I830(dev) || IS_845G(dev)) {
576 I915_WRITE(DEBUG_RESET_I830,
577 DEBUG_RESET_DISPLAY |
580 POSTING_READ(DEBUG_RESET_I830);
583 I915_WRITE(DEBUG_RESET_I830, 0);
584 POSTING_READ(DEBUG_RESET_I830);
589 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
590 POSTING_READ(D_STATE);
595 static int i965_reset_complete(struct drm_device *dev)
598 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
602 static int i965_do_reset(struct drm_device *dev, u8 flags)
607 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
608 * well as the reset bit (GR/bit 0). Setting the GR bit
609 * triggers the reset; when done, the hardware will clear it.
611 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
612 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
614 return wait_for(i965_reset_complete(dev), 500);
617 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
619 struct drm_i915_private *dev_priv = dev->dev_private;
620 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
621 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
622 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
625 static int gen6_do_reset(struct drm_device *dev, u8 flags)
627 struct drm_i915_private *dev_priv = dev->dev_private;
629 unsigned long irqflags;
631 /* Hold gt_lock across reset to prevent any register access
632 * with forcewake not set correctly
634 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
638 /* GEN6_GDRST is not in the gt power well, no need to check
639 * for fifo space for the write or forcewake the chip for
642 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
644 /* Spin waiting for the device to ack the reset request */
645 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
647 /* If reset with a user forcewake, try to restore, otherwise turn it off */
648 if (dev_priv->forcewake_count)
649 dev_priv->display.force_wake_get(dev_priv);
651 dev_priv->display.force_wake_put(dev_priv);
653 /* Restore fifo count */
654 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
656 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
661 * i915_reset - reset chip after a hang
662 * @dev: drm device to reset
663 * @flags: reset domains
665 * Reset the chip. Useful if a hang is detected. Returns zero on successful
666 * reset or otherwise an error code.
668 * Procedure is fairly simple:
669 * - reset the chip using the reset reg
670 * - re-init context state
671 * - re-init hardware status page
672 * - re-init ring buffer
673 * - re-init interrupt state
676 int i915_reset(struct drm_device *dev, u8 flags)
678 drm_i915_private_t *dev_priv = dev->dev_private;
680 * We really should only reset the display subsystem if we actually
683 bool need_display = true;
689 if (!mutex_trylock(&dev->struct_mutex))
695 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
696 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
697 } else switch (INTEL_INFO(dev)->gen) {
700 ret = gen6_do_reset(dev, flags);
703 ret = ironlake_do_reset(dev, flags);
706 ret = i965_do_reset(dev, flags);
709 ret = i8xx_do_reset(dev, flags);
712 dev_priv->last_gpu_reset = get_seconds();
714 DRM_ERROR("Failed to reset chip.\n");
715 mutex_unlock(&dev->struct_mutex);
719 /* Ok, now get things going again... */
722 * Everything depends on having the GTT running, so we need to start
723 * there. Fortunately we don't need to do this unless we reset the
724 * chip at a PCI level.
726 * Next we need to restore the context, but we don't use those
729 * Ring buffer needs to be re-initialized in the KMS case, or if X
730 * was running at the time of the reset (i.e. we weren't VT
733 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
734 !dev_priv->mm.suspended) {
735 dev_priv->mm.suspended = 0;
737 i915_gem_init_swizzling(dev);
739 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
741 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
743 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
745 i915_gem_init_ppgtt(dev);
747 mutex_unlock(&dev->struct_mutex);
748 drm_irq_uninstall(dev);
749 drm_mode_config_reset(dev);
750 drm_irq_install(dev);
751 mutex_lock(&dev->struct_mutex);
754 mutex_unlock(&dev->struct_mutex);
757 * Perform a full modeset as on later generations, e.g. Ironlake, we may
758 * need to retrain the display link and cannot just restore the register
762 mutex_lock(&dev->mode_config.mutex);
763 drm_helper_resume_force_mode(dev);
764 mutex_unlock(&dev->mode_config.mutex);
772 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
774 /* Only bind to function 0 of the device. Early generations
775 * used function 1 as a placeholder for multi-head. This causes
776 * us confusion instead, especially on the systems where both
777 * functions have the same PCI-ID!
779 if (PCI_FUNC(pdev->devfn))
782 return drm_get_pci_dev(pdev, ent, &driver);
786 i915_pci_remove(struct pci_dev *pdev)
788 struct drm_device *dev = pci_get_drvdata(pdev);
793 static int i915_pm_suspend(struct device *dev)
795 struct pci_dev *pdev = to_pci_dev(dev);
796 struct drm_device *drm_dev = pci_get_drvdata(pdev);
799 if (!drm_dev || !drm_dev->dev_private) {
800 dev_err(dev, "DRM not initialized, aborting suspend.\n");
804 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
807 error = i915_drm_freeze(drm_dev);
811 pci_disable_device(pdev);
812 pci_set_power_state(pdev, PCI_D3hot);
817 static int i915_pm_resume(struct device *dev)
819 struct pci_dev *pdev = to_pci_dev(dev);
820 struct drm_device *drm_dev = pci_get_drvdata(pdev);
822 return i915_resume(drm_dev);
825 static int i915_pm_freeze(struct device *dev)
827 struct pci_dev *pdev = to_pci_dev(dev);
828 struct drm_device *drm_dev = pci_get_drvdata(pdev);
830 if (!drm_dev || !drm_dev->dev_private) {
831 dev_err(dev, "DRM not initialized, aborting suspend.\n");
835 return i915_drm_freeze(drm_dev);
838 static int i915_pm_thaw(struct device *dev)
840 struct pci_dev *pdev = to_pci_dev(dev);
841 struct drm_device *drm_dev = pci_get_drvdata(pdev);
843 return i915_drm_thaw(drm_dev);
846 static int i915_pm_poweroff(struct device *dev)
848 struct pci_dev *pdev = to_pci_dev(dev);
849 struct drm_device *drm_dev = pci_get_drvdata(pdev);
851 return i915_drm_freeze(drm_dev);
854 static const struct dev_pm_ops i915_pm_ops = {
855 .suspend = i915_pm_suspend,
856 .resume = i915_pm_resume,
857 .freeze = i915_pm_freeze,
858 .thaw = i915_pm_thaw,
859 .poweroff = i915_pm_poweroff,
860 .restore = i915_pm_resume,
863 static struct vm_operations_struct i915_gem_vm_ops = {
864 .fault = i915_gem_fault,
865 .open = drm_gem_vm_open,
866 .close = drm_gem_vm_close,
869 static const struct file_operations i915_driver_fops = {
870 .owner = THIS_MODULE,
872 .release = drm_release,
873 .unlocked_ioctl = drm_ioctl,
874 .mmap = drm_gem_mmap,
876 .fasync = drm_fasync,
879 .compat_ioctl = i915_compat_ioctl,
881 .llseek = noop_llseek,
884 static struct drm_driver driver = {
885 /* Don't use MTRRs here; the Xserver or userspace app should
886 * deal with them for Intel hardware.
889 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
890 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
891 .load = i915_driver_load,
892 .unload = i915_driver_unload,
893 .open = i915_driver_open,
894 .lastclose = i915_driver_lastclose,
895 .preclose = i915_driver_preclose,
896 .postclose = i915_driver_postclose,
898 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
899 .suspend = i915_suspend,
900 .resume = i915_resume,
902 .device_is_agp = i915_driver_device_is_agp,
903 .reclaim_buffers = drm_core_reclaim_buffers,
904 .master_create = i915_master_create,
905 .master_destroy = i915_master_destroy,
906 #if defined(CONFIG_DEBUG_FS)
907 .debugfs_init = i915_debugfs_init,
908 .debugfs_cleanup = i915_debugfs_cleanup,
910 .gem_init_object = i915_gem_init_object,
911 .gem_free_object = i915_gem_free_object,
912 .gem_vm_ops = &i915_gem_vm_ops,
913 .dumb_create = i915_gem_dumb_create,
914 .dumb_map_offset = i915_gem_mmap_gtt,
915 .dumb_destroy = i915_gem_dumb_destroy,
916 .ioctls = i915_ioctls,
917 .fops = &i915_driver_fops,
921 .major = DRIVER_MAJOR,
922 .minor = DRIVER_MINOR,
923 .patchlevel = DRIVER_PATCHLEVEL,
926 static struct pci_driver i915_pci_driver = {
928 .id_table = pciidlist,
929 .probe = i915_pci_probe,
930 .remove = i915_pci_remove,
931 .driver.pm = &i915_pm_ops,
934 static int __init i915_init(void)
936 if (!intel_agp_enabled) {
937 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
941 driver.num_ioctls = i915_max_ioctl;
944 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
945 * explicitly disabled with the module pararmeter.
947 * Otherwise, just follow the parameter (defaulting to off).
949 * Allow optional vga_text_mode_force boot option to override
950 * the default behavior.
952 #if defined(CONFIG_DRM_I915_KMS)
953 if (i915_modeset != 0)
954 driver.driver_features |= DRIVER_MODESET;
956 if (i915_modeset == 1)
957 driver.driver_features |= DRIVER_MODESET;
959 #ifdef CONFIG_VGA_CONSOLE
960 if (vgacon_text_force() && i915_modeset == -1)
961 driver.driver_features &= ~DRIVER_MODESET;
964 if (!(driver.driver_features & DRIVER_MODESET))
965 driver.get_vblank_timestamp = NULL;
967 return drm_pci_init(&driver, &i915_pci_driver);
970 static void __exit i915_exit(void)
972 drm_pci_exit(&driver, &i915_pci_driver);
975 module_init(i915_init);
976 module_exit(i915_exit);
978 MODULE_AUTHOR(DRIVER_AUTHOR);
979 MODULE_DESCRIPTION(DRIVER_DESC);
980 MODULE_LICENSE("GPL and additional rights");
982 #define __i915_read(x, y) \
983 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
985 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
986 unsigned long irqflags; \
987 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
988 if (dev_priv->forcewake_count == 0) \
989 dev_priv->display.force_wake_get(dev_priv); \
990 val = read##y(dev_priv->regs + reg); \
991 if (dev_priv->forcewake_count == 0) \
992 dev_priv->display.force_wake_put(dev_priv); \
993 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
995 val = read##y(dev_priv->regs + reg); \
997 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1007 #define __i915_write(x, y) \
1008 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1009 u32 __fifo_ret = 0; \
1010 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1011 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1012 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1014 write##y(val, dev_priv->regs + reg); \
1015 if (unlikely(__fifo_ret)) { \
1016 gen6_gt_check_fifodbg(dev_priv); \