drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_panel_use_ssc __read_mostly = -1;
  88 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  89 MODULE_PARM_DESC(lvds_use_ssc,
  90                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  91                 "(default: auto from VBT)");
  92
  93 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  94 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  95 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  96                 "Override selection of SDVO panel mode in the VBT "
  97                 "(default: auto)");
  98
  99 static bool i915_try_reset __read_mostly = true;
 100 module_param_named(reset, i915_try_reset, bool, 0600);
 101 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 102
 103 bool i915_enable_hangcheck __read_mostly = true;
 104 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 105 MODULE_PARM_DESC(enable_hangcheck,
 106                 "Periodically check GPU activity for detecting hangs. "
 107                 "WARNING: Disabling this can cause system wide hangs. "
 108                 "(default: true)");
 109
 110 bool i915_enable_ppgtt __read_mostly = 1;
 111 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
 112 MODULE_PARM_DESC(i915_enable_ppgtt,
 113                 "Enable PPGTT (default: true)");
 114
 115 static struct drm_driver driver;
 116 extern int intel_agp_enabled;
 117
 118 #define INTEL_VGA_DEVICE(id, info) {            \
 119         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 120         .class_mask = 0xff0000,                 \
 121         .vendor = 0x8086,                       \
 122         .device = id,                           \
 123         .subvendor = PCI_ANY_ID,                \
 124         .subdevice = PCI_ANY_ID,                \
 125         .driver_data = (unsigned long) info }
 126
 127 static const struct intel_device_info intel_i830_info = {
 128         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 129         .has_overlay = 1, .overlay_needs_physical = 1,
 130 };
 131
 132 static const struct intel_device_info intel_845g_info = {
 133         .gen = 2,
 134         .has_overlay = 1, .overlay_needs_physical = 1,
 135 };
 136
 137 static const struct intel_device_info intel_i85x_info = {
 138         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 139         .cursor_needs_physical = 1,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142
 143 static const struct intel_device_info intel_i865g_info = {
 144         .gen = 2,
 145         .has_overlay = 1, .overlay_needs_physical = 1,
 146 };
 147
 148 static const struct intel_device_info intel_i915g_info = {
 149         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 150         .has_overlay = 1, .overlay_needs_physical = 1,
 151 };
 152 static const struct intel_device_info intel_i915gm_info = {
 153         .gen = 3, .is_mobile = 1,
 154         .cursor_needs_physical = 1,
 155         .has_overlay = 1, .overlay_needs_physical = 1,
 156         .supports_tv = 1,
 157 };
 158 static const struct intel_device_info intel_i945g_info = {
 159         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 160         .has_overlay = 1, .overlay_needs_physical = 1,
 161 };
 162 static const struct intel_device_info intel_i945gm_info = {
 163         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 164         .has_hotplug = 1, .cursor_needs_physical = 1,
 165         .has_overlay = 1, .overlay_needs_physical = 1,
 166         .supports_tv = 1,
 167 };
 168
 169 static const struct intel_device_info intel_i965g_info = {
 170         .gen = 4, .is_broadwater = 1,
 171         .has_hotplug = 1,
 172         .has_overlay = 1,
 173 };
 174
 175 static const struct intel_device_info intel_i965gm_info = {
 176         .gen = 4, .is_crestline = 1,
 177         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 178         .has_overlay = 1,
 179         .supports_tv = 1,
 180 };
 181
 182 static const struct intel_device_info intel_g33_info = {
 183         .gen = 3, .is_g33 = 1,
 184         .need_gfx_hws = 1, .has_hotplug = 1,
 185         .has_overlay = 1,
 186 };
 187
 188 static const struct intel_device_info intel_g45_info = {
 189         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 190         .has_pipe_cxsr = 1, .has_hotplug = 1,
 191         .has_bsd_ring = 1,
 192 };
 193
 194 static const struct intel_device_info intel_gm45_info = {
 195         .gen = 4, .is_g4x = 1,
 196         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 197         .has_pipe_cxsr = 1, .has_hotplug = 1,
 198         .supports_tv = 1,
 199         .has_bsd_ring = 1,
 200 };
 201
 202 static const struct intel_device_info intel_pineview_info = {
 203         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 204         .need_gfx_hws = 1, .has_hotplug = 1,
 205         .has_overlay = 1,
 206 };
 207
 208 static const struct intel_device_info intel_ironlake_d_info = {
 209         .gen = 5,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_bsd_ring = 1,
 212 };
 213
 214 static const struct intel_device_info intel_ironlake_m_info = {
 215         .gen = 5, .is_mobile = 1,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_fbc = 1,
 218         .has_bsd_ring = 1,
 219 };
 220
 221 static const struct intel_device_info intel_sandybridge_d_info = {
 222         .gen = 6,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_bsd_ring = 1,
 225         .has_blt_ring = 1,
 226         .has_llc = 1,
 227 };
 228
 229 static const struct intel_device_info intel_sandybridge_m_info = {
 230         .gen = 6, .is_mobile = 1,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_fbc = 1,
 233         .has_bsd_ring = 1,
 234         .has_blt_ring = 1,
 235         .has_llc = 1,
 236 };
 237
 238 static const struct intel_device_info intel_ivybridge_d_info = {
 239         .is_ivybridge = 1, .gen = 7,
 240         .need_gfx_hws = 1, .has_hotplug = 1,
 241         .has_bsd_ring = 1,
 242         .has_blt_ring = 1,
 243         .has_llc = 1,
 244 };
 245
 246 static const struct intel_device_info intel_ivybridge_m_info = {
 247         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 248         .need_gfx_hws = 1, .has_hotplug = 1,
 249         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 250         .has_bsd_ring = 1,
 251         .has_blt_ring = 1,
 252         .has_llc = 1,
 253 };
 254
 255 static const struct pci_device_id pciidlist[] = {               /* aka */
 256         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 257         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 258         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 259         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 260         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 261         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 262         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 263         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 264         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 265         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 266         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 267         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 268         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 269         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 270         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 271         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 272         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 273         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 274         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 275         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 276         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 277         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 278         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 279         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 280         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 281         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 282         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 283         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 284         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 285         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 286         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 287         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 288         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 289         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 290         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 291         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 292         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 293         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 294         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 295         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 296         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 297         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 298         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 299         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 300         {0, 0, 0}
 301 };
 302
 303 #if defined(CONFIG_DRM_I915_KMS)
 304 MODULE_DEVICE_TABLE(pci, pciidlist);
 305 #endif
 306
 307 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 308 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 309 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 310 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 311
 312 void intel_detect_pch(struct drm_device *dev)
 313 {
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315         struct pci_dev *pch;
 316
 317         /*
 318          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 319          * make graphics device passthrough work easy for VMM, that only
 320          * need to expose ISA bridge to let driver know the real hardware
 321          * underneath. This is a requirement from virtualization team.
 322          */
 323         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 324         if (pch) {
 325                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 326                         int id;
 327                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 328
 329                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 330                                 dev_priv->pch_type = PCH_IBX;
 331                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 332                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 333                                 dev_priv->pch_type = PCH_CPT;
 334                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 335                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 336                                 /* PantherPoint is CPT compatible */
 337                                 dev_priv->pch_type = PCH_CPT;
 338                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 339                         }
 340                 }
 341                 pci_dev_put(pch);
 342         }
 343 }
 344
 345 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 346 {
 347         int count;
 348
 349         count = 0;
 350         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 351                 udelay(10);
 352
 353         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 354         POSTING_READ(FORCEWAKE);
 355
 356         count = 0;
 357         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 358                 udelay(10);
 359 }
 360
 361 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 362 {
 363         int count;
 364
 365         count = 0;
 366         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 367                 udelay(10);
 368
 369         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 370         POSTING_READ(FORCEWAKE_MT);
 371
 372         count = 0;
 373         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 374                 udelay(10);
 375 }
 376
 377 /*
 378  * Generally this is called implicitly by the register read function. However,
 379  * if some sequence requires the GT to not power down then this function should
 380  * be called at the beginning of the sequence followed by a call to
 381  * gen6_gt_force_wake_put() at the end of the sequence.
 382  */
 383 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 384 {
 385         unsigned long irqflags;
 386
 387         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 388         if (dev_priv->forcewake_count++ == 0)
 389                 dev_priv->display.force_wake_get(dev_priv);
 390         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 391 }
 392
 393 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 394 {
 395         u32 gtfifodbg;
 396         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 397         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 398              "MMIO read or write has been dropped %x\n", gtfifodbg))
 399                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 400 }
 401
 402 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 403 {
 404         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 405         /* The below doubles as a POSTING_READ */
 406         gen6_gt_check_fifodbg(dev_priv);
 407 }
 408
 409 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 410 {
 411         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 412         /* The below doubles as a POSTING_READ */
 413         gen6_gt_check_fifodbg(dev_priv);
 414 }
 415
 416 /*
 417  * see gen6_gt_force_wake_get()
 418  */
 419 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 420 {
 421         unsigned long irqflags;
 422
 423         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 424         if (--dev_priv->forcewake_count == 0)
 425                 dev_priv->display.force_wake_put(dev_priv);
 426         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 427 }
 428
 429 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 430 {
 431         int ret = 0;
 432
 433         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 434                 int loop = 500;
 435                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 436                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 437                         udelay(10);
 438                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 439                 }
 440                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 441                         ++ret;
 442                 dev_priv->gt_fifo_count = fifo;
 443         }
 444         dev_priv->gt_fifo_count--;
 445
 446         return ret;
 447 }
 448
 449 static int i915_drm_freeze(struct drm_device *dev)
 450 {
 451         struct drm_i915_private *dev_priv = dev->dev_private;
 452
 453         drm_kms_helper_poll_disable(dev);
 454
 455         pci_save_state(dev->pdev);
 456
 457         /* If KMS is active, we do the leavevt stuff here */
 458         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 459                 int error = i915_gem_idle(dev);
 460                 if (error) {
 461                         dev_err(&dev->pdev->dev,
 462                                 "GEM idle failed, resume might fail\n");
 463                         return error;
 464                 }
 465                 drm_irq_uninstall(dev);
 466         }
 467
 468         i915_save_state(dev);
 469
 470         intel_opregion_fini(dev);
 471
 472         /* Modeset on resume, not lid events */
 473         dev_priv->modeset_on_lid = 0;
 474
 475         console_lock();
 476         intel_fbdev_set_suspend(dev, 1);
 477         console_unlock();
 478
 479         return 0;
 480 }
 481
 482 int i915_suspend(struct drm_device *dev, pm_message_t state)
 483 {
 484         int error;
 485
 486         if (!dev || !dev->dev_private) {
 487                 DRM_ERROR("dev: %p\n", dev);
 488                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 489                 return -ENODEV;
 490         }
 491
 492         if (state.event == PM_EVENT_PRETHAW)
 493                 return 0;
 494
 495
 496         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 497                 return 0;
 498
 499         error = i915_drm_freeze(dev);
 500         if (error)
 501                 return error;
 502
 503         if (state.event == PM_EVENT_SUSPEND) {
 504                 /* Shut down the device */
 505                 pci_disable_device(dev->pdev);
 506                 pci_set_power_state(dev->pdev, PCI_D3hot);
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int i915_drm_thaw(struct drm_device *dev)
 513 {
 514         struct drm_i915_private *dev_priv = dev->dev_private;
 515         int error = 0;
 516
 517         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 518                 mutex_lock(&dev->struct_mutex);
 519                 i915_gem_restore_gtt_mappings(dev);
 520                 mutex_unlock(&dev->struct_mutex);
 521         }
 522
 523         i915_restore_state(dev);
 524         intel_opregion_setup(dev);
 525
 526         /* KMS EnterVT equivalent */
 527         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 528                 mutex_lock(&dev->struct_mutex);
 529                 dev_priv->mm.suspended = 0;
 530
 531                 error = i915_gem_init_hw(dev);
 532                 mutex_unlock(&dev->struct_mutex);
 533
 534                 if (HAS_PCH_SPLIT(dev))
 535                         ironlake_init_pch_refclk(dev);
 536
 537                 drm_mode_config_reset(dev);
 538                 drm_irq_install(dev);
 539
 540                 /* Resume the modeset for every activated CRTC */
 541                 drm_helper_resume_force_mode(dev);
 542
 543                 if (IS_IRONLAKE_M(dev))
 544                         ironlake_enable_rc6(dev);
 545         }
 546
 547         intel_opregion_init(dev);
 548
 549         dev_priv->modeset_on_lid = 0;
 550
 551         console_lock();
 552         intel_fbdev_set_suspend(dev, 0);
 553         console_unlock();
 554         return error;
 555 }
 556
 557 int i915_resume(struct drm_device *dev)
 558 {
 559         int ret;
 560
 561         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 562                 return 0;
 563
 564         if (pci_enable_device(dev->pdev))
 565                 return -EIO;
 566
 567         pci_set_master(dev->pdev);
 568
 569         ret = i915_drm_thaw(dev);
 570         if (ret)
 571                 return ret;
 572
 573         drm_kms_helper_poll_enable(dev);
 574         return 0;
 575 }
 576
 577 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 578 {
 579         struct drm_i915_private *dev_priv = dev->dev_private;
 580
 581         if (IS_I85X(dev))
 582                 return -ENODEV;
 583
 584         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 585         POSTING_READ(D_STATE);
 586
 587         if (IS_I830(dev) || IS_845G(dev)) {
 588                 I915_WRITE(DEBUG_RESET_I830,
 589                            DEBUG_RESET_DISPLAY |
 590                            DEBUG_RESET_RENDER |
 591                            DEBUG_RESET_FULL);
 592                 POSTING_READ(DEBUG_RESET_I830);
 593                 msleep(1);
 594
 595                 I915_WRITE(DEBUG_RESET_I830, 0);
 596                 POSTING_READ(DEBUG_RESET_I830);
 597         }
 598
 599         msleep(1);
 600
 601         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 602         POSTING_READ(D_STATE);
 603
 604         return 0;
 605 }
 606
 607 static int i965_reset_complete(struct drm_device *dev)
 608 {
 609         u8 gdrst;
 610         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 611         return gdrst & 0x1;
 612 }
 613
 614 static int i965_do_reset(struct drm_device *dev, u8 flags)
 615 {
 616         u8 gdrst;
 617
 618         /*
 619          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 620          * well as the reset bit (GR/bit 0).  Setting the GR bit
 621          * triggers the reset; when done, the hardware will clear it.
 622          */
 623         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 624         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 625
 626         return wait_for(i965_reset_complete(dev), 500);
 627 }
 628
 629 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 630 {
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 633         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 634         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 635 }
 636
 637 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         int     ret;
 641         unsigned long irqflags;
 642
 643         /* Hold gt_lock across reset to prevent any register access
 644          * with forcewake not set correctly
 645          */
 646         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 647
 648         /* Reset the chip */
 649
 650         /* GEN6_GDRST is not in the gt power well, no need to check
 651          * for fifo space for the write or forcewake the chip for
 652          * the read
 653          */
 654         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 655
 656         /* Spin waiting for the device to ack the reset request */
 657         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 658
 659         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 660         if (dev_priv->forcewake_count)
 661                 dev_priv->display.force_wake_get(dev_priv);
 662         else
 663                 dev_priv->display.force_wake_put(dev_priv);
 664
 665         /* Restore fifo count */
 666         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 667
 668         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 669         return ret;
 670 }
 671
 672 /**
 673  * i915_reset - reset chip after a hang
 674  * @dev: drm device to reset
 675  * @flags: reset domains
 676  *
 677  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 678  * reset or otherwise an error code.
 679  *
 680  * Procedure is fairly simple:
 681  *   - reset the chip using the reset reg
 682  *   - re-init context state
 683  *   - re-init hardware status page
 684  *   - re-init ring buffer
 685  *   - re-init interrupt state
 686  *   - re-init display
 687  */
 688 int i915_reset(struct drm_device *dev, u8 flags)
 689 {
 690         drm_i915_private_t *dev_priv = dev->dev_private;
 691         /*
 692          * We really should only reset the display subsystem if we actually
 693          * need to
 694          */
 695         bool need_display = true;
 696         int ret;
 697
 698         if (!i915_try_reset)
 699                 return 0;
 700
 701         if (!mutex_trylock(&dev->struct_mutex))
 702                 return -EBUSY;
 703
 704         i915_gem_reset(dev);
 705
 706         ret = -ENODEV;
 707         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 708                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 709         } else switch (INTEL_INFO(dev)->gen) {
 710         case 7:
 711         case 6:
 712                 ret = gen6_do_reset(dev, flags);
 713                 break;
 714         case 5:
 715                 ret = ironlake_do_reset(dev, flags);
 716                 break;
 717         case 4:
 718                 ret = i965_do_reset(dev, flags);
 719                 break;
 720         case 2:
 721                 ret = i8xx_do_reset(dev, flags);
 722                 break;
 723         }
 724         dev_priv->last_gpu_reset = get_seconds();
 725         if (ret) {
 726                 DRM_ERROR("Failed to reset chip.\n");
 727                 mutex_unlock(&dev->struct_mutex);
 728                 return ret;
 729         }
 730
 731         /* Ok, now get things going again... */
 732
 733         /*
 734          * Everything depends on having the GTT running, so we need to start
 735          * there.  Fortunately we don't need to do this unless we reset the
 736          * chip at a PCI level.
 737          *
 738          * Next we need to restore the context, but we don't use those
 739          * yet either...
 740          *
 741          * Ring buffer needs to be re-initialized in the KMS case, or if X
 742          * was running at the time of the reset (i.e. we weren't VT
 743          * switched away).
 744          */
 745         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 746                         !dev_priv->mm.suspended) {
 747                 dev_priv->mm.suspended = 0;
 748
 749                 i915_gem_init_swizzling(dev);
 750
 751                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 752                 if (HAS_BSD(dev))
 753                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 754                 if (HAS_BLT(dev))
 755                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 756
 757                 i915_gem_init_ppgtt(dev);
 758
 759                 mutex_unlock(&dev->struct_mutex);
 760                 drm_irq_uninstall(dev);
 761                 drm_mode_config_reset(dev);
 762                 drm_irq_install(dev);
 763                 mutex_lock(&dev->struct_mutex);
 764         }
 765
 766         mutex_unlock(&dev->struct_mutex);
 767
 768         /*
 769          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 770          * need to retrain the display link and cannot just restore the register
 771          * values.
 772          */
 773         if (need_display) {
 774                 mutex_lock(&dev->mode_config.mutex);
 775                 drm_helper_resume_force_mode(dev);
 776                 mutex_unlock(&dev->mode_config.mutex);
 777         }
 778
 779         return 0;
 780 }
 781
 782
 783 static int __devinit
 784 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 785 {
 786         /* Only bind to function 0 of the device. Early generations
 787          * used function 1 as a placeholder for multi-head. This causes
 788          * us confusion instead, especially on the systems where both
 789          * functions have the same PCI-ID!
 790          */
 791         if (PCI_FUNC(pdev->devfn))
 792                 return -ENODEV;
 793
 794         return drm_get_pci_dev(pdev, ent, &driver);
 795 }
 796
 797 static void
 798 i915_pci_remove(struct pci_dev *pdev)
 799 {
 800         struct drm_device *dev = pci_get_drvdata(pdev);
 801
 802         drm_put_dev(dev);
 803 }
 804
 805 static int i915_pm_suspend(struct device *dev)
 806 {
 807         struct pci_dev *pdev = to_pci_dev(dev);
 808         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 809         int error;
 810
 811         if (!drm_dev || !drm_dev->dev_private) {
 812                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 813                 return -ENODEV;
 814         }
 815
 816         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 817                 return 0;
 818
 819         error = i915_drm_freeze(drm_dev);
 820         if (error)
 821                 return error;
 822
 823         pci_disable_device(pdev);
 824         pci_set_power_state(pdev, PCI_D3hot);
 825
 826         return 0;
 827 }
 828
 829 static int i915_pm_resume(struct device *dev)
 830 {
 831         struct pci_dev *pdev = to_pci_dev(dev);
 832         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 833
 834         return i915_resume(drm_dev);
 835 }
 836
 837 static int i915_pm_freeze(struct device *dev)
 838 {
 839         struct pci_dev *pdev = to_pci_dev(dev);
 840         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 841
 842         if (!drm_dev || !drm_dev->dev_private) {
 843                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 844                 return -ENODEV;
 845         }
 846
 847         return i915_drm_freeze(drm_dev);
 848 }
 849
 850 static int i915_pm_thaw(struct device *dev)
 851 {
 852         struct pci_dev *pdev = to_pci_dev(dev);
 853         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 854
 855         return i915_drm_thaw(drm_dev);
 856 }
 857
 858 static int i915_pm_poweroff(struct device *dev)
 859 {
 860         struct pci_dev *pdev = to_pci_dev(dev);
 861         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 862
 863         return i915_drm_freeze(drm_dev);
 864 }
 865
 866 static const struct dev_pm_ops i915_pm_ops = {
 867         .suspend = i915_pm_suspend,
 868         .resume = i915_pm_resume,
 869         .freeze = i915_pm_freeze,
 870         .thaw = i915_pm_thaw,
 871         .poweroff = i915_pm_poweroff,
 872         .restore = i915_pm_resume,
 873 };
 874
 875 static struct vm_operations_struct i915_gem_vm_ops = {
 876         .fault = i915_gem_fault,
 877         .open = drm_gem_vm_open,
 878         .close = drm_gem_vm_close,
 879 };
 880
 881 static const struct file_operations i915_driver_fops = {
 882         .owner = THIS_MODULE,
 883         .open = drm_open,
 884         .release = drm_release,
 885         .unlocked_ioctl = drm_ioctl,
 886         .mmap = drm_gem_mmap,
 887         .poll = drm_poll,
 888         .fasync = drm_fasync,
 889         .read = drm_read,
 890 #ifdef CONFIG_COMPAT
 891         .compat_ioctl = i915_compat_ioctl,
 892 #endif
 893         .llseek = noop_llseek,
 894 };
 895
 896 static struct drm_driver driver = {
 897         /* Don't use MTRRs here; the Xserver or userspace app should
 898          * deal with them for Intel hardware.
 899          */
 900         .driver_features =
 901             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 902             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 903         .load = i915_driver_load,
 904         .unload = i915_driver_unload,
 905         .open = i915_driver_open,
 906         .lastclose = i915_driver_lastclose,
 907         .preclose = i915_driver_preclose,
 908         .postclose = i915_driver_postclose,
 909
 910         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 911         .suspend = i915_suspend,
 912         .resume = i915_resume,
 913
 914         .device_is_agp = i915_driver_device_is_agp,
 915         .reclaim_buffers = drm_core_reclaim_buffers,
 916         .master_create = i915_master_create,
 917         .master_destroy = i915_master_destroy,
 918 #if defined(CONFIG_DEBUG_FS)
 919         .debugfs_init = i915_debugfs_init,
 920         .debugfs_cleanup = i915_debugfs_cleanup,
 921 #endif
 922         .gem_init_object = i915_gem_init_object,
 923         .gem_free_object = i915_gem_free_object,
 924         .gem_vm_ops = &i915_gem_vm_ops,
 925         .dumb_create = i915_gem_dumb_create,
 926         .dumb_map_offset = i915_gem_mmap_gtt,
 927         .dumb_destroy = i915_gem_dumb_destroy,
 928         .ioctls = i915_ioctls,
 929         .fops = &i915_driver_fops,
 930         .name = DRIVER_NAME,
 931         .desc = DRIVER_DESC,
 932         .date = DRIVER_DATE,
 933         .major = DRIVER_MAJOR,
 934         .minor = DRIVER_MINOR,
 935         .patchlevel = DRIVER_PATCHLEVEL,
 936 };
 937
 938 static struct pci_driver i915_pci_driver = {
 939         .name = DRIVER_NAME,
 940         .id_table = pciidlist,
 941         .probe = i915_pci_probe,
 942         .remove = i915_pci_remove,
 943         .driver.pm = &i915_pm_ops,
 944 };
 945
 946 static int __init i915_init(void)
 947 {
 948         if (!intel_agp_enabled) {
 949                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 950                 return -ENODEV;
 951         }
 952
 953         driver.num_ioctls = i915_max_ioctl;
 954
 955         /*
 956          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 957          * explicitly disabled with the module pararmeter.
 958          *
 959          * Otherwise, just follow the parameter (defaulting to off).
 960          *
 961          * Allow optional vga_text_mode_force boot option to override
 962          * the default behavior.
 963          */
 964 #if defined(CONFIG_DRM_I915_KMS)
 965         if (i915_modeset != 0)
 966                 driver.driver_features |= DRIVER_MODESET;
 967 #endif
 968         if (i915_modeset == 1)
 969                 driver.driver_features |= DRIVER_MODESET;
 970
 971 #ifdef CONFIG_VGA_CONSOLE
 972         if (vgacon_text_force() && i915_modeset == -1)
 973                 driver.driver_features &= ~DRIVER_MODESET;
 974 #endif
 975
 976         if (!(driver.driver_features & DRIVER_MODESET))
 977                 driver.get_vblank_timestamp = NULL;
 978
 979         return drm_pci_init(&driver, &i915_pci_driver);
 980 }
 981
 982 static void __exit i915_exit(void)
 983 {
 984         drm_pci_exit(&driver, &i915_pci_driver);
 985 }
 986
 987 module_init(i915_init);
 988 module_exit(i915_exit);
 989
 990 MODULE_AUTHOR(DRIVER_AUTHOR);
 991 MODULE_DESCRIPTION(DRIVER_DESC);
 992 MODULE_LICENSE("GPL and additional rights");
 993
 994 #define __i915_read(x, y) \
 995 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 996         u##x val = 0; \
 997         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 998                 unsigned long irqflags; \
 999                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1000                 if (dev_priv->forcewake_count == 0) \
1001                         dev_priv->display.force_wake_get(dev_priv); \
1002                 val = read##y(dev_priv->regs + reg); \
1003                 if (dev_priv->forcewake_count == 0) \
1004                         dev_priv->display.force_wake_put(dev_priv); \
1005                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1006         } else { \
1007                 val = read##y(dev_priv->regs + reg); \
1008         } \
1009         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1010         return val; \
1011 }
1012
1013 __i915_read(8, b)
1014 __i915_read(16, w)
1015 __i915_read(32, l)
1016 __i915_read(64, q)
1017 #undef __i915_read
1018
1019 #define __i915_write(x, y) \
1020 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1021         u32 __fifo_ret = 0; \
1022         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1023         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1024                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1025         } \
1026         write##y(val, dev_priv->regs + reg); \
1027         if (unlikely(__fifo_ret)) { \
1028                 gen6_gt_check_fifodbg(dev_priv); \
1029         } \
1030 }
1031 __i915_write(8, b)
1032 __i915_write(16, w)
1033 __i915_write(32, l)
1034 __i915_write(64, q)
1035 #undef __i915_write