1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
40 static int i915_modeset = -1;
41 module_param_named(modeset, i915_modeset, int, 0400);
43 unsigned int i915_fbpercrtc = 0;
44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
46 unsigned int i915_powersave = 1;
47 module_param_named(powersave, i915_powersave, int, 0600);
49 unsigned int i915_lvds_downclock = 0;
50 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
52 static struct drm_driver driver;
53 extern int intel_agp_enabled;
55 #define INTEL_VGA_DEVICE(id, info) { \
56 .class = PCI_CLASS_DISPLAY_VGA << 8, \
57 .class_mask = 0xffff00, \
60 .subvendor = PCI_ANY_ID, \
61 .subdevice = PCI_ANY_ID, \
62 .driver_data = (unsigned long) info }
64 static const struct intel_device_info intel_i830_info = {
65 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
66 .has_overlay = 1, .overlay_needs_physical = 1,
69 static const struct intel_device_info intel_845g_info = {
71 .has_overlay = 1, .overlay_needs_physical = 1,
74 static const struct intel_device_info intel_i85x_info = {
75 .gen = 2, .is_i85x = 1, .is_mobile = 1,
76 .cursor_needs_physical = 1,
77 .has_overlay = 1, .overlay_needs_physical = 1,
80 static const struct intel_device_info intel_i865g_info = {
82 .has_overlay = 1, .overlay_needs_physical = 1,
85 static const struct intel_device_info intel_i915g_info = {
86 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
87 .has_overlay = 1, .overlay_needs_physical = 1,
89 static const struct intel_device_info intel_i915gm_info = {
90 .gen = 3, .is_mobile = 1,
91 .cursor_needs_physical = 1,
92 .has_overlay = 1, .overlay_needs_physical = 1,
95 static const struct intel_device_info intel_i945g_info = {
96 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
97 .has_overlay = 1, .overlay_needs_physical = 1,
99 static const struct intel_device_info intel_i945gm_info = {
100 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
101 .has_hotplug = 1, .cursor_needs_physical = 1,
102 .has_overlay = 1, .overlay_needs_physical = 1,
106 static const struct intel_device_info intel_i965g_info = {
107 .gen = 4, .is_broadwater = 1,
112 static const struct intel_device_info intel_i965gm_info = {
113 .gen = 4, .is_crestline = 1,
114 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
119 static const struct intel_device_info intel_g33_info = {
120 .gen = 3, .is_g33 = 1,
121 .need_gfx_hws = 1, .has_hotplug = 1,
125 static const struct intel_device_info intel_g45_info = {
126 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
127 .has_pipe_cxsr = 1, .has_hotplug = 1,
131 static const struct intel_device_info intel_gm45_info = {
132 .gen = 4, .is_g4x = 1,
133 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
134 .has_pipe_cxsr = 1, .has_hotplug = 1,
139 static const struct intel_device_info intel_pineview_info = {
140 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
141 .need_gfx_hws = 1, .has_hotplug = 1,
145 static const struct intel_device_info intel_ironlake_d_info = {
147 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
151 static const struct intel_device_info intel_ironlake_m_info = {
152 .gen = 5, .is_mobile = 1,
153 .need_gfx_hws = 1, .has_hotplug = 1,
154 .has_fbc = 0, /* disabled due to buggy hardware */
158 static const struct intel_device_info intel_sandybridge_d_info = {
160 .need_gfx_hws = 1, .has_hotplug = 1,
165 static const struct intel_device_info intel_sandybridge_m_info = {
166 .gen = 6, .is_mobile = 1,
167 .need_gfx_hws = 1, .has_hotplug = 1,
172 static const struct pci_device_id pciidlist[] = { /* aka */
173 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
174 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
175 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
176 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
177 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
178 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
179 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
180 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
181 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
182 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
183 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
184 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
185 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
186 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
187 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
188 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
189 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
190 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
191 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
192 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
193 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
194 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
195 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
196 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
197 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
198 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
199 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
200 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
201 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
202 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
203 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
204 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
205 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
206 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
207 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
208 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
209 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
210 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
214 #if defined(CONFIG_DRM_I915_KMS)
215 MODULE_DEVICE_TABLE(pci, pciidlist);
218 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
219 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
221 void intel_detect_pch (struct drm_device *dev)
223 struct drm_i915_private *dev_priv = dev->dev_private;
227 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
228 * make graphics device passthrough work easy for VMM, that only
229 * need to expose ISA bridge to let driver know the real hardware
230 * underneath. This is a requirement from virtualization team.
232 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
234 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
236 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
238 if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
239 dev_priv->pch_type = PCH_CPT;
240 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
247 static int i915_drm_freeze(struct drm_device *dev)
249 struct drm_i915_private *dev_priv = dev->dev_private;
251 pci_save_state(dev->pdev);
253 /* If KMS is active, we do the leavevt stuff here */
254 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
255 int error = i915_gem_idle(dev);
257 dev_err(&dev->pdev->dev,
258 "GEM idle failed, resume might fail\n");
261 drm_irq_uninstall(dev);
264 i915_save_state(dev);
266 intel_opregion_fini(dev);
268 /* Modeset on resume, not lid events */
269 dev_priv->modeset_on_lid = 0;
274 int i915_suspend(struct drm_device *dev, pm_message_t state)
278 if (!dev || !dev->dev_private) {
279 DRM_ERROR("dev: %p\n", dev);
280 DRM_ERROR("DRM not initialized, aborting suspend.\n");
284 if (state.event == PM_EVENT_PRETHAW)
287 drm_kms_helper_poll_disable(dev);
289 error = i915_drm_freeze(dev);
293 if (state.event == PM_EVENT_SUSPEND) {
294 /* Shut down the device */
295 pci_disable_device(dev->pdev);
296 pci_set_power_state(dev->pdev, PCI_D3hot);
302 static int i915_drm_thaw(struct drm_device *dev)
304 struct drm_i915_private *dev_priv = dev->dev_private;
307 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
308 mutex_lock(&dev->struct_mutex);
309 i915_gem_restore_gtt_mappings(dev);
310 mutex_unlock(&dev->struct_mutex);
313 i915_restore_state(dev);
314 intel_opregion_setup(dev);
316 /* KMS EnterVT equivalent */
317 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
318 mutex_lock(&dev->struct_mutex);
319 dev_priv->mm.suspended = 0;
321 error = i915_gem_init_ringbuffer(dev);
322 mutex_unlock(&dev->struct_mutex);
324 drm_irq_install(dev);
326 /* Resume the modeset for every activated CRTC */
327 drm_helper_resume_force_mode(dev);
330 intel_opregion_init(dev);
332 dev_priv->modeset_on_lid = 0;
337 int i915_resume(struct drm_device *dev)
341 if (pci_enable_device(dev->pdev))
344 pci_set_master(dev->pdev);
346 ret = i915_drm_thaw(dev);
350 drm_kms_helper_poll_enable(dev);
354 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
356 struct drm_i915_private *dev_priv = dev->dev_private;
361 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
362 POSTING_READ(D_STATE);
364 if (IS_I830(dev) || IS_845G(dev)) {
365 I915_WRITE(DEBUG_RESET_I830,
366 DEBUG_RESET_DISPLAY |
369 POSTING_READ(DEBUG_RESET_I830);
372 I915_WRITE(DEBUG_RESET_I830, 0);
373 POSTING_READ(DEBUG_RESET_I830);
378 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
379 POSTING_READ(D_STATE);
384 static int i965_reset_complete(struct drm_device *dev)
387 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
391 static int i965_do_reset(struct drm_device *dev, u8 flags)
396 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
397 * well as the reset bit (GR/bit 0). Setting the GR bit
398 * triggers the reset; when done, the hardware will clear it.
400 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
401 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
403 return wait_for(i965_reset_complete(dev), 500);
406 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
410 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
411 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
414 static int gen6_do_reset(struct drm_device *dev, u8 flags)
416 struct drm_i915_private *dev_priv = dev->dev_private;
418 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
419 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
423 * i965_reset - reset chip after a hang
424 * @dev: drm device to reset
425 * @flags: reset domains
427 * Reset the chip. Useful if a hang is detected. Returns zero on successful
428 * reset or otherwise an error code.
430 * Procedure is fairly simple:
431 * - reset the chip using the reset reg
432 * - re-init context state
433 * - re-init hardware status page
434 * - re-init ring buffer
435 * - re-init interrupt state
438 int i915_reset(struct drm_device *dev, u8 flags)
440 drm_i915_private_t *dev_priv = dev->dev_private;
442 * We really should only reset the display subsystem if we actually
445 bool need_display = true;
448 if (!mutex_trylock(&dev->struct_mutex))
454 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
455 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
456 } else switch (INTEL_INFO(dev)->gen) {
458 ret = gen6_do_reset(dev, flags);
461 ret = ironlake_do_reset(dev, flags);
464 ret = i965_do_reset(dev, flags);
467 ret = i8xx_do_reset(dev, flags);
470 dev_priv->last_gpu_reset = get_seconds();
472 DRM_ERROR("Failed to reset chip.\n");
473 mutex_unlock(&dev->struct_mutex);
477 /* Ok, now get things going again... */
480 * Everything depends on having the GTT running, so we need to start
481 * there. Fortunately we don't need to do this unless we reset the
482 * chip at a PCI level.
484 * Next we need to restore the context, but we don't use those
487 * Ring buffer needs to be re-initialized in the KMS case, or if X
488 * was running at the time of the reset (i.e. we weren't VT
491 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
492 !dev_priv->mm.suspended) {
493 dev_priv->mm.suspended = 0;
495 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
497 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
499 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
501 mutex_unlock(&dev->struct_mutex);
502 drm_irq_uninstall(dev);
503 drm_irq_install(dev);
504 mutex_lock(&dev->struct_mutex);
507 mutex_unlock(&dev->struct_mutex);
510 * Perform a full modeset as on later generations, e.g. Ironlake, we may
511 * need to retrain the display link and cannot just restore the register
515 mutex_lock(&dev->mode_config.mutex);
516 drm_helper_resume_force_mode(dev);
517 mutex_unlock(&dev->mode_config.mutex);
525 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
527 return drm_get_pci_dev(pdev, ent, &driver);
531 i915_pci_remove(struct pci_dev *pdev)
533 struct drm_device *dev = pci_get_drvdata(pdev);
538 static int i915_pm_suspend(struct device *dev)
540 struct pci_dev *pdev = to_pci_dev(dev);
541 struct drm_device *drm_dev = pci_get_drvdata(pdev);
544 if (!drm_dev || !drm_dev->dev_private) {
545 dev_err(dev, "DRM not initialized, aborting suspend.\n");
549 error = i915_drm_freeze(drm_dev);
553 pci_disable_device(pdev);
554 pci_set_power_state(pdev, PCI_D3hot);
559 static int i915_pm_resume(struct device *dev)
561 struct pci_dev *pdev = to_pci_dev(dev);
562 struct drm_device *drm_dev = pci_get_drvdata(pdev);
564 return i915_resume(drm_dev);
567 static int i915_pm_freeze(struct device *dev)
569 struct pci_dev *pdev = to_pci_dev(dev);
570 struct drm_device *drm_dev = pci_get_drvdata(pdev);
572 if (!drm_dev || !drm_dev->dev_private) {
573 dev_err(dev, "DRM not initialized, aborting suspend.\n");
577 return i915_drm_freeze(drm_dev);
580 static int i915_pm_thaw(struct device *dev)
582 struct pci_dev *pdev = to_pci_dev(dev);
583 struct drm_device *drm_dev = pci_get_drvdata(pdev);
585 return i915_drm_thaw(drm_dev);
588 static int i915_pm_poweroff(struct device *dev)
590 struct pci_dev *pdev = to_pci_dev(dev);
591 struct drm_device *drm_dev = pci_get_drvdata(pdev);
593 return i915_drm_freeze(drm_dev);
596 static const struct dev_pm_ops i915_pm_ops = {
597 .suspend = i915_pm_suspend,
598 .resume = i915_pm_resume,
599 .freeze = i915_pm_freeze,
600 .thaw = i915_pm_thaw,
601 .poweroff = i915_pm_poweroff,
602 .restore = i915_pm_resume,
605 static struct vm_operations_struct i915_gem_vm_ops = {
606 .fault = i915_gem_fault,
607 .open = drm_gem_vm_open,
608 .close = drm_gem_vm_close,
611 static struct drm_driver driver = {
612 /* don't use mtrr's here, the Xserver or user space app should
613 * deal with them for intel hardware.
616 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
617 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
618 .load = i915_driver_load,
619 .unload = i915_driver_unload,
620 .open = i915_driver_open,
621 .lastclose = i915_driver_lastclose,
622 .preclose = i915_driver_preclose,
623 .postclose = i915_driver_postclose,
625 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
626 .suspend = i915_suspend,
627 .resume = i915_resume,
629 .device_is_agp = i915_driver_device_is_agp,
630 .enable_vblank = i915_enable_vblank,
631 .disable_vblank = i915_disable_vblank,
632 .irq_preinstall = i915_driver_irq_preinstall,
633 .irq_postinstall = i915_driver_irq_postinstall,
634 .irq_uninstall = i915_driver_irq_uninstall,
635 .irq_handler = i915_driver_irq_handler,
636 .reclaim_buffers = drm_core_reclaim_buffers,
637 .master_create = i915_master_create,
638 .master_destroy = i915_master_destroy,
639 #if defined(CONFIG_DEBUG_FS)
640 .debugfs_init = i915_debugfs_init,
641 .debugfs_cleanup = i915_debugfs_cleanup,
643 .gem_init_object = i915_gem_init_object,
644 .gem_free_object = i915_gem_free_object,
645 .gem_vm_ops = &i915_gem_vm_ops,
646 .ioctls = i915_ioctls,
648 .owner = THIS_MODULE,
650 .release = drm_release,
651 .unlocked_ioctl = drm_ioctl,
652 .mmap = drm_gem_mmap,
654 .fasync = drm_fasync,
657 .compat_ioctl = i915_compat_ioctl,
659 .llseek = noop_llseek,
664 .id_table = pciidlist,
665 .probe = i915_pci_probe,
666 .remove = i915_pci_remove,
667 .driver.pm = &i915_pm_ops,
673 .major = DRIVER_MAJOR,
674 .minor = DRIVER_MINOR,
675 .patchlevel = DRIVER_PATCHLEVEL,
678 static int __init i915_init(void)
680 if (!intel_agp_enabled) {
681 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
685 driver.num_ioctls = i915_max_ioctl;
688 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
689 * explicitly disabled with the module pararmeter.
691 * Otherwise, just follow the parameter (defaulting to off).
693 * Allow optional vga_text_mode_force boot option to override
694 * the default behavior.
696 #if defined(CONFIG_DRM_I915_KMS)
697 if (i915_modeset != 0)
698 driver.driver_features |= DRIVER_MODESET;
700 if (i915_modeset == 1)
701 driver.driver_features |= DRIVER_MODESET;
703 #ifdef CONFIG_VGA_CONSOLE
704 if (vgacon_text_force() && i915_modeset == -1)
705 driver.driver_features &= ~DRIVER_MODESET;
708 return drm_init(&driver);
711 static void __exit i915_exit(void)
716 module_init(i915_init);
717 module_exit(i915_exit);
719 MODULE_AUTHOR(DRIVER_AUTHOR);
720 MODULE_DESCRIPTION(DRIVER_DESC);
721 MODULE_LICENSE("GPL and additional rights");