drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 unsigned int i915_powersave = 1;
  47 module_param_named(powersave, i915_powersave, int, 0600);
  48
  49 unsigned int i915_lvds_downclock = 0;
  50 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  51
  52 bool i915_try_reset = true;
  53 module_param_named(reset, i915_try_reset, bool, 0600);
  54
  55 static struct drm_driver driver;
  56 extern int intel_agp_enabled;
  57
  58 #define INTEL_VGA_DEVICE(id, info) {            \
  59         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  60         .class_mask = 0xffff00,                 \
  61         .vendor = 0x8086,                       \
  62         .device = id,                           \
  63         .subvendor = PCI_ANY_ID,                \
  64         .subdevice = PCI_ANY_ID,                \
  65         .driver_data = (unsigned long) info }
  66
  67 static const struct intel_device_info intel_i830_info = {
  68         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  69         .has_overlay = 1, .overlay_needs_physical = 1,
  70 };
  71
  72 static const struct intel_device_info intel_845g_info = {
  73         .gen = 2,
  74         .has_overlay = 1, .overlay_needs_physical = 1,
  75 };
  76
  77 static const struct intel_device_info intel_i85x_info = {
  78         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  79         .cursor_needs_physical = 1,
  80         .has_overlay = 1, .overlay_needs_physical = 1,
  81 };
  82
  83 static const struct intel_device_info intel_i865g_info = {
  84         .gen = 2,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86 };
  87
  88 static const struct intel_device_info intel_i915g_info = {
  89         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  90         .has_overlay = 1, .overlay_needs_physical = 1,
  91 };
  92 static const struct intel_device_info intel_i915gm_info = {
  93         .gen = 3, .is_mobile = 1,
  94         .cursor_needs_physical = 1,
  95         .has_overlay = 1, .overlay_needs_physical = 1,
  96         .supports_tv = 1,
  97 };
  98 static const struct intel_device_info intel_i945g_info = {
  99         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 100         .has_overlay = 1, .overlay_needs_physical = 1,
 101 };
 102 static const struct intel_device_info intel_i945gm_info = {
 103         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 104         .has_hotplug = 1, .cursor_needs_physical = 1,
 105         .has_overlay = 1, .overlay_needs_physical = 1,
 106         .supports_tv = 1,
 107 };
 108
 109 static const struct intel_device_info intel_i965g_info = {
 110         .gen = 4, .is_broadwater = 1,
 111         .has_hotplug = 1,
 112         .has_overlay = 1,
 113 };
 114
 115 static const struct intel_device_info intel_i965gm_info = {
 116         .gen = 4, .is_crestline = 1,
 117         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 118         .has_overlay = 1,
 119         .supports_tv = 1,
 120 };
 121
 122 static const struct intel_device_info intel_g33_info = {
 123         .gen = 3, .is_g33 = 1,
 124         .need_gfx_hws = 1, .has_hotplug = 1,
 125         .has_overlay = 1,
 126 };
 127
 128 static const struct intel_device_info intel_g45_info = {
 129         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 130         .has_pipe_cxsr = 1, .has_hotplug = 1,
 131         .has_bsd_ring = 1,
 132 };
 133
 134 static const struct intel_device_info intel_gm45_info = {
 135         .gen = 4, .is_g4x = 1,
 136         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 137         .has_pipe_cxsr = 1, .has_hotplug = 1,
 138         .supports_tv = 1,
 139         .has_bsd_ring = 1,
 140 };
 141
 142 static const struct intel_device_info intel_pineview_info = {
 143         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 144         .need_gfx_hws = 1, .has_hotplug = 1,
 145         .has_overlay = 1,
 146 };
 147
 148 static const struct intel_device_info intel_ironlake_d_info = {
 149         .gen = 5,
 150         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 151         .has_bsd_ring = 1,
 152 };
 153
 154 static const struct intel_device_info intel_ironlake_m_info = {
 155         .gen = 5, .is_mobile = 1,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_fbc = 0, /* disabled due to buggy hardware */
 158         .has_bsd_ring = 1,
 159 };
 160
 161 static const struct intel_device_info intel_sandybridge_d_info = {
 162         .gen = 6,
 163         .need_gfx_hws = 1, .has_hotplug = 1,
 164         .has_bsd_ring = 1,
 165         .has_blt_ring = 1,
 166 };
 167
 168 static const struct intel_device_info intel_sandybridge_m_info = {
 169         .gen = 6, .is_mobile = 1,
 170         .need_gfx_hws = 1, .has_hotplug = 1,
 171         .has_fbc = 1,
 172         .has_bsd_ring = 1,
 173         .has_blt_ring = 1,
 174 };
 175
 176 static const struct pci_device_id pciidlist[] = {               /* aka */
 177         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 178         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 179         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 180         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 181         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 182         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 183         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 184         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 185         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 186         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 187         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 188         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 189         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 190         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 191         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 192         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 193         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 194         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 195         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 196         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 197         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 198         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 199         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 200         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 201         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 202         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 203         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 204         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 205         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 206         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 207         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 208         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 209         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 210         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 211         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 212         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 213         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 214         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 215         {0, 0, 0}
 216 };
 217
 218 #if defined(CONFIG_DRM_I915_KMS)
 219 MODULE_DEVICE_TABLE(pci, pciidlist);
 220 #endif
 221
 222 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 223 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 224
 225 void intel_detect_pch (struct drm_device *dev)
 226 {
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228         struct pci_dev *pch;
 229
 230         /*
 231          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 232          * make graphics device passthrough work easy for VMM, that only
 233          * need to expose ISA bridge to let driver know the real hardware
 234          * underneath. This is a requirement from virtualization team.
 235          */
 236         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 237         if (pch) {
 238                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 239                         int id;
 240                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 241
 242                         if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 243                                 dev_priv->pch_type = PCH_CPT;
 244                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 245                         }
 246                 }
 247                 pci_dev_put(pch);
 248         }
 249 }
 250
 251 void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
 252 {
 253         int count;
 254
 255         count = 0;
 256         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 257                 udelay(10);
 258
 259         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 260         POSTING_READ(FORCEWAKE);
 261
 262         count = 0;
 263         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 264                 udelay(10);
 265 }
 266
 267 void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
 268 {
 269         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 270         POSTING_READ(FORCEWAKE);
 271 }
 272
 273 static int i915_drm_freeze(struct drm_device *dev)
 274 {
 275         struct drm_i915_private *dev_priv = dev->dev_private;
 276
 277         drm_kms_helper_poll_disable(dev);
 278
 279         pci_save_state(dev->pdev);
 280
 281         /* If KMS is active, we do the leavevt stuff here */
 282         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 283                 int error = i915_gem_idle(dev);
 284                 if (error) {
 285                         dev_err(&dev->pdev->dev,
 286                                 "GEM idle failed, resume might fail\n");
 287                         return error;
 288                 }
 289                 drm_irq_uninstall(dev);
 290         }
 291
 292         i915_save_state(dev);
 293
 294         intel_opregion_fini(dev);
 295
 296         /* Modeset on resume, not lid events */
 297         dev_priv->modeset_on_lid = 0;
 298
 299         return 0;
 300 }
 301
 302 int i915_suspend(struct drm_device *dev, pm_message_t state)
 303 {
 304         int error;
 305
 306         if (!dev || !dev->dev_private) {
 307                 DRM_ERROR("dev: %p\n", dev);
 308                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 309                 return -ENODEV;
 310         }
 311
 312         if (state.event == PM_EVENT_PRETHAW)
 313                 return 0;
 314
 315
 316         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 317                 return 0;
 318
 319         error = i915_drm_freeze(dev);
 320         if (error)
 321                 return error;
 322
 323         if (state.event == PM_EVENT_SUSPEND) {
 324                 /* Shut down the device */
 325                 pci_disable_device(dev->pdev);
 326                 pci_set_power_state(dev->pdev, PCI_D3hot);
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int i915_drm_thaw(struct drm_device *dev)
 333 {
 334         struct drm_i915_private *dev_priv = dev->dev_private;
 335         int error = 0;
 336
 337         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 338                 mutex_lock(&dev->struct_mutex);
 339                 i915_gem_restore_gtt_mappings(dev);
 340                 mutex_unlock(&dev->struct_mutex);
 341         }
 342
 343         i915_restore_state(dev);
 344         intel_opregion_setup(dev);
 345
 346         /* KMS EnterVT equivalent */
 347         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 348                 mutex_lock(&dev->struct_mutex);
 349                 dev_priv->mm.suspended = 0;
 350
 351                 error = i915_gem_init_ringbuffer(dev);
 352                 mutex_unlock(&dev->struct_mutex);
 353
 354                 drm_irq_install(dev);
 355
 356                 /* Resume the modeset for every activated CRTC */
 357                 drm_helper_resume_force_mode(dev);
 358         }
 359
 360         intel_opregion_init(dev);
 361
 362         dev_priv->modeset_on_lid = 0;
 363
 364         return error;
 365 }
 366
 367 int i915_resume(struct drm_device *dev)
 368 {
 369         int ret;
 370
 371         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 372                 return 0;
 373
 374         if (pci_enable_device(dev->pdev))
 375                 return -EIO;
 376
 377         pci_set_master(dev->pdev);
 378
 379         ret = i915_drm_thaw(dev);
 380         if (ret)
 381                 return ret;
 382
 383         drm_kms_helper_poll_enable(dev);
 384         return 0;
 385 }
 386
 387 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390
 391         if (IS_I85X(dev))
 392                 return -ENODEV;
 393
 394         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 395         POSTING_READ(D_STATE);
 396
 397         if (IS_I830(dev) || IS_845G(dev)) {
 398                 I915_WRITE(DEBUG_RESET_I830,
 399                            DEBUG_RESET_DISPLAY |
 400                            DEBUG_RESET_RENDER |
 401                            DEBUG_RESET_FULL);
 402                 POSTING_READ(DEBUG_RESET_I830);
 403                 msleep(1);
 404
 405                 I915_WRITE(DEBUG_RESET_I830, 0);
 406                 POSTING_READ(DEBUG_RESET_I830);
 407         }
 408
 409         msleep(1);
 410
 411         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 412         POSTING_READ(D_STATE);
 413
 414         return 0;
 415 }
 416
 417 static int i965_reset_complete(struct drm_device *dev)
 418 {
 419         u8 gdrst;
 420         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 421         return gdrst & 0x1;
 422 }
 423
 424 static int i965_do_reset(struct drm_device *dev, u8 flags)
 425 {
 426         u8 gdrst;
 427
 428         /*
 429          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 430          * well as the reset bit (GR/bit 0).  Setting the GR bit
 431          * triggers the reset; when done, the hardware will clear it.
 432          */
 433         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 434         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 435
 436         return wait_for(i965_reset_complete(dev), 500);
 437 }
 438
 439 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 440 {
 441         struct drm_i915_private *dev_priv = dev->dev_private;
 442         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 443         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 444         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 445 }
 446
 447 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 448 {
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450
 451         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 452         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 453 }
 454
 455 /**
 456  * i965_reset - reset chip after a hang
 457  * @dev: drm device to reset
 458  * @flags: reset domains
 459  *
 460  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 461  * reset or otherwise an error code.
 462  *
 463  * Procedure is fairly simple:
 464  *   - reset the chip using the reset reg
 465  *   - re-init context state
 466  *   - re-init hardware status page
 467  *   - re-init ring buffer
 468  *   - re-init interrupt state
 469  *   - re-init display
 470  */
 471 int i915_reset(struct drm_device *dev, u8 flags)
 472 {
 473         drm_i915_private_t *dev_priv = dev->dev_private;
 474         /*
 475          * We really should only reset the display subsystem if we actually
 476          * need to
 477          */
 478         bool need_display = true;
 479         int ret;
 480
 481         if (!i915_try_reset)
 482                 return 0;
 483
 484         if (!mutex_trylock(&dev->struct_mutex))
 485                 return -EBUSY;
 486
 487         i915_gem_reset(dev);
 488
 489         ret = -ENODEV;
 490         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 491                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 492         } else switch (INTEL_INFO(dev)->gen) {
 493         case 6:
 494                 ret = gen6_do_reset(dev, flags);
 495                 break;
 496         case 5:
 497                 ret = ironlake_do_reset(dev, flags);
 498                 break;
 499         case 4:
 500                 ret = i965_do_reset(dev, flags);
 501                 break;
 502         case 2:
 503                 ret = i8xx_do_reset(dev, flags);
 504                 break;
 505         }
 506         dev_priv->last_gpu_reset = get_seconds();
 507         if (ret) {
 508                 DRM_ERROR("Failed to reset chip.\n");
 509                 mutex_unlock(&dev->struct_mutex);
 510                 return ret;
 511         }
 512
 513         /* Ok, now get things going again... */
 514
 515         /*
 516          * Everything depends on having the GTT running, so we need to start
 517          * there.  Fortunately we don't need to do this unless we reset the
 518          * chip at a PCI level.
 519          *
 520          * Next we need to restore the context, but we don't use those
 521          * yet either...
 522          *
 523          * Ring buffer needs to be re-initialized in the KMS case, or if X
 524          * was running at the time of the reset (i.e. we weren't VT
 525          * switched away).
 526          */
 527         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 528                         !dev_priv->mm.suspended) {
 529                 dev_priv->mm.suspended = 0;
 530
 531                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 532                 if (HAS_BSD(dev))
 533                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 534                 if (HAS_BLT(dev))
 535                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 536
 537                 mutex_unlock(&dev->struct_mutex);
 538                 drm_irq_uninstall(dev);
 539                 drm_irq_install(dev);
 540                 mutex_lock(&dev->struct_mutex);
 541         }
 542
 543         mutex_unlock(&dev->struct_mutex);
 544
 545         /*
 546          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 547          * need to retrain the display link and cannot just restore the register
 548          * values.
 549          */
 550         if (need_display) {
 551                 mutex_lock(&dev->mode_config.mutex);
 552                 drm_helper_resume_force_mode(dev);
 553                 mutex_unlock(&dev->mode_config.mutex);
 554         }
 555
 556         return 0;
 557 }
 558
 559
 560 static int __devinit
 561 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 562 {
 563         return drm_get_pci_dev(pdev, ent, &driver);
 564 }
 565
 566 static void
 567 i915_pci_remove(struct pci_dev *pdev)
 568 {
 569         struct drm_device *dev = pci_get_drvdata(pdev);
 570
 571         drm_put_dev(dev);
 572 }
 573
 574 static int i915_pm_suspend(struct device *dev)
 575 {
 576         struct pci_dev *pdev = to_pci_dev(dev);
 577         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 578         int error;
 579
 580         if (!drm_dev || !drm_dev->dev_private) {
 581                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 582                 return -ENODEV;
 583         }
 584
 585         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 586                 return 0;
 587
 588         error = i915_drm_freeze(drm_dev);
 589         if (error)
 590                 return error;
 591
 592         pci_disable_device(pdev);
 593         pci_set_power_state(pdev, PCI_D3hot);
 594
 595         return 0;
 596 }
 597
 598 static int i915_pm_resume(struct device *dev)
 599 {
 600         struct pci_dev *pdev = to_pci_dev(dev);
 601         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 602
 603         return i915_resume(drm_dev);
 604 }
 605
 606 static int i915_pm_freeze(struct device *dev)
 607 {
 608         struct pci_dev *pdev = to_pci_dev(dev);
 609         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 610
 611         if (!drm_dev || !drm_dev->dev_private) {
 612                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 613                 return -ENODEV;
 614         }
 615
 616         return i915_drm_freeze(drm_dev);
 617 }
 618
 619 static int i915_pm_thaw(struct device *dev)
 620 {
 621         struct pci_dev *pdev = to_pci_dev(dev);
 622         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 623
 624         return i915_drm_thaw(drm_dev);
 625 }
 626
 627 static int i915_pm_poweroff(struct device *dev)
 628 {
 629         struct pci_dev *pdev = to_pci_dev(dev);
 630         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 631
 632         return i915_drm_freeze(drm_dev);
 633 }
 634
 635 static const struct dev_pm_ops i915_pm_ops = {
 636      .suspend = i915_pm_suspend,
 637      .resume = i915_pm_resume,
 638      .freeze = i915_pm_freeze,
 639      .thaw = i915_pm_thaw,
 640      .poweroff = i915_pm_poweroff,
 641      .restore = i915_pm_resume,
 642 };
 643
 644 static struct vm_operations_struct i915_gem_vm_ops = {
 645         .fault = i915_gem_fault,
 646         .open = drm_gem_vm_open,
 647         .close = drm_gem_vm_close,
 648 };
 649
 650 static struct drm_driver driver = {
 651         /* don't use mtrr's here, the Xserver or user space app should
 652          * deal with them for intel hardware.
 653          */
 654         .driver_features =
 655             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 656             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 657         .load = i915_driver_load,
 658         .unload = i915_driver_unload,
 659         .open = i915_driver_open,
 660         .lastclose = i915_driver_lastclose,
 661         .preclose = i915_driver_preclose,
 662         .postclose = i915_driver_postclose,
 663
 664         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 665         .suspend = i915_suspend,
 666         .resume = i915_resume,
 667
 668         .device_is_agp = i915_driver_device_is_agp,
 669         .enable_vblank = i915_enable_vblank,
 670         .disable_vblank = i915_disable_vblank,
 671         .get_vblank_timestamp = i915_get_vblank_timestamp,
 672         .get_scanout_position = i915_get_crtc_scanoutpos,
 673         .irq_preinstall = i915_driver_irq_preinstall,
 674         .irq_postinstall = i915_driver_irq_postinstall,
 675         .irq_uninstall = i915_driver_irq_uninstall,
 676         .irq_handler = i915_driver_irq_handler,
 677         .reclaim_buffers = drm_core_reclaim_buffers,
 678         .master_create = i915_master_create,
 679         .master_destroy = i915_master_destroy,
 680 #if defined(CONFIG_DEBUG_FS)
 681         .debugfs_init = i915_debugfs_init,
 682         .debugfs_cleanup = i915_debugfs_cleanup,
 683 #endif
 684         .gem_init_object = i915_gem_init_object,
 685         .gem_free_object = i915_gem_free_object,
 686         .gem_vm_ops = &i915_gem_vm_ops,
 687         .ioctls = i915_ioctls,
 688         .fops = {
 689                  .owner = THIS_MODULE,
 690                  .open = drm_open,
 691                  .release = drm_release,
 692                  .unlocked_ioctl = drm_ioctl,
 693                  .mmap = drm_gem_mmap,
 694                  .poll = drm_poll,
 695                  .fasync = drm_fasync,
 696                  .read = drm_read,
 697 #ifdef CONFIG_COMPAT
 698                  .compat_ioctl = i915_compat_ioctl,
 699 #endif
 700                  .llseek = noop_llseek,
 701         },
 702
 703         .pci_driver = {
 704                  .name = DRIVER_NAME,
 705                  .id_table = pciidlist,
 706                  .probe = i915_pci_probe,
 707                  .remove = i915_pci_remove,
 708                  .driver.pm = &i915_pm_ops,
 709         },
 710
 711         .name = DRIVER_NAME,
 712         .desc = DRIVER_DESC,
 713         .date = DRIVER_DATE,
 714         .major = DRIVER_MAJOR,
 715         .minor = DRIVER_MINOR,
 716         .patchlevel = DRIVER_PATCHLEVEL,
 717 };
 718
 719 static int __init i915_init(void)
 720 {
 721         if (!intel_agp_enabled) {
 722                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 723                 return -ENODEV;
 724         }
 725
 726         driver.num_ioctls = i915_max_ioctl;
 727
 728         /*
 729          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 730          * explicitly disabled with the module pararmeter.
 731          *
 732          * Otherwise, just follow the parameter (defaulting to off).
 733          *
 734          * Allow optional vga_text_mode_force boot option to override
 735          * the default behavior.
 736          */
 737 #if defined(CONFIG_DRM_I915_KMS)
 738         if (i915_modeset != 0)
 739                 driver.driver_features |= DRIVER_MODESET;
 740 #endif
 741         if (i915_modeset == 1)
 742                 driver.driver_features |= DRIVER_MODESET;
 743
 744 #ifdef CONFIG_VGA_CONSOLE
 745         if (vgacon_text_force() && i915_modeset == -1)
 746                 driver.driver_features &= ~DRIVER_MODESET;
 747 #endif
 748
 749         return drm_init(&driver);
 750 }
 751
 752 static void __exit i915_exit(void)
 753 {
 754         drm_exit(&driver);
 755 }
 756
 757 module_init(i915_init);
 758 module_exit(i915_exit);
 759
 760 MODULE_AUTHOR(DRIVER_AUTHOR);
 761 MODULE_DESCRIPTION(DRIVER_DESC);
 762 MODULE_LICENSE("GPL and additional rights");