1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay;
118 struct intel_overlay_error_state;
120 struct drm_i915_master_private {
121 drm_local_map_t *sarea;
122 struct _drm_i915_sarea *sarea_priv;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg {
127 struct drm_gem_object *obj;
128 struct list_head lru_list;
132 struct sdvo_device_mapping {
142 struct drm_i915_error_state {
151 u32 error; /* gen6+ */
152 u32 bcs_acthd; /* gen6+ blt engine */
157 u32 vcs_acthd; /* gen6+ bsd engine */
168 struct drm_i915_error_object {
172 } *ringbuffer, *batchbuffer[2];
173 struct drm_i915_error_buffer {
188 struct intel_overlay_error_state *overlay;
191 struct drm_i915_display_funcs {
192 void (*dpms)(struct drm_crtc *crtc, int mode);
193 bool (*fbc_enabled)(struct drm_device *dev);
194 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
195 void (*disable_fbc)(struct drm_device *dev);
196 int (*get_display_clock_speed)(struct drm_device *dev);
197 int (*get_fifo_size)(struct drm_device *dev, int plane);
198 void (*update_wm)(struct drm_device *dev, int planea_clock,
199 int planeb_clock, int sr_hdisplay, int sr_htotal,
201 /* clock updates for mode set */
203 /* render clock increase/decrease */
204 /* display clock increase/decrease */
205 /* pll clock increase/decrease */
206 /* clock gating init */
209 struct intel_device_info {
219 u8 is_broadwater : 1;
223 u8 has_pipe_cxsr : 1;
225 u8 cursor_needs_physical : 1;
227 u8 overlay_needs_physical : 1;
234 FBC_NO_OUTPUT, /* no outputs enabled to compress */
235 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
236 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
237 FBC_MODE_TOO_LARGE, /* mode too large for compression */
238 FBC_BAD_PLANE, /* fbc not supported on plane */
239 FBC_NOT_TILED, /* buffer not tiled */
240 FBC_MULTIPLE_PIPES, /* more than one pipe active */
244 PCH_IBX, /* Ibexpeak PCH */
245 PCH_CPT, /* Cougarpoint PCH */
248 #define QUIRK_PIPEA_FORCE (1<<0)
252 typedef struct drm_i915_private {
253 struct drm_device *dev;
255 const struct intel_device_info *info;
262 struct i2c_adapter adapter;
263 struct i2c_adapter *force_bit;
267 struct pci_dev *bridge_dev;
268 struct intel_ring_buffer render_ring;
269 struct intel_ring_buffer bsd_ring;
270 struct intel_ring_buffer blt_ring;
273 drm_dma_handle_t *status_page_dmah;
275 dma_addr_t dma_status_page;
277 unsigned int seqno_gfx_addr;
278 drm_local_map_t hws_map;
279 struct drm_gem_object *seqno_obj;
280 struct drm_gem_object *pwrctx;
281 struct drm_gem_object *renderctx;
283 struct resource mch_res;
291 wait_queue_head_t irq_queue;
292 atomic_t irq_received;
293 /** Protects user_irq_refcount and irq_mask_reg */
294 spinlock_t user_irq_lock;
296 /** Cached value of IMR to avoid reads in updating the bitfield */
299 /** splitted irq regs for graphics and display engine on Ironlake,
300 irq_mask_reg is still used for display irq. */
302 u32 gt_irq_enable_reg;
303 u32 de_irq_enable_reg;
304 u32 pch_irq_mask_reg;
305 u32 pch_irq_enable_reg;
307 u32 hotplug_supported_mask;
308 struct work_struct hotplug_work;
310 int tex_lru_log_granularity;
311 int allow_batchbuffer;
312 struct mem_block *agp_heap;
313 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
317 /* For hangcheck timer */
318 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
319 struct timer_list hangcheck_timer;
322 uint32_t last_instdone;
323 uint32_t last_instdone1;
325 unsigned long cfb_size;
326 unsigned long cfb_pitch;
327 unsigned long cfb_offset;
334 struct intel_opregion opregion;
337 struct intel_overlay *overlay;
340 int backlight_level; /* restore backlight to this value */
341 struct drm_display_mode *panel_fixed_mode;
342 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
343 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
345 /* Feature bits from the VBIOS */
346 unsigned int int_tv_support:1;
347 unsigned int lvds_dither:1;
348 unsigned int lvds_vbt:1;
349 unsigned int int_crt_support:1;
350 unsigned int lvds_use_ssc:1;
361 struct edp_power_seq pps;
363 bool no_aux_handshake;
365 struct notifier_block lid_notifier;
368 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
369 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
370 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
372 unsigned int fsb_freq, mem_freq, is_ddr3;
374 spinlock_t error_lock;
375 struct drm_i915_error_state *first_error;
376 struct work_struct error_work;
377 struct completion error_completion;
378 struct workqueue_struct *wq;
380 /* Display functions */
381 struct drm_i915_display_funcs display;
383 /* PCH chipset type */
384 enum intel_pch pch_type;
386 unsigned long quirks;
411 u32 saveTRANS_HTOTAL_A;
412 u32 saveTRANS_HBLANK_A;
413 u32 saveTRANS_HSYNC_A;
414 u32 saveTRANS_VTOTAL_A;
415 u32 saveTRANS_VBLANK_A;
416 u32 saveTRANS_VSYNC_A;
424 u32 savePFIT_PGM_RATIOS;
425 u32 saveBLC_HIST_CTL;
427 u32 saveBLC_PWM_CTL2;
428 u32 saveBLC_CPU_PWM_CTL;
429 u32 saveBLC_CPU_PWM_CTL2;
442 u32 saveTRANS_HTOTAL_B;
443 u32 saveTRANS_HBLANK_B;
444 u32 saveTRANS_HSYNC_B;
445 u32 saveTRANS_VTOTAL_B;
446 u32 saveTRANS_VBLANK_B;
447 u32 saveTRANS_VSYNC_B;
461 u32 savePP_ON_DELAYS;
462 u32 savePP_OFF_DELAYS;
470 u32 savePFIT_CONTROL;
471 u32 save_palette_a[256];
472 u32 save_palette_b[256];
473 u32 saveDPFC_CB_BASE;
474 u32 saveFBC_CFB_BASE;
477 u32 saveFBC_CONTROL2;
487 u32 saveCACHE_MODE_0;
488 u32 saveMI_ARB_STATE;
499 uint64_t saveFENCE[16];
510 u32 savePIPEA_GMCH_DATA_M;
511 u32 savePIPEB_GMCH_DATA_M;
512 u32 savePIPEA_GMCH_DATA_N;
513 u32 savePIPEB_GMCH_DATA_N;
514 u32 savePIPEA_DP_LINK_M;
515 u32 savePIPEB_DP_LINK_M;
516 u32 savePIPEA_DP_LINK_N;
517 u32 savePIPEB_DP_LINK_N;
528 u32 savePCH_DREF_CONTROL;
529 u32 saveDISP_ARB_CTL;
530 u32 savePIPEA_DATA_M1;
531 u32 savePIPEA_DATA_N1;
532 u32 savePIPEA_LINK_M1;
533 u32 savePIPEA_LINK_N1;
534 u32 savePIPEB_DATA_M1;
535 u32 savePIPEB_DATA_N1;
536 u32 savePIPEB_LINK_M1;
537 u32 savePIPEB_LINK_N1;
538 u32 saveMCHBAR_RENDER_STANDBY;
541 /** Bridge to intel-gtt-ko */
542 struct intel_gtt *gtt;
543 /** Memory allocator for GTT stolen memory */
545 /** Memory allocator for GTT */
546 struct drm_mm gtt_space;
547 /** End of mappable part of GTT */
548 unsigned long gtt_mappable_end;
550 struct io_mapping *gtt_mapping;
553 struct shrinker inactive_shrinker;
556 * List of objects currently involved in rendering.
558 * Includes buffers having the contents of their GPU caches
559 * flushed, not necessarily primitives. last_rendering_seqno
560 * represents when the rendering involved will be completed.
562 * A reference is held on the buffer while on this list.
564 struct list_head active_list;
567 * List of objects which are not in the ringbuffer but which
568 * still have a write_domain which needs to be flushed before
571 * last_rendering_seqno is 0 while an object is in this list.
573 * A reference is held on the buffer while on this list.
575 struct list_head flushing_list;
578 * LRU list of objects which are not in the ringbuffer and
579 * are ready to unbind, but are still in the GTT.
581 * last_rendering_seqno is 0 while an object is in this list.
583 * A reference is not held on the buffer while on this list,
584 * as merely being GTT-bound shouldn't prevent its being
585 * freed, and we'll pull it off the list in the free path.
587 struct list_head inactive_list;
590 * LRU list of objects which are not in the ringbuffer but
591 * are still pinned in the GTT.
593 struct list_head pinned_list;
595 /** LRU list of objects with fence regs on them. */
596 struct list_head fence_list;
599 * List of objects currently pending being freed.
601 * These objects are no longer in use, but due to a signal
602 * we were prevented from freeing them at the appointed time.
604 struct list_head deferred_free_list;
607 * We leave the user IRQ off as much as possible,
608 * but this means that requests will finish and never
609 * be retired once the system goes idle. Set a timer to
610 * fire periodically while the ring is running. When it
611 * fires, go retire requests.
613 struct delayed_work retire_work;
616 * Flag if the X Server, and thus DRM, is not currently in
617 * control of the device.
619 * This is set between LeaveVT and EnterVT. It needs to be
620 * replaced with a semaphore. It also needs to be
621 * transitioned away from for kernel modesetting.
626 * Flag if the hardware appears to be wedged.
628 * This is set when attempts to idle the device timeout.
629 * It prevents command submission from occuring and makes
630 * every pending request fail
634 /** Bit 6 swizzling required for X tiling */
635 uint32_t bit_6_swizzle_x;
636 /** Bit 6 swizzling required for Y tiling */
637 uint32_t bit_6_swizzle_y;
639 /* storage for physical objects */
640 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
642 /* accounting, useful for userland debugging */
643 size_t object_memory;
646 size_t gtt_mappable_memory;
647 size_t mappable_gtt_used;
648 size_t mappable_gtt_total;
652 u32 gtt_mappable_count;
655 struct sdvo_device_mapping sdvo_mappings[2];
656 /* indicate whether the LVDS_BORDER should be enabled or not */
657 unsigned int lvds_border_bits;
658 /* Panel fitter placement and size for Ironlake+ */
659 u32 pch_pf_pos, pch_pf_size;
661 struct drm_crtc *plane_to_crtc_mapping[2];
662 struct drm_crtc *pipe_to_crtc_mapping[2];
663 wait_queue_head_t pending_flip_queue;
664 bool flip_pending_is_done;
666 /* Reclocking support */
667 bool render_reclock_avail;
668 bool lvds_downclock_avail;
669 /* indicates the reduced downclock for LVDS*/
671 struct work_struct idle_work;
672 struct timer_list idle_timer;
676 struct child_device_config *child_dev;
677 struct drm_connector *int_lvds_connector;
679 bool mchbar_need_disable;
688 unsigned long last_time1;
690 struct timespec last_time2;
691 unsigned long gfx_power;
695 spinlock_t *mchdev_lock;
697 enum no_fbc_reason no_fbc_reason;
699 struct drm_mm_node *compressed_fb;
700 struct drm_mm_node *compressed_llb;
702 unsigned long last_gpu_reset;
704 /* list of fbdev register on this device */
705 struct intel_fbdev *fbdev;
706 } drm_i915_private_t;
708 /** driver private structure attached to each drm_gem_object */
709 struct drm_i915_gem_object {
710 struct drm_gem_object base;
712 /** Current space allocated to this object in the GTT, if any. */
713 struct drm_mm_node *gtt_space;
715 /** This object's place on the active/flushing/inactive lists */
716 struct list_head ring_list;
717 struct list_head mm_list;
718 /** This object's place on GPU write list */
719 struct list_head gpu_write_list;
720 /** This object's place on eviction list */
721 struct list_head evict_list;
724 * This is set if the object is on the active or flushing lists
725 * (has pending rendering), and is not set if it's on inactive (ready
728 unsigned int active : 1;
731 * This is set if the object has been written to since last bound
734 unsigned int dirty : 1;
737 * Fence register bits (if any) for this object. Will be set
738 * as needed when mapped into the GTT.
739 * Protected by dev->struct_mutex.
741 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
743 signed int fence_reg : 5;
746 * Used for checking the object doesn't appear more than once
747 * in an execbuffer object list.
749 unsigned int in_execbuffer : 1;
752 * Advice: are the backing pages purgeable?
754 unsigned int madv : 2;
755 unsigned int fenceable : 1;
756 unsigned int mappable : 1;
759 * Current tiling mode for the object.
761 unsigned int tiling_mode : 2;
763 /** How many users have pinned this object in GTT space. The following
764 * users can each hold at most one reference: pwrite/pread, pin_ioctl
765 * (via user_pin_count), execbuffer (objects are not allowed multiple
766 * times for the same batchbuffer), and the framebuffer code. When
767 * switching/pageflipping, the framebuffer code has at most two buffers
770 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
771 * bits with absolutely no headroom. So use 4 bits. */
772 unsigned int pin_count : 4;
773 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
776 * Whether the current gtt mapping needs to be mappable (and isn't just
777 * mappable by accident). Track pin and fault separate for a more
778 * accurate mappable working set.
780 unsigned int fault_mappable : 1;
781 unsigned int pin_mappable : 1;
783 /** AGP memory structure for our GTT binding. */
784 DRM_AGP_MEM *agp_mem;
789 * Current offset of the object in GTT space.
791 * This is the same as gtt_space->start
795 /* Which ring is refering to is this object */
796 struct intel_ring_buffer *ring;
798 /** Breadcrumb of last rendering to the buffer. */
799 uint32_t last_rendering_seqno;
801 /** Current tiling stride for the object, if it's tiled. */
804 /** Record of address bit 17 of each page at last unbind. */
805 unsigned long *bit_17;
807 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
811 * If present, while GEM_DOMAIN_CPU is in the read domain this array
812 * flags which individual pages are valid.
814 uint8_t *page_cpu_valid;
816 /** User space pin count and filp owning the pin */
817 uint32_t user_pin_count;
818 struct drm_file *pin_filp;
820 /** for phy allocated objects */
821 struct drm_i915_gem_phys_object *phys_obj;
824 * Number of crtcs where this object is currently the fb, but
825 * will be page flipped away on the next vblank. When it
826 * reaches 0, dev_priv->pending_flip_queue will be woken up.
828 atomic_t pending_flip;
831 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
834 * Request queue structure.
836 * The request queue allows us to note sequence numbers that have been emitted
837 * and may be associated with active buffers to be retired.
839 * By keeping this list, we can avoid having to do questionable
840 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
841 * an emission time with seqnos for tracking how far ahead of the GPU we are.
843 struct drm_i915_gem_request {
844 /** On Which ring this request was generated */
845 struct intel_ring_buffer *ring;
847 /** GEM sequence number associated with this request. */
850 /** Time at which this request was emitted, in jiffies. */
851 unsigned long emitted_jiffies;
853 /** global list entry for this request */
854 struct list_head list;
856 struct drm_i915_file_private *file_priv;
857 /** file_priv list entry for this request */
858 struct list_head client_list;
861 struct drm_i915_file_private {
863 struct spinlock lock;
864 struct list_head request_list;
868 enum intel_chip_family {
875 extern struct drm_ioctl_desc i915_ioctls[];
876 extern int i915_max_ioctl;
877 extern unsigned int i915_fbpercrtc;
878 extern unsigned int i915_powersave;
879 extern unsigned int i915_lvds_downclock;
881 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
882 extern int i915_resume(struct drm_device *dev);
883 extern void i915_save_display(struct drm_device *dev);
884 extern void i915_restore_display(struct drm_device *dev);
885 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
886 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
889 extern void i915_kernel_lost_context(struct drm_device * dev);
890 extern int i915_driver_load(struct drm_device *, unsigned long flags);
891 extern int i915_driver_unload(struct drm_device *);
892 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
893 extern void i915_driver_lastclose(struct drm_device * dev);
894 extern void i915_driver_preclose(struct drm_device *dev,
895 struct drm_file *file_priv);
896 extern void i915_driver_postclose(struct drm_device *dev,
897 struct drm_file *file_priv);
898 extern int i915_driver_device_is_agp(struct drm_device * dev);
899 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
901 extern int i915_emit_box(struct drm_device *dev,
902 struct drm_clip_rect *boxes,
903 int i, int DR1, int DR4);
904 extern int i915_reset(struct drm_device *dev, u8 flags);
905 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
906 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
907 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
908 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
912 void i915_hangcheck_elapsed(unsigned long data);
913 extern int i915_irq_emit(struct drm_device *dev, void *data,
914 struct drm_file *file_priv);
915 extern int i915_irq_wait(struct drm_device *dev, void *data,
916 struct drm_file *file_priv);
917 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
918 extern void i915_enable_interrupt (struct drm_device *dev);
920 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
921 extern void i915_driver_irq_preinstall(struct drm_device * dev);
922 extern int i915_driver_irq_postinstall(struct drm_device *dev);
923 extern void i915_driver_irq_uninstall(struct drm_device * dev);
924 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
925 struct drm_file *file_priv);
926 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
927 struct drm_file *file_priv);
928 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
929 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
930 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
931 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
932 extern int i915_vblank_swap(struct drm_device *dev, void *data,
933 struct drm_file *file_priv);
934 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
935 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
936 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
938 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
942 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
945 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
947 void intel_enable_asle (struct drm_device *dev);
949 #ifdef CONFIG_DEBUG_FS
950 extern void i915_destroy_error_state(struct drm_device *dev);
952 #define i915_destroy_error_state(x)
957 extern int i915_mem_alloc(struct drm_device *dev, void *data,
958 struct drm_file *file_priv);
959 extern int i915_mem_free(struct drm_device *dev, void *data,
960 struct drm_file *file_priv);
961 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
962 struct drm_file *file_priv);
963 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
964 struct drm_file *file_priv);
965 extern void i915_mem_takedown(struct mem_block **heap);
966 extern void i915_mem_release(struct drm_device * dev,
967 struct drm_file *file_priv, struct mem_block *heap);
969 int i915_gem_check_is_wedged(struct drm_device *dev);
970 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
971 struct drm_file *file_priv);
972 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
973 struct drm_file *file_priv);
974 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
975 struct drm_file *file_priv);
976 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv);
978 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv);
980 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv);
982 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
983 struct drm_file *file_priv);
984 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
985 struct drm_file *file_priv);
986 int i915_gem_execbuffer(struct drm_device *dev, void *data,
987 struct drm_file *file_priv);
988 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
989 struct drm_file *file_priv);
990 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
991 struct drm_file *file_priv);
992 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
993 struct drm_file *file_priv);
994 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
995 struct drm_file *file_priv);
996 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
997 struct drm_file *file_priv);
998 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
999 struct drm_file *file_priv);
1000 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1001 struct drm_file *file_priv);
1002 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1003 struct drm_file *file_priv);
1004 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1005 struct drm_file *file_priv);
1006 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv);
1008 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010 void i915_gem_load(struct drm_device *dev);
1011 int i915_gem_init_object(struct drm_gem_object *obj);
1012 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
1014 void i915_gem_free_object(struct drm_gem_object *obj);
1015 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
1016 bool mappable, bool need_fence);
1017 void i915_gem_object_unpin(struct drm_gem_object *obj);
1018 int i915_gem_object_unbind(struct drm_gem_object *obj);
1019 void i915_gem_release_mmap(struct drm_gem_object *obj);
1020 void i915_gem_lastclose(struct drm_device *dev);
1023 * Returns true if seq1 is later than seq2.
1026 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1028 return (int32_t)(seq1 - seq2) >= 0;
1031 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
1032 bool interruptible);
1033 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
1034 bool interruptible);
1035 void i915_gem_retire_requests(struct drm_device *dev);
1036 void i915_gem_reset(struct drm_device *dev);
1037 void i915_gem_clflush_object(struct drm_gem_object *obj);
1038 int i915_gem_object_set_domain(struct drm_gem_object *obj,
1039 uint32_t read_domains,
1040 uint32_t write_domain);
1041 int i915_gem_init_ringbuffer(struct drm_device *dev);
1042 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1043 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1044 unsigned long mappable_end, unsigned long end);
1045 int i915_gpu_idle(struct drm_device *dev);
1046 int i915_gem_idle(struct drm_device *dev);
1047 int i915_add_request(struct drm_device *dev,
1048 struct drm_file *file_priv,
1049 struct drm_i915_gem_request *request,
1050 struct intel_ring_buffer *ring);
1051 int i915_do_wait_request(struct drm_device *dev,
1054 struct intel_ring_buffer *ring);
1055 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1056 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
1058 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
1060 int i915_gem_attach_phys_object(struct drm_device *dev,
1061 struct drm_gem_object *obj,
1064 void i915_gem_detach_phys_object(struct drm_device *dev,
1065 struct drm_gem_object *obj);
1066 void i915_gem_free_all_phys_object(struct drm_device *dev);
1067 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
1069 /* i915_gem_evict.c */
1070 int i915_gem_evict_something(struct drm_device *dev, int min_size,
1071 unsigned alignment, bool mappable);
1072 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1073 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only);
1075 /* i915_gem_tiling.c */
1076 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1077 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
1078 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
1080 /* i915_gem_debug.c */
1081 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1082 const char *where, uint32_t mark);
1084 int i915_verify_lists(struct drm_device *dev);
1086 #define i915_verify_lists(dev) 0
1088 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1089 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1090 const char *where, uint32_t mark);
1092 /* i915_debugfs.c */
1093 int i915_debugfs_init(struct drm_minor *minor);
1094 void i915_debugfs_cleanup(struct drm_minor *minor);
1096 /* i915_suspend.c */
1097 extern int i915_save_state(struct drm_device *dev);
1098 extern int i915_restore_state(struct drm_device *dev);
1100 /* i915_suspend.c */
1101 extern int i915_save_state(struct drm_device *dev);
1102 extern int i915_restore_state(struct drm_device *dev);
1105 extern int intel_setup_gmbus(struct drm_device *dev);
1106 extern void intel_teardown_gmbus(struct drm_device *dev);
1107 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1108 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1109 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1111 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1113 extern void intel_i2c_reset(struct drm_device *dev);
1115 /* intel_opregion.c */
1116 extern int intel_opregion_setup(struct drm_device *dev);
1118 extern void intel_opregion_init(struct drm_device *dev);
1119 extern void intel_opregion_fini(struct drm_device *dev);
1120 extern void intel_opregion_asle_intr(struct drm_device *dev);
1121 extern void intel_opregion_gse_intr(struct drm_device *dev);
1122 extern void intel_opregion_enable_asle(struct drm_device *dev);
1124 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1125 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1126 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1127 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1128 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1133 extern void intel_register_dsm_handler(void);
1134 extern void intel_unregister_dsm_handler(void);
1136 static inline void intel_register_dsm_handler(void) { return; }
1137 static inline void intel_unregister_dsm_handler(void) { return; }
1138 #endif /* CONFIG_ACPI */
1141 extern void intel_modeset_init(struct drm_device *dev);
1142 extern void intel_modeset_cleanup(struct drm_device *dev);
1143 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1144 extern void i8xx_disable_fbc(struct drm_device *dev);
1145 extern void g4x_disable_fbc(struct drm_device *dev);
1146 extern void ironlake_disable_fbc(struct drm_device *dev);
1147 extern void intel_disable_fbc(struct drm_device *dev);
1148 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1149 extern bool intel_fbc_enabled(struct drm_device *dev);
1150 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1151 extern void intel_detect_pch (struct drm_device *dev);
1152 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1155 #ifdef CONFIG_DEBUG_FS
1156 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1157 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1161 * Lock test for when it's just for synchronization of ring access.
1163 * In that case, we don't need to do it when GEM is initialized as nobody else
1164 * has access to the ring.
1166 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1167 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1169 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1172 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1173 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1174 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1175 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1176 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1177 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1178 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1179 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1180 #define POSTING_READ(reg) (void)I915_READ(reg)
1181 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1183 #define BEGIN_LP_RING(n) \
1184 intel_ring_begin(&dev_priv->render_ring, (n))
1186 #define OUT_RING(x) \
1187 intel_ring_emit(&dev_priv->render_ring, x)
1189 #define ADVANCE_LP_RING() \
1190 intel_ring_advance(&dev_priv->render_ring)
1193 * Reads a dword out of the status page, which is written to from the command
1194 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1195 * MI_STORE_DATA_IMM.
1197 * The following dwords have a reserved meaning:
1198 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1199 * 0x04: ring 0 head pointer
1200 * 0x05: ring 1 head pointer (915-class)
1201 * 0x06: ring 2 head pointer (915-class)
1202 * 0x10-0x1b: Context status DWords (GM45)
1203 * 0x1f: Last written status offset. (GM45)
1205 * The area from dword 0x20 to 0x3ff is available for driver usage.
1207 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1208 (dev_priv->render_ring.status_page.page_addr))[reg])
1209 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1210 #define I915_GEM_HWS_INDEX 0x20
1211 #define I915_BREADCRUMB_INDEX 0x21
1213 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1215 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1216 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1217 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1218 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1219 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1220 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1221 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1222 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1223 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1224 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1225 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1226 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1227 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1228 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1229 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1230 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1231 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1232 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1233 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1235 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1236 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1237 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1238 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1239 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1241 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1242 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1243 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1245 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1246 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1248 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1249 * rows, which changed the alignment requirements and fence programming.
1251 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1253 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1254 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1255 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1256 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1257 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1258 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1259 /* dsparb controlled by hw only */
1260 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1262 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1263 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1264 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1265 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1267 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1268 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1270 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1271 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1273 #define PRIMARY_RINGBUFFER_SIZE (128*1024)