1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "i915_gem_gtt.h"
39 #include <linux/io-mapping.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <drm/intel-gtt.h>
43 #include <linux/backlight.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/kref.h>
46 #include <linux/pm_qos.h>
48 /* General customization:
51 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
53 #define DRIVER_NAME "i915"
54 #define DRIVER_DESC "Intel Graphics"
55 #define DRIVER_DATE "20080730"
63 I915_MAX_PIPES = _PIPE_EDP
65 #define pipe_name(p) ((p) + 'A')
74 #define transcoder_name(t) ((t) + 'A')
81 #define plane_name(p) ((p) + 'A')
83 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
93 #define port_name(p) ((p) + 'A')
95 #define I915_NUM_PHYS_VLV 1
107 enum intel_display_power_domain {
111 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
114 POWER_DOMAIN_TRANSCODER_A,
115 POWER_DOMAIN_TRANSCODER_B,
116 POWER_DOMAIN_TRANSCODER_C,
117 POWER_DOMAIN_TRANSCODER_EDP,
118 POWER_DOMAIN_PORT_DDI_A_2_LANES,
119 POWER_DOMAIN_PORT_DDI_A_4_LANES,
120 POWER_DOMAIN_PORT_DDI_B_2_LANES,
121 POWER_DOMAIN_PORT_DDI_B_4_LANES,
122 POWER_DOMAIN_PORT_DDI_C_2_LANES,
123 POWER_DOMAIN_PORT_DDI_C_4_LANES,
124 POWER_DOMAIN_PORT_DDI_D_2_LANES,
125 POWER_DOMAIN_PORT_DDI_D_4_LANES,
126 POWER_DOMAIN_PORT_DSI,
127 POWER_DOMAIN_PORT_CRT,
128 POWER_DOMAIN_PORT_OTHER,
136 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
137 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
138 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
139 #define POWER_DOMAIN_TRANSCODER(tran) \
140 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
141 (tran) + POWER_DOMAIN_TRANSCODER_A)
145 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
146 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
156 #define I915_GEM_GPU_DOMAINS \
157 (I915_GEM_DOMAIN_RENDER | \
158 I915_GEM_DOMAIN_SAMPLER | \
159 I915_GEM_DOMAIN_COMMAND | \
160 I915_GEM_DOMAIN_INSTRUCTION | \
161 I915_GEM_DOMAIN_VERTEX)
163 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
164 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
166 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
167 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
168 if ((intel_encoder)->base.crtc == (__crtc))
170 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
171 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
172 if ((intel_connector)->base.encoder == (__encoder))
174 struct drm_i915_private;
177 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
178 /* real shared dpll ids must be >= 0 */
182 #define I915_NUM_PLLS 2
184 struct intel_dpll_hw_state {
191 struct intel_shared_dpll {
192 int refcount; /* count of number of CRTCs sharing this PLL */
193 int active; /* count of number of active CRTCs (i.e. DPMS on) */
194 bool on; /* is the PLL actually active? Disabled during modeset */
196 /* should match the index in the dev_priv->shared_dplls array */
197 enum intel_dpll_id id;
198 struct intel_dpll_hw_state hw_state;
199 void (*mode_set)(struct drm_i915_private *dev_priv,
200 struct intel_shared_dpll *pll);
201 void (*enable)(struct drm_i915_private *dev_priv,
202 struct intel_shared_dpll *pll);
203 void (*disable)(struct drm_i915_private *dev_priv,
204 struct intel_shared_dpll *pll);
205 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
206 struct intel_shared_dpll *pll,
207 struct intel_dpll_hw_state *hw_state);
210 /* Used by dp and fdi links */
211 struct intel_link_m_n {
219 void intel_link_compute_m_n(int bpp, int nlanes,
220 int pixel_clock, int link_clock,
221 struct intel_link_m_n *m_n);
223 struct intel_ddi_plls {
229 /* Interface history:
232 * 1.2: Add Power Management
233 * 1.3: Add vblank support
234 * 1.4: Fix cmdbuffer path, add heap destroy
235 * 1.5: Add vblank pipe configuration
236 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
237 * - Support vertical blank on secondary display pipe
239 #define DRIVER_MAJOR 1
240 #define DRIVER_MINOR 6
241 #define DRIVER_PATCHLEVEL 0
243 #define WATCH_LISTS 0
246 #define I915_GEM_PHYS_CURSOR_0 1
247 #define I915_GEM_PHYS_CURSOR_1 2
248 #define I915_GEM_PHYS_OVERLAY_REGS 3
249 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
251 struct drm_i915_gem_phys_object {
253 struct page **page_list;
254 drm_dma_handle_t *handle;
255 struct drm_i915_gem_object *cur_obj;
258 struct opregion_header;
259 struct opregion_acpi;
260 struct opregion_swsci;
261 struct opregion_asle;
263 struct intel_opregion {
264 struct opregion_header __iomem *header;
265 struct opregion_acpi __iomem *acpi;
266 struct opregion_swsci __iomem *swsci;
267 u32 swsci_gbda_sub_functions;
268 u32 swsci_sbcb_sub_functions;
269 struct opregion_asle __iomem *asle;
271 u32 __iomem *lid_state;
272 struct work_struct asle_work;
274 #define OPREGION_SIZE (8*1024)
276 struct intel_overlay;
277 struct intel_overlay_error_state;
279 struct drm_i915_master_private {
280 drm_local_map_t *sarea;
281 struct _drm_i915_sarea *sarea_priv;
283 #define I915_FENCE_REG_NONE -1
284 #define I915_MAX_NUM_FENCES 32
285 /* 32 fences + sign bit for FENCE_REG_NONE */
286 #define I915_MAX_NUM_FENCE_BITS 6
288 struct drm_i915_fence_reg {
289 struct list_head lru_list;
290 struct drm_i915_gem_object *obj;
294 struct sdvo_device_mapping {
303 struct intel_display_error_state;
305 struct drm_i915_error_state {
313 /* Generic register state */
320 u32 error; /* gen6+ */
321 u32 err_int; /* gen7 */
327 u32 extra_instdone[I915_NUM_INSTDONE_REG];
328 u32 pipestat[I915_MAX_PIPES];
329 u64 fence[I915_MAX_NUM_FENCES];
330 struct intel_overlay_error_state *overlay;
331 struct intel_display_error_state *display;
333 struct drm_i915_error_ring {
335 /* Software tracked state */
338 enum intel_ring_hangcheck_action hangcheck_action;
341 /* our own tracking of ring head and tail */
345 u32 semaphore_seqno[I915_NUM_RINGS - 1];
363 u32 rc_psmi; /* sleep state */
364 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
366 struct drm_i915_error_object {
370 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
372 struct drm_i915_error_request {
387 char comm[TASK_COMM_LEN];
388 } ring[I915_NUM_RINGS];
389 struct drm_i915_error_buffer {
396 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
403 } **active_bo, **pinned_bo;
405 u32 *active_bo_count, *pinned_bo_count;
408 struct intel_connector;
409 struct intel_crtc_config;
410 struct intel_plane_config;
415 struct drm_i915_display_funcs {
416 bool (*fbc_enabled)(struct drm_device *dev);
417 void (*enable_fbc)(struct drm_crtc *crtc);
418 void (*disable_fbc)(struct drm_device *dev);
419 int (*get_display_clock_speed)(struct drm_device *dev);
420 int (*get_fifo_size)(struct drm_device *dev, int plane);
422 * find_dpll() - Find the best values for the PLL
423 * @limit: limits for the PLL
424 * @crtc: current CRTC
425 * @target: target frequency in kHz
426 * @refclk: reference clock frequency in kHz
427 * @match_clock: if provided, @best_clock P divider must
428 * match the P divider from @match_clock
429 * used for LVDS downclocking
430 * @best_clock: best PLL values found
432 * Returns true on success, false on failure.
434 bool (*find_dpll)(const struct intel_limit *limit,
435 struct drm_crtc *crtc,
436 int target, int refclk,
437 struct dpll *match_clock,
438 struct dpll *best_clock);
439 void (*update_wm)(struct drm_crtc *crtc);
440 void (*update_sprite_wm)(struct drm_plane *plane,
441 struct drm_crtc *crtc,
442 uint32_t sprite_width, int pixel_size,
443 bool enable, bool scaled);
444 void (*modeset_global_resources)(struct drm_device *dev);
445 /* Returns the active state of the crtc, and if the crtc is active,
446 * fills out the pipe-config with the hw state. */
447 bool (*get_pipe_config)(struct intel_crtc *,
448 struct intel_crtc_config *);
449 void (*get_plane_config)(struct intel_crtc *,
450 struct intel_plane_config *);
451 int (*crtc_mode_set)(struct drm_crtc *crtc,
453 struct drm_framebuffer *old_fb);
454 void (*crtc_enable)(struct drm_crtc *crtc);
455 void (*crtc_disable)(struct drm_crtc *crtc);
456 void (*off)(struct drm_crtc *crtc);
457 void (*write_eld)(struct drm_connector *connector,
458 struct drm_crtc *crtc,
459 struct drm_display_mode *mode);
460 void (*fdi_link_train)(struct drm_crtc *crtc);
461 void (*init_clock_gating)(struct drm_device *dev);
462 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
463 struct drm_framebuffer *fb,
464 struct drm_i915_gem_object *obj,
466 int (*update_primary_plane)(struct drm_crtc *crtc,
467 struct drm_framebuffer *fb,
469 void (*hpd_irq_setup)(struct drm_device *dev);
470 /* clock updates for mode set */
472 /* render clock increase/decrease */
473 /* display clock increase/decrease */
474 /* pll clock increase/decrease */
476 int (*setup_backlight)(struct intel_connector *connector);
477 uint32_t (*get_backlight)(struct intel_connector *connector);
478 void (*set_backlight)(struct intel_connector *connector,
480 void (*disable_backlight)(struct intel_connector *connector);
481 void (*enable_backlight)(struct intel_connector *connector);
484 struct intel_uncore_funcs {
485 void (*force_wake_get)(struct drm_i915_private *dev_priv,
487 void (*force_wake_put)(struct drm_i915_private *dev_priv,
490 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
491 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
492 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
493 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
495 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
496 uint8_t val, bool trace);
497 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
498 uint16_t val, bool trace);
499 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
500 uint32_t val, bool trace);
501 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
502 uint64_t val, bool trace);
505 struct intel_uncore {
506 spinlock_t lock; /** lock is also taken in irq contexts. */
508 struct intel_uncore_funcs funcs;
511 unsigned forcewake_count;
513 unsigned fw_rendercount;
514 unsigned fw_mediacount;
516 struct timer_list force_wake_timer;
519 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
520 func(is_mobile) sep \
523 func(is_i945gm) sep \
525 func(need_gfx_hws) sep \
527 func(is_pineview) sep \
528 func(is_broadwater) sep \
529 func(is_crestline) sep \
530 func(is_ivybridge) sep \
531 func(is_valleyview) sep \
532 func(is_haswell) sep \
533 func(is_preliminary) sep \
535 func(has_pipe_cxsr) sep \
536 func(has_hotplug) sep \
537 func(cursor_needs_physical) sep \
538 func(has_overlay) sep \
539 func(overlay_needs_physical) sep \
540 func(supports_tv) sep \
545 #define DEFINE_FLAG(name) u8 name:1
546 #define SEP_SEMICOLON ;
548 struct intel_device_info {
549 u32 display_mmio_offset;
551 u8 num_sprites[I915_MAX_PIPES];
553 u8 ring_mask; /* Rings supported by the HW */
554 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
555 /* Register offsets for the various display pipes and transcoders */
556 int pipe_offsets[I915_MAX_TRANSCODERS];
557 int trans_offsets[I915_MAX_TRANSCODERS];
558 int dpll_offsets[I915_MAX_PIPES];
559 int dpll_md_offsets[I915_MAX_PIPES];
560 int palette_offsets[I915_MAX_PIPES];
566 enum i915_cache_level {
568 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
569 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
570 caches, eg sampler/render caches, and the
571 large Last-Level-Cache. LLC is coherent with
572 the CPU, but L3 is only visible to the GPU. */
573 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
576 struct i915_ctx_hang_stats {
577 /* This context had batch pending when hang was declared */
578 unsigned batch_pending;
580 /* This context had batch active when hang was declared */
581 unsigned batch_active;
583 /* Time when this context was last blamed for a GPU reset */
584 unsigned long guilty_ts;
586 /* This context is banned to submit more work */
590 /* This must match up with the value previously used for execbuf2.rsvd1. */
591 #define DEFAULT_CONTEXT_ID 0
592 struct i915_hw_context {
597 struct drm_i915_file_private *file_priv;
598 struct intel_ring_buffer *last_ring;
599 struct drm_i915_gem_object *obj;
600 struct i915_ctx_hang_stats hang_stats;
601 struct i915_address_space *vm;
603 struct list_head link;
612 struct drm_mm_node *compressed_fb;
613 struct drm_mm_node *compressed_llb;
615 struct intel_fbc_work {
616 struct delayed_work work;
617 struct drm_crtc *crtc;
618 struct drm_framebuffer *fb;
622 FBC_OK, /* FBC is enabled */
623 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
624 FBC_NO_OUTPUT, /* no outputs enabled to compress */
625 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
626 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
627 FBC_MODE_TOO_LARGE, /* mode too large for compression */
628 FBC_BAD_PLANE, /* fbc not supported on plane */
629 FBC_NOT_TILED, /* buffer not tiled */
630 FBC_MULTIPLE_PIPES, /* more than one pipe active */
632 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
642 PCH_NONE = 0, /* No PCH present */
643 PCH_IBX, /* Ibexpeak PCH */
644 PCH_CPT, /* Cougarpoint PCH */
645 PCH_LPT, /* Lynxpoint PCH */
649 enum intel_sbi_destination {
654 #define QUIRK_PIPEA_FORCE (1<<0)
655 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
656 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
659 struct intel_fbc_work;
662 struct i2c_adapter adapter;
666 struct i2c_algo_bit_data bit_algo;
667 struct drm_i915_private *dev_priv;
670 struct i915_suspend_saved_registers {
691 u32 saveTRANS_HTOTAL_A;
692 u32 saveTRANS_HBLANK_A;
693 u32 saveTRANS_HSYNC_A;
694 u32 saveTRANS_VTOTAL_A;
695 u32 saveTRANS_VBLANK_A;
696 u32 saveTRANS_VSYNC_A;
704 u32 savePFIT_PGM_RATIOS;
705 u32 saveBLC_HIST_CTL;
707 u32 saveBLC_PWM_CTL2;
708 u32 saveBLC_HIST_CTL_B;
709 u32 saveBLC_CPU_PWM_CTL;
710 u32 saveBLC_CPU_PWM_CTL2;
723 u32 saveTRANS_HTOTAL_B;
724 u32 saveTRANS_HBLANK_B;
725 u32 saveTRANS_HSYNC_B;
726 u32 saveTRANS_VTOTAL_B;
727 u32 saveTRANS_VBLANK_B;
728 u32 saveTRANS_VSYNC_B;
742 u32 savePP_ON_DELAYS;
743 u32 savePP_OFF_DELAYS;
751 u32 savePFIT_CONTROL;
752 u32 save_palette_a[256];
753 u32 save_palette_b[256];
764 u32 saveCACHE_MODE_0;
765 u32 saveMI_ARB_STATE;
776 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
787 u32 savePIPEA_GMCH_DATA_M;
788 u32 savePIPEB_GMCH_DATA_M;
789 u32 savePIPEA_GMCH_DATA_N;
790 u32 savePIPEB_GMCH_DATA_N;
791 u32 savePIPEA_DP_LINK_M;
792 u32 savePIPEB_DP_LINK_M;
793 u32 savePIPEA_DP_LINK_N;
794 u32 savePIPEB_DP_LINK_N;
805 u32 savePCH_DREF_CONTROL;
806 u32 saveDISP_ARB_CTL;
807 u32 savePIPEA_DATA_M1;
808 u32 savePIPEA_DATA_N1;
809 u32 savePIPEA_LINK_M1;
810 u32 savePIPEA_LINK_N1;
811 u32 savePIPEB_DATA_M1;
812 u32 savePIPEB_DATA_N1;
813 u32 savePIPEB_LINK_M1;
814 u32 savePIPEB_LINK_N1;
815 u32 saveMCHBAR_RENDER_STANDBY;
816 u32 savePCH_PORT_HOTPLUG;
819 struct intel_gen6_power_mgmt {
820 /* work and pm_iir are protected by dev_priv->irq_lock */
821 struct work_struct work;
824 /* Frequencies are stored in potentially platform dependent multiples.
825 * In other words, *_freq needs to be multiplied by X to be interesting.
826 * Soft limits are those which are used for the dynamic reclocking done
827 * by the driver (raise frequencies under heavy loads, and lower for
828 * lighter loads). Hard limits are those imposed by the hardware.
830 * A distinction is made for overclocking, which is never enabled by
831 * default, and is considered to be above the hard limit if it's
834 u8 cur_freq; /* Current frequency (cached, may not == HW) */
835 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
836 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
837 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
838 u8 min_freq; /* AKA RPn. Minimum frequency */
839 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
840 u8 rp1_freq; /* "less than" RP0 power/freqency */
841 u8 rp0_freq; /* Non-overclocked max frequency. */
844 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
847 struct delayed_work delayed_resume_work;
850 * Protects RPS/RC6 register access and PCU communication.
851 * Must be taken after struct_mutex if nested.
853 struct mutex hw_lock;
856 /* defined intel_pm.c */
857 extern spinlock_t mchdev_lock;
859 struct intel_ilk_power_mgmt {
867 unsigned long last_time1;
868 unsigned long chipset_power;
870 struct timespec last_time2;
871 unsigned long gfx_power;
877 struct drm_i915_gem_object *pwrctx;
878 struct drm_i915_gem_object *renderctx;
881 struct drm_i915_private;
882 struct i915_power_well;
884 struct i915_power_well_ops {
886 * Synchronize the well's hw state to match the current sw state, for
887 * example enable/disable it based on the current refcount. Called
888 * during driver init and resume time, possibly after first calling
889 * the enable/disable handlers.
891 void (*sync_hw)(struct drm_i915_private *dev_priv,
892 struct i915_power_well *power_well);
894 * Enable the well and resources that depend on it (for example
895 * interrupts located on the well). Called after the 0->1 refcount
898 void (*enable)(struct drm_i915_private *dev_priv,
899 struct i915_power_well *power_well);
901 * Disable the well and resources that depend on it. Called after
902 * the 1->0 refcount transition.
904 void (*disable)(struct drm_i915_private *dev_priv,
905 struct i915_power_well *power_well);
906 /* Returns the hw enabled state. */
907 bool (*is_enabled)(struct drm_i915_private *dev_priv,
908 struct i915_power_well *power_well);
911 /* Power well structure for haswell */
912 struct i915_power_well {
915 /* power well enable/disable usage count */
917 unsigned long domains;
919 const struct i915_power_well_ops *ops;
922 struct i915_power_domains {
924 * Power wells needed for initialization at driver init and suspend
925 * time are on. They are kept on until after the first modeset.
928 int power_well_count;
931 int domain_use_count[POWER_DOMAIN_NUM];
932 struct i915_power_well *power_wells;
935 struct i915_dri1_state {
936 unsigned allow_batchbuffer : 1;
937 u32 __iomem *gfx_hws_cpu_addr;
948 struct i915_ums_state {
950 * Flag if the X Server, and thus DRM, is not currently in
951 * control of the device.
953 * This is set between LeaveVT and EnterVT. It needs to be
954 * replaced with a semaphore. It also needs to be
955 * transitioned away from for kernel modesetting.
960 #define MAX_L3_SLICES 2
961 struct intel_l3_parity {
962 u32 *remap_info[MAX_L3_SLICES];
963 struct work_struct error_work;
968 /** Memory allocator for GTT stolen memory */
969 struct drm_mm stolen;
970 /** List of all objects in gtt_space. Used to restore gtt
971 * mappings on resume */
972 struct list_head bound_list;
974 * List of objects which are not bound to the GTT (thus
975 * are idle and not used by the GPU) but still have
976 * (presumably uncached) pages still attached.
978 struct list_head unbound_list;
980 /** Usable portion of the GTT for GEM */
981 unsigned long stolen_base; /* limited to low memory (32-bit) */
983 /** PPGTT used for aliasing the PPGTT with the GTT */
984 struct i915_hw_ppgtt *aliasing_ppgtt;
986 struct shrinker inactive_shrinker;
987 bool shrinker_no_lock_stealing;
989 /** LRU list of objects with fence regs on them. */
990 struct list_head fence_list;
993 * We leave the user IRQ off as much as possible,
994 * but this means that requests will finish and never
995 * be retired once the system goes idle. Set a timer to
996 * fire periodically while the ring is running. When it
997 * fires, go retire requests.
999 struct delayed_work retire_work;
1002 * When we detect an idle GPU, we want to turn on
1003 * powersaving features. So once we see that there
1004 * are no more requests outstanding and no more
1005 * arrive within a small period of time, we fire
1006 * off the idle_work.
1008 struct delayed_work idle_work;
1011 * Are we in a non-interruptible section of code like
1017 * Is the GPU currently considered idle, or busy executing userspace
1018 * requests? Whilst idle, we attempt to power down the hardware and
1019 * display clocks. In order to reduce the effect on performance, there
1020 * is a slight delay before we do so.
1024 /** Bit 6 swizzling required for X tiling */
1025 uint32_t bit_6_swizzle_x;
1026 /** Bit 6 swizzling required for Y tiling */
1027 uint32_t bit_6_swizzle_y;
1029 /* storage for physical objects */
1030 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1032 /* accounting, useful for userland debugging */
1033 spinlock_t object_stat_lock;
1034 size_t object_memory;
1038 struct drm_i915_error_state_buf {
1047 struct i915_error_state_file_priv {
1048 struct drm_device *dev;
1049 struct drm_i915_error_state *error;
1052 struct i915_gpu_error {
1053 /* For hangcheck timer */
1054 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1055 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1056 /* Hang gpu twice in this window and your context gets banned */
1057 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1059 struct timer_list hangcheck_timer;
1061 /* For reset and error_state handling. */
1063 /* Protected by the above dev->gpu_error.lock. */
1064 struct drm_i915_error_state *first_error;
1065 struct work_struct work;
1068 unsigned long missed_irq_rings;
1071 * State variable controlling the reset flow and count
1073 * This is a counter which gets incremented when reset is triggered,
1074 * and again when reset has been handled. So odd values (lowest bit set)
1075 * means that reset is in progress and even values that
1076 * (reset_counter >> 1):th reset was successfully completed.
1078 * If reset is not completed succesfully, the I915_WEDGE bit is
1079 * set meaning that hardware is terminally sour and there is no
1080 * recovery. All waiters on the reset_queue will be woken when
1083 * This counter is used by the wait_seqno code to notice that reset
1084 * event happened and it needs to restart the entire ioctl (since most
1085 * likely the seqno it waited for won't ever signal anytime soon).
1087 * This is important for lock-free wait paths, where no contended lock
1088 * naturally enforces the correct ordering between the bail-out of the
1089 * waiter and the gpu reset work code.
1091 atomic_t reset_counter;
1093 #define I915_RESET_IN_PROGRESS_FLAG 1
1094 #define I915_WEDGED (1 << 31)
1097 * Waitqueue to signal when the reset has completed. Used by clients
1098 * that wait for dev_priv->mm.wedged to settle.
1100 wait_queue_head_t reset_queue;
1102 /* For gpu hang simulation. */
1103 unsigned int stop_rings;
1105 /* For missed irq/seqno simulation. */
1106 unsigned int test_irq_rings;
1109 enum modeset_restore {
1110 MODESET_ON_LID_OPEN,
1115 struct ddi_vbt_port_info {
1116 uint8_t hdmi_level_shift;
1118 uint8_t supports_dvi:1;
1119 uint8_t supports_hdmi:1;
1120 uint8_t supports_dp:1;
1123 struct intel_vbt_data {
1124 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1125 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1128 unsigned int int_tv_support:1;
1129 unsigned int lvds_dither:1;
1130 unsigned int lvds_vbt:1;
1131 unsigned int int_crt_support:1;
1132 unsigned int lvds_use_ssc:1;
1133 unsigned int display_clock_mode:1;
1134 unsigned int fdi_rx_polarity_inverted:1;
1136 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1141 int edp_preemphasis;
1143 bool edp_initialized;
1146 struct edp_power_seq edp_pps;
1150 bool active_low_pwm;
1161 union child_device_config *child_dev;
1163 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1166 enum intel_ddb_partitioning {
1168 INTEL_DDB_PART_5_6, /* IVB+ */
1171 struct intel_wm_level {
1179 struct ilk_wm_values {
1180 uint32_t wm_pipe[3];
1182 uint32_t wm_lp_spr[3];
1183 uint32_t wm_linetime[3];
1185 enum intel_ddb_partitioning partitioning;
1189 * This struct helps tracking the state needed for runtime PM, which puts the
1190 * device in PCI D3 state. Notice that when this happens, nothing on the
1191 * graphics device works, even register access, so we don't get interrupts nor
1194 * Every piece of our code that needs to actually touch the hardware needs to
1195 * either call intel_runtime_pm_get or call intel_display_power_get with the
1196 * appropriate power domain.
1198 * Our driver uses the autosuspend delay feature, which means we'll only really
1199 * suspend if we stay with zero refcount for a certain amount of time. The
1200 * default value is currently very conservative (see intel_init_runtime_pm), but
1201 * it can be changed with the standard runtime PM files from sysfs.
1203 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1204 * goes back to false exactly before we reenable the IRQs. We use this variable
1205 * to check if someone is trying to enable/disable IRQs while they're supposed
1206 * to be disabled. This shouldn't happen and we'll print some error messages in
1207 * case it happens, but if it actually happens we'll also update the variables
1208 * inside struct regsave so when we restore the IRQs they will contain the
1209 * latest expected values.
1211 * For more, read the Documentation/power/runtime_pm.txt.
1213 struct i915_runtime_pm {
1222 uint32_t gen6_pmimr;
1226 enum intel_pipe_crc_source {
1227 INTEL_PIPE_CRC_SOURCE_NONE,
1228 INTEL_PIPE_CRC_SOURCE_PLANE1,
1229 INTEL_PIPE_CRC_SOURCE_PLANE2,
1230 INTEL_PIPE_CRC_SOURCE_PF,
1231 INTEL_PIPE_CRC_SOURCE_PIPE,
1232 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1233 INTEL_PIPE_CRC_SOURCE_TV,
1234 INTEL_PIPE_CRC_SOURCE_DP_B,
1235 INTEL_PIPE_CRC_SOURCE_DP_C,
1236 INTEL_PIPE_CRC_SOURCE_DP_D,
1237 INTEL_PIPE_CRC_SOURCE_AUTO,
1238 INTEL_PIPE_CRC_SOURCE_MAX,
1241 struct intel_pipe_crc_entry {
1246 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1247 struct intel_pipe_crc {
1249 bool opened; /* exclusive access to the result file */
1250 struct intel_pipe_crc_entry *entries;
1251 enum intel_pipe_crc_source source;
1253 wait_queue_head_t wq;
1256 struct drm_i915_private {
1257 struct drm_device *dev;
1258 struct kmem_cache *slab;
1260 const struct intel_device_info info;
1262 int relative_constants_mode;
1266 struct intel_uncore uncore;
1268 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1271 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1272 * controller on different i2c buses. */
1273 struct mutex gmbus_mutex;
1276 * Base address of the gmbus and gpio block.
1278 uint32_t gpio_mmio_base;
1280 wait_queue_head_t gmbus_wait_queue;
1282 struct pci_dev *bridge_dev;
1283 struct intel_ring_buffer ring[I915_NUM_RINGS];
1284 uint32_t last_seqno, next_seqno;
1286 drm_dma_handle_t *status_page_dmah;
1287 struct resource mch_res;
1289 /* protects the irq masks */
1290 spinlock_t irq_lock;
1292 bool display_irqs_enabled;
1294 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1295 struct pm_qos_request pm_qos;
1297 /* DPIO indirect register protection */
1298 struct mutex dpio_lock;
1300 /** Cached value of IMR to avoid reads in updating the bitfield */
1303 u32 de_irq_mask[I915_MAX_PIPES];
1308 u32 pipestat_irq_mask[I915_MAX_PIPES];
1310 struct work_struct hotplug_work;
1311 bool enable_hotplug_processing;
1313 unsigned long hpd_last_jiffies;
1318 HPD_MARK_DISABLED = 2
1320 } hpd_stats[HPD_NUM_PINS];
1322 struct timer_list hotplug_reenable_timer;
1324 struct i915_fbc fbc;
1325 struct intel_opregion opregion;
1326 struct intel_vbt_data vbt;
1329 struct intel_overlay *overlay;
1331 /* backlight registers and fields in struct intel_panel */
1332 spinlock_t backlight_lock;
1335 bool no_aux_handshake;
1337 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1338 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1339 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1341 unsigned int fsb_freq, mem_freq, is_ddr3;
1342 unsigned int vlv_cdclk_freq;
1345 * wq - Driver workqueue for GEM.
1347 * NOTE: Work items scheduled here are not allowed to grab any modeset
1348 * locks, for otherwise the flushing done in the pageflip code will
1349 * result in deadlocks.
1351 struct workqueue_struct *wq;
1353 /* Display functions */
1354 struct drm_i915_display_funcs display;
1356 /* PCH chipset type */
1357 enum intel_pch pch_type;
1358 unsigned short pch_id;
1360 unsigned long quirks;
1362 enum modeset_restore modeset_restore;
1363 struct mutex modeset_restore_lock;
1365 struct list_head vm_list; /* Global list of all address spaces */
1366 struct i915_gtt gtt; /* VM representing the global address space */
1368 struct i915_gem_mm mm;
1370 /* Kernel Modesetting */
1372 struct sdvo_device_mapping sdvo_mappings[2];
1374 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1375 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1376 wait_queue_head_t pending_flip_queue;
1378 #ifdef CONFIG_DEBUG_FS
1379 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1382 int num_shared_dpll;
1383 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1384 struct intel_ddi_plls ddi_plls;
1385 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1387 /* Reclocking support */
1388 bool render_reclock_avail;
1389 bool lvds_downclock_avail;
1390 /* indicates the reduced downclock for LVDS*/
1394 bool mchbar_need_disable;
1396 struct intel_l3_parity l3_parity;
1398 /* Cannot be determined by PCIID. You must always read a register. */
1401 /* gen6+ rps state */
1402 struct intel_gen6_power_mgmt rps;
1404 /* ilk-only ips/rps state. Everything in here is protected by the global
1405 * mchdev_lock in intel_pm.c */
1406 struct intel_ilk_power_mgmt ips;
1408 struct i915_power_domains power_domains;
1410 struct i915_psr psr;
1412 struct i915_gpu_error gpu_error;
1414 struct drm_i915_gem_object *vlv_pctx;
1416 #ifdef CONFIG_DRM_I915_FBDEV
1417 /* list of fbdev register on this device */
1418 struct intel_fbdev *fbdev;
1422 * The console may be contended at resume, but we don't
1423 * want it to block on it.
1425 struct work_struct console_resume_work;
1427 struct drm_property *broadcast_rgb_property;
1428 struct drm_property *force_audio_property;
1430 uint32_t hw_context_size;
1431 struct list_head context_list;
1436 struct i915_suspend_saved_registers regfile;
1440 * Raw watermark latency values:
1441 * in 0.1us units for WM0,
1442 * in 0.5us units for WM1+.
1445 uint16_t pri_latency[5];
1447 uint16_t spr_latency[5];
1449 uint16_t cur_latency[5];
1451 /* current hardware state */
1452 struct ilk_wm_values hw;
1455 struct i915_runtime_pm pm;
1457 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1459 struct i915_dri1_state dri1;
1460 /* Old ums support infrastructure, same warning applies. */
1461 struct i915_ums_state ums;
1464 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1466 return dev->dev_private;
1469 /* Iterate over initialised rings */
1470 #define for_each_ring(ring__, dev_priv__, i__) \
1471 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1472 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1474 enum hdmi_force_audio {
1475 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1476 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1477 HDMI_AUDIO_AUTO, /* trust EDID */
1478 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1481 #define I915_GTT_OFFSET_NONE ((u32)-1)
1483 struct drm_i915_gem_object_ops {
1484 /* Interface between the GEM object and its backing storage.
1485 * get_pages() is called once prior to the use of the associated set
1486 * of pages before to binding them into the GTT, and put_pages() is
1487 * called after we no longer need them. As we expect there to be
1488 * associated cost with migrating pages between the backing storage
1489 * and making them available for the GPU (e.g. clflush), we may hold
1490 * onto the pages after they are no longer referenced by the GPU
1491 * in case they may be used again shortly (for example migrating the
1492 * pages to a different memory domain within the GTT). put_pages()
1493 * will therefore most likely be called when the object itself is
1494 * being released or under memory pressure (where we attempt to
1495 * reap pages for the shrinker).
1497 int (*get_pages)(struct drm_i915_gem_object *);
1498 void (*put_pages)(struct drm_i915_gem_object *);
1501 struct drm_i915_gem_object {
1502 struct drm_gem_object base;
1504 const struct drm_i915_gem_object_ops *ops;
1506 /** List of VMAs backed by this object */
1507 struct list_head vma_list;
1509 /** Stolen memory for this object, instead of being backed by shmem. */
1510 struct drm_mm_node *stolen;
1511 struct list_head global_list;
1513 struct list_head ring_list;
1514 /** Used in execbuf to temporarily hold a ref */
1515 struct list_head obj_exec_link;
1518 * This is set if the object is on the active lists (has pending
1519 * rendering and so a non-zero seqno), and is not set if it i s on
1520 * inactive (ready to be unbound) list.
1522 unsigned int active:1;
1525 * This is set if the object has been written to since last bound
1528 unsigned int dirty:1;
1531 * Fence register bits (if any) for this object. Will be set
1532 * as needed when mapped into the GTT.
1533 * Protected by dev->struct_mutex.
1535 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1538 * Advice: are the backing pages purgeable?
1540 unsigned int madv:2;
1543 * Current tiling mode for the object.
1545 unsigned int tiling_mode:2;
1547 * Whether the tiling parameters for the currently associated fence
1548 * register have changed. Note that for the purposes of tracking
1549 * tiling changes we also treat the unfenced register, the register
1550 * slot that the object occupies whilst it executes a fenced
1551 * command (such as BLT on gen2/3), as a "fence".
1553 unsigned int fence_dirty:1;
1556 * Is the object at the current location in the gtt mappable and
1557 * fenceable? Used to avoid costly recalculations.
1559 unsigned int map_and_fenceable:1;
1562 * Whether the current gtt mapping needs to be mappable (and isn't just
1563 * mappable by accident). Track pin and fault separate for a more
1564 * accurate mappable working set.
1566 unsigned int fault_mappable:1;
1567 unsigned int pin_mappable:1;
1568 unsigned int pin_display:1;
1571 * Is the GPU currently using a fence to access this buffer,
1573 unsigned int pending_fenced_gpu_access:1;
1574 unsigned int fenced_gpu_access:1;
1576 unsigned int cache_level:3;
1578 unsigned int has_aliasing_ppgtt_mapping:1;
1579 unsigned int has_global_gtt_mapping:1;
1580 unsigned int has_dma_mapping:1;
1582 struct sg_table *pages;
1583 int pages_pin_count;
1585 /* prime dma-buf support */
1586 void *dma_buf_vmapping;
1589 struct intel_ring_buffer *ring;
1591 /** Breadcrumb of last rendering to the buffer. */
1592 uint32_t last_read_seqno;
1593 uint32_t last_write_seqno;
1594 /** Breadcrumb of last fenced GPU access to the buffer. */
1595 uint32_t last_fenced_seqno;
1597 /** Current tiling stride for the object, if it's tiled. */
1600 /** References from framebuffers, locks out tiling changes. */
1601 unsigned long framebuffer_references;
1603 /** Record of address bit 17 of each page at last unbind. */
1604 unsigned long *bit_17;
1606 /** User space pin count and filp owning the pin */
1607 unsigned long user_pin_count;
1608 struct drm_file *pin_filp;
1610 /** for phy allocated objects */
1611 struct drm_i915_gem_phys_object *phys_obj;
1614 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1617 * Request queue structure.
1619 * The request queue allows us to note sequence numbers that have been emitted
1620 * and may be associated with active buffers to be retired.
1622 * By keeping this list, we can avoid having to do questionable
1623 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1624 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1626 struct drm_i915_gem_request {
1627 /** On Which ring this request was generated */
1628 struct intel_ring_buffer *ring;
1630 /** GEM sequence number associated with this request. */
1633 /** Position in the ringbuffer of the start of the request */
1636 /** Position in the ringbuffer of the end of the request */
1639 /** Context related to this request */
1640 struct i915_hw_context *ctx;
1642 /** Batch buffer related to this request if any */
1643 struct drm_i915_gem_object *batch_obj;
1645 /** Time at which this request was emitted, in jiffies. */
1646 unsigned long emitted_jiffies;
1648 /** global list entry for this request */
1649 struct list_head list;
1651 struct drm_i915_file_private *file_priv;
1652 /** file_priv list entry for this request */
1653 struct list_head client_list;
1656 struct drm_i915_file_private {
1657 struct drm_i915_private *dev_priv;
1658 struct drm_file *file;
1662 struct list_head request_list;
1663 struct delayed_work idle_work;
1665 struct idr context_idr;
1667 struct i915_hw_context *private_default_ctx;
1668 atomic_t rps_wait_boost;
1672 * A command that requires special handling by the command parser.
1674 struct drm_i915_cmd_descriptor {
1676 * Flags describing how the command parser processes the command.
1678 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1679 * a length mask if not set
1680 * CMD_DESC_SKIP: The command is allowed but does not follow the
1681 * standard length encoding for the opcode range in
1683 * CMD_DESC_REJECT: The command is never allowed
1684 * CMD_DESC_REGISTER: The command should be checked against the
1685 * register whitelist for the appropriate ring
1686 * CMD_DESC_MASTER: The command is allowed if the submitting process
1690 #define CMD_DESC_FIXED (1<<0)
1691 #define CMD_DESC_SKIP (1<<1)
1692 #define CMD_DESC_REJECT (1<<2)
1693 #define CMD_DESC_REGISTER (1<<3)
1694 #define CMD_DESC_BITMASK (1<<4)
1695 #define CMD_DESC_MASTER (1<<5)
1698 * The command's unique identification bits and the bitmask to get them.
1699 * This isn't strictly the opcode field as defined in the spec and may
1700 * also include type, subtype, and/or subop fields.
1708 * The command's length. The command is either fixed length (i.e. does
1709 * not include a length field) or has a length field mask. The flag
1710 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1711 * a length mask. All command entries in a command table must include
1712 * length information.
1720 * Describes where to find a register address in the command to check
1721 * against the ring's register whitelist. Only valid if flags has the
1722 * CMD_DESC_REGISTER bit set.
1729 #define MAX_CMD_DESC_BITMASKS 3
1731 * Describes command checks where a particular dword is masked and
1732 * compared against an expected value. If the command does not match
1733 * the expected value, the parser rejects it. Only valid if flags has
1734 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1737 * If the check specifies a non-zero condition_mask then the parser
1738 * only performs the check when the bits specified by condition_mask
1745 u32 condition_offset;
1747 } bits[MAX_CMD_DESC_BITMASKS];
1751 * A table of commands requiring special handling by the command parser.
1753 * Each ring has an array of tables. Each table consists of an array of command
1754 * descriptors, which must be sorted with command opcodes in ascending order.
1756 struct drm_i915_cmd_table {
1757 const struct drm_i915_cmd_descriptor *table;
1761 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1763 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1764 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1765 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1766 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1767 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1768 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1769 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1770 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1771 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1772 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1773 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1774 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1775 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1776 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1777 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1778 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1779 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1780 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1781 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1782 (dev)->pdev->device == 0x0152 || \
1783 (dev)->pdev->device == 0x015a)
1784 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1785 (dev)->pdev->device == 0x0106 || \
1786 (dev)->pdev->device == 0x010A)
1787 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1788 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1789 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1790 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1791 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1792 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1793 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1794 (((dev)->pdev->device & 0xf) == 0x2 || \
1795 ((dev)->pdev->device & 0xf) == 0x6 || \
1796 ((dev)->pdev->device & 0xf) == 0xe))
1797 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1798 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1799 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1800 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1801 ((dev)->pdev->device & 0x00F0) == 0x0020)
1802 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1805 * The genX designation typically refers to the render engine, so render
1806 * capability related checks should use IS_GEN, while display and other checks
1807 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1810 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1811 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1812 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1813 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1814 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1815 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1816 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1818 #define RENDER_RING (1<<RCS)
1819 #define BSD_RING (1<<VCS)
1820 #define BLT_RING (1<<BCS)
1821 #define VEBOX_RING (1<<VECS)
1822 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1823 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1824 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1825 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1826 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1827 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1829 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1830 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1831 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1832 && !IS_BROADWELL(dev))
1833 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1834 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1836 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1837 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1839 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1840 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1842 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1843 * even when in MSI mode. This results in spurious interrupt warnings if the
1844 * legacy irq no. is shared with another device. The kernel then disables that
1845 * interrupt source and so prevents the other device from working properly.
1847 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1848 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1850 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1851 * rows, which changed the alignment requirements and fence programming.
1853 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1855 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1856 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1857 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1858 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1859 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1861 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1862 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1863 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1865 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1867 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1868 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1869 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1870 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
1871 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
1873 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1874 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1875 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1876 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1877 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1878 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1880 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1881 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1882 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1883 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1884 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1885 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1887 /* DPF == dynamic parity feature */
1888 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1889 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1891 #define GT_FREQUENCY_MULTIPLIER 50
1893 #include "i915_trace.h"
1895 extern const struct drm_ioctl_desc i915_ioctls[];
1896 extern int i915_max_ioctl;
1898 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1899 extern int i915_resume(struct drm_device *dev);
1900 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1901 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1904 struct i915_params {
1906 int panel_ignore_lid;
1907 unsigned int powersave;
1909 unsigned int lvds_downclock;
1910 int lvds_channel_mode;
1912 int vbt_sdvo_panel_type;
1917 unsigned int preliminary_hw_support;
1918 int disable_power_well;
1920 int invert_brightness;
1921 int enable_cmd_parser;
1922 /* leave bools at the end to not create holes */
1923 bool enable_hangcheck;
1925 bool prefault_disable;
1927 bool disable_display;
1929 extern struct i915_params i915 __read_mostly;
1932 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1933 extern void i915_kernel_lost_context(struct drm_device * dev);
1934 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1935 extern int i915_driver_unload(struct drm_device *);
1936 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1937 extern void i915_driver_lastclose(struct drm_device * dev);
1938 extern void i915_driver_preclose(struct drm_device *dev,
1939 struct drm_file *file_priv);
1940 extern void i915_driver_postclose(struct drm_device *dev,
1941 struct drm_file *file_priv);
1942 extern int i915_driver_device_is_agp(struct drm_device * dev);
1943 #ifdef CONFIG_COMPAT
1944 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1947 extern int i915_emit_box(struct drm_device *dev,
1948 struct drm_clip_rect *box,
1950 extern int intel_gpu_reset(struct drm_device *dev);
1951 extern int i915_reset(struct drm_device *dev);
1952 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1953 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1954 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1955 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1957 extern void intel_console_resume(struct work_struct *work);
1960 void i915_queue_hangcheck(struct drm_device *dev);
1962 void i915_handle_error(struct drm_device *dev, bool wedged,
1963 const char *fmt, ...);
1965 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
1967 extern void intel_irq_init(struct drm_device *dev);
1968 extern void intel_hpd_init(struct drm_device *dev);
1970 extern void intel_uncore_sanitize(struct drm_device *dev);
1971 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1972 extern void intel_uncore_init(struct drm_device *dev);
1973 extern void intel_uncore_check_errors(struct drm_device *dev);
1974 extern void intel_uncore_fini(struct drm_device *dev);
1977 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
1981 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
1984 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
1985 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
1988 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1989 struct drm_file *file_priv);
1990 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1991 struct drm_file *file_priv);
1992 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1993 struct drm_file *file_priv);
1994 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1995 struct drm_file *file_priv);
1996 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1997 struct drm_file *file_priv);
1998 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1999 struct drm_file *file_priv);
2000 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2001 struct drm_file *file_priv);
2002 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2003 struct drm_file *file_priv);
2004 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2005 struct drm_file *file_priv);
2006 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2007 struct drm_file *file_priv);
2008 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2009 struct drm_file *file_priv);
2010 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2011 struct drm_file *file_priv);
2012 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2013 struct drm_file *file_priv);
2014 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2015 struct drm_file *file);
2016 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *file);
2018 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2019 struct drm_file *file_priv);
2020 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2021 struct drm_file *file_priv);
2022 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2023 struct drm_file *file_priv);
2024 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2025 struct drm_file *file_priv);
2026 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2027 struct drm_file *file_priv);
2028 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2029 struct drm_file *file_priv);
2030 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *file_priv);
2032 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *file_priv);
2034 void i915_gem_load(struct drm_device *dev);
2035 void *i915_gem_object_alloc(struct drm_device *dev);
2036 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2037 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2038 const struct drm_i915_gem_object_ops *ops);
2039 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2041 void i915_init_vm(struct drm_i915_private *dev_priv,
2042 struct i915_address_space *vm);
2043 void i915_gem_free_object(struct drm_gem_object *obj);
2044 void i915_gem_vma_destroy(struct i915_vma *vma);
2046 #define PIN_MAPPABLE 0x1
2047 #define PIN_NONBLOCK 0x2
2048 #define PIN_GLOBAL 0x4
2049 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2050 struct i915_address_space *vm,
2053 int __must_check i915_vma_unbind(struct i915_vma *vma);
2054 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2055 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2056 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2057 void i915_gem_lastclose(struct drm_device *dev);
2059 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2060 int *needs_clflush);
2062 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2063 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2065 struct sg_page_iter sg_iter;
2067 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2068 return sg_page_iter_page(&sg_iter);
2072 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2074 BUG_ON(obj->pages == NULL);
2075 obj->pages_pin_count++;
2077 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2079 BUG_ON(obj->pages_pin_count == 0);
2080 obj->pages_pin_count--;
2083 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2084 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2085 struct intel_ring_buffer *to);
2086 void i915_vma_move_to_active(struct i915_vma *vma,
2087 struct intel_ring_buffer *ring);
2088 int i915_gem_dumb_create(struct drm_file *file_priv,
2089 struct drm_device *dev,
2090 struct drm_mode_create_dumb *args);
2091 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2092 uint32_t handle, uint64_t *offset);
2094 * Returns true if seq1 is later than seq2.
2097 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2099 return (int32_t)(seq1 - seq2) >= 0;
2102 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2103 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2104 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2105 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2108 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2110 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2111 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2112 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2119 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2121 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2122 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2123 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2124 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2128 struct drm_i915_gem_request *
2129 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2131 bool i915_gem_retire_requests(struct drm_device *dev);
2132 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2133 bool interruptible);
2134 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2136 return unlikely(atomic_read(&error->reset_counter)
2137 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2140 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2142 return atomic_read(&error->reset_counter) & I915_WEDGED;
2145 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2147 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2150 void i915_gem_reset(struct drm_device *dev);
2151 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2152 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2153 int __must_check i915_gem_init(struct drm_device *dev);
2154 int __must_check i915_gem_init_hw(struct drm_device *dev);
2155 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2156 void i915_gem_init_swizzling(struct drm_device *dev);
2157 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2158 int __must_check i915_gpu_idle(struct drm_device *dev);
2159 int __must_check i915_gem_suspend(struct drm_device *dev);
2160 int __i915_add_request(struct intel_ring_buffer *ring,
2161 struct drm_file *file,
2162 struct drm_i915_gem_object *batch_obj,
2164 #define i915_add_request(ring, seqno) \
2165 __i915_add_request(ring, NULL, NULL, seqno)
2166 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2168 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2170 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2173 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2175 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2177 struct intel_ring_buffer *pipelined);
2178 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2179 int i915_gem_attach_phys_object(struct drm_device *dev,
2180 struct drm_i915_gem_object *obj,
2183 void i915_gem_detach_phys_object(struct drm_device *dev,
2184 struct drm_i915_gem_object *obj);
2185 void i915_gem_free_all_phys_object(struct drm_device *dev);
2186 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2187 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2190 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2192 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2193 int tiling_mode, bool fenced);
2195 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2196 enum i915_cache_level cache_level);
2198 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2199 struct dma_buf *dma_buf);
2201 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2202 struct drm_gem_object *gem_obj, int flags);
2204 void i915_gem_restore_fences(struct drm_device *dev);
2206 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2207 struct i915_address_space *vm);
2208 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2209 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2210 struct i915_address_space *vm);
2211 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2212 struct i915_address_space *vm);
2213 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2214 struct i915_address_space *vm);
2216 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2217 struct i915_address_space *vm);
2219 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2220 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2221 struct i915_vma *vma;
2222 list_for_each_entry(vma, &obj->vma_list, vma_link)
2223 if (vma->pin_count > 0)
2228 /* Some GGTT VM helpers */
2229 #define obj_to_ggtt(obj) \
2230 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2231 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2233 struct i915_address_space *ggtt =
2234 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2238 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2240 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2243 static inline unsigned long
2244 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2246 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2249 static inline unsigned long
2250 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2252 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2255 static inline int __must_check
2256 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2260 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2264 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2266 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2269 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2271 /* i915_gem_context.c */
2272 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2273 int __must_check i915_gem_context_init(struct drm_device *dev);
2274 void i915_gem_context_fini(struct drm_device *dev);
2275 void i915_gem_context_reset(struct drm_device *dev);
2276 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2277 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2278 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2279 int i915_switch_context(struct intel_ring_buffer *ring,
2280 struct drm_file *file, struct i915_hw_context *to);
2281 struct i915_hw_context *
2282 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2283 void i915_gem_context_free(struct kref *ctx_ref);
2284 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2286 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2287 kref_get(&ctx->ref);
2290 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2292 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2293 kref_put(&ctx->ref, i915_gem_context_free);
2296 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2298 return c->id == DEFAULT_CONTEXT_ID;
2301 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2302 struct drm_file *file);
2303 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2304 struct drm_file *file);
2306 /* i915_gem_evict.c */
2307 int __must_check i915_gem_evict_something(struct drm_device *dev,
2308 struct i915_address_space *vm,
2311 unsigned cache_level,
2313 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2314 int i915_gem_evict_everything(struct drm_device *dev);
2316 /* belongs in i915_gem_gtt.h */
2317 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2319 if (INTEL_INFO(dev)->gen < 6)
2320 intel_gtt_chipset_flush();
2323 /* i915_gem_stolen.c */
2324 int i915_gem_init_stolen(struct drm_device *dev);
2325 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2326 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2327 void i915_gem_cleanup_stolen(struct drm_device *dev);
2328 struct drm_i915_gem_object *
2329 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2330 struct drm_i915_gem_object *
2331 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2335 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2337 /* i915_gem_tiling.c */
2338 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2340 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2342 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2343 obj->tiling_mode != I915_TILING_NONE;
2346 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2347 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2348 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2350 /* i915_gem_debug.c */
2352 int i915_verify_lists(struct drm_device *dev);
2354 #define i915_verify_lists(dev) 0
2357 /* i915_debugfs.c */
2358 int i915_debugfs_init(struct drm_minor *minor);
2359 void i915_debugfs_cleanup(struct drm_minor *minor);
2360 #ifdef CONFIG_DEBUG_FS
2361 void intel_display_crc_init(struct drm_device *dev);
2363 static inline void intel_display_crc_init(struct drm_device *dev) {}
2366 /* i915_gpu_error.c */
2368 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2369 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2370 const struct i915_error_state_file_priv *error);
2371 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2372 size_t count, loff_t pos);
2373 static inline void i915_error_state_buf_release(
2374 struct drm_i915_error_state_buf *eb)
2378 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2379 const char *error_msg);
2380 void i915_error_state_get(struct drm_device *dev,
2381 struct i915_error_state_file_priv *error_priv);
2382 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2383 void i915_destroy_error_state(struct drm_device *dev);
2385 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2386 const char *i915_cache_level_str(int type);
2388 /* i915_cmd_parser.c */
2389 int i915_cmd_parser_get_version(void);
2390 void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2391 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2392 int i915_parse_cmds(struct intel_ring_buffer *ring,
2393 struct drm_i915_gem_object *batch_obj,
2394 u32 batch_start_offset,
2397 /* i915_suspend.c */
2398 extern int i915_save_state(struct drm_device *dev);
2399 extern int i915_restore_state(struct drm_device *dev);
2402 void i915_save_display_reg(struct drm_device *dev);
2403 void i915_restore_display_reg(struct drm_device *dev);
2406 void i915_setup_sysfs(struct drm_device *dev_priv);
2407 void i915_teardown_sysfs(struct drm_device *dev_priv);
2410 extern int intel_setup_gmbus(struct drm_device *dev);
2411 extern void intel_teardown_gmbus(struct drm_device *dev);
2412 static inline bool intel_gmbus_is_port_valid(unsigned port)
2414 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2417 extern struct i2c_adapter *intel_gmbus_get_adapter(
2418 struct drm_i915_private *dev_priv, unsigned port);
2419 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2420 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2421 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2423 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2425 extern void intel_i2c_reset(struct drm_device *dev);
2427 /* intel_opregion.c */
2428 struct intel_encoder;
2430 extern int intel_opregion_setup(struct drm_device *dev);
2431 extern void intel_opregion_init(struct drm_device *dev);
2432 extern void intel_opregion_fini(struct drm_device *dev);
2433 extern void intel_opregion_asle_intr(struct drm_device *dev);
2434 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2436 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2439 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2440 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2441 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2442 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2444 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2449 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2457 extern void intel_register_dsm_handler(void);
2458 extern void intel_unregister_dsm_handler(void);
2460 static inline void intel_register_dsm_handler(void) { return; }
2461 static inline void intel_unregister_dsm_handler(void) { return; }
2462 #endif /* CONFIG_ACPI */
2465 extern void intel_modeset_init_hw(struct drm_device *dev);
2466 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2467 extern void intel_modeset_init(struct drm_device *dev);
2468 extern void intel_modeset_gem_init(struct drm_device *dev);
2469 extern void intel_modeset_cleanup(struct drm_device *dev);
2470 extern void intel_connector_unregister(struct intel_connector *);
2471 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2472 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2473 bool force_restore);
2474 extern void i915_redisable_vga(struct drm_device *dev);
2475 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2476 extern bool intel_fbc_enabled(struct drm_device *dev);
2477 extern void intel_disable_fbc(struct drm_device *dev);
2478 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2479 extern void intel_init_pch_refclk(struct drm_device *dev);
2480 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2481 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2482 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2483 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2484 extern void intel_detect_pch(struct drm_device *dev);
2485 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2486 extern int intel_enable_rc6(const struct drm_device *dev);
2488 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2489 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2490 struct drm_file *file);
2491 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2492 struct drm_file *file);
2495 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2496 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2497 struct intel_overlay_error_state *error);
2499 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2500 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2501 struct drm_device *dev,
2502 struct intel_display_error_state *error);
2504 /* On SNB platform, before reading ring registers forcewake bit
2505 * must be set to prevent GT core from power down and stale values being
2508 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2509 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2510 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2512 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2513 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2515 /* intel_sideband.c */
2516 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2517 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2518 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2519 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2520 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2521 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2522 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2523 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2524 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2525 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2526 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2527 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2528 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2529 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2530 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2531 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2532 enum intel_sbi_destination destination);
2533 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2534 enum intel_sbi_destination destination);
2535 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2536 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2538 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2539 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2541 #define FORCEWAKE_RENDER (1 << 0)
2542 #define FORCEWAKE_MEDIA (1 << 1)
2543 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2546 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2547 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2549 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2550 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2551 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2552 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2554 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2555 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2556 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2557 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2559 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2560 * will be implemented using 2 32-bit writes in an arbitrary order with
2561 * an arbitrary delay between them. This can cause the hardware to
2562 * act upon the intermediate value, possibly leading to corruption and
2563 * machine death. You have been warned.
2565 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2566 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2568 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2569 u32 upper = I915_READ(upper_reg); \
2570 u32 lower = I915_READ(lower_reg); \
2571 u32 tmp = I915_READ(upper_reg); \
2572 if (upper != tmp) { \
2574 lower = I915_READ(lower_reg); \
2575 WARN_ON(I915_READ(upper_reg) != upper); \
2577 (u64)upper << 32 | lower; })
2579 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2580 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2582 /* "Broadcast RGB" property */
2583 #define INTEL_BROADCAST_RGB_AUTO 0
2584 #define INTEL_BROADCAST_RGB_FULL 1
2585 #define INTEL_BROADCAST_RGB_LIMITED 2
2587 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2589 if (HAS_PCH_SPLIT(dev))
2590 return CPU_VGACNTRL;
2591 else if (IS_VALLEYVIEW(dev))
2592 return VLV_VGACNTRL;
2597 static inline void __user *to_user_ptr(u64 address)
2599 return (void __user *)(uintptr_t)address;
2602 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2604 unsigned long j = msecs_to_jiffies(m);
2606 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2609 static inline unsigned long
2610 timespec_to_jiffies_timeout(const struct timespec *value)
2612 unsigned long j = timespec_to_jiffies(value);
2614 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2618 * If you need to wait X milliseconds between events A and B, but event B
2619 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2620 * when event A happened, then just before event B you call this function and
2621 * pass the timestamp as the first argument, and X as the second argument.
2624 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2626 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2629 * Don't re-read the value of "jiffies" every time since it may change
2630 * behind our back and break the math.
2632 tmp_jiffies = jiffies;
2633 target_jiffies = timestamp_jiffies +
2634 msecs_to_jiffies_timeout(to_wait_ms);
2636 if (time_after(target_jiffies, tmp_jiffies)) {
2637 remaining_jiffies = target_jiffies - tmp_jiffies;
2638 while (remaining_jiffies)
2640 schedule_timeout_uninterruptible(remaining_jiffies);