1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
93 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
94 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
104 #define I915_GEM_GPU_DOMAINS \
105 (I915_GEM_DOMAIN_RENDER | \
106 I915_GEM_DOMAIN_SAMPLER | \
107 I915_GEM_DOMAIN_COMMAND | \
108 I915_GEM_DOMAIN_INSTRUCTION | \
109 I915_GEM_DOMAIN_VERTEX)
111 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
113 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
114 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
115 if ((intel_encoder)->base.crtc == (__crtc))
117 struct intel_pch_pll {
118 int refcount; /* count of number of CRTCs sharing this PLL */
119 int active; /* count of number of active CRTCs (i.e. DPMS on) */
120 bool on; /* is the PLL actually active? Disabled during modeset */
125 #define I915_NUM_PLLS 2
127 /* Used by dp and fdi links */
128 struct intel_link_m_n {
136 void intel_link_compute_m_n(int bpp, int nlanes,
137 int pixel_clock, int link_clock,
138 struct intel_link_m_n *m_n);
140 struct intel_ddi_plls {
146 /* Interface history:
149 * 1.2: Add Power Management
150 * 1.3: Add vblank support
151 * 1.4: Fix cmdbuffer path, add heap destroy
152 * 1.5: Add vblank pipe configuration
153 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
154 * - Support vertical blank on secondary display pipe
156 #define DRIVER_MAJOR 1
157 #define DRIVER_MINOR 6
158 #define DRIVER_PATCHLEVEL 0
160 #define WATCH_COHERENCY 0
161 #define WATCH_LISTS 0
164 #define I915_GEM_PHYS_CURSOR_0 1
165 #define I915_GEM_PHYS_CURSOR_1 2
166 #define I915_GEM_PHYS_OVERLAY_REGS 3
167 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
169 struct drm_i915_gem_phys_object {
171 struct page **page_list;
172 drm_dma_handle_t *handle;
173 struct drm_i915_gem_object *cur_obj;
176 struct opregion_header;
177 struct opregion_acpi;
178 struct opregion_swsci;
179 struct opregion_asle;
180 struct drm_i915_private;
182 struct intel_opregion {
183 struct opregion_header __iomem *header;
184 struct opregion_acpi __iomem *acpi;
185 struct opregion_swsci __iomem *swsci;
186 struct opregion_asle __iomem *asle;
188 u32 __iomem *lid_state;
190 #define OPREGION_SIZE (8*1024)
192 struct intel_overlay;
193 struct intel_overlay_error_state;
195 struct drm_i915_master_private {
196 drm_local_map_t *sarea;
197 struct _drm_i915_sarea *sarea_priv;
199 #define I915_FENCE_REG_NONE -1
200 #define I915_MAX_NUM_FENCES 32
201 /* 32 fences + sign bit for FENCE_REG_NONE */
202 #define I915_MAX_NUM_FENCE_BITS 6
204 struct drm_i915_fence_reg {
205 struct list_head lru_list;
206 struct drm_i915_gem_object *obj;
210 struct sdvo_device_mapping {
219 struct intel_display_error_state;
221 struct drm_i915_error_state {
229 bool waiting[I915_NUM_RINGS];
230 u32 pipestat[I915_MAX_PIPES];
231 u32 tail[I915_NUM_RINGS];
232 u32 head[I915_NUM_RINGS];
233 u32 ctl[I915_NUM_RINGS];
234 u32 ipeir[I915_NUM_RINGS];
235 u32 ipehr[I915_NUM_RINGS];
236 u32 instdone[I915_NUM_RINGS];
237 u32 acthd[I915_NUM_RINGS];
238 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
239 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
240 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
241 /* our own tracking of ring head and tail */
242 u32 cpu_ring_head[I915_NUM_RINGS];
243 u32 cpu_ring_tail[I915_NUM_RINGS];
244 u32 error; /* gen6+ */
245 u32 err_int; /* gen7 */
246 u32 instpm[I915_NUM_RINGS];
247 u32 instps[I915_NUM_RINGS];
248 u32 extra_instdone[I915_NUM_INSTDONE_REG];
249 u32 seqno[I915_NUM_RINGS];
251 u32 fault_reg[I915_NUM_RINGS];
253 u32 faddr[I915_NUM_RINGS];
254 u64 fence[I915_MAX_NUM_FENCES];
256 struct drm_i915_error_ring {
257 struct drm_i915_error_object {
261 } *ringbuffer, *batchbuffer, *ctx;
262 struct drm_i915_error_request {
268 } ring[I915_NUM_RINGS];
269 struct drm_i915_error_buffer {
276 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
283 } *active_bo, *pinned_bo;
284 u32 active_bo_count, pinned_bo_count;
285 struct intel_overlay_error_state *overlay;
286 struct intel_display_error_state *display;
289 struct intel_crtc_config;
292 struct drm_i915_display_funcs {
293 bool (*fbc_enabled)(struct drm_device *dev);
294 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
295 void (*disable_fbc)(struct drm_device *dev);
296 int (*get_display_clock_speed)(struct drm_device *dev);
297 int (*get_fifo_size)(struct drm_device *dev, int plane);
298 void (*update_wm)(struct drm_device *dev);
299 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
300 uint32_t sprite_width, int pixel_size);
301 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
302 struct drm_display_mode *mode);
303 void (*modeset_global_resources)(struct drm_device *dev);
304 /* Returns the active state of the crtc, and if the crtc is active,
305 * fills out the pipe-config with the hw state. */
306 bool (*get_pipe_config)(struct intel_crtc *,
307 struct intel_crtc_config *);
308 int (*crtc_mode_set)(struct drm_crtc *crtc,
310 struct drm_framebuffer *old_fb);
311 void (*crtc_enable)(struct drm_crtc *crtc);
312 void (*crtc_disable)(struct drm_crtc *crtc);
313 void (*off)(struct drm_crtc *crtc);
314 void (*write_eld)(struct drm_connector *connector,
315 struct drm_crtc *crtc);
316 void (*fdi_link_train)(struct drm_crtc *crtc);
317 void (*init_clock_gating)(struct drm_device *dev);
318 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
319 struct drm_framebuffer *fb,
320 struct drm_i915_gem_object *obj);
321 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
323 void (*hpd_irq_setup)(struct drm_device *dev);
324 /* clock updates for mode set */
326 /* render clock increase/decrease */
327 /* display clock increase/decrease */
328 /* pll clock increase/decrease */
331 struct drm_i915_gt_funcs {
332 void (*force_wake_get)(struct drm_i915_private *dev_priv);
333 void (*force_wake_put)(struct drm_i915_private *dev_priv);
336 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
337 func(is_mobile) sep \
340 func(is_i945gm) sep \
342 func(need_gfx_hws) sep \
344 func(is_pineview) sep \
345 func(is_broadwater) sep \
346 func(is_crestline) sep \
347 func(is_ivybridge) sep \
348 func(is_valleyview) sep \
349 func(is_haswell) sep \
350 func(has_force_wake) sep \
352 func(has_pipe_cxsr) sep \
353 func(has_hotplug) sep \
354 func(cursor_needs_physical) sep \
355 func(has_overlay) sep \
356 func(overlay_needs_physical) sep \
357 func(supports_tv) sep \
358 func(has_bsd_ring) sep \
359 func(has_blt_ring) sep \
364 #define DEFINE_FLAG(name) u8 name:1
365 #define SEP_SEMICOLON ;
367 struct intel_device_info {
368 u32 display_mmio_offset;
371 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
377 enum i915_cache_level {
380 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
383 typedef uint32_t gen6_gtt_pte_t;
385 /* The Graphics Translation Table is the way in which GEN hardware translates a
386 * Graphics Virtual Address into a Physical Address. In addition to the normal
387 * collateral associated with any va->pa translations GEN hardware also has a
388 * portion of the GTT which can be mapped by the CPU and remain both coherent
389 * and correct (in cases like swizzling). That region is referred to as GMADR in
393 unsigned long start; /* Start offset of used GTT */
394 size_t total; /* Total size GTT can map */
395 size_t stolen_size; /* Total size of stolen memory */
397 unsigned long mappable_end; /* End offset that we can CPU map */
398 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
399 phys_addr_t mappable_base; /* PA of our GMADR */
401 /** "Graphics Stolen Memory" holds the global PTEs */
405 dma_addr_t scratch_page_dma;
406 struct page *scratch_page;
409 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
410 size_t *stolen, phys_addr_t *mappable_base,
411 unsigned long *mappable_end);
412 void (*gtt_remove)(struct drm_device *dev);
413 void (*gtt_clear_range)(struct drm_device *dev,
414 unsigned int first_entry,
415 unsigned int num_entries);
416 void (*gtt_insert_entries)(struct drm_device *dev,
418 unsigned int pg_start,
419 enum i915_cache_level cache_level);
420 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
422 enum i915_cache_level level);
424 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
426 #define I915_PPGTT_PD_ENTRIES 512
427 #define I915_PPGTT_PT_ENTRIES 1024
428 struct i915_hw_ppgtt {
429 struct drm_device *dev;
430 unsigned num_pd_entries;
431 struct page **pt_pages;
433 dma_addr_t *pt_dma_addr;
434 dma_addr_t scratch_page_dma_addr;
436 /* pte functions, mirroring the interface of the global gtt. */
437 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
438 unsigned int first_entry,
439 unsigned int num_entries);
440 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
442 unsigned int pg_start,
443 enum i915_cache_level cache_level);
444 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
446 enum i915_cache_level level);
447 int (*enable)(struct drm_device *dev);
448 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
452 /* This must match up with the value previously used for execbuf2.rsvd1. */
453 #define DEFAULT_CONTEXT_ID 0
454 struct i915_hw_context {
458 struct drm_i915_file_private *file_priv;
459 struct intel_ring_buffer *ring;
460 struct drm_i915_gem_object *obj;
464 FBC_NO_OUTPUT, /* no outputs enabled to compress */
465 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
466 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
467 FBC_MODE_TOO_LARGE, /* mode too large for compression */
468 FBC_BAD_PLANE, /* fbc not supported on plane */
469 FBC_NOT_TILED, /* buffer not tiled */
470 FBC_MULTIPLE_PIPES, /* more than one pipe active */
475 PCH_NONE = 0, /* No PCH present */
476 PCH_IBX, /* Ibexpeak PCH */
477 PCH_CPT, /* Cougarpoint PCH */
478 PCH_LPT, /* Lynxpoint PCH */
482 enum intel_sbi_destination {
487 #define QUIRK_PIPEA_FORCE (1<<0)
488 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
489 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
492 struct intel_fbc_work;
495 struct i2c_adapter adapter;
499 struct i2c_algo_bit_data bit_algo;
500 struct drm_i915_private *dev_priv;
503 struct i915_suspend_saved_registers {
524 u32 saveTRANS_HTOTAL_A;
525 u32 saveTRANS_HBLANK_A;
526 u32 saveTRANS_HSYNC_A;
527 u32 saveTRANS_VTOTAL_A;
528 u32 saveTRANS_VBLANK_A;
529 u32 saveTRANS_VSYNC_A;
537 u32 savePFIT_PGM_RATIOS;
538 u32 saveBLC_HIST_CTL;
540 u32 saveBLC_PWM_CTL2;
541 u32 saveBLC_CPU_PWM_CTL;
542 u32 saveBLC_CPU_PWM_CTL2;
555 u32 saveTRANS_HTOTAL_B;
556 u32 saveTRANS_HBLANK_B;
557 u32 saveTRANS_HSYNC_B;
558 u32 saveTRANS_VTOTAL_B;
559 u32 saveTRANS_VBLANK_B;
560 u32 saveTRANS_VSYNC_B;
574 u32 savePP_ON_DELAYS;
575 u32 savePP_OFF_DELAYS;
583 u32 savePFIT_CONTROL;
584 u32 save_palette_a[256];
585 u32 save_palette_b[256];
586 u32 saveDPFC_CB_BASE;
587 u32 saveFBC_CFB_BASE;
590 u32 saveFBC_CONTROL2;
600 u32 saveCACHE_MODE_0;
601 u32 saveMI_ARB_STATE;
612 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
623 u32 savePIPEA_GMCH_DATA_M;
624 u32 savePIPEB_GMCH_DATA_M;
625 u32 savePIPEA_GMCH_DATA_N;
626 u32 savePIPEB_GMCH_DATA_N;
627 u32 savePIPEA_DP_LINK_M;
628 u32 savePIPEB_DP_LINK_M;
629 u32 savePIPEA_DP_LINK_N;
630 u32 savePIPEB_DP_LINK_N;
641 u32 savePCH_DREF_CONTROL;
642 u32 saveDISP_ARB_CTL;
643 u32 savePIPEA_DATA_M1;
644 u32 savePIPEA_DATA_N1;
645 u32 savePIPEA_LINK_M1;
646 u32 savePIPEA_LINK_N1;
647 u32 savePIPEB_DATA_M1;
648 u32 savePIPEB_DATA_N1;
649 u32 savePIPEB_LINK_M1;
650 u32 savePIPEB_LINK_N1;
651 u32 saveMCHBAR_RENDER_STANDBY;
652 u32 savePCH_PORT_HOTPLUG;
655 struct intel_gen6_power_mgmt {
656 struct work_struct work;
657 struct delayed_work vlv_work;
659 /* lock - irqsave spinlock that protectects the work_struct and
663 /* The below variables an all the rps hw state are protected by
664 * dev->struct mutext. */
671 struct delayed_work delayed_resume_work;
674 * Protects RPS/RC6 register access and PCU communication.
675 * Must be taken after struct_mutex if nested.
677 struct mutex hw_lock;
680 /* defined intel_pm.c */
681 extern spinlock_t mchdev_lock;
683 struct intel_ilk_power_mgmt {
691 unsigned long last_time1;
692 unsigned long chipset_power;
694 struct timespec last_time2;
695 unsigned long gfx_power;
701 struct drm_i915_gem_object *pwrctx;
702 struct drm_i915_gem_object *renderctx;
705 struct i915_dri1_state {
706 unsigned allow_batchbuffer : 1;
707 u32 __iomem *gfx_hws_cpu_addr;
718 struct intel_l3_parity {
720 struct work_struct error_work;
724 /** Memory allocator for GTT stolen memory */
725 struct drm_mm stolen;
726 /** Memory allocator for GTT */
727 struct drm_mm gtt_space;
728 /** List of all objects in gtt_space. Used to restore gtt
729 * mappings on resume */
730 struct list_head bound_list;
732 * List of objects which are not bound to the GTT (thus
733 * are idle and not used by the GPU) but still have
734 * (presumably uncached) pages still attached.
736 struct list_head unbound_list;
738 /** Usable portion of the GTT for GEM */
739 unsigned long stolen_base; /* limited to low memory (32-bit) */
743 /** PPGTT used for aliasing the PPGTT with the GTT */
744 struct i915_hw_ppgtt *aliasing_ppgtt;
746 struct shrinker inactive_shrinker;
747 bool shrinker_no_lock_stealing;
750 * List of objects currently involved in rendering.
752 * Includes buffers having the contents of their GPU caches
753 * flushed, not necessarily primitives. last_rendering_seqno
754 * represents when the rendering involved will be completed.
756 * A reference is held on the buffer while on this list.
758 struct list_head active_list;
761 * LRU list of objects which are not in the ringbuffer and
762 * are ready to unbind, but are still in the GTT.
764 * last_rendering_seqno is 0 while an object is in this list.
766 * A reference is not held on the buffer while on this list,
767 * as merely being GTT-bound shouldn't prevent its being
768 * freed, and we'll pull it off the list in the free path.
770 struct list_head inactive_list;
772 /** LRU list of objects with fence regs on them. */
773 struct list_head fence_list;
776 * We leave the user IRQ off as much as possible,
777 * but this means that requests will finish and never
778 * be retired once the system goes idle. Set a timer to
779 * fire periodically while the ring is running. When it
780 * fires, go retire requests.
782 struct delayed_work retire_work;
785 * Are we in a non-interruptible section of code like
791 * Flag if the X Server, and thus DRM, is not currently in
792 * control of the device.
794 * This is set between LeaveVT and EnterVT. It needs to be
795 * replaced with a semaphore. It also needs to be
796 * transitioned away from for kernel modesetting.
800 /** Bit 6 swizzling required for X tiling */
801 uint32_t bit_6_swizzle_x;
802 /** Bit 6 swizzling required for Y tiling */
803 uint32_t bit_6_swizzle_y;
805 /* storage for physical objects */
806 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
808 /* accounting, useful for userland debugging */
809 size_t object_memory;
813 struct i915_gpu_error {
814 /* For hangcheck timer */
815 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
816 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
817 struct timer_list hangcheck_timer;
819 uint32_t last_acthd[I915_NUM_RINGS];
820 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
822 /* For reset and error_state handling. */
824 /* Protected by the above dev->gpu_error.lock. */
825 struct drm_i915_error_state *first_error;
826 struct work_struct work;
828 unsigned long last_reset;
831 * State variable and reset counter controlling the reset flow
833 * Upper bits are for the reset counter. This counter is used by the
834 * wait_seqno code to race-free noticed that a reset event happened and
835 * that it needs to restart the entire ioctl (since most likely the
836 * seqno it waited for won't ever signal anytime soon).
838 * This is important for lock-free wait paths, where no contended lock
839 * naturally enforces the correct ordering between the bail-out of the
840 * waiter and the gpu reset work code.
842 * Lowest bit controls the reset state machine: Set means a reset is in
843 * progress. This state will (presuming we don't have any bugs) decay
844 * into either unset (successful reset) or the special WEDGED value (hw
845 * terminally sour). All waiters on the reset_queue will be woken when
848 atomic_t reset_counter;
851 * Special values/flags for reset_counter
853 * Note that the code relies on
854 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
857 #define I915_RESET_IN_PROGRESS_FLAG 1
858 #define I915_WEDGED 0xffffffff
861 * Waitqueue to signal when the reset has completed. Used by clients
862 * that wait for dev_priv->mm.wedged to settle.
864 wait_queue_head_t reset_queue;
866 /* For gpu hang simulation. */
867 unsigned int stop_rings;
870 enum modeset_restore {
876 typedef struct drm_i915_private {
877 struct drm_device *dev;
878 struct kmem_cache *slab;
880 const struct intel_device_info *info;
882 int relative_constants_mode;
886 struct drm_i915_gt_funcs gt;
887 /** gt_fifo_count and the subsequent register write are synchronized
888 * with dev->struct_mutex. */
889 unsigned gt_fifo_count;
890 /** forcewake_count is protected by gt_lock */
891 unsigned forcewake_count;
892 /** gt_lock is also taken in irq contexts. */
895 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
898 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
899 * controller on different i2c buses. */
900 struct mutex gmbus_mutex;
903 * Base address of the gmbus and gpio block.
905 uint32_t gpio_mmio_base;
907 wait_queue_head_t gmbus_wait_queue;
909 struct pci_dev *bridge_dev;
910 struct intel_ring_buffer ring[I915_NUM_RINGS];
911 uint32_t last_seqno, next_seqno;
913 drm_dma_handle_t *status_page_dmah;
914 struct resource mch_res;
916 atomic_t irq_received;
918 /* protects the irq masks */
921 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
922 struct pm_qos_request pm_qos;
924 /* DPIO indirect register protection */
925 struct mutex dpio_lock;
927 /** Cached value of IMR to avoid reads in updating the bitfield */
931 struct work_struct hotplug_work;
932 bool enable_hotplug_processing;
934 unsigned long hpd_last_jiffies;
939 HPD_MARK_DISABLED = 2
941 } hpd_stats[HPD_NUM_PINS];
943 struct timer_list hotplug_reenable_timer;
948 unsigned long cfb_size;
950 enum plane cfb_plane;
952 struct intel_fbc_work *fbc_work;
954 struct intel_opregion opregion;
957 struct intel_overlay *overlay;
958 unsigned int sprite_scaling_enabled;
964 spinlock_t lock; /* bl registers and the above bl fields */
965 struct backlight_device *device;
969 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
970 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
972 /* Feature bits from the VBIOS */
973 unsigned int int_tv_support:1;
974 unsigned int lvds_dither:1;
975 unsigned int lvds_vbt:1;
976 unsigned int int_crt_support:1;
977 unsigned int lvds_use_ssc:1;
978 unsigned int display_clock_mode:1;
979 unsigned int fdi_rx_polarity_inverted:1;
981 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
991 struct edp_power_seq pps;
993 bool no_aux_handshake;
996 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
997 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
998 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1000 unsigned int fsb_freq, mem_freq, is_ddr3;
1002 struct workqueue_struct *wq;
1004 /* Display functions */
1005 struct drm_i915_display_funcs display;
1007 /* PCH chipset type */
1008 enum intel_pch pch_type;
1009 unsigned short pch_id;
1011 unsigned long quirks;
1013 enum modeset_restore modeset_restore;
1014 struct mutex modeset_restore_lock;
1016 struct i915_gtt gtt;
1018 struct i915_gem_mm mm;
1020 /* Kernel Modesetting */
1022 struct sdvo_device_mapping sdvo_mappings[2];
1024 struct drm_crtc *plane_to_crtc_mapping[3];
1025 struct drm_crtc *pipe_to_crtc_mapping[3];
1026 wait_queue_head_t pending_flip_queue;
1028 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
1029 struct intel_ddi_plls ddi_plls;
1031 /* Reclocking support */
1032 bool render_reclock_avail;
1033 bool lvds_downclock_avail;
1034 /* indicates the reduced downclock for LVDS*/
1038 struct child_device_config *child_dev;
1040 bool mchbar_need_disable;
1042 struct intel_l3_parity l3_parity;
1044 /* gen6+ rps state */
1045 struct intel_gen6_power_mgmt rps;
1047 /* ilk-only ips/rps state. Everything in here is protected by the global
1048 * mchdev_lock in intel_pm.c */
1049 struct intel_ilk_power_mgmt ips;
1051 enum no_fbc_reason no_fbc_reason;
1053 struct drm_mm_node *compressed_fb;
1054 struct drm_mm_node *compressed_llb;
1056 struct i915_gpu_error gpu_error;
1058 /* list of fbdev register on this device */
1059 struct intel_fbdev *fbdev;
1062 * The console may be contended at resume, but we don't
1063 * want it to block on it.
1065 struct work_struct console_resume_work;
1067 struct drm_property *broadcast_rgb_property;
1068 struct drm_property *force_audio_property;
1070 bool hw_contexts_disabled;
1071 uint32_t hw_context_size;
1075 struct i915_suspend_saved_registers regfile;
1077 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1079 struct i915_dri1_state dri1;
1080 } drm_i915_private_t;
1082 /* Iterate over initialised rings */
1083 #define for_each_ring(ring__, dev_priv__, i__) \
1084 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1085 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1087 enum hdmi_force_audio {
1088 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1089 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1090 HDMI_AUDIO_AUTO, /* trust EDID */
1091 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1094 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1096 struct drm_i915_gem_object_ops {
1097 /* Interface between the GEM object and its backing storage.
1098 * get_pages() is called once prior to the use of the associated set
1099 * of pages before to binding them into the GTT, and put_pages() is
1100 * called after we no longer need them. As we expect there to be
1101 * associated cost with migrating pages between the backing storage
1102 * and making them available for the GPU (e.g. clflush), we may hold
1103 * onto the pages after they are no longer referenced by the GPU
1104 * in case they may be used again shortly (for example migrating the
1105 * pages to a different memory domain within the GTT). put_pages()
1106 * will therefore most likely be called when the object itself is
1107 * being released or under memory pressure (where we attempt to
1108 * reap pages for the shrinker).
1110 int (*get_pages)(struct drm_i915_gem_object *);
1111 void (*put_pages)(struct drm_i915_gem_object *);
1114 struct drm_i915_gem_object {
1115 struct drm_gem_object base;
1117 const struct drm_i915_gem_object_ops *ops;
1119 /** Current space allocated to this object in the GTT, if any. */
1120 struct drm_mm_node *gtt_space;
1121 /** Stolen memory for this object, instead of being backed by shmem. */
1122 struct drm_mm_node *stolen;
1123 struct list_head gtt_list;
1125 /** This object's place on the active/inactive lists */
1126 struct list_head ring_list;
1127 struct list_head mm_list;
1128 /** This object's place in the batchbuffer or on the eviction list */
1129 struct list_head exec_list;
1132 * This is set if the object is on the active lists (has pending
1133 * rendering and so a non-zero seqno), and is not set if it i s on
1134 * inactive (ready to be unbound) list.
1136 unsigned int active:1;
1139 * This is set if the object has been written to since last bound
1142 unsigned int dirty:1;
1145 * Fence register bits (if any) for this object. Will be set
1146 * as needed when mapped into the GTT.
1147 * Protected by dev->struct_mutex.
1149 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1152 * Advice: are the backing pages purgeable?
1154 unsigned int madv:2;
1157 * Current tiling mode for the object.
1159 unsigned int tiling_mode:2;
1161 * Whether the tiling parameters for the currently associated fence
1162 * register have changed. Note that for the purposes of tracking
1163 * tiling changes we also treat the unfenced register, the register
1164 * slot that the object occupies whilst it executes a fenced
1165 * command (such as BLT on gen2/3), as a "fence".
1167 unsigned int fence_dirty:1;
1169 /** How many users have pinned this object in GTT space. The following
1170 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1171 * (via user_pin_count), execbuffer (objects are not allowed multiple
1172 * times for the same batchbuffer), and the framebuffer code. When
1173 * switching/pageflipping, the framebuffer code has at most two buffers
1176 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1177 * bits with absolutely no headroom. So use 4 bits. */
1178 unsigned int pin_count:4;
1179 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1182 * Is the object at the current location in the gtt mappable and
1183 * fenceable? Used to avoid costly recalculations.
1185 unsigned int map_and_fenceable:1;
1188 * Whether the current gtt mapping needs to be mappable (and isn't just
1189 * mappable by accident). Track pin and fault separate for a more
1190 * accurate mappable working set.
1192 unsigned int fault_mappable:1;
1193 unsigned int pin_mappable:1;
1196 * Is the GPU currently using a fence to access this buffer,
1198 unsigned int pending_fenced_gpu_access:1;
1199 unsigned int fenced_gpu_access:1;
1201 unsigned int cache_level:2;
1203 unsigned int has_aliasing_ppgtt_mapping:1;
1204 unsigned int has_global_gtt_mapping:1;
1205 unsigned int has_dma_mapping:1;
1207 struct sg_table *pages;
1208 int pages_pin_count;
1210 /* prime dma-buf support */
1211 void *dma_buf_vmapping;
1215 * Used for performing relocations during execbuffer insertion.
1217 struct hlist_node exec_node;
1218 unsigned long exec_handle;
1219 struct drm_i915_gem_exec_object2 *exec_entry;
1222 * Current offset of the object in GTT space.
1224 * This is the same as gtt_space->start
1226 uint32_t gtt_offset;
1228 struct intel_ring_buffer *ring;
1230 /** Breadcrumb of last rendering to the buffer. */
1231 uint32_t last_read_seqno;
1232 uint32_t last_write_seqno;
1233 /** Breadcrumb of last fenced GPU access to the buffer. */
1234 uint32_t last_fenced_seqno;
1236 /** Current tiling stride for the object, if it's tiled. */
1239 /** Record of address bit 17 of each page at last unbind. */
1240 unsigned long *bit_17;
1242 /** User space pin count and filp owning the pin */
1243 uint32_t user_pin_count;
1244 struct drm_file *pin_filp;
1246 /** for phy allocated objects */
1247 struct drm_i915_gem_phys_object *phys_obj;
1249 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1251 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1254 * Request queue structure.
1256 * The request queue allows us to note sequence numbers that have been emitted
1257 * and may be associated with active buffers to be retired.
1259 * By keeping this list, we can avoid having to do questionable
1260 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1261 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1263 struct drm_i915_gem_request {
1264 /** On Which ring this request was generated */
1265 struct intel_ring_buffer *ring;
1267 /** GEM sequence number associated with this request. */
1270 /** Postion in the ringbuffer of the end of the request */
1273 /** Context related to this request */
1274 struct i915_hw_context *ctx;
1276 /** Time at which this request was emitted, in jiffies. */
1277 unsigned long emitted_jiffies;
1279 /** global list entry for this request */
1280 struct list_head list;
1282 struct drm_i915_file_private *file_priv;
1283 /** file_priv list entry for this request */
1284 struct list_head client_list;
1287 struct drm_i915_file_private {
1290 struct list_head request_list;
1292 struct idr context_idr;
1295 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1297 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1298 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1299 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1300 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1301 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1302 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1303 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1304 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1305 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1306 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1307 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1308 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1309 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1310 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1311 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1312 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1313 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1314 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1315 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1316 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1317 (dev)->pci_device == 0x0152 || \
1318 (dev)->pci_device == 0x015a)
1319 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1320 (dev)->pci_device == 0x0106 || \
1321 (dev)->pci_device == 0x010A)
1322 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1323 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1324 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1325 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1326 ((dev)->pci_device & 0xFF00) == 0x0A00)
1329 * The genX designation typically refers to the render engine, so render
1330 * capability related checks should use IS_GEN, while display and other checks
1331 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1334 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1335 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1336 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1337 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1338 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1339 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1341 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1342 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1343 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1344 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1346 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1347 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1349 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1350 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1352 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1353 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1355 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1356 * rows, which changed the alignment requirements and fence programming.
1358 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1360 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1361 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1362 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1363 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1364 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1365 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1366 /* dsparb controlled by hw only */
1367 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1369 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1370 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1371 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1373 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1375 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1376 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1377 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1379 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1380 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1381 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1382 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1383 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1384 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1386 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1387 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1388 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1389 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1390 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1391 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1393 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1395 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1397 #define GT_FREQUENCY_MULTIPLIER 50
1399 #include "i915_trace.h"
1402 * RC6 is a special power stage which allows the GPU to enter an very
1403 * low-voltage mode when idle, using down to 0V while at this stage. This
1404 * stage is entered automatically when the GPU is idle when RC6 support is
1405 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1407 * There are different RC6 modes available in Intel GPU, which differentiate
1408 * among each other with the latency required to enter and leave RC6 and
1409 * voltage consumed by the GPU in different states.
1411 * The combination of the following flags define which states GPU is allowed
1412 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1413 * RC6pp is deepest RC6. Their support by hardware varies according to the
1414 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1415 * which brings the most power savings; deeper states save more power, but
1416 * require higher latency to switch to and wake up.
1418 #define INTEL_RC6_ENABLE (1<<0)
1419 #define INTEL_RC6p_ENABLE (1<<1)
1420 #define INTEL_RC6pp_ENABLE (1<<2)
1422 extern struct drm_ioctl_desc i915_ioctls[];
1423 extern int i915_max_ioctl;
1424 extern unsigned int i915_fbpercrtc __always_unused;
1425 extern int i915_panel_ignore_lid __read_mostly;
1426 extern unsigned int i915_powersave __read_mostly;
1427 extern int i915_semaphores __read_mostly;
1428 extern unsigned int i915_lvds_downclock __read_mostly;
1429 extern int i915_lvds_channel_mode __read_mostly;
1430 extern int i915_panel_use_ssc __read_mostly;
1431 extern int i915_vbt_sdvo_panel_type __read_mostly;
1432 extern int i915_enable_rc6 __read_mostly;
1433 extern int i915_enable_fbc __read_mostly;
1434 extern bool i915_enable_hangcheck __read_mostly;
1435 extern int i915_enable_ppgtt __read_mostly;
1436 extern unsigned int i915_preliminary_hw_support __read_mostly;
1437 extern int i915_disable_power_well __read_mostly;
1439 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1440 extern int i915_resume(struct drm_device *dev);
1441 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1442 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1445 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1446 extern void i915_kernel_lost_context(struct drm_device * dev);
1447 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1448 extern int i915_driver_unload(struct drm_device *);
1449 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1450 extern void i915_driver_lastclose(struct drm_device * dev);
1451 extern void i915_driver_preclose(struct drm_device *dev,
1452 struct drm_file *file_priv);
1453 extern void i915_driver_postclose(struct drm_device *dev,
1454 struct drm_file *file_priv);
1455 extern int i915_driver_device_is_agp(struct drm_device * dev);
1456 #ifdef CONFIG_COMPAT
1457 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1460 extern int i915_emit_box(struct drm_device *dev,
1461 struct drm_clip_rect *box,
1463 extern int intel_gpu_reset(struct drm_device *dev);
1464 extern int i915_reset(struct drm_device *dev);
1465 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1466 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1467 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1468 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1470 extern void intel_console_resume(struct work_struct *work);
1473 void i915_hangcheck_elapsed(unsigned long data);
1474 void i915_handle_error(struct drm_device *dev, bool wedged);
1476 extern void intel_irq_init(struct drm_device *dev);
1477 extern void intel_hpd_init(struct drm_device *dev);
1478 extern void intel_gt_init(struct drm_device *dev);
1479 extern void intel_gt_reset(struct drm_device *dev);
1481 void i915_error_state_free(struct kref *error_ref);
1484 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1487 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1489 #ifdef CONFIG_DEBUG_FS
1490 extern void i915_destroy_error_state(struct drm_device *dev);
1492 #define i915_destroy_error_state(x)
1497 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1498 struct drm_file *file_priv);
1499 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file_priv);
1501 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1502 struct drm_file *file_priv);
1503 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1504 struct drm_file *file_priv);
1505 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1506 struct drm_file *file_priv);
1507 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1508 struct drm_file *file_priv);
1509 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1510 struct drm_file *file_priv);
1511 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *file_priv);
1513 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1514 struct drm_file *file_priv);
1515 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1516 struct drm_file *file_priv);
1517 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
1519 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1520 struct drm_file *file_priv);
1521 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *file_priv);
1523 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1524 struct drm_file *file);
1525 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1526 struct drm_file *file);
1527 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1528 struct drm_file *file_priv);
1529 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1530 struct drm_file *file_priv);
1531 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file_priv);
1533 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1534 struct drm_file *file_priv);
1535 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1536 struct drm_file *file_priv);
1537 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1538 struct drm_file *file_priv);
1539 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1540 struct drm_file *file_priv);
1541 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1542 struct drm_file *file_priv);
1543 void i915_gem_load(struct drm_device *dev);
1544 void *i915_gem_object_alloc(struct drm_device *dev);
1545 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1546 int i915_gem_init_object(struct drm_gem_object *obj);
1547 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1548 const struct drm_i915_gem_object_ops *ops);
1549 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1551 void i915_gem_free_object(struct drm_gem_object *obj);
1553 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1555 bool map_and_fenceable,
1557 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1558 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1559 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1560 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1561 void i915_gem_lastclose(struct drm_device *dev);
1563 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1564 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1566 struct sg_page_iter sg_iter;
1568 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1569 return sg_page_iter_page(&sg_iter);
1573 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1575 BUG_ON(obj->pages == NULL);
1576 obj->pages_pin_count++;
1578 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1580 BUG_ON(obj->pages_pin_count == 0);
1581 obj->pages_pin_count--;
1584 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1585 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1586 struct intel_ring_buffer *to);
1587 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1588 struct intel_ring_buffer *ring);
1590 int i915_gem_dumb_create(struct drm_file *file_priv,
1591 struct drm_device *dev,
1592 struct drm_mode_create_dumb *args);
1593 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1594 uint32_t handle, uint64_t *offset);
1595 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1598 * Returns true if seq1 is later than seq2.
1601 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1603 return (int32_t)(seq1 - seq2) >= 0;
1606 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1607 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1608 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1609 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1612 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1614 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1615 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1616 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1623 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1625 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1626 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1627 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1631 void i915_gem_retire_requests(struct drm_device *dev);
1632 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1633 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1634 bool interruptible);
1635 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1637 return unlikely(atomic_read(&error->reset_counter)
1638 & I915_RESET_IN_PROGRESS_FLAG);
1641 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1643 return atomic_read(&error->reset_counter) == I915_WEDGED;
1646 void i915_gem_reset(struct drm_device *dev);
1647 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1648 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1649 uint32_t read_domains,
1650 uint32_t write_domain);
1651 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1652 int __must_check i915_gem_init(struct drm_device *dev);
1653 int __must_check i915_gem_init_hw(struct drm_device *dev);
1654 void i915_gem_l3_remap(struct drm_device *dev);
1655 void i915_gem_init_swizzling(struct drm_device *dev);
1656 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1657 int __must_check i915_gpu_idle(struct drm_device *dev);
1658 int __must_check i915_gem_idle(struct drm_device *dev);
1659 int i915_add_request(struct intel_ring_buffer *ring,
1660 struct drm_file *file,
1662 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1664 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1666 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1669 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1671 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1673 struct intel_ring_buffer *pipelined);
1674 int i915_gem_attach_phys_object(struct drm_device *dev,
1675 struct drm_i915_gem_object *obj,
1678 void i915_gem_detach_phys_object(struct drm_device *dev,
1679 struct drm_i915_gem_object *obj);
1680 void i915_gem_free_all_phys_object(struct drm_device *dev);
1681 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1684 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1686 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1687 int tiling_mode, bool fenced);
1689 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1690 enum i915_cache_level cache_level);
1692 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1693 struct dma_buf *dma_buf);
1695 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1696 struct drm_gem_object *gem_obj, int flags);
1698 /* i915_gem_context.c */
1699 void i915_gem_context_init(struct drm_device *dev);
1700 void i915_gem_context_fini(struct drm_device *dev);
1701 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1702 int i915_switch_context(struct intel_ring_buffer *ring,
1703 struct drm_file *file, int to_id);
1704 void i915_gem_context_free(struct kref *ctx_ref);
1705 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1707 kref_get(&ctx->ref);
1710 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1712 kref_put(&ctx->ref, i915_gem_context_free);
1715 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1716 struct drm_file *file);
1717 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1718 struct drm_file *file);
1720 /* i915_gem_gtt.c */
1721 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1722 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1723 struct drm_i915_gem_object *obj,
1724 enum i915_cache_level cache_level);
1725 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1726 struct drm_i915_gem_object *obj);
1728 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1729 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1730 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1731 enum i915_cache_level cache_level);
1732 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1733 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1734 void i915_gem_init_global_gtt(struct drm_device *dev);
1735 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1736 unsigned long mappable_end, unsigned long end);
1737 int i915_gem_gtt_init(struct drm_device *dev);
1738 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1740 if (INTEL_INFO(dev)->gen < 6)
1741 intel_gtt_chipset_flush();
1745 /* i915_gem_evict.c */
1746 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1748 unsigned cache_level,
1751 int i915_gem_evict_everything(struct drm_device *dev);
1753 /* i915_gem_stolen.c */
1754 int i915_gem_init_stolen(struct drm_device *dev);
1755 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1756 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1757 void i915_gem_cleanup_stolen(struct drm_device *dev);
1758 struct drm_i915_gem_object *
1759 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1760 struct drm_i915_gem_object *
1761 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1765 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1767 /* i915_gem_tiling.c */
1768 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1770 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1772 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1773 obj->tiling_mode != I915_TILING_NONE;
1776 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1777 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1778 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1780 /* i915_gem_debug.c */
1781 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1782 const char *where, uint32_t mark);
1784 int i915_verify_lists(struct drm_device *dev);
1786 #define i915_verify_lists(dev) 0
1788 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1790 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1791 const char *where, uint32_t mark);
1793 /* i915_debugfs.c */
1794 int i915_debugfs_init(struct drm_minor *minor);
1795 void i915_debugfs_cleanup(struct drm_minor *minor);
1797 /* i915_suspend.c */
1798 extern int i915_save_state(struct drm_device *dev);
1799 extern int i915_restore_state(struct drm_device *dev);
1802 void i915_save_display_reg(struct drm_device *dev);
1803 void i915_restore_display_reg(struct drm_device *dev);
1806 void i915_setup_sysfs(struct drm_device *dev_priv);
1807 void i915_teardown_sysfs(struct drm_device *dev_priv);
1810 extern int intel_setup_gmbus(struct drm_device *dev);
1811 extern void intel_teardown_gmbus(struct drm_device *dev);
1812 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1814 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1817 extern struct i2c_adapter *intel_gmbus_get_adapter(
1818 struct drm_i915_private *dev_priv, unsigned port);
1819 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1820 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1821 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1823 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1825 extern void intel_i2c_reset(struct drm_device *dev);
1827 /* intel_opregion.c */
1828 extern int intel_opregion_setup(struct drm_device *dev);
1830 extern void intel_opregion_init(struct drm_device *dev);
1831 extern void intel_opregion_fini(struct drm_device *dev);
1832 extern void intel_opregion_asle_intr(struct drm_device *dev);
1834 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1835 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1836 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1841 extern void intel_register_dsm_handler(void);
1842 extern void intel_unregister_dsm_handler(void);
1844 static inline void intel_register_dsm_handler(void) { return; }
1845 static inline void intel_unregister_dsm_handler(void) { return; }
1846 #endif /* CONFIG_ACPI */
1849 extern void intel_modeset_init_hw(struct drm_device *dev);
1850 extern void intel_modeset_init(struct drm_device *dev);
1851 extern void intel_modeset_gem_init(struct drm_device *dev);
1852 extern void intel_modeset_cleanup(struct drm_device *dev);
1853 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1854 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1855 bool force_restore);
1856 extern void i915_redisable_vga(struct drm_device *dev);
1857 extern bool intel_fbc_enabled(struct drm_device *dev);
1858 extern void intel_disable_fbc(struct drm_device *dev);
1859 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1860 extern void intel_init_pch_refclk(struct drm_device *dev);
1861 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1862 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1863 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1864 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
1865 extern void intel_detect_pch(struct drm_device *dev);
1866 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1867 extern int intel_enable_rc6(const struct drm_device *dev);
1869 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1870 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1871 struct drm_file *file);
1874 #ifdef CONFIG_DEBUG_FS
1875 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1876 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1878 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1879 extern void intel_display_print_error_state(struct seq_file *m,
1880 struct drm_device *dev,
1881 struct intel_display_error_state *error);
1884 /* On SNB platform, before reading ring registers forcewake bit
1885 * must be set to prevent GT core from power down and stale values being
1888 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1889 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1890 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1892 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1893 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1894 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1895 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1896 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1898 int vlv_gpu_freq(int ddr_freq, int val);
1899 int vlv_freq_opcode(int ddr_freq, int val);
1901 #define __i915_read(x, y) \
1902 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1910 #define __i915_write(x, y) \
1911 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1919 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1920 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1922 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1923 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1924 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1925 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1927 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1928 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1929 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1930 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1932 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1933 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1935 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1936 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1938 /* "Broadcast RGB" property */
1939 #define INTEL_BROADCAST_RGB_AUTO 0
1940 #define INTEL_BROADCAST_RGB_FULL 1
1941 #define INTEL_BROADCAST_RGB_LIMITED 2
1943 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1945 if (HAS_PCH_SPLIT(dev))
1946 return CPU_VGACNTRL;
1947 else if (IS_VALLEYVIEW(dev))
1948 return VLV_VGACNTRL;
1953 static inline void __user *to_user_ptr(u64 address)
1955 return (void __user *)(uintptr_t)address;