1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 I915_MAX_PIPES = _PIPE_EDP
64 #define pipe_name(p) ((p) + 'A')
73 #define transcoder_name(t) ((t) + 'A')
80 #define plane_name(p) ((p) + 'A')
82 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
92 #define port_name(p) ((p) + 'A')
94 #define I915_NUM_PHYS_VLV 1
106 enum intel_display_power_domain {
110 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
111 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
113 POWER_DOMAIN_TRANSCODER_A,
114 POWER_DOMAIN_TRANSCODER_B,
115 POWER_DOMAIN_TRANSCODER_C,
116 POWER_DOMAIN_TRANSCODER_EDP,
117 POWER_DOMAIN_PORT_DDI_A_2_LANES,
118 POWER_DOMAIN_PORT_DDI_A_4_LANES,
119 POWER_DOMAIN_PORT_DDI_B_2_LANES,
120 POWER_DOMAIN_PORT_DDI_B_4_LANES,
121 POWER_DOMAIN_PORT_DDI_C_2_LANES,
122 POWER_DOMAIN_PORT_DDI_C_4_LANES,
123 POWER_DOMAIN_PORT_DDI_D_2_LANES,
124 POWER_DOMAIN_PORT_DDI_D_4_LANES,
125 POWER_DOMAIN_PORT_DSI,
126 POWER_DOMAIN_PORT_CRT,
127 POWER_DOMAIN_PORT_OTHER,
135 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
136 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
137 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
138 #define POWER_DOMAIN_TRANSCODER(tran) \
139 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
140 (tran) + POWER_DOMAIN_TRANSCODER_A)
144 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
145 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
155 #define I915_GEM_GPU_DOMAINS \
156 (I915_GEM_DOMAIN_RENDER | \
157 I915_GEM_DOMAIN_SAMPLER | \
158 I915_GEM_DOMAIN_COMMAND | \
159 I915_GEM_DOMAIN_INSTRUCTION | \
160 I915_GEM_DOMAIN_VERTEX)
162 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
163 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
165 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
166 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
167 if ((intel_encoder)->base.crtc == (__crtc))
169 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
170 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
171 if ((intel_connector)->base.encoder == (__encoder))
173 struct drm_i915_private;
176 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
177 /* real shared dpll ids must be >= 0 */
181 #define I915_NUM_PLLS 2
183 struct intel_dpll_hw_state {
190 struct intel_shared_dpll {
191 int refcount; /* count of number of CRTCs sharing this PLL */
192 int active; /* count of number of active CRTCs (i.e. DPMS on) */
193 bool on; /* is the PLL actually active? Disabled during modeset */
195 /* should match the index in the dev_priv->shared_dplls array */
196 enum intel_dpll_id id;
197 struct intel_dpll_hw_state hw_state;
198 void (*mode_set)(struct drm_i915_private *dev_priv,
199 struct intel_shared_dpll *pll);
200 void (*enable)(struct drm_i915_private *dev_priv,
201 struct intel_shared_dpll *pll);
202 void (*disable)(struct drm_i915_private *dev_priv,
203 struct intel_shared_dpll *pll);
204 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
205 struct intel_shared_dpll *pll,
206 struct intel_dpll_hw_state *hw_state);
209 /* Used by dp and fdi links */
210 struct intel_link_m_n {
218 void intel_link_compute_m_n(int bpp, int nlanes,
219 int pixel_clock, int link_clock,
220 struct intel_link_m_n *m_n);
222 struct intel_ddi_plls {
228 /* Interface history:
231 * 1.2: Add Power Management
232 * 1.3: Add vblank support
233 * 1.4: Fix cmdbuffer path, add heap destroy
234 * 1.5: Add vblank pipe configuration
235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
236 * - Support vertical blank on secondary display pipe
238 #define DRIVER_MAJOR 1
239 #define DRIVER_MINOR 6
240 #define DRIVER_PATCHLEVEL 0
242 #define WATCH_LISTS 0
245 #define I915_GEM_PHYS_CURSOR_0 1
246 #define I915_GEM_PHYS_CURSOR_1 2
247 #define I915_GEM_PHYS_OVERLAY_REGS 3
248 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
250 struct drm_i915_gem_phys_object {
252 struct page **page_list;
253 drm_dma_handle_t *handle;
254 struct drm_i915_gem_object *cur_obj;
257 struct opregion_header;
258 struct opregion_acpi;
259 struct opregion_swsci;
260 struct opregion_asle;
262 struct intel_opregion {
263 struct opregion_header __iomem *header;
264 struct opregion_acpi __iomem *acpi;
265 struct opregion_swsci __iomem *swsci;
266 u32 swsci_gbda_sub_functions;
267 u32 swsci_sbcb_sub_functions;
268 struct opregion_asle __iomem *asle;
270 u32 __iomem *lid_state;
271 struct work_struct asle_work;
273 #define OPREGION_SIZE (8*1024)
275 struct intel_overlay;
276 struct intel_overlay_error_state;
278 struct drm_i915_master_private {
279 drm_local_map_t *sarea;
280 struct _drm_i915_sarea *sarea_priv;
282 #define I915_FENCE_REG_NONE -1
283 #define I915_MAX_NUM_FENCES 32
284 /* 32 fences + sign bit for FENCE_REG_NONE */
285 #define I915_MAX_NUM_FENCE_BITS 6
287 struct drm_i915_fence_reg {
288 struct list_head lru_list;
289 struct drm_i915_gem_object *obj;
293 struct sdvo_device_mapping {
302 struct intel_display_error_state;
304 struct drm_i915_error_state {
312 /* Generic register state */
319 u32 error; /* gen6+ */
320 u32 err_int; /* gen7 */
326 u32 extra_instdone[I915_NUM_INSTDONE_REG];
327 u32 pipestat[I915_MAX_PIPES];
328 u64 fence[I915_MAX_NUM_FENCES];
329 struct intel_overlay_error_state *overlay;
330 struct intel_display_error_state *display;
332 struct drm_i915_error_ring {
334 /* Software tracked state */
337 enum intel_ring_hangcheck_action hangcheck_action;
340 /* our own tracking of ring head and tail */
344 u32 semaphore_seqno[I915_NUM_RINGS - 1];
362 u32 rc_psmi; /* sleep state */
363 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
365 struct drm_i915_error_object {
369 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
371 struct drm_i915_error_request {
386 char comm[TASK_COMM_LEN];
387 } ring[I915_NUM_RINGS];
388 struct drm_i915_error_buffer {
395 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
402 } **active_bo, **pinned_bo;
404 u32 *active_bo_count, *pinned_bo_count;
407 struct intel_connector;
408 struct intel_crtc_config;
413 struct drm_i915_display_funcs {
414 bool (*fbc_enabled)(struct drm_device *dev);
415 void (*enable_fbc)(struct drm_crtc *crtc);
416 void (*disable_fbc)(struct drm_device *dev);
417 int (*get_display_clock_speed)(struct drm_device *dev);
418 int (*get_fifo_size)(struct drm_device *dev, int plane);
420 * find_dpll() - Find the best values for the PLL
421 * @limit: limits for the PLL
422 * @crtc: current CRTC
423 * @target: target frequency in kHz
424 * @refclk: reference clock frequency in kHz
425 * @match_clock: if provided, @best_clock P divider must
426 * match the P divider from @match_clock
427 * used for LVDS downclocking
428 * @best_clock: best PLL values found
430 * Returns true on success, false on failure.
432 bool (*find_dpll)(const struct intel_limit *limit,
433 struct drm_crtc *crtc,
434 int target, int refclk,
435 struct dpll *match_clock,
436 struct dpll *best_clock);
437 void (*update_wm)(struct drm_crtc *crtc);
438 void (*update_sprite_wm)(struct drm_plane *plane,
439 struct drm_crtc *crtc,
440 uint32_t sprite_width, int pixel_size,
441 bool enable, bool scaled);
442 void (*modeset_global_resources)(struct drm_device *dev);
443 /* Returns the active state of the crtc, and if the crtc is active,
444 * fills out the pipe-config with the hw state. */
445 bool (*get_pipe_config)(struct intel_crtc *,
446 struct intel_crtc_config *);
447 int (*crtc_mode_set)(struct drm_crtc *crtc,
449 struct drm_framebuffer *old_fb);
450 void (*crtc_enable)(struct drm_crtc *crtc);
451 void (*crtc_disable)(struct drm_crtc *crtc);
452 void (*off)(struct drm_crtc *crtc);
453 void (*write_eld)(struct drm_connector *connector,
454 struct drm_crtc *crtc,
455 struct drm_display_mode *mode);
456 void (*fdi_link_train)(struct drm_crtc *crtc);
457 void (*init_clock_gating)(struct drm_device *dev);
458 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
459 struct drm_framebuffer *fb,
460 struct drm_i915_gem_object *obj,
462 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
464 void (*hpd_irq_setup)(struct drm_device *dev);
465 /* clock updates for mode set */
467 /* render clock increase/decrease */
468 /* display clock increase/decrease */
469 /* pll clock increase/decrease */
471 int (*setup_backlight)(struct intel_connector *connector);
472 uint32_t (*get_backlight)(struct intel_connector *connector);
473 void (*set_backlight)(struct intel_connector *connector,
475 void (*disable_backlight)(struct intel_connector *connector);
476 void (*enable_backlight)(struct intel_connector *connector);
479 struct intel_uncore_funcs {
480 void (*force_wake_get)(struct drm_i915_private *dev_priv,
482 void (*force_wake_put)(struct drm_i915_private *dev_priv,
485 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
486 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
487 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
488 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
490 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
491 uint8_t val, bool trace);
492 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
493 uint16_t val, bool trace);
494 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
495 uint32_t val, bool trace);
496 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
497 uint64_t val, bool trace);
500 struct intel_uncore {
501 spinlock_t lock; /** lock is also taken in irq contexts. */
503 struct intel_uncore_funcs funcs;
506 unsigned forcewake_count;
508 unsigned fw_rendercount;
509 unsigned fw_mediacount;
511 struct timer_list force_wake_timer;
514 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
515 func(is_mobile) sep \
518 func(is_i945gm) sep \
520 func(need_gfx_hws) sep \
522 func(is_pineview) sep \
523 func(is_broadwater) sep \
524 func(is_crestline) sep \
525 func(is_ivybridge) sep \
526 func(is_valleyview) sep \
527 func(is_haswell) sep \
528 func(is_preliminary) sep \
530 func(has_pipe_cxsr) sep \
531 func(has_hotplug) sep \
532 func(cursor_needs_physical) sep \
533 func(has_overlay) sep \
534 func(overlay_needs_physical) sep \
535 func(supports_tv) sep \
540 #define DEFINE_FLAG(name) u8 name:1
541 #define SEP_SEMICOLON ;
543 struct intel_device_info {
544 u32 display_mmio_offset;
546 u8 num_sprites[I915_MAX_PIPES];
548 u8 ring_mask; /* Rings supported by the HW */
549 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
550 /* Register offsets for the various display pipes and transcoders */
551 int pipe_offsets[I915_MAX_TRANSCODERS];
552 int trans_offsets[I915_MAX_TRANSCODERS];
553 int dpll_offsets[I915_MAX_PIPES];
554 int dpll_md_offsets[I915_MAX_PIPES];
555 int palette_offsets[I915_MAX_PIPES];
561 enum i915_cache_level {
563 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
564 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
565 caches, eg sampler/render caches, and the
566 large Last-Level-Cache. LLC is coherent with
567 the CPU, but L3 is only visible to the GPU. */
568 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
571 typedef uint32_t gen6_gtt_pte_t;
574 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
575 * VMA's presence cannot be guaranteed before binding, or after unbinding the
576 * object into/from the address space.
578 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
579 * will always be <= an objects lifetime. So object refcounting should cover us.
582 struct drm_mm_node node;
583 struct drm_i915_gem_object *obj;
584 struct i915_address_space *vm;
586 /** This object's place on the active/inactive lists */
587 struct list_head mm_list;
589 struct list_head vma_link; /* Link in the object's VMA list */
591 /** This vma's place in the batchbuffer or on the eviction list */
592 struct list_head exec_list;
595 * Used for performing relocations during execbuffer insertion.
597 struct hlist_node exec_node;
598 unsigned long exec_handle;
599 struct drm_i915_gem_exec_object2 *exec_entry;
602 * How many users have pinned this object in GTT space. The following
603 * users can each hold at most one reference: pwrite/pread, pin_ioctl
604 * (via user_pin_count), execbuffer (objects are not allowed multiple
605 * times for the same batchbuffer), and the framebuffer code. When
606 * switching/pageflipping, the framebuffer code has at most two buffers
609 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
610 * bits with absolutely no headroom. So use 4 bits. */
611 unsigned int pin_count:4;
612 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
614 /** Unmap an object from an address space. This usually consists of
615 * setting the valid PTE entries to a reserved scratch page. */
616 void (*unbind_vma)(struct i915_vma *vma);
617 /* Map an object into an address space with the given cache flags. */
618 #define GLOBAL_BIND (1<<0)
619 void (*bind_vma)(struct i915_vma *vma,
620 enum i915_cache_level cache_level,
624 struct i915_address_space {
626 struct drm_device *dev;
627 struct list_head global_link;
628 unsigned long start; /* Start offset always 0 for dri2 */
629 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
637 * List of objects currently involved in rendering.
639 * Includes buffers having the contents of their GPU caches
640 * flushed, not necessarily primitives. last_rendering_seqno
641 * represents when the rendering involved will be completed.
643 * A reference is held on the buffer while on this list.
645 struct list_head active_list;
648 * LRU list of objects which are not in the ringbuffer and
649 * are ready to unbind, but are still in the GTT.
651 * last_rendering_seqno is 0 while an object is in this list.
653 * A reference is not held on the buffer while on this list,
654 * as merely being GTT-bound shouldn't prevent its being
655 * freed, and we'll pull it off the list in the free path.
657 struct list_head inactive_list;
659 /* FIXME: Need a more generic return type */
660 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
661 enum i915_cache_level level,
662 bool valid); /* Create a valid PTE */
663 void (*clear_range)(struct i915_address_space *vm,
667 void (*insert_entries)(struct i915_address_space *vm,
670 enum i915_cache_level cache_level);
671 void (*cleanup)(struct i915_address_space *vm);
674 /* The Graphics Translation Table is the way in which GEN hardware translates a
675 * Graphics Virtual Address into a Physical Address. In addition to the normal
676 * collateral associated with any va->pa translations GEN hardware also has a
677 * portion of the GTT which can be mapped by the CPU and remain both coherent
678 * and correct (in cases like swizzling). That region is referred to as GMADR in
682 struct i915_address_space base;
683 size_t stolen_size; /* Total size of stolen memory */
685 unsigned long mappable_end; /* End offset that we can CPU map */
686 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
687 phys_addr_t mappable_base; /* PA of our GMADR */
689 /** "Graphics Stolen Memory" holds the global PTEs */
697 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
698 size_t *stolen, phys_addr_t *mappable_base,
699 unsigned long *mappable_end);
701 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
703 #define GEN8_LEGACY_PDPS 4
704 struct i915_hw_ppgtt {
705 struct i915_address_space base;
707 struct drm_mm_node node;
708 unsigned num_pd_entries;
709 unsigned num_pd_pages; /* gen8+ */
711 struct page **pt_pages;
712 struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
714 struct page *pd_pages;
717 dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
720 dma_addr_t *pt_dma_addr;
721 dma_addr_t *gen8_pt_dma_addr[4];
724 int (*enable)(struct i915_hw_ppgtt *ppgtt);
725 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
726 struct intel_ring_buffer *ring,
728 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
731 struct i915_ctx_hang_stats {
732 /* This context had batch pending when hang was declared */
733 unsigned batch_pending;
735 /* This context had batch active when hang was declared */
736 unsigned batch_active;
738 /* Time when this context was last blamed for a GPU reset */
739 unsigned long guilty_ts;
741 /* This context is banned to submit more work */
745 /* This must match up with the value previously used for execbuf2.rsvd1. */
746 #define DEFAULT_CONTEXT_ID 0
747 struct i915_hw_context {
752 struct drm_i915_file_private *file_priv;
753 struct intel_ring_buffer *last_ring;
754 struct drm_i915_gem_object *obj;
755 struct i915_ctx_hang_stats hang_stats;
756 struct i915_address_space *vm;
758 struct list_head link;
767 struct drm_mm_node *compressed_fb;
768 struct drm_mm_node *compressed_llb;
770 struct intel_fbc_work {
771 struct delayed_work work;
772 struct drm_crtc *crtc;
773 struct drm_framebuffer *fb;
777 FBC_OK, /* FBC is enabled */
778 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
779 FBC_NO_OUTPUT, /* no outputs enabled to compress */
780 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
781 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
782 FBC_MODE_TOO_LARGE, /* mode too large for compression */
783 FBC_BAD_PLANE, /* fbc not supported on plane */
784 FBC_NOT_TILED, /* buffer not tiled */
785 FBC_MULTIPLE_PIPES, /* more than one pipe active */
787 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
797 PCH_NONE = 0, /* No PCH present */
798 PCH_IBX, /* Ibexpeak PCH */
799 PCH_CPT, /* Cougarpoint PCH */
800 PCH_LPT, /* Lynxpoint PCH */
804 enum intel_sbi_destination {
809 #define QUIRK_PIPEA_FORCE (1<<0)
810 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
811 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
814 struct intel_fbc_work;
817 struct i2c_adapter adapter;
821 struct i2c_algo_bit_data bit_algo;
822 struct drm_i915_private *dev_priv;
825 struct i915_suspend_saved_registers {
846 u32 saveTRANS_HTOTAL_A;
847 u32 saveTRANS_HBLANK_A;
848 u32 saveTRANS_HSYNC_A;
849 u32 saveTRANS_VTOTAL_A;
850 u32 saveTRANS_VBLANK_A;
851 u32 saveTRANS_VSYNC_A;
859 u32 savePFIT_PGM_RATIOS;
860 u32 saveBLC_HIST_CTL;
862 u32 saveBLC_PWM_CTL2;
863 u32 saveBLC_HIST_CTL_B;
864 u32 saveBLC_CPU_PWM_CTL;
865 u32 saveBLC_CPU_PWM_CTL2;
878 u32 saveTRANS_HTOTAL_B;
879 u32 saveTRANS_HBLANK_B;
880 u32 saveTRANS_HSYNC_B;
881 u32 saveTRANS_VTOTAL_B;
882 u32 saveTRANS_VBLANK_B;
883 u32 saveTRANS_VSYNC_B;
897 u32 savePP_ON_DELAYS;
898 u32 savePP_OFF_DELAYS;
906 u32 savePFIT_CONTROL;
907 u32 save_palette_a[256];
908 u32 save_palette_b[256];
919 u32 saveCACHE_MODE_0;
920 u32 saveMI_ARB_STATE;
931 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
942 u32 savePIPEA_GMCH_DATA_M;
943 u32 savePIPEB_GMCH_DATA_M;
944 u32 savePIPEA_GMCH_DATA_N;
945 u32 savePIPEB_GMCH_DATA_N;
946 u32 savePIPEA_DP_LINK_M;
947 u32 savePIPEB_DP_LINK_M;
948 u32 savePIPEA_DP_LINK_N;
949 u32 savePIPEB_DP_LINK_N;
960 u32 savePCH_DREF_CONTROL;
961 u32 saveDISP_ARB_CTL;
962 u32 savePIPEA_DATA_M1;
963 u32 savePIPEA_DATA_N1;
964 u32 savePIPEA_LINK_M1;
965 u32 savePIPEA_LINK_N1;
966 u32 savePIPEB_DATA_M1;
967 u32 savePIPEB_DATA_N1;
968 u32 savePIPEB_LINK_M1;
969 u32 savePIPEB_LINK_N1;
970 u32 saveMCHBAR_RENDER_STANDBY;
971 u32 savePCH_PORT_HOTPLUG;
974 struct intel_gen6_power_mgmt {
975 /* work and pm_iir are protected by dev_priv->irq_lock */
976 struct work_struct work;
991 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
994 struct delayed_work delayed_resume_work;
997 * Protects RPS/RC6 register access and PCU communication.
998 * Must be taken after struct_mutex if nested.
1000 struct mutex hw_lock;
1003 /* defined intel_pm.c */
1004 extern spinlock_t mchdev_lock;
1006 struct intel_ilk_power_mgmt {
1014 unsigned long last_time1;
1015 unsigned long chipset_power;
1017 struct timespec last_time2;
1018 unsigned long gfx_power;
1024 struct drm_i915_gem_object *pwrctx;
1025 struct drm_i915_gem_object *renderctx;
1028 struct drm_i915_private;
1029 struct i915_power_well;
1031 struct i915_power_well_ops {
1033 * Synchronize the well's hw state to match the current sw state, for
1034 * example enable/disable it based on the current refcount. Called
1035 * during driver init and resume time, possibly after first calling
1036 * the enable/disable handlers.
1038 void (*sync_hw)(struct drm_i915_private *dev_priv,
1039 struct i915_power_well *power_well);
1041 * Enable the well and resources that depend on it (for example
1042 * interrupts located on the well). Called after the 0->1 refcount
1045 void (*enable)(struct drm_i915_private *dev_priv,
1046 struct i915_power_well *power_well);
1048 * Disable the well and resources that depend on it. Called after
1049 * the 1->0 refcount transition.
1051 void (*disable)(struct drm_i915_private *dev_priv,
1052 struct i915_power_well *power_well);
1053 /* Returns the hw enabled state. */
1054 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1055 struct i915_power_well *power_well);
1058 /* Power well structure for haswell */
1059 struct i915_power_well {
1062 /* power well enable/disable usage count */
1064 unsigned long domains;
1066 const struct i915_power_well_ops *ops;
1069 struct i915_power_domains {
1071 * Power wells needed for initialization at driver init and suspend
1072 * time are on. They are kept on until after the first modeset.
1075 int power_well_count;
1078 int domain_use_count[POWER_DOMAIN_NUM];
1079 struct i915_power_well *power_wells;
1082 struct i915_dri1_state {
1083 unsigned allow_batchbuffer : 1;
1084 u32 __iomem *gfx_hws_cpu_addr;
1095 struct i915_ums_state {
1097 * Flag if the X Server, and thus DRM, is not currently in
1098 * control of the device.
1100 * This is set between LeaveVT and EnterVT. It needs to be
1101 * replaced with a semaphore. It also needs to be
1102 * transitioned away from for kernel modesetting.
1107 #define MAX_L3_SLICES 2
1108 struct intel_l3_parity {
1109 u32 *remap_info[MAX_L3_SLICES];
1110 struct work_struct error_work;
1114 struct i915_gem_mm {
1115 /** Memory allocator for GTT stolen memory */
1116 struct drm_mm stolen;
1117 /** List of all objects in gtt_space. Used to restore gtt
1118 * mappings on resume */
1119 struct list_head bound_list;
1121 * List of objects which are not bound to the GTT (thus
1122 * are idle and not used by the GPU) but still have
1123 * (presumably uncached) pages still attached.
1125 struct list_head unbound_list;
1127 /** Usable portion of the GTT for GEM */
1128 unsigned long stolen_base; /* limited to low memory (32-bit) */
1130 /** PPGTT used for aliasing the PPGTT with the GTT */
1131 struct i915_hw_ppgtt *aliasing_ppgtt;
1133 struct shrinker inactive_shrinker;
1134 bool shrinker_no_lock_stealing;
1136 /** LRU list of objects with fence regs on them. */
1137 struct list_head fence_list;
1140 * We leave the user IRQ off as much as possible,
1141 * but this means that requests will finish and never
1142 * be retired once the system goes idle. Set a timer to
1143 * fire periodically while the ring is running. When it
1144 * fires, go retire requests.
1146 struct delayed_work retire_work;
1149 * When we detect an idle GPU, we want to turn on
1150 * powersaving features. So once we see that there
1151 * are no more requests outstanding and no more
1152 * arrive within a small period of time, we fire
1153 * off the idle_work.
1155 struct delayed_work idle_work;
1158 * Are we in a non-interruptible section of code like
1164 * Is the GPU currently considered idle, or busy executing userspace
1165 * requests? Whilst idle, we attempt to power down the hardware and
1166 * display clocks. In order to reduce the effect on performance, there
1167 * is a slight delay before we do so.
1171 /** Bit 6 swizzling required for X tiling */
1172 uint32_t bit_6_swizzle_x;
1173 /** Bit 6 swizzling required for Y tiling */
1174 uint32_t bit_6_swizzle_y;
1176 /* storage for physical objects */
1177 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1179 /* accounting, useful for userland debugging */
1180 spinlock_t object_stat_lock;
1181 size_t object_memory;
1185 struct drm_i915_error_state_buf {
1194 struct i915_error_state_file_priv {
1195 struct drm_device *dev;
1196 struct drm_i915_error_state *error;
1199 struct i915_gpu_error {
1200 /* For hangcheck timer */
1201 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1202 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1203 /* Hang gpu twice in this window and your context gets banned */
1204 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1206 struct timer_list hangcheck_timer;
1208 /* For reset and error_state handling. */
1210 /* Protected by the above dev->gpu_error.lock. */
1211 struct drm_i915_error_state *first_error;
1212 struct work_struct work;
1215 unsigned long missed_irq_rings;
1218 * State variable controlling the reset flow and count
1220 * This is a counter which gets incremented when reset is triggered,
1221 * and again when reset has been handled. So odd values (lowest bit set)
1222 * means that reset is in progress and even values that
1223 * (reset_counter >> 1):th reset was successfully completed.
1225 * If reset is not completed succesfully, the I915_WEDGE bit is
1226 * set meaning that hardware is terminally sour and there is no
1227 * recovery. All waiters on the reset_queue will be woken when
1230 * This counter is used by the wait_seqno code to notice that reset
1231 * event happened and it needs to restart the entire ioctl (since most
1232 * likely the seqno it waited for won't ever signal anytime soon).
1234 * This is important for lock-free wait paths, where no contended lock
1235 * naturally enforces the correct ordering between the bail-out of the
1236 * waiter and the gpu reset work code.
1238 atomic_t reset_counter;
1240 #define I915_RESET_IN_PROGRESS_FLAG 1
1241 #define I915_WEDGED (1 << 31)
1244 * Waitqueue to signal when the reset has completed. Used by clients
1245 * that wait for dev_priv->mm.wedged to settle.
1247 wait_queue_head_t reset_queue;
1249 /* For gpu hang simulation. */
1250 unsigned int stop_rings;
1252 /* For missed irq/seqno simulation. */
1253 unsigned int test_irq_rings;
1256 enum modeset_restore {
1257 MODESET_ON_LID_OPEN,
1262 struct ddi_vbt_port_info {
1263 uint8_t hdmi_level_shift;
1265 uint8_t supports_dvi:1;
1266 uint8_t supports_hdmi:1;
1267 uint8_t supports_dp:1;
1270 struct intel_vbt_data {
1271 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1272 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1275 unsigned int int_tv_support:1;
1276 unsigned int lvds_dither:1;
1277 unsigned int lvds_vbt:1;
1278 unsigned int int_crt_support:1;
1279 unsigned int lvds_use_ssc:1;
1280 unsigned int display_clock_mode:1;
1281 unsigned int fdi_rx_polarity_inverted:1;
1283 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1288 int edp_preemphasis;
1290 bool edp_initialized;
1293 struct edp_power_seq edp_pps;
1297 bool active_low_pwm;
1308 union child_device_config *child_dev;
1310 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1313 enum intel_ddb_partitioning {
1315 INTEL_DDB_PART_5_6, /* IVB+ */
1318 struct intel_wm_level {
1326 struct ilk_wm_values {
1327 uint32_t wm_pipe[3];
1329 uint32_t wm_lp_spr[3];
1330 uint32_t wm_linetime[3];
1332 enum intel_ddb_partitioning partitioning;
1336 * This struct tracks the state needed for the Package C8+ feature.
1338 * Package states C8 and deeper are really deep PC states that can only be
1339 * reached when all the devices on the system allow it, so even if the graphics
1340 * device allows PC8+, it doesn't mean the system will actually get to these
1343 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1344 * is disabled and the GPU is idle. When these conditions are met, we manually
1345 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1348 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1349 * the state of some registers, so when we come back from PC8+ we need to
1350 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1351 * need to take care of the registers kept by RC6.
1353 * The interrupt disabling is part of the requirements. We can only leave the
1354 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1355 * can lock the machine.
1357 * Ideally every piece of our code that needs PC8+ disabled would call
1358 * hsw_disable_package_c8, which would increment disable_count and prevent the
1359 * system from reaching PC8+. But we don't have a symmetric way to do this for
1360 * everything, so we have the requirements_met variable. When we switch
1361 * requirements_met to true we decrease disable_count, and increase it in the
1362 * opposite case. The requirements_met variable is true when all the CRTCs,
1363 * encoders and the power well are disabled.
1365 * In addition to everything, we only actually enable PC8+ if disable_count
1366 * stays at zero for at least some seconds. This is implemented with the
1367 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1368 * consecutive times when all screens are disabled and some background app
1369 * queries the state of our connectors, or we have some application constantly
1370 * waking up to use the GPU. Only after the enable_work function actually
1371 * enables PC8+ the "enable" variable will become true, which means that it can
1372 * be false even if disable_count is 0.
1374 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1375 * goes back to false exactly before we reenable the IRQs. We use this variable
1376 * to check if someone is trying to enable/disable IRQs while they're supposed
1377 * to be disabled. This shouldn't happen and we'll print some error messages in
1378 * case it happens, but if it actually happens we'll also update the variables
1379 * inside struct regsave so when we restore the IRQs they will contain the
1380 * latest expected values.
1382 * For more, read "Display Sequences for Package C8" on our documentation.
1384 struct i915_package_c8 {
1385 bool requirements_met;
1387 /* Only true after the delayed work task actually enables it. */
1391 struct delayed_work enable_work;
1398 uint32_t gen6_pmimr;
1402 struct i915_runtime_pm {
1406 enum intel_pipe_crc_source {
1407 INTEL_PIPE_CRC_SOURCE_NONE,
1408 INTEL_PIPE_CRC_SOURCE_PLANE1,
1409 INTEL_PIPE_CRC_SOURCE_PLANE2,
1410 INTEL_PIPE_CRC_SOURCE_PF,
1411 INTEL_PIPE_CRC_SOURCE_PIPE,
1412 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1413 INTEL_PIPE_CRC_SOURCE_TV,
1414 INTEL_PIPE_CRC_SOURCE_DP_B,
1415 INTEL_PIPE_CRC_SOURCE_DP_C,
1416 INTEL_PIPE_CRC_SOURCE_DP_D,
1417 INTEL_PIPE_CRC_SOURCE_AUTO,
1418 INTEL_PIPE_CRC_SOURCE_MAX,
1421 struct intel_pipe_crc_entry {
1426 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1427 struct intel_pipe_crc {
1429 bool opened; /* exclusive access to the result file */
1430 struct intel_pipe_crc_entry *entries;
1431 enum intel_pipe_crc_source source;
1433 wait_queue_head_t wq;
1436 typedef struct drm_i915_private {
1437 struct drm_device *dev;
1438 struct kmem_cache *slab;
1440 const struct intel_device_info info;
1442 int relative_constants_mode;
1446 struct intel_uncore uncore;
1448 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1451 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1452 * controller on different i2c buses. */
1453 struct mutex gmbus_mutex;
1456 * Base address of the gmbus and gpio block.
1458 uint32_t gpio_mmio_base;
1460 wait_queue_head_t gmbus_wait_queue;
1462 struct pci_dev *bridge_dev;
1463 struct intel_ring_buffer ring[I915_NUM_RINGS];
1464 uint32_t last_seqno, next_seqno;
1466 drm_dma_handle_t *status_page_dmah;
1467 struct resource mch_res;
1469 /* protects the irq masks */
1470 spinlock_t irq_lock;
1472 bool display_irqs_enabled;
1474 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1475 struct pm_qos_request pm_qos;
1477 /* DPIO indirect register protection */
1478 struct mutex dpio_lock;
1480 /** Cached value of IMR to avoid reads in updating the bitfield */
1483 u32 de_irq_mask[I915_MAX_PIPES];
1487 u32 pipestat_irq_mask[I915_MAX_PIPES];
1489 struct work_struct hotplug_work;
1490 bool enable_hotplug_processing;
1492 unsigned long hpd_last_jiffies;
1497 HPD_MARK_DISABLED = 2
1499 } hpd_stats[HPD_NUM_PINS];
1501 struct timer_list hotplug_reenable_timer;
1503 struct i915_fbc fbc;
1504 struct intel_opregion opregion;
1505 struct intel_vbt_data vbt;
1508 struct intel_overlay *overlay;
1510 /* backlight registers and fields in struct intel_panel */
1511 spinlock_t backlight_lock;
1514 bool no_aux_handshake;
1516 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1517 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1518 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1520 unsigned int fsb_freq, mem_freq, is_ddr3;
1523 * wq - Driver workqueue for GEM.
1525 * NOTE: Work items scheduled here are not allowed to grab any modeset
1526 * locks, for otherwise the flushing done in the pageflip code will
1527 * result in deadlocks.
1529 struct workqueue_struct *wq;
1531 /* Display functions */
1532 struct drm_i915_display_funcs display;
1534 /* PCH chipset type */
1535 enum intel_pch pch_type;
1536 unsigned short pch_id;
1538 unsigned long quirks;
1540 enum modeset_restore modeset_restore;
1541 struct mutex modeset_restore_lock;
1543 struct list_head vm_list; /* Global list of all address spaces */
1544 struct i915_gtt gtt; /* VMA representing the global address space */
1546 struct i915_gem_mm mm;
1548 /* Kernel Modesetting */
1550 struct sdvo_device_mapping sdvo_mappings[2];
1552 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1553 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1554 wait_queue_head_t pending_flip_queue;
1556 #ifdef CONFIG_DEBUG_FS
1557 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1560 int num_shared_dpll;
1561 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1562 struct intel_ddi_plls ddi_plls;
1563 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1565 /* Reclocking support */
1566 bool render_reclock_avail;
1567 bool lvds_downclock_avail;
1568 /* indicates the reduced downclock for LVDS*/
1572 bool mchbar_need_disable;
1574 struct intel_l3_parity l3_parity;
1576 /* Cannot be determined by PCIID. You must always read a register. */
1579 /* gen6+ rps state */
1580 struct intel_gen6_power_mgmt rps;
1582 /* ilk-only ips/rps state. Everything in here is protected by the global
1583 * mchdev_lock in intel_pm.c */
1584 struct intel_ilk_power_mgmt ips;
1586 struct i915_power_domains power_domains;
1588 struct i915_psr psr;
1590 struct i915_gpu_error gpu_error;
1592 struct drm_i915_gem_object *vlv_pctx;
1594 #ifdef CONFIG_DRM_I915_FBDEV
1595 /* list of fbdev register on this device */
1596 struct intel_fbdev *fbdev;
1600 * The console may be contended at resume, but we don't
1601 * want it to block on it.
1603 struct work_struct console_resume_work;
1605 struct drm_property *broadcast_rgb_property;
1606 struct drm_property *force_audio_property;
1608 uint32_t hw_context_size;
1609 struct list_head context_list;
1613 struct i915_suspend_saved_registers regfile;
1617 * Raw watermark latency values:
1618 * in 0.1us units for WM0,
1619 * in 0.5us units for WM1+.
1622 uint16_t pri_latency[5];
1624 uint16_t spr_latency[5];
1626 uint16_t cur_latency[5];
1628 /* current hardware state */
1629 struct ilk_wm_values hw;
1632 struct i915_package_c8 pc8;
1634 struct i915_runtime_pm pm;
1636 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1638 struct i915_dri1_state dri1;
1639 /* Old ums support infrastructure, same warning applies. */
1640 struct i915_ums_state ums;
1643 } drm_i915_private_t;
1645 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1647 return dev->dev_private;
1650 /* Iterate over initialised rings */
1651 #define for_each_ring(ring__, dev_priv__, i__) \
1652 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1653 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1655 enum hdmi_force_audio {
1656 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1657 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1658 HDMI_AUDIO_AUTO, /* trust EDID */
1659 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1662 #define I915_GTT_OFFSET_NONE ((u32)-1)
1664 struct drm_i915_gem_object_ops {
1665 /* Interface between the GEM object and its backing storage.
1666 * get_pages() is called once prior to the use of the associated set
1667 * of pages before to binding them into the GTT, and put_pages() is
1668 * called after we no longer need them. As we expect there to be
1669 * associated cost with migrating pages between the backing storage
1670 * and making them available for the GPU (e.g. clflush), we may hold
1671 * onto the pages after they are no longer referenced by the GPU
1672 * in case they may be used again shortly (for example migrating the
1673 * pages to a different memory domain within the GTT). put_pages()
1674 * will therefore most likely be called when the object itself is
1675 * being released or under memory pressure (where we attempt to
1676 * reap pages for the shrinker).
1678 int (*get_pages)(struct drm_i915_gem_object *);
1679 void (*put_pages)(struct drm_i915_gem_object *);
1682 struct drm_i915_gem_object {
1683 struct drm_gem_object base;
1685 const struct drm_i915_gem_object_ops *ops;
1687 /** List of VMAs backed by this object */
1688 struct list_head vma_list;
1690 /** Stolen memory for this object, instead of being backed by shmem. */
1691 struct drm_mm_node *stolen;
1692 struct list_head global_list;
1694 struct list_head ring_list;
1695 /** Used in execbuf to temporarily hold a ref */
1696 struct list_head obj_exec_link;
1699 * This is set if the object is on the active lists (has pending
1700 * rendering and so a non-zero seqno), and is not set if it i s on
1701 * inactive (ready to be unbound) list.
1703 unsigned int active:1;
1706 * This is set if the object has been written to since last bound
1709 unsigned int dirty:1;
1712 * Fence register bits (if any) for this object. Will be set
1713 * as needed when mapped into the GTT.
1714 * Protected by dev->struct_mutex.
1716 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1719 * Advice: are the backing pages purgeable?
1721 unsigned int madv:2;
1724 * Current tiling mode for the object.
1726 unsigned int tiling_mode:2;
1728 * Whether the tiling parameters for the currently associated fence
1729 * register have changed. Note that for the purposes of tracking
1730 * tiling changes we also treat the unfenced register, the register
1731 * slot that the object occupies whilst it executes a fenced
1732 * command (such as BLT on gen2/3), as a "fence".
1734 unsigned int fence_dirty:1;
1737 * Is the object at the current location in the gtt mappable and
1738 * fenceable? Used to avoid costly recalculations.
1740 unsigned int map_and_fenceable:1;
1743 * Whether the current gtt mapping needs to be mappable (and isn't just
1744 * mappable by accident). Track pin and fault separate for a more
1745 * accurate mappable working set.
1747 unsigned int fault_mappable:1;
1748 unsigned int pin_mappable:1;
1749 unsigned int pin_display:1;
1752 * Is the GPU currently using a fence to access this buffer,
1754 unsigned int pending_fenced_gpu_access:1;
1755 unsigned int fenced_gpu_access:1;
1757 unsigned int cache_level:3;
1759 unsigned int has_aliasing_ppgtt_mapping:1;
1760 unsigned int has_global_gtt_mapping:1;
1761 unsigned int has_dma_mapping:1;
1763 struct sg_table *pages;
1764 int pages_pin_count;
1766 /* prime dma-buf support */
1767 void *dma_buf_vmapping;
1770 struct intel_ring_buffer *ring;
1772 /** Breadcrumb of last rendering to the buffer. */
1773 uint32_t last_read_seqno;
1774 uint32_t last_write_seqno;
1775 /** Breadcrumb of last fenced GPU access to the buffer. */
1776 uint32_t last_fenced_seqno;
1778 /** Current tiling stride for the object, if it's tiled. */
1781 /** References from framebuffers, locks out tiling changes. */
1782 unsigned long framebuffer_references;
1784 /** Record of address bit 17 of each page at last unbind. */
1785 unsigned long *bit_17;
1787 /** User space pin count and filp owning the pin */
1788 unsigned long user_pin_count;
1789 struct drm_file *pin_filp;
1791 /** for phy allocated objects */
1792 struct drm_i915_gem_phys_object *phys_obj;
1795 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1798 * Request queue structure.
1800 * The request queue allows us to note sequence numbers that have been emitted
1801 * and may be associated with active buffers to be retired.
1803 * By keeping this list, we can avoid having to do questionable
1804 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1805 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1807 struct drm_i915_gem_request {
1808 /** On Which ring this request was generated */
1809 struct intel_ring_buffer *ring;
1811 /** GEM sequence number associated with this request. */
1814 /** Position in the ringbuffer of the start of the request */
1817 /** Position in the ringbuffer of the end of the request */
1820 /** Context related to this request */
1821 struct i915_hw_context *ctx;
1823 /** Batch buffer related to this request if any */
1824 struct drm_i915_gem_object *batch_obj;
1826 /** Time at which this request was emitted, in jiffies. */
1827 unsigned long emitted_jiffies;
1829 /** global list entry for this request */
1830 struct list_head list;
1832 struct drm_i915_file_private *file_priv;
1833 /** file_priv list entry for this request */
1834 struct list_head client_list;
1837 struct drm_i915_file_private {
1838 struct drm_i915_private *dev_priv;
1839 struct drm_file *file;
1843 struct list_head request_list;
1844 struct delayed_work idle_work;
1846 struct idr context_idr;
1848 struct i915_hw_context *private_default_ctx;
1849 atomic_t rps_wait_boost;
1852 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1854 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1855 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1856 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1857 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1858 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1859 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1860 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1861 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1862 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1863 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1864 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1865 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1866 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1867 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1868 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1869 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1870 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1871 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1872 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1873 (dev)->pdev->device == 0x0152 || \
1874 (dev)->pdev->device == 0x015a)
1875 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1876 (dev)->pdev->device == 0x0106 || \
1877 (dev)->pdev->device == 0x010A)
1878 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1879 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1880 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1881 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1882 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1883 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1884 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1885 (((dev)->pdev->device & 0xf) == 0x2 || \
1886 ((dev)->pdev->device & 0xf) == 0x6 || \
1887 ((dev)->pdev->device & 0xf) == 0xe))
1888 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1889 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1890 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1891 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1892 ((dev)->pdev->device & 0x00F0) == 0x0020)
1893 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1896 * The genX designation typically refers to the render engine, so render
1897 * capability related checks should use IS_GEN, while display and other checks
1898 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1901 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1902 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1903 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1904 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1905 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1906 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1907 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1909 #define RENDER_RING (1<<RCS)
1910 #define BSD_RING (1<<VCS)
1911 #define BLT_RING (1<<BCS)
1912 #define VEBOX_RING (1<<VECS)
1913 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1914 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1915 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1916 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1917 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1918 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1920 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1921 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1922 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1923 && !IS_BROADWELL(dev))
1924 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1925 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1927 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1928 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1930 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1931 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1933 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1934 * rows, which changed the alignment requirements and fence programming.
1936 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1938 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1939 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1940 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1941 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1942 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1944 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1945 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1946 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1948 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1950 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1951 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1952 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1953 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
1954 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
1956 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1957 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1958 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1959 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1960 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1961 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1963 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1964 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1965 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1966 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1967 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1968 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1970 /* DPF == dynamic parity feature */
1971 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1972 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1974 #define GT_FREQUENCY_MULTIPLIER 50
1976 #include "i915_trace.h"
1978 extern const struct drm_ioctl_desc i915_ioctls[];
1979 extern int i915_max_ioctl;
1981 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1982 extern int i915_resume(struct drm_device *dev);
1983 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1984 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1987 struct i915_params {
1989 int panel_ignore_lid;
1990 unsigned int powersave;
1992 unsigned int lvds_downclock;
1993 int lvds_channel_mode;
1995 int vbt_sdvo_panel_type;
2000 unsigned int preliminary_hw_support;
2001 int disable_power_well;
2005 int invert_brightness;
2006 /* leave bools at the end to not create holes */
2007 bool enable_hangcheck;
2009 bool prefault_disable;
2011 bool disable_display;
2013 extern struct i915_params i915 __read_mostly;
2016 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2017 extern void i915_kernel_lost_context(struct drm_device * dev);
2018 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2019 extern int i915_driver_unload(struct drm_device *);
2020 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2021 extern void i915_driver_lastclose(struct drm_device * dev);
2022 extern void i915_driver_preclose(struct drm_device *dev,
2023 struct drm_file *file_priv);
2024 extern void i915_driver_postclose(struct drm_device *dev,
2025 struct drm_file *file_priv);
2026 extern int i915_driver_device_is_agp(struct drm_device * dev);
2027 #ifdef CONFIG_COMPAT
2028 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2031 extern int i915_emit_box(struct drm_device *dev,
2032 struct drm_clip_rect *box,
2034 extern int intel_gpu_reset(struct drm_device *dev);
2035 extern int i915_reset(struct drm_device *dev);
2036 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2037 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2038 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2039 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2041 extern void intel_console_resume(struct work_struct *work);
2044 void i915_queue_hangcheck(struct drm_device *dev);
2046 void i915_handle_error(struct drm_device *dev, bool wedged,
2047 const char *fmt, ...);
2049 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2051 extern void intel_irq_init(struct drm_device *dev);
2052 extern void intel_hpd_init(struct drm_device *dev);
2054 extern void intel_uncore_sanitize(struct drm_device *dev);
2055 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2056 extern void intel_uncore_init(struct drm_device *dev);
2057 extern void intel_uncore_check_errors(struct drm_device *dev);
2058 extern void intel_uncore_fini(struct drm_device *dev);
2061 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2065 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2068 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2069 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2072 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2073 struct drm_file *file_priv);
2074 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2075 struct drm_file *file_priv);
2076 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2077 struct drm_file *file_priv);
2078 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2079 struct drm_file *file_priv);
2080 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2081 struct drm_file *file_priv);
2082 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2083 struct drm_file *file_priv);
2084 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2085 struct drm_file *file_priv);
2086 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2087 struct drm_file *file_priv);
2088 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2089 struct drm_file *file_priv);
2090 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2091 struct drm_file *file_priv);
2092 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2093 struct drm_file *file_priv);
2094 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2095 struct drm_file *file_priv);
2096 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2097 struct drm_file *file_priv);
2098 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2099 struct drm_file *file);
2100 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *file);
2102 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *file_priv);
2104 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
2110 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2113 struct drm_file *file_priv);
2114 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *file_priv);
2116 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
2118 void i915_gem_load(struct drm_device *dev);
2119 void *i915_gem_object_alloc(struct drm_device *dev);
2120 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2121 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2122 const struct drm_i915_gem_object_ops *ops);
2123 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2125 void i915_init_vm(struct drm_i915_private *dev_priv,
2126 struct i915_address_space *vm);
2127 void i915_gem_free_object(struct drm_gem_object *obj);
2128 void i915_gem_vma_destroy(struct i915_vma *vma);
2130 #define PIN_MAPPABLE 0x1
2131 #define PIN_NONBLOCK 0x2
2132 #define PIN_GLOBAL 0x4
2133 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2134 struct i915_address_space *vm,
2137 int __must_check i915_vma_unbind(struct i915_vma *vma);
2138 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2139 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2140 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2141 void i915_gem_lastclose(struct drm_device *dev);
2143 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2144 int *needs_clflush);
2146 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2147 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2149 struct sg_page_iter sg_iter;
2151 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2152 return sg_page_iter_page(&sg_iter);
2156 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2158 BUG_ON(obj->pages == NULL);
2159 obj->pages_pin_count++;
2161 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2163 BUG_ON(obj->pages_pin_count == 0);
2164 obj->pages_pin_count--;
2167 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2168 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2169 struct intel_ring_buffer *to);
2170 void i915_vma_move_to_active(struct i915_vma *vma,
2171 struct intel_ring_buffer *ring);
2172 int i915_gem_dumb_create(struct drm_file *file_priv,
2173 struct drm_device *dev,
2174 struct drm_mode_create_dumb *args);
2175 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2176 uint32_t handle, uint64_t *offset);
2178 * Returns true if seq1 is later than seq2.
2181 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2183 return (int32_t)(seq1 - seq2) >= 0;
2186 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2187 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2188 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2189 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2192 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2194 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2195 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2196 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2203 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2205 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2206 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2207 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2208 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2212 struct drm_i915_gem_request *
2213 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2215 bool i915_gem_retire_requests(struct drm_device *dev);
2216 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2217 bool interruptible);
2218 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2220 return unlikely(atomic_read(&error->reset_counter)
2221 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2224 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2226 return atomic_read(&error->reset_counter) & I915_WEDGED;
2229 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2231 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2234 void i915_gem_reset(struct drm_device *dev);
2235 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2236 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2237 int __must_check i915_gem_init(struct drm_device *dev);
2238 int __must_check i915_gem_init_hw(struct drm_device *dev);
2239 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2240 void i915_gem_init_swizzling(struct drm_device *dev);
2241 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2242 int __must_check i915_gpu_idle(struct drm_device *dev);
2243 int __must_check i915_gem_suspend(struct drm_device *dev);
2244 int __i915_add_request(struct intel_ring_buffer *ring,
2245 struct drm_file *file,
2246 struct drm_i915_gem_object *batch_obj,
2248 #define i915_add_request(ring, seqno) \
2249 __i915_add_request(ring, NULL, NULL, seqno)
2250 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2252 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2254 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2257 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2259 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2261 struct intel_ring_buffer *pipelined);
2262 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2263 int i915_gem_attach_phys_object(struct drm_device *dev,
2264 struct drm_i915_gem_object *obj,
2267 void i915_gem_detach_phys_object(struct drm_device *dev,
2268 struct drm_i915_gem_object *obj);
2269 void i915_gem_free_all_phys_object(struct drm_device *dev);
2270 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2271 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2274 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2276 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2277 int tiling_mode, bool fenced);
2279 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2280 enum i915_cache_level cache_level);
2282 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2283 struct dma_buf *dma_buf);
2285 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2286 struct drm_gem_object *gem_obj, int flags);
2288 void i915_gem_restore_fences(struct drm_device *dev);
2290 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2291 struct i915_address_space *vm);
2292 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2293 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2294 struct i915_address_space *vm);
2295 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2296 struct i915_address_space *vm);
2297 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2298 struct i915_address_space *vm);
2300 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2301 struct i915_address_space *vm);
2303 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2304 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2305 struct i915_vma *vma;
2306 list_for_each_entry(vma, &obj->vma_list, vma_link)
2307 if (vma->pin_count > 0)
2312 /* Some GGTT VM helpers */
2313 #define obj_to_ggtt(obj) \
2314 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2315 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2317 struct i915_address_space *ggtt =
2318 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2322 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2324 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2327 static inline unsigned long
2328 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2330 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2333 static inline unsigned long
2334 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2336 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2339 static inline int __must_check
2340 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2344 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2348 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2350 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2353 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2355 /* i915_gem_context.c */
2356 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2357 int __must_check i915_gem_context_init(struct drm_device *dev);
2358 void i915_gem_context_fini(struct drm_device *dev);
2359 void i915_gem_context_reset(struct drm_device *dev);
2360 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2361 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2362 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2363 int i915_switch_context(struct intel_ring_buffer *ring,
2364 struct drm_file *file, struct i915_hw_context *to);
2365 struct i915_hw_context *
2366 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2367 void i915_gem_context_free(struct kref *ctx_ref);
2368 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2370 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2371 kref_get(&ctx->ref);
2374 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2376 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2377 kref_put(&ctx->ref, i915_gem_context_free);
2380 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2382 return c->id == DEFAULT_CONTEXT_ID;
2385 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2386 struct drm_file *file);
2387 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2388 struct drm_file *file);
2390 /* i915_gem_evict.c */
2391 int __must_check i915_gem_evict_something(struct drm_device *dev,
2392 struct i915_address_space *vm,
2395 unsigned cache_level,
2397 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2398 int i915_gem_evict_everything(struct drm_device *dev);
2400 /* i915_gem_gtt.c */
2401 void i915_check_and_clear_faults(struct drm_device *dev);
2402 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2403 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2404 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2405 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2406 void i915_gem_init_global_gtt(struct drm_device *dev);
2407 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2408 unsigned long mappable_end, unsigned long end);
2409 int i915_gem_gtt_init(struct drm_device *dev);
2410 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2412 if (INTEL_INFO(dev)->gen < 6)
2413 intel_gtt_chipset_flush();
2415 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
2416 bool intel_enable_ppgtt(struct drm_device *dev, bool full);
2418 /* i915_gem_stolen.c */
2419 int i915_gem_init_stolen(struct drm_device *dev);
2420 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2421 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2422 void i915_gem_cleanup_stolen(struct drm_device *dev);
2423 struct drm_i915_gem_object *
2424 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2425 struct drm_i915_gem_object *
2426 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2430 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2432 /* i915_gem_tiling.c */
2433 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2435 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2437 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2438 obj->tiling_mode != I915_TILING_NONE;
2441 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2442 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2443 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2445 /* i915_gem_debug.c */
2447 int i915_verify_lists(struct drm_device *dev);
2449 #define i915_verify_lists(dev) 0
2452 /* i915_debugfs.c */
2453 int i915_debugfs_init(struct drm_minor *minor);
2454 void i915_debugfs_cleanup(struct drm_minor *minor);
2455 #ifdef CONFIG_DEBUG_FS
2456 void intel_display_crc_init(struct drm_device *dev);
2458 static inline void intel_display_crc_init(struct drm_device *dev) {}
2461 /* i915_gpu_error.c */
2463 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2464 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2465 const struct i915_error_state_file_priv *error);
2466 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2467 size_t count, loff_t pos);
2468 static inline void i915_error_state_buf_release(
2469 struct drm_i915_error_state_buf *eb)
2473 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2474 const char *error_msg);
2475 void i915_error_state_get(struct drm_device *dev,
2476 struct i915_error_state_file_priv *error_priv);
2477 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2478 void i915_destroy_error_state(struct drm_device *dev);
2480 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2481 const char *i915_cache_level_str(int type);
2483 /* i915_suspend.c */
2484 extern int i915_save_state(struct drm_device *dev);
2485 extern int i915_restore_state(struct drm_device *dev);
2488 void i915_save_display_reg(struct drm_device *dev);
2489 void i915_restore_display_reg(struct drm_device *dev);
2492 void i915_setup_sysfs(struct drm_device *dev_priv);
2493 void i915_teardown_sysfs(struct drm_device *dev_priv);
2496 extern int intel_setup_gmbus(struct drm_device *dev);
2497 extern void intel_teardown_gmbus(struct drm_device *dev);
2498 static inline bool intel_gmbus_is_port_valid(unsigned port)
2500 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2503 extern struct i2c_adapter *intel_gmbus_get_adapter(
2504 struct drm_i915_private *dev_priv, unsigned port);
2505 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2506 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2507 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2509 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2511 extern void intel_i2c_reset(struct drm_device *dev);
2513 /* intel_opregion.c */
2514 struct intel_encoder;
2515 extern int intel_opregion_setup(struct drm_device *dev);
2517 extern void intel_opregion_init(struct drm_device *dev);
2518 extern void intel_opregion_fini(struct drm_device *dev);
2519 extern void intel_opregion_asle_intr(struct drm_device *dev);
2520 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2522 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2525 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2526 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2527 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2529 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2534 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2542 extern void intel_register_dsm_handler(void);
2543 extern void intel_unregister_dsm_handler(void);
2545 static inline void intel_register_dsm_handler(void) { return; }
2546 static inline void intel_unregister_dsm_handler(void) { return; }
2547 #endif /* CONFIG_ACPI */
2550 extern void intel_modeset_init_hw(struct drm_device *dev);
2551 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2552 extern void intel_modeset_init(struct drm_device *dev);
2553 extern void intel_modeset_gem_init(struct drm_device *dev);
2554 extern void intel_modeset_cleanup(struct drm_device *dev);
2555 extern void intel_connector_unregister(struct intel_connector *);
2556 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2557 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2558 bool force_restore);
2559 extern void i915_redisable_vga(struct drm_device *dev);
2560 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2561 extern bool intel_fbc_enabled(struct drm_device *dev);
2562 extern void intel_disable_fbc(struct drm_device *dev);
2563 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2564 extern void intel_init_pch_refclk(struct drm_device *dev);
2565 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2566 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2567 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2568 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2569 extern void intel_detect_pch(struct drm_device *dev);
2570 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2571 extern int intel_enable_rc6(const struct drm_device *dev);
2573 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2574 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2575 struct drm_file *file);
2576 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2577 struct drm_file *file);
2580 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2581 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2582 struct intel_overlay_error_state *error);
2584 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2585 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2586 struct drm_device *dev,
2587 struct intel_display_error_state *error);
2589 /* On SNB platform, before reading ring registers forcewake bit
2590 * must be set to prevent GT core from power down and stale values being
2593 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2594 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2595 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2597 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2598 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2600 /* intel_sideband.c */
2601 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2602 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2603 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2604 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2605 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2606 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2607 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2608 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2609 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2610 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2611 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2612 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2613 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2614 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2615 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2616 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2617 enum intel_sbi_destination destination);
2618 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2619 enum intel_sbi_destination destination);
2620 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2621 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2623 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2624 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2626 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2627 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2629 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2630 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2631 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2632 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2633 ((reg) >= 0x2E000 && (reg) < 0x30000))
2635 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2636 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2637 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2638 ((reg) >= 0x30000 && (reg) < 0x40000))
2640 #define FORCEWAKE_RENDER (1 << 0)
2641 #define FORCEWAKE_MEDIA (1 << 1)
2642 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2645 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2646 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2648 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2649 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2650 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2651 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2653 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2654 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2655 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2656 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2658 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2659 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2661 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2662 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2664 /* "Broadcast RGB" property */
2665 #define INTEL_BROADCAST_RGB_AUTO 0
2666 #define INTEL_BROADCAST_RGB_FULL 1
2667 #define INTEL_BROADCAST_RGB_LIMITED 2
2669 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2671 if (HAS_PCH_SPLIT(dev))
2672 return CPU_VGACNTRL;
2673 else if (IS_VALLEYVIEW(dev))
2674 return VLV_VGACNTRL;
2679 static inline void __user *to_user_ptr(u64 address)
2681 return (void __user *)(uintptr_t)address;
2684 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2686 unsigned long j = msecs_to_jiffies(m);
2688 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2691 static inline unsigned long
2692 timespec_to_jiffies_timeout(const struct timespec *value)
2694 unsigned long j = timespec_to_jiffies(value);
2696 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2700 * If you need to wait X milliseconds between events A and B, but event B
2701 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2702 * when event A happened, then just before event B you call this function and
2703 * pass the timestamp as the first argument, and X as the second argument.
2706 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2708 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2711 * Don't re-read the value of "jiffies" every time since it may change
2712 * behind our back and break the math.
2714 tmp_jiffies = jiffies;
2715 target_jiffies = timestamp_jiffies +
2716 msecs_to_jiffies_timeout(to_wait_ms);
2718 if (time_after(target_jiffies, tmp_jiffies)) {
2719 remaining_jiffies = target_jiffies - tmp_jiffies;
2720 while (remaining_jiffies)
2722 schedule_timeout_uninterruptible(remaining_jiffies);