1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
53 #include "intel_guc.h"
55 /* General customization:
58 #define DRIVER_NAME "i915"
59 #define DRIVER_DESC "Intel Graphics"
60 #define DRIVER_DATE "20150731"
63 /* Many gcc seem to no see through this and fall over :( */
65 #define WARN_ON(x) ({ \
66 bool __i915_warn_cond = (x); \
67 if (__builtin_constant_p(__i915_warn_cond)) \
68 BUILD_BUG_ON(__i915_warn_cond); \
69 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
71 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
75 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
77 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
78 (long) (x), __func__);
80 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
82 * which may not necessarily be a user visible problem. This will either
83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
84 * enable distros and users to tailor their preferred amount of i915 abrt
87 #define I915_STATE_WARN(condition, format...) ({ \
88 int __ret_warn_on = !!(condition); \
89 if (unlikely(__ret_warn_on)) { \
90 if (i915.verbose_state_checks) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(condition) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) { \
101 if (i915.verbose_state_checks) \
102 WARN(1, "WARN_ON(" #condition ")\n"); \
104 DRM_ERROR("WARN_ON(" #condition ")\n"); \
106 unlikely(__ret_warn_on); \
115 I915_MAX_PIPES = _PIPE_EDP
117 #define pipe_name(p) ((p) + 'A')
126 #define transcoder_name(t) ((t) + 'A')
129 * This is the maximum (across all platforms) number of planes (primary +
130 * sprites) that can be active at the same time on one pipe.
132 * This value doesn't count the cursor plane.
134 #define I915_MAX_PLANES 4
141 #define plane_name(p) ((p) + 'A')
143 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
153 #define port_name(p) ((p) + 'A')
155 #define I915_NUM_PHYS_VLV 2
167 enum intel_display_power_domain {
171 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
173 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
174 POWER_DOMAIN_TRANSCODER_A,
175 POWER_DOMAIN_TRANSCODER_B,
176 POWER_DOMAIN_TRANSCODER_C,
177 POWER_DOMAIN_TRANSCODER_EDP,
178 POWER_DOMAIN_PORT_DDI_A_2_LANES,
179 POWER_DOMAIN_PORT_DDI_A_4_LANES,
180 POWER_DOMAIN_PORT_DDI_B_2_LANES,
181 POWER_DOMAIN_PORT_DDI_B_4_LANES,
182 POWER_DOMAIN_PORT_DDI_C_2_LANES,
183 POWER_DOMAIN_PORT_DDI_C_4_LANES,
184 POWER_DOMAIN_PORT_DDI_D_2_LANES,
185 POWER_DOMAIN_PORT_DDI_D_4_LANES,
186 POWER_DOMAIN_PORT_DSI,
187 POWER_DOMAIN_PORT_CRT,
188 POWER_DOMAIN_PORT_OTHER,
201 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204 #define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
221 #define for_each_hpd_pin(__pin) \
222 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
224 struct i915_hotplug {
225 struct work_struct hotplug_work;
228 unsigned long last_jiffies;
233 HPD_MARK_DISABLED = 2
235 } stats[HPD_NUM_PINS];
237 struct delayed_work reenable_work;
239 struct intel_digital_port *irq_port[I915_MAX_PORTS];
242 struct work_struct dig_port_work;
245 * if we get a HPD irq from DP and a HPD irq from non-DP
246 * the non-DP HPD could block the workqueue on a mode config
247 * mutex getting, that userspace may have taken. However
248 * userspace is waiting on the DP workqueue to run which is
249 * blocked behind the non-DP one.
251 struct workqueue_struct *dp_wq;
254 #define I915_GEM_GPU_DOMAINS \
255 (I915_GEM_DOMAIN_RENDER | \
256 I915_GEM_DOMAIN_SAMPLER | \
257 I915_GEM_DOMAIN_COMMAND | \
258 I915_GEM_DOMAIN_INSTRUCTION | \
259 I915_GEM_DOMAIN_VERTEX)
261 #define for_each_pipe(__dev_priv, __p) \
262 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
263 #define for_each_plane(__dev_priv, __pipe, __p) \
265 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
267 #define for_each_sprite(__dev_priv, __p, __s) \
269 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
272 #define for_each_crtc(dev, crtc) \
273 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
275 #define for_each_intel_plane(dev, intel_plane) \
276 list_for_each_entry(intel_plane, \
277 &dev->mode_config.plane_list, \
280 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
281 list_for_each_entry(intel_plane, \
282 &(dev)->mode_config.plane_list, \
284 if ((intel_plane)->pipe == (intel_crtc)->pipe)
286 #define for_each_intel_crtc(dev, intel_crtc) \
287 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
289 #define for_each_intel_encoder(dev, intel_encoder) \
290 list_for_each_entry(intel_encoder, \
291 &(dev)->mode_config.encoder_list, \
294 #define for_each_intel_connector(dev, intel_connector) \
295 list_for_each_entry(intel_connector, \
296 &dev->mode_config.connector_list, \
299 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
300 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
301 if ((intel_encoder)->base.crtc == (__crtc))
303 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
304 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
305 if ((intel_connector)->base.encoder == (__encoder))
307 #define for_each_power_domain(domain, mask) \
308 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
309 if ((1 << (domain)) & (mask))
311 struct drm_i915_private;
312 struct i915_mm_struct;
313 struct i915_mmu_object;
315 struct drm_i915_file_private {
316 struct drm_i915_private *dev_priv;
317 struct drm_file *file;
321 struct list_head request_list;
322 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
323 * chosen to prevent the CPU getting more than a frame ahead of the GPU
324 * (when using lax throttling for the frontbuffer). We also use it to
325 * offer free GPU waitboosts for severely congested workloads.
327 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
329 struct idr context_idr;
331 struct intel_rps_client {
332 struct list_head link;
336 struct intel_engine_cs *bsd_ring;
340 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
341 /* real shared dpll ids must be >= 0 */
342 DPLL_ID_PCH_PLL_A = 0,
343 DPLL_ID_PCH_PLL_B = 1,
348 DPLL_ID_SKL_DPLL1 = 0,
349 DPLL_ID_SKL_DPLL2 = 1,
350 DPLL_ID_SKL_DPLL3 = 2,
352 #define I915_NUM_PLLS 3
354 struct intel_dpll_hw_state {
366 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
367 * lower part of ctrl1 and they get shifted into position when writing
368 * the register. This allows us to easily compare the state to share
372 /* HDMI only, 0 when used for DP */
373 uint32_t cfgcr1, cfgcr2;
376 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
380 struct intel_shared_dpll_config {
381 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
382 struct intel_dpll_hw_state hw_state;
385 struct intel_shared_dpll {
386 struct intel_shared_dpll_config config;
388 int active; /* count of number of active CRTCs (i.e. DPMS on) */
389 bool on; /* is the PLL actually active? Disabled during modeset */
391 /* should match the index in the dev_priv->shared_dplls array */
392 enum intel_dpll_id id;
393 /* The mode_set hook is optional and should be used together with the
394 * intel_prepare_shared_dpll function. */
395 void (*mode_set)(struct drm_i915_private *dev_priv,
396 struct intel_shared_dpll *pll);
397 void (*enable)(struct drm_i915_private *dev_priv,
398 struct intel_shared_dpll *pll);
399 void (*disable)(struct drm_i915_private *dev_priv,
400 struct intel_shared_dpll *pll);
401 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
402 struct intel_shared_dpll *pll,
403 struct intel_dpll_hw_state *hw_state);
411 /* Used by dp and fdi links */
412 struct intel_link_m_n {
420 void intel_link_compute_m_n(int bpp, int nlanes,
421 int pixel_clock, int link_clock,
422 struct intel_link_m_n *m_n);
424 /* Interface history:
427 * 1.2: Add Power Management
428 * 1.3: Add vblank support
429 * 1.4: Fix cmdbuffer path, add heap destroy
430 * 1.5: Add vblank pipe configuration
431 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
432 * - Support vertical blank on secondary display pipe
434 #define DRIVER_MAJOR 1
435 #define DRIVER_MINOR 6
436 #define DRIVER_PATCHLEVEL 0
438 #define WATCH_LISTS 0
440 struct opregion_header;
441 struct opregion_acpi;
442 struct opregion_swsci;
443 struct opregion_asle;
445 struct intel_opregion {
446 struct opregion_header __iomem *header;
447 struct opregion_acpi __iomem *acpi;
448 struct opregion_swsci __iomem *swsci;
449 u32 swsci_gbda_sub_functions;
450 u32 swsci_sbcb_sub_functions;
451 struct opregion_asle __iomem *asle;
453 u32 __iomem *lid_state;
454 struct work_struct asle_work;
456 #define OPREGION_SIZE (8*1024)
458 struct intel_overlay;
459 struct intel_overlay_error_state;
461 #define I915_FENCE_REG_NONE -1
462 #define I915_MAX_NUM_FENCES 32
463 /* 32 fences + sign bit for FENCE_REG_NONE */
464 #define I915_MAX_NUM_FENCE_BITS 6
466 struct drm_i915_fence_reg {
467 struct list_head lru_list;
468 struct drm_i915_gem_object *obj;
472 struct sdvo_device_mapping {
481 struct intel_display_error_state;
483 struct drm_i915_error_state {
492 /* Generic register state */
500 u32 error; /* gen6+ */
501 u32 err_int; /* gen7 */
502 u32 fault_data0; /* gen8, gen9 */
503 u32 fault_data1; /* gen8, gen9 */
509 u32 extra_instdone[I915_NUM_INSTDONE_REG];
510 u64 fence[I915_MAX_NUM_FENCES];
511 struct intel_overlay_error_state *overlay;
512 struct intel_display_error_state *display;
513 struct drm_i915_error_object *semaphore_obj;
515 struct drm_i915_error_ring {
517 /* Software tracked state */
520 enum intel_ring_hangcheck_action hangcheck_action;
523 /* our own tracking of ring head and tail */
527 u32 semaphore_seqno[I915_NUM_RINGS - 1];
546 u32 rc_psmi; /* sleep state */
547 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
549 struct drm_i915_error_object {
553 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
555 struct drm_i915_error_request {
570 char comm[TASK_COMM_LEN];
571 } ring[I915_NUM_RINGS];
573 struct drm_i915_error_buffer {
576 u32 rseqno[I915_NUM_RINGS], wseqno;
580 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
588 } **active_bo, **pinned_bo;
590 u32 *active_bo_count, *pinned_bo_count;
594 struct intel_connector;
595 struct intel_encoder;
596 struct intel_crtc_state;
597 struct intel_initial_plane_config;
602 struct drm_i915_display_funcs {
603 int (*get_display_clock_speed)(struct drm_device *dev);
604 int (*get_fifo_size)(struct drm_device *dev, int plane);
606 * find_dpll() - Find the best values for the PLL
607 * @limit: limits for the PLL
608 * @crtc: current CRTC
609 * @target: target frequency in kHz
610 * @refclk: reference clock frequency in kHz
611 * @match_clock: if provided, @best_clock P divider must
612 * match the P divider from @match_clock
613 * used for LVDS downclocking
614 * @best_clock: best PLL values found
616 * Returns true on success, false on failure.
618 bool (*find_dpll)(const struct intel_limit *limit,
619 struct intel_crtc_state *crtc_state,
620 int target, int refclk,
621 struct dpll *match_clock,
622 struct dpll *best_clock);
623 void (*update_wm)(struct drm_crtc *crtc);
624 void (*update_sprite_wm)(struct drm_plane *plane,
625 struct drm_crtc *crtc,
626 uint32_t sprite_width, uint32_t sprite_height,
627 int pixel_size, bool enable, bool scaled);
628 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
629 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
630 /* Returns the active state of the crtc, and if the crtc is active,
631 * fills out the pipe-config with the hw state. */
632 bool (*get_pipe_config)(struct intel_crtc *,
633 struct intel_crtc_state *);
634 void (*get_initial_plane_config)(struct intel_crtc *,
635 struct intel_initial_plane_config *);
636 int (*crtc_compute_clock)(struct intel_crtc *crtc,
637 struct intel_crtc_state *crtc_state);
638 void (*crtc_enable)(struct drm_crtc *crtc);
639 void (*crtc_disable)(struct drm_crtc *crtc);
640 void (*audio_codec_enable)(struct drm_connector *connector,
641 struct intel_encoder *encoder,
642 struct drm_display_mode *mode);
643 void (*audio_codec_disable)(struct intel_encoder *encoder);
644 void (*fdi_link_train)(struct drm_crtc *crtc);
645 void (*init_clock_gating)(struct drm_device *dev);
646 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
647 struct drm_framebuffer *fb,
648 struct drm_i915_gem_object *obj,
649 struct drm_i915_gem_request *req,
651 void (*update_primary_plane)(struct drm_crtc *crtc,
652 struct drm_framebuffer *fb,
654 void (*hpd_irq_setup)(struct drm_device *dev);
655 /* clock updates for mode set */
657 /* render clock increase/decrease */
658 /* display clock increase/decrease */
659 /* pll clock increase/decrease */
661 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
662 uint32_t (*get_backlight)(struct intel_connector *connector);
663 void (*set_backlight)(struct intel_connector *connector,
665 void (*disable_backlight)(struct intel_connector *connector);
666 void (*enable_backlight)(struct intel_connector *connector);
669 enum forcewake_domain_id {
670 FW_DOMAIN_ID_RENDER = 0,
671 FW_DOMAIN_ID_BLITTER,
677 enum forcewake_domains {
678 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
679 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
680 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
681 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
686 struct intel_uncore_funcs {
687 void (*force_wake_get)(struct drm_i915_private *dev_priv,
688 enum forcewake_domains domains);
689 void (*force_wake_put)(struct drm_i915_private *dev_priv,
690 enum forcewake_domains domains);
692 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
693 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
694 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
695 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
697 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
698 uint8_t val, bool trace);
699 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
700 uint16_t val, bool trace);
701 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
702 uint32_t val, bool trace);
703 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
704 uint64_t val, bool trace);
707 struct intel_uncore {
708 spinlock_t lock; /** lock is also taken in irq contexts. */
710 struct intel_uncore_funcs funcs;
713 enum forcewake_domains fw_domains;
715 struct intel_uncore_forcewake_domain {
716 struct drm_i915_private *i915;
717 enum forcewake_domain_id id;
719 struct timer_list timer;
726 } fw_domain[FW_DOMAIN_ID_COUNT];
729 /* Iterate over initialised fw domains */
730 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
731 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
732 (i__) < FW_DOMAIN_ID_COUNT; \
733 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
734 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
736 #define for_each_fw_domain(domain__, dev_priv__, i__) \
737 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
740 FW_UNINITIALIZED = 0,
747 uint32_t *dmc_payload;
748 uint32_t dmc_fw_size;
750 uint32_t mmioaddr[8];
751 uint32_t mmiodata[8];
752 enum csr_state state;
755 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
756 func(is_mobile) sep \
759 func(is_i945gm) sep \
761 func(need_gfx_hws) sep \
763 func(is_pineview) sep \
764 func(is_broadwater) sep \
765 func(is_crestline) sep \
766 func(is_ivybridge) sep \
767 func(is_valleyview) sep \
768 func(is_haswell) sep \
769 func(is_skylake) sep \
770 func(is_preliminary) sep \
772 func(has_pipe_cxsr) sep \
773 func(has_hotplug) sep \
774 func(cursor_needs_physical) sep \
775 func(has_overlay) sep \
776 func(overlay_needs_physical) sep \
777 func(supports_tv) sep \
782 #define DEFINE_FLAG(name) u8 name:1
783 #define SEP_SEMICOLON ;
785 struct intel_device_info {
786 u32 display_mmio_offset;
789 u8 num_sprites[I915_MAX_PIPES];
791 u8 ring_mask; /* Rings supported by the HW */
792 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
793 /* Register offsets for the various display pipes and transcoders */
794 int pipe_offsets[I915_MAX_TRANSCODERS];
795 int trans_offsets[I915_MAX_TRANSCODERS];
796 int palette_offsets[I915_MAX_PIPES];
797 int cursor_offsets[I915_MAX_PIPES];
799 /* Slice/subslice/EU info */
802 u8 subslice_per_slice;
805 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
808 u8 has_subslice_pg:1;
815 enum i915_cache_level {
817 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
818 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
819 caches, eg sampler/render caches, and the
820 large Last-Level-Cache. LLC is coherent with
821 the CPU, but L3 is only visible to the GPU. */
822 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
825 struct i915_ctx_hang_stats {
826 /* This context had batch pending when hang was declared */
827 unsigned batch_pending;
829 /* This context had batch active when hang was declared */
830 unsigned batch_active;
832 /* Time when this context was last blamed for a GPU reset */
833 unsigned long guilty_ts;
835 /* If the contexts causes a second GPU hang within this time,
836 * it is permanently banned from submitting any more work.
838 unsigned long ban_period_seconds;
840 /* This context is banned to submit more work */
844 /* This must match up with the value previously used for execbuf2.rsvd1. */
845 #define DEFAULT_CONTEXT_HANDLE 0
847 #define CONTEXT_NO_ZEROMAP (1<<0)
849 * struct intel_context - as the name implies, represents a context.
850 * @ref: reference count.
851 * @user_handle: userspace tracking identity for this context.
852 * @remap_slice: l3 row remapping information.
853 * @flags: context specific flags:
854 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
855 * @file_priv: filp associated with this context (NULL for global default
857 * @hang_stats: information about the role of this context in possible GPU
859 * @ppgtt: virtual memory space used by this context.
860 * @legacy_hw_ctx: render context backing object and whether it is correctly
861 * initialized (legacy ring submission mechanism only).
862 * @link: link in the global list of contexts.
864 * Contexts are memory images used by the hardware to store copies of their
867 struct intel_context {
871 struct drm_i915_private *i915;
873 struct drm_i915_file_private *file_priv;
874 struct i915_ctx_hang_stats hang_stats;
875 struct i915_hw_ppgtt *ppgtt;
877 /* Legacy ring buffer submission */
879 struct drm_i915_gem_object *rcs_state;
884 bool rcs_initialized;
886 struct drm_i915_gem_object *state;
887 struct intel_ringbuffer *ringbuf;
889 } engine[I915_NUM_RINGS];
891 struct list_head link;
903 /* This is always the inner lock when overlapping with struct_mutex and
904 * it's the outer lock when overlapping with stolen_lock. */
906 unsigned long uncompressed_size;
909 unsigned int possible_framebuffer_bits;
910 unsigned int busy_bits;
911 struct intel_crtc *crtc;
914 struct drm_mm_node compressed_fb;
915 struct drm_mm_node *compressed_llb;
919 /* Tracks whether the HW is actually enabled, not whether the feature is
923 struct intel_fbc_work {
924 struct delayed_work work;
925 struct intel_crtc *crtc;
926 struct drm_framebuffer *fb;
930 FBC_OK, /* FBC is enabled */
931 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
932 FBC_NO_OUTPUT, /* no outputs enabled to compress */
933 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
934 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
935 FBC_MODE_TOO_LARGE, /* mode too large for compression */
936 FBC_BAD_PLANE, /* fbc not supported on plane */
937 FBC_NOT_TILED, /* buffer not tiled */
938 FBC_MULTIPLE_PIPES, /* more than one pipe active */
940 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
941 FBC_ROTATION, /* rotation is not supported */
942 FBC_IN_DBG_MASTER, /* kernel debugger is active */
945 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
946 void (*enable_fbc)(struct intel_crtc *crtc);
947 void (*disable_fbc)(struct drm_i915_private *dev_priv);
951 * HIGH_RR is the highest eDP panel refresh rate read from EDID
952 * LOW_RR is the lowest eDP panel refresh rate found from EDID
953 * parsing for same resolution.
955 enum drrs_refresh_rate_type {
958 DRRS_MAX_RR, /* RR count */
961 enum drrs_support_type {
962 DRRS_NOT_SUPPORTED = 0,
963 STATIC_DRRS_SUPPORT = 1,
964 SEAMLESS_DRRS_SUPPORT = 2
970 struct delayed_work work;
972 unsigned busy_frontbuffer_bits;
973 enum drrs_refresh_rate_type refresh_rate_type;
974 enum drrs_support_type type;
981 struct intel_dp *enabled;
983 struct delayed_work work;
984 unsigned busy_frontbuffer_bits;
990 PCH_NONE = 0, /* No PCH present */
991 PCH_IBX, /* Ibexpeak PCH */
992 PCH_CPT, /* Cougarpoint PCH */
993 PCH_LPT, /* Lynxpoint PCH */
994 PCH_SPT, /* Sunrisepoint PCH */
998 enum intel_sbi_destination {
1003 #define QUIRK_PIPEA_FORCE (1<<0)
1004 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1005 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1006 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1007 #define QUIRK_PIPEB_FORCE (1<<4)
1008 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1011 struct intel_fbc_work;
1013 struct intel_gmbus {
1014 struct i2c_adapter adapter;
1018 struct i2c_algo_bit_data bit_algo;
1019 struct drm_i915_private *dev_priv;
1022 struct i915_suspend_saved_registers {
1025 u32 savePP_ON_DELAYS;
1026 u32 savePP_OFF_DELAYS;
1031 u32 saveFBC_CONTROL;
1032 u32 saveCACHE_MODE_0;
1033 u32 saveMI_ARB_STATE;
1037 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1038 u32 savePCH_PORT_HOTPLUG;
1042 struct vlv_s0ix_state {
1049 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1050 u32 media_max_req_count;
1051 u32 gfx_max_req_count;
1077 u32 rp_down_timeout;
1083 /* Display 1 CZ domain */
1088 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1090 /* GT SA CZ domain */
1097 /* Display 2 CZ domain */
1101 u32 clock_gate_dis2;
1104 struct intel_rps_ei {
1110 struct intel_gen6_power_mgmt {
1112 * work, interrupts_enabled and pm_iir are protected by
1113 * dev_priv->irq_lock
1115 struct work_struct work;
1116 bool interrupts_enabled;
1119 /* Frequencies are stored in potentially platform dependent multiples.
1120 * In other words, *_freq needs to be multiplied by X to be interesting.
1121 * Soft limits are those which are used for the dynamic reclocking done
1122 * by the driver (raise frequencies under heavy loads, and lower for
1123 * lighter loads). Hard limits are those imposed by the hardware.
1125 * A distinction is made for overclocking, which is never enabled by
1126 * default, and is considered to be above the hard limit if it's
1129 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1130 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1131 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1132 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1133 u8 min_freq; /* AKA RPn. Minimum frequency */
1134 u8 idle_freq; /* Frequency to request when we are idle */
1135 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1136 u8 rp1_freq; /* "less than" RP0 power/freqency */
1137 u8 rp0_freq; /* Non-overclocked max frequency. */
1140 u8 up_threshold; /* Current %busy required to uplock */
1141 u8 down_threshold; /* Current %busy required to downclock */
1144 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1146 spinlock_t client_lock;
1147 struct list_head clients;
1151 struct delayed_work delayed_resume_work;
1154 struct intel_rps_client semaphores, mmioflips;
1156 /* manual wa residency calculations */
1157 struct intel_rps_ei up_ei, down_ei;
1160 * Protects RPS/RC6 register access and PCU communication.
1161 * Must be taken after struct_mutex if nested. Note that
1162 * this lock may be held for long periods of time when
1163 * talking to hw - so only take it when talking to hw!
1165 struct mutex hw_lock;
1168 /* defined intel_pm.c */
1169 extern spinlock_t mchdev_lock;
1171 struct intel_ilk_power_mgmt {
1179 unsigned long last_time1;
1180 unsigned long chipset_power;
1183 unsigned long gfx_power;
1190 struct drm_i915_private;
1191 struct i915_power_well;
1193 struct i915_power_well_ops {
1195 * Synchronize the well's hw state to match the current sw state, for
1196 * example enable/disable it based on the current refcount. Called
1197 * during driver init and resume time, possibly after first calling
1198 * the enable/disable handlers.
1200 void (*sync_hw)(struct drm_i915_private *dev_priv,
1201 struct i915_power_well *power_well);
1203 * Enable the well and resources that depend on it (for example
1204 * interrupts located on the well). Called after the 0->1 refcount
1207 void (*enable)(struct drm_i915_private *dev_priv,
1208 struct i915_power_well *power_well);
1210 * Disable the well and resources that depend on it. Called after
1211 * the 1->0 refcount transition.
1213 void (*disable)(struct drm_i915_private *dev_priv,
1214 struct i915_power_well *power_well);
1215 /* Returns the hw enabled state. */
1216 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1217 struct i915_power_well *power_well);
1220 /* Power well structure for haswell */
1221 struct i915_power_well {
1224 /* power well enable/disable usage count */
1226 /* cached hw enabled state */
1228 unsigned long domains;
1230 const struct i915_power_well_ops *ops;
1233 struct i915_power_domains {
1235 * Power wells needed for initialization at driver init and suspend
1236 * time are on. They are kept on until after the first modeset.
1240 int power_well_count;
1243 int domain_use_count[POWER_DOMAIN_NUM];
1244 struct i915_power_well *power_wells;
1247 #define MAX_L3_SLICES 2
1248 struct intel_l3_parity {
1249 u32 *remap_info[MAX_L3_SLICES];
1250 struct work_struct error_work;
1254 struct i915_gem_mm {
1255 /** Memory allocator for GTT stolen memory */
1256 struct drm_mm stolen;
1257 /** Protects the usage of the GTT stolen memory allocator. This is
1258 * always the inner lock when overlapping with struct_mutex. */
1259 struct mutex stolen_lock;
1261 /** List of all objects in gtt_space. Used to restore gtt
1262 * mappings on resume */
1263 struct list_head bound_list;
1265 * List of objects which are not bound to the GTT (thus
1266 * are idle and not used by the GPU) but still have
1267 * (presumably uncached) pages still attached.
1269 struct list_head unbound_list;
1271 /** Usable portion of the GTT for GEM */
1272 unsigned long stolen_base; /* limited to low memory (32-bit) */
1274 /** PPGTT used for aliasing the PPGTT with the GTT */
1275 struct i915_hw_ppgtt *aliasing_ppgtt;
1277 struct notifier_block oom_notifier;
1278 struct shrinker shrinker;
1279 bool shrinker_no_lock_stealing;
1281 /** LRU list of objects with fence regs on them. */
1282 struct list_head fence_list;
1285 * We leave the user IRQ off as much as possible,
1286 * but this means that requests will finish and never
1287 * be retired once the system goes idle. Set a timer to
1288 * fire periodically while the ring is running. When it
1289 * fires, go retire requests.
1291 struct delayed_work retire_work;
1294 * When we detect an idle GPU, we want to turn on
1295 * powersaving features. So once we see that there
1296 * are no more requests outstanding and no more
1297 * arrive within a small period of time, we fire
1298 * off the idle_work.
1300 struct delayed_work idle_work;
1303 * Are we in a non-interruptible section of code like
1309 * Is the GPU currently considered idle, or busy executing userspace
1310 * requests? Whilst idle, we attempt to power down the hardware and
1311 * display clocks. In order to reduce the effect on performance, there
1312 * is a slight delay before we do so.
1316 /* the indicator for dispatch video commands on two BSD rings */
1317 int bsd_ring_dispatch_index;
1319 /** Bit 6 swizzling required for X tiling */
1320 uint32_t bit_6_swizzle_x;
1321 /** Bit 6 swizzling required for Y tiling */
1322 uint32_t bit_6_swizzle_y;
1324 /* accounting, useful for userland debugging */
1325 spinlock_t object_stat_lock;
1326 size_t object_memory;
1330 struct drm_i915_error_state_buf {
1331 struct drm_i915_private *i915;
1340 struct i915_error_state_file_priv {
1341 struct drm_device *dev;
1342 struct drm_i915_error_state *error;
1345 struct i915_gpu_error {
1346 /* For hangcheck timer */
1347 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1348 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1349 /* Hang gpu twice in this window and your context gets banned */
1350 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1352 struct workqueue_struct *hangcheck_wq;
1353 struct delayed_work hangcheck_work;
1355 /* For reset and error_state handling. */
1357 /* Protected by the above dev->gpu_error.lock. */
1358 struct drm_i915_error_state *first_error;
1360 unsigned long missed_irq_rings;
1363 * State variable controlling the reset flow and count
1365 * This is a counter which gets incremented when reset is triggered,
1366 * and again when reset has been handled. So odd values (lowest bit set)
1367 * means that reset is in progress and even values that
1368 * (reset_counter >> 1):th reset was successfully completed.
1370 * If reset is not completed succesfully, the I915_WEDGE bit is
1371 * set meaning that hardware is terminally sour and there is no
1372 * recovery. All waiters on the reset_queue will be woken when
1375 * This counter is used by the wait_seqno code to notice that reset
1376 * event happened and it needs to restart the entire ioctl (since most
1377 * likely the seqno it waited for won't ever signal anytime soon).
1379 * This is important for lock-free wait paths, where no contended lock
1380 * naturally enforces the correct ordering between the bail-out of the
1381 * waiter and the gpu reset work code.
1383 atomic_t reset_counter;
1385 #define I915_RESET_IN_PROGRESS_FLAG 1
1386 #define I915_WEDGED (1 << 31)
1389 * Waitqueue to signal when the reset has completed. Used by clients
1390 * that wait for dev_priv->mm.wedged to settle.
1392 wait_queue_head_t reset_queue;
1394 /* Userspace knobs for gpu hang simulation;
1395 * combines both a ring mask, and extra flags
1398 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1399 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1401 /* For missed irq/seqno simulation. */
1402 unsigned int test_irq_rings;
1404 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1405 bool reload_in_reset;
1408 enum modeset_restore {
1409 MODESET_ON_LID_OPEN,
1414 #define DP_AUX_A 0x40
1415 #define DP_AUX_B 0x10
1416 #define DP_AUX_C 0x20
1417 #define DP_AUX_D 0x30
1419 struct ddi_vbt_port_info {
1421 * This is an index in the HDMI/DVI DDI buffer translation table.
1422 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1423 * populate this field.
1425 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1426 uint8_t hdmi_level_shift;
1428 uint8_t supports_dvi:1;
1429 uint8_t supports_hdmi:1;
1430 uint8_t supports_dp:1;
1432 uint8_t alternate_aux_channel;
1434 uint8_t dp_boost_level;
1435 uint8_t hdmi_boost_level;
1438 enum psr_lines_to_wait {
1439 PSR_0_LINES_TO_WAIT = 0,
1441 PSR_4_LINES_TO_WAIT,
1445 struct intel_vbt_data {
1446 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1447 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1450 unsigned int int_tv_support:1;
1451 unsigned int lvds_dither:1;
1452 unsigned int lvds_vbt:1;
1453 unsigned int int_crt_support:1;
1454 unsigned int lvds_use_ssc:1;
1455 unsigned int display_clock_mode:1;
1456 unsigned int fdi_rx_polarity_inverted:1;
1457 unsigned int has_mipi:1;
1459 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1461 enum drrs_support_type drrs_type;
1466 int edp_preemphasis;
1468 bool edp_initialized;
1471 struct edp_power_seq edp_pps;
1475 bool require_aux_wakeup;
1477 enum psr_lines_to_wait lines_to_wait;
1478 int tp1_wakeup_time;
1479 int tp2_tp3_wakeup_time;
1485 bool active_low_pwm;
1486 u8 min_brightness; /* min_brightness/255 of max */
1493 struct mipi_config *config;
1494 struct mipi_pps_data *pps;
1498 u8 *sequence[MIPI_SEQ_MAX];
1504 union child_device_config *child_dev;
1506 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1509 enum intel_ddb_partitioning {
1511 INTEL_DDB_PART_5_6, /* IVB+ */
1514 struct intel_wm_level {
1522 struct ilk_wm_values {
1523 uint32_t wm_pipe[3];
1525 uint32_t wm_lp_spr[3];
1526 uint32_t wm_linetime[3];
1528 enum intel_ddb_partitioning partitioning;
1531 struct vlv_pipe_wm {
1542 struct vlv_wm_values {
1543 struct vlv_pipe_wm pipe[3];
1544 struct vlv_sr_wm sr;
1554 struct skl_ddb_entry {
1555 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1558 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1560 return entry->end - entry->start;
1563 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1564 const struct skl_ddb_entry *e2)
1566 if (e1->start == e2->start && e1->end == e2->end)
1572 struct skl_ddb_allocation {
1573 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1574 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1575 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1576 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1579 struct skl_wm_values {
1580 bool dirty[I915_MAX_PIPES];
1581 struct skl_ddb_allocation ddb;
1582 uint32_t wm_linetime[I915_MAX_PIPES];
1583 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1584 uint32_t cursor[I915_MAX_PIPES][8];
1585 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1586 uint32_t cursor_trans[I915_MAX_PIPES];
1589 struct skl_wm_level {
1590 bool plane_en[I915_MAX_PLANES];
1592 uint16_t plane_res_b[I915_MAX_PLANES];
1593 uint8_t plane_res_l[I915_MAX_PLANES];
1594 uint16_t cursor_res_b;
1595 uint8_t cursor_res_l;
1599 * This struct helps tracking the state needed for runtime PM, which puts the
1600 * device in PCI D3 state. Notice that when this happens, nothing on the
1601 * graphics device works, even register access, so we don't get interrupts nor
1604 * Every piece of our code that needs to actually touch the hardware needs to
1605 * either call intel_runtime_pm_get or call intel_display_power_get with the
1606 * appropriate power domain.
1608 * Our driver uses the autosuspend delay feature, which means we'll only really
1609 * suspend if we stay with zero refcount for a certain amount of time. The
1610 * default value is currently very conservative (see intel_runtime_pm_enable), but
1611 * it can be changed with the standard runtime PM files from sysfs.
1613 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1614 * goes back to false exactly before we reenable the IRQs. We use this variable
1615 * to check if someone is trying to enable/disable IRQs while they're supposed
1616 * to be disabled. This shouldn't happen and we'll print some error messages in
1619 * For more, read the Documentation/power/runtime_pm.txt.
1621 struct i915_runtime_pm {
1626 enum intel_pipe_crc_source {
1627 INTEL_PIPE_CRC_SOURCE_NONE,
1628 INTEL_PIPE_CRC_SOURCE_PLANE1,
1629 INTEL_PIPE_CRC_SOURCE_PLANE2,
1630 INTEL_PIPE_CRC_SOURCE_PF,
1631 INTEL_PIPE_CRC_SOURCE_PIPE,
1632 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1633 INTEL_PIPE_CRC_SOURCE_TV,
1634 INTEL_PIPE_CRC_SOURCE_DP_B,
1635 INTEL_PIPE_CRC_SOURCE_DP_C,
1636 INTEL_PIPE_CRC_SOURCE_DP_D,
1637 INTEL_PIPE_CRC_SOURCE_AUTO,
1638 INTEL_PIPE_CRC_SOURCE_MAX,
1641 struct intel_pipe_crc_entry {
1646 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1647 struct intel_pipe_crc {
1649 bool opened; /* exclusive access to the result file */
1650 struct intel_pipe_crc_entry *entries;
1651 enum intel_pipe_crc_source source;
1653 wait_queue_head_t wq;
1656 struct i915_frontbuffer_tracking {
1660 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1667 struct i915_wa_reg {
1670 /* bitmask representing WA bits */
1674 #define I915_MAX_WA_REGS 16
1676 struct i915_workarounds {
1677 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1681 struct i915_virtual_gpu {
1685 struct i915_execbuffer_params {
1686 struct drm_device *dev;
1687 struct drm_file *file;
1688 uint32_t dispatch_flags;
1689 uint32_t args_batch_start_offset;
1690 uint64_t batch_obj_vm_offset;
1691 struct intel_engine_cs *ring;
1692 struct drm_i915_gem_object *batch_obj;
1693 struct intel_context *ctx;
1694 struct drm_i915_gem_request *request;
1697 struct drm_i915_private {
1698 struct drm_device *dev;
1699 struct kmem_cache *objects;
1700 struct kmem_cache *vmas;
1701 struct kmem_cache *requests;
1703 const struct intel_device_info info;
1705 int relative_constants_mode;
1709 struct intel_uncore uncore;
1711 struct i915_virtual_gpu vgpu;
1713 struct intel_guc guc;
1715 struct intel_csr csr;
1717 /* Display CSR-related protection */
1718 struct mutex csr_lock;
1720 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1722 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1723 * controller on different i2c buses. */
1724 struct mutex gmbus_mutex;
1727 * Base address of the gmbus and gpio block.
1729 uint32_t gpio_mmio_base;
1731 /* MMIO base address for MIPI regs */
1732 uint32_t mipi_mmio_base;
1734 wait_queue_head_t gmbus_wait_queue;
1736 struct pci_dev *bridge_dev;
1737 struct intel_engine_cs ring[I915_NUM_RINGS];
1738 struct drm_i915_gem_object *semaphore_obj;
1739 uint32_t last_seqno, next_seqno;
1741 struct drm_dma_handle *status_page_dmah;
1742 struct resource mch_res;
1744 /* protects the irq masks */
1745 spinlock_t irq_lock;
1747 /* protects the mmio flip data */
1748 spinlock_t mmio_flip_lock;
1750 bool display_irqs_enabled;
1752 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1753 struct pm_qos_request pm_qos;
1755 /* Sideband mailbox protection */
1756 struct mutex sb_lock;
1758 /** Cached value of IMR to avoid reads in updating the bitfield */
1761 u32 de_irq_mask[I915_MAX_PIPES];
1766 u32 pipestat_irq_mask[I915_MAX_PIPES];
1768 struct i915_hotplug hotplug;
1769 struct i915_fbc fbc;
1770 struct i915_drrs drrs;
1771 struct intel_opregion opregion;
1772 struct intel_vbt_data vbt;
1774 bool preserve_bios_swizzle;
1777 struct intel_overlay *overlay;
1779 /* backlight registers and fields in struct intel_panel */
1780 struct mutex backlight_lock;
1783 bool no_aux_handshake;
1785 /* protects panel power sequencer state */
1786 struct mutex pps_mutex;
1788 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1789 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1790 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1792 unsigned int fsb_freq, mem_freq, is_ddr3;
1793 unsigned int skl_boot_cdclk;
1794 unsigned int cdclk_freq, max_cdclk_freq;
1795 unsigned int hpll_freq;
1798 * wq - Driver workqueue for GEM.
1800 * NOTE: Work items scheduled here are not allowed to grab any modeset
1801 * locks, for otherwise the flushing done in the pageflip code will
1802 * result in deadlocks.
1804 struct workqueue_struct *wq;
1806 /* Display functions */
1807 struct drm_i915_display_funcs display;
1809 /* PCH chipset type */
1810 enum intel_pch pch_type;
1811 unsigned short pch_id;
1813 unsigned long quirks;
1815 enum modeset_restore modeset_restore;
1816 struct mutex modeset_restore_lock;
1818 struct list_head vm_list; /* Global list of all address spaces */
1819 struct i915_gtt gtt; /* VM representing the global address space */
1821 struct i915_gem_mm mm;
1822 DECLARE_HASHTABLE(mm_structs, 7);
1823 struct mutex mm_lock;
1825 /* Kernel Modesetting */
1827 struct sdvo_device_mapping sdvo_mappings[2];
1829 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1830 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1831 wait_queue_head_t pending_flip_queue;
1833 #ifdef CONFIG_DEBUG_FS
1834 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1837 int num_shared_dpll;
1838 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1839 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1841 struct i915_workarounds workarounds;
1843 /* Reclocking support */
1844 bool render_reclock_avail;
1846 struct i915_frontbuffer_tracking fb_tracking;
1850 bool mchbar_need_disable;
1852 struct intel_l3_parity l3_parity;
1854 /* Cannot be determined by PCIID. You must always read a register. */
1857 /* gen6+ rps state */
1858 struct intel_gen6_power_mgmt rps;
1860 /* ilk-only ips/rps state. Everything in here is protected by the global
1861 * mchdev_lock in intel_pm.c */
1862 struct intel_ilk_power_mgmt ips;
1864 struct i915_power_domains power_domains;
1866 struct i915_psr psr;
1868 struct i915_gpu_error gpu_error;
1870 struct drm_i915_gem_object *vlv_pctx;
1872 #ifdef CONFIG_DRM_I915_FBDEV
1873 /* list of fbdev register on this device */
1874 struct intel_fbdev *fbdev;
1875 struct work_struct fbdev_suspend_work;
1878 struct drm_property *broadcast_rgb_property;
1879 struct drm_property *force_audio_property;
1881 /* hda/i915 audio component */
1882 bool audio_component_registered;
1884 uint32_t hw_context_size;
1885 struct list_head context_list;
1889 u32 chv_phy_control;
1892 struct i915_suspend_saved_registers regfile;
1893 struct vlv_s0ix_state vlv_s0ix_state;
1897 * Raw watermark latency values:
1898 * in 0.1us units for WM0,
1899 * in 0.5us units for WM1+.
1902 uint16_t pri_latency[5];
1904 uint16_t spr_latency[5];
1906 uint16_t cur_latency[5];
1908 * Raw watermark memory latency values
1909 * for SKL for all 8 levels
1912 uint16_t skl_latency[8];
1915 * The skl_wm_values structure is a bit too big for stack
1916 * allocation, so we keep the staging struct where we store
1917 * intermediate results here instead.
1919 struct skl_wm_values skl_results;
1921 /* current hardware state */
1923 struct ilk_wm_values hw;
1924 struct skl_wm_values skl_hw;
1925 struct vlv_wm_values vlv;
1929 struct i915_runtime_pm pm;
1931 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1933 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1934 struct drm_i915_gem_execbuffer2 *args,
1935 struct list_head *vmas);
1936 int (*init_rings)(struct drm_device *dev);
1937 void (*cleanup_ring)(struct intel_engine_cs *ring);
1938 void (*stop_ring)(struct intel_engine_cs *ring);
1941 bool edp_low_vswing;
1944 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1945 * will be rejected. Instead look for a better place.
1949 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1951 return dev->dev_private;
1954 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1956 return to_i915(dev_get_drvdata(dev));
1959 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1961 return container_of(guc, struct drm_i915_private, guc);
1964 /* Iterate over initialised rings */
1965 #define for_each_ring(ring__, dev_priv__, i__) \
1966 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1967 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1969 enum hdmi_force_audio {
1970 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1971 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1972 HDMI_AUDIO_AUTO, /* trust EDID */
1973 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1976 #define I915_GTT_OFFSET_NONE ((u32)-1)
1978 struct drm_i915_gem_object_ops {
1979 /* Interface between the GEM object and its backing storage.
1980 * get_pages() is called once prior to the use of the associated set
1981 * of pages before to binding them into the GTT, and put_pages() is
1982 * called after we no longer need them. As we expect there to be
1983 * associated cost with migrating pages between the backing storage
1984 * and making them available for the GPU (e.g. clflush), we may hold
1985 * onto the pages after they are no longer referenced by the GPU
1986 * in case they may be used again shortly (for example migrating the
1987 * pages to a different memory domain within the GTT). put_pages()
1988 * will therefore most likely be called when the object itself is
1989 * being released or under memory pressure (where we attempt to
1990 * reap pages for the shrinker).
1992 int (*get_pages)(struct drm_i915_gem_object *);
1993 void (*put_pages)(struct drm_i915_gem_object *);
1994 int (*dmabuf_export)(struct drm_i915_gem_object *);
1995 void (*release)(struct drm_i915_gem_object *);
1999 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2000 * considered to be the frontbuffer for the given plane interface-vise. This
2001 * doesn't mean that the hw necessarily already scans it out, but that any
2002 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2004 * We have one bit per pipe and per scanout plane type.
2006 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
2007 #define INTEL_FRONTBUFFER_BITS \
2008 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2009 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2010 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2011 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2012 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2013 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
2014 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2015 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2016 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2017 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2018 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2020 struct drm_i915_gem_object {
2021 struct drm_gem_object base;
2023 const struct drm_i915_gem_object_ops *ops;
2025 /** List of VMAs backed by this object */
2026 struct list_head vma_list;
2028 /** Stolen memory for this object, instead of being backed by shmem. */
2029 struct drm_mm_node *stolen;
2030 struct list_head global_list;
2032 struct list_head ring_list[I915_NUM_RINGS];
2033 /** Used in execbuf to temporarily hold a ref */
2034 struct list_head obj_exec_link;
2036 struct list_head batch_pool_link;
2039 * This is set if the object is on the active lists (has pending
2040 * rendering and so a non-zero seqno), and is not set if it i s on
2041 * inactive (ready to be unbound) list.
2043 unsigned int active:I915_NUM_RINGS;
2046 * This is set if the object has been written to since last bound
2049 unsigned int dirty:1;
2052 * Fence register bits (if any) for this object. Will be set
2053 * as needed when mapped into the GTT.
2054 * Protected by dev->struct_mutex.
2056 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2059 * Advice: are the backing pages purgeable?
2061 unsigned int madv:2;
2064 * Current tiling mode for the object.
2066 unsigned int tiling_mode:2;
2068 * Whether the tiling parameters for the currently associated fence
2069 * register have changed. Note that for the purposes of tracking
2070 * tiling changes we also treat the unfenced register, the register
2071 * slot that the object occupies whilst it executes a fenced
2072 * command (such as BLT on gen2/3), as a "fence".
2074 unsigned int fence_dirty:1;
2077 * Is the object at the current location in the gtt mappable and
2078 * fenceable? Used to avoid costly recalculations.
2080 unsigned int map_and_fenceable:1;
2083 * Whether the current gtt mapping needs to be mappable (and isn't just
2084 * mappable by accident). Track pin and fault separate for a more
2085 * accurate mappable working set.
2087 unsigned int fault_mappable:1;
2090 * Is the object to be mapped as read-only to the GPU
2091 * Only honoured if hardware has relevant pte bit
2093 unsigned long gt_ro:1;
2094 unsigned int cache_level:3;
2095 unsigned int cache_dirty:1;
2097 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2099 unsigned int pin_display;
2101 struct sg_table *pages;
2102 int pages_pin_count;
2104 struct scatterlist *sg;
2108 /* prime dma-buf support */
2109 void *dma_buf_vmapping;
2112 /** Breadcrumb of last rendering to the buffer.
2113 * There can only be one writer, but we allow for multiple readers.
2114 * If there is a writer that necessarily implies that all other
2115 * read requests are complete - but we may only be lazily clearing
2116 * the read requests. A read request is naturally the most recent
2117 * request on a ring, so we may have two different write and read
2118 * requests on one ring where the write request is older than the
2119 * read request. This allows for the CPU to read from an active
2120 * buffer by only waiting for the write to complete.
2122 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2123 struct drm_i915_gem_request *last_write_req;
2124 /** Breadcrumb of last fenced GPU access to the buffer. */
2125 struct drm_i915_gem_request *last_fenced_req;
2127 /** Current tiling stride for the object, if it's tiled. */
2130 /** References from framebuffers, locks out tiling changes. */
2131 unsigned long framebuffer_references;
2133 /** Record of address bit 17 of each page at last unbind. */
2134 unsigned long *bit_17;
2137 /** for phy allocated objects */
2138 struct drm_dma_handle *phys_handle;
2140 struct i915_gem_userptr {
2142 unsigned read_only :1;
2143 unsigned workers :4;
2144 #define I915_GEM_USERPTR_MAX_WORKERS 15
2146 struct i915_mm_struct *mm;
2147 struct i915_mmu_object *mmu_object;
2148 struct work_struct *work;
2152 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2154 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2155 struct drm_i915_gem_object *new,
2156 unsigned frontbuffer_bits);
2159 * Request queue structure.
2161 * The request queue allows us to note sequence numbers that have been emitted
2162 * and may be associated with active buffers to be retired.
2164 * By keeping this list, we can avoid having to do questionable sequence
2165 * number comparisons on buffer last_read|write_seqno. It also allows an
2166 * emission time to be associated with the request for tracking how far ahead
2167 * of the GPU the submission is.
2169 * The requests are reference counted, so upon creation they should have an
2170 * initial reference taken using kref_init
2172 struct drm_i915_gem_request {
2175 /** On Which ring this request was generated */
2176 struct drm_i915_private *i915;
2177 struct intel_engine_cs *ring;
2179 /** GEM sequence number associated with this request. */
2182 /** Position in the ringbuffer of the start of the request */
2186 * Position in the ringbuffer of the start of the postfix.
2187 * This is required to calculate the maximum available ringbuffer
2188 * space without overwriting the postfix.
2192 /** Position in the ringbuffer of the end of the whole request */
2196 * Context and ring buffer related to this request
2197 * Contexts are refcounted, so when this request is associated with a
2198 * context, we must increment the context's refcount, to guarantee that
2199 * it persists while any request is linked to it. Requests themselves
2200 * are also refcounted, so the request will only be freed when the last
2201 * reference to it is dismissed, and the code in
2202 * i915_gem_request_free() will then decrement the refcount on the
2205 struct intel_context *ctx;
2206 struct intel_ringbuffer *ringbuf;
2208 /** Batch buffer related to this request if any (used for
2209 error state dump only) */
2210 struct drm_i915_gem_object *batch_obj;
2212 /** Time at which this request was emitted, in jiffies. */
2213 unsigned long emitted_jiffies;
2215 /** global list entry for this request */
2216 struct list_head list;
2218 struct drm_i915_file_private *file_priv;
2219 /** file_priv list entry for this request */
2220 struct list_head client_list;
2222 /** process identifier submitting this request */
2226 * The ELSP only accepts two elements at a time, so we queue
2227 * context/tail pairs on a given queue (ring->execlist_queue) until the
2228 * hardware is available. The queue serves a double purpose: we also use
2229 * it to keep track of the up to 2 contexts currently in the hardware
2230 * (usually one in execution and the other queued up by the GPU): We
2231 * only remove elements from the head of the queue when the hardware
2232 * informs us that an element has been completed.
2234 * All accesses to the queue are mediated by a spinlock
2235 * (ring->execlist_lock).
2238 /** Execlist link in the submission queue.*/
2239 struct list_head execlist_link;
2241 /** Execlists no. of times this request has been sent to the ELSP */
2246 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2247 struct intel_context *ctx,
2248 struct drm_i915_gem_request **req_out);
2249 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2250 void i915_gem_request_free(struct kref *req_ref);
2251 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2252 struct drm_file *file);
2254 static inline uint32_t
2255 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2257 return req ? req->seqno : 0;
2260 static inline struct intel_engine_cs *
2261 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2263 return req ? req->ring : NULL;
2266 static inline struct drm_i915_gem_request *
2267 i915_gem_request_reference(struct drm_i915_gem_request *req)
2270 kref_get(&req->ref);
2275 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2277 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2278 kref_put(&req->ref, i915_gem_request_free);
2282 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2284 struct drm_device *dev;
2289 dev = req->ring->dev;
2290 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2291 mutex_unlock(&dev->struct_mutex);
2294 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2295 struct drm_i915_gem_request *src)
2298 i915_gem_request_reference(src);
2301 i915_gem_request_unreference(*pdst);
2307 * XXX: i915_gem_request_completed should be here but currently needs the
2308 * definition of i915_seqno_passed() which is below. It will be moved in
2309 * a later patch when the call to i915_seqno_passed() is obsoleted...
2313 * A command that requires special handling by the command parser.
2315 struct drm_i915_cmd_descriptor {
2317 * Flags describing how the command parser processes the command.
2319 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2320 * a length mask if not set
2321 * CMD_DESC_SKIP: The command is allowed but does not follow the
2322 * standard length encoding for the opcode range in
2324 * CMD_DESC_REJECT: The command is never allowed
2325 * CMD_DESC_REGISTER: The command should be checked against the
2326 * register whitelist for the appropriate ring
2327 * CMD_DESC_MASTER: The command is allowed if the submitting process
2331 #define CMD_DESC_FIXED (1<<0)
2332 #define CMD_DESC_SKIP (1<<1)
2333 #define CMD_DESC_REJECT (1<<2)
2334 #define CMD_DESC_REGISTER (1<<3)
2335 #define CMD_DESC_BITMASK (1<<4)
2336 #define CMD_DESC_MASTER (1<<5)
2339 * The command's unique identification bits and the bitmask to get them.
2340 * This isn't strictly the opcode field as defined in the spec and may
2341 * also include type, subtype, and/or subop fields.
2349 * The command's length. The command is either fixed length (i.e. does
2350 * not include a length field) or has a length field mask. The flag
2351 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2352 * a length mask. All command entries in a command table must include
2353 * length information.
2361 * Describes where to find a register address in the command to check
2362 * against the ring's register whitelist. Only valid if flags has the
2363 * CMD_DESC_REGISTER bit set.
2365 * A non-zero step value implies that the command may access multiple
2366 * registers in sequence (e.g. LRI), in that case step gives the
2367 * distance in dwords between individual offset fields.
2375 #define MAX_CMD_DESC_BITMASKS 3
2377 * Describes command checks where a particular dword is masked and
2378 * compared against an expected value. If the command does not match
2379 * the expected value, the parser rejects it. Only valid if flags has
2380 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2383 * If the check specifies a non-zero condition_mask then the parser
2384 * only performs the check when the bits specified by condition_mask
2391 u32 condition_offset;
2393 } bits[MAX_CMD_DESC_BITMASKS];
2397 * A table of commands requiring special handling by the command parser.
2399 * Each ring has an array of tables. Each table consists of an array of command
2400 * descriptors, which must be sorted with command opcodes in ascending order.
2402 struct drm_i915_cmd_table {
2403 const struct drm_i915_cmd_descriptor *table;
2407 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2408 #define __I915__(p) ({ \
2409 struct drm_i915_private *__p; \
2410 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2411 __p = (struct drm_i915_private *)p; \
2412 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2413 __p = to_i915((struct drm_device *)p); \
2418 #define INTEL_INFO(p) (&__I915__(p)->info)
2419 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2420 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2422 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2423 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2424 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2425 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2426 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2427 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2428 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2429 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2430 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2431 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2432 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2433 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2434 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2435 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2436 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2437 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2438 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2439 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2440 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2441 INTEL_DEVID(dev) == 0x0152 || \
2442 INTEL_DEVID(dev) == 0x015a)
2443 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2444 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2445 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2446 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2447 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2448 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2449 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2450 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2451 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2452 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2453 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2454 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2455 (INTEL_DEVID(dev) & 0xf) == 0xe))
2456 /* ULX machines are also considered ULT. */
2457 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2458 (INTEL_DEVID(dev) & 0xf) == 0xe)
2459 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2460 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2461 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2462 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2463 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2464 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2465 /* ULX machines are also considered ULT. */
2466 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2467 INTEL_DEVID(dev) == 0x0A1E)
2468 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2469 INTEL_DEVID(dev) == 0x1913 || \
2470 INTEL_DEVID(dev) == 0x1916 || \
2471 INTEL_DEVID(dev) == 0x1921 || \
2472 INTEL_DEVID(dev) == 0x1926)
2473 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2474 INTEL_DEVID(dev) == 0x1915 || \
2475 INTEL_DEVID(dev) == 0x191E)
2476 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2478 #define SKL_REVID_A0 (0x0)
2479 #define SKL_REVID_B0 (0x1)
2480 #define SKL_REVID_C0 (0x2)
2481 #define SKL_REVID_D0 (0x3)
2482 #define SKL_REVID_E0 (0x4)
2483 #define SKL_REVID_F0 (0x5)
2485 #define BXT_REVID_A0 (0x0)
2486 #define BXT_REVID_B0 (0x3)
2487 #define BXT_REVID_C0 (0x6)
2490 * The genX designation typically refers to the render engine, so render
2491 * capability related checks should use IS_GEN, while display and other checks
2492 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2495 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2496 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2497 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2498 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2499 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2500 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2501 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2502 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2504 #define RENDER_RING (1<<RCS)
2505 #define BSD_RING (1<<VCS)
2506 #define BLT_RING (1<<BCS)
2507 #define VEBOX_RING (1<<VECS)
2508 #define BSD2_RING (1<<VCS2)
2509 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2510 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2511 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2512 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2513 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2514 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2515 __I915__(dev)->ellc_size)
2516 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2518 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2519 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2520 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2521 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2522 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2524 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2525 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2527 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2528 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2530 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2531 * even when in MSI mode. This results in spurious interrupt warnings if the
2532 * legacy irq no. is shared with another device. The kernel then disables that
2533 * interrupt source and so prevents the other device from working properly.
2535 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2536 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2538 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2539 * rows, which changed the alignment requirements and fence programming.
2541 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2543 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2544 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2546 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2547 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2548 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2550 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2552 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2553 INTEL_INFO(dev)->gen >= 9)
2555 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2556 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2557 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2558 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2560 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2561 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2563 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2564 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2566 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2568 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2569 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2571 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2572 INTEL_INFO(dev)->gen >= 8)
2574 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2575 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2577 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2578 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2579 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2580 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2581 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2582 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2583 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2584 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2586 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2587 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2588 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2589 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2590 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2591 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2592 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2594 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2596 /* DPF == dynamic parity feature */
2597 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2598 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2600 #define GT_FREQUENCY_MULTIPLIER 50
2601 #define GEN9_FREQ_SCALER 3
2603 #include "i915_trace.h"
2605 extern const struct drm_ioctl_desc i915_ioctls[];
2606 extern int i915_max_ioctl;
2608 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2609 extern int i915_resume_legacy(struct drm_device *dev);
2612 struct i915_params {
2614 int panel_ignore_lid;
2616 int lvds_channel_mode;
2618 int vbt_sdvo_panel_type;
2622 int enable_execlists;
2624 unsigned int preliminary_hw_support;
2625 int disable_power_well;
2627 int invert_brightness;
2628 int enable_cmd_parser;
2629 /* leave bools at the end to not create holes */
2630 bool enable_hangcheck;
2632 bool prefault_disable;
2633 bool load_detect_test;
2635 bool disable_display;
2636 bool disable_vtd_wa;
2637 bool enable_guc_submission;
2641 bool verbose_state_checks;
2644 extern struct i915_params i915 __read_mostly;
2647 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2648 extern int i915_driver_unload(struct drm_device *);
2649 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2650 extern void i915_driver_lastclose(struct drm_device * dev);
2651 extern void i915_driver_preclose(struct drm_device *dev,
2652 struct drm_file *file);
2653 extern void i915_driver_postclose(struct drm_device *dev,
2654 struct drm_file *file);
2655 #ifdef CONFIG_COMPAT
2656 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2659 extern int intel_gpu_reset(struct drm_device *dev);
2660 extern bool intel_has_gpu_reset(struct drm_device *dev);
2661 extern int i915_reset(struct drm_device *dev);
2662 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2663 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2664 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2665 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2666 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2667 void i915_firmware_load_error_print(const char *fw_path, int err);
2669 /* intel_hotplug.c */
2670 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2671 void intel_hpd_init(struct drm_i915_private *dev_priv);
2672 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2673 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2674 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2677 void i915_queue_hangcheck(struct drm_device *dev);
2679 void i915_handle_error(struct drm_device *dev, bool wedged,
2680 const char *fmt, ...);
2682 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2683 int intel_irq_install(struct drm_i915_private *dev_priv);
2684 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2686 extern void intel_uncore_sanitize(struct drm_device *dev);
2687 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2688 bool restore_forcewake);
2689 extern void intel_uncore_init(struct drm_device *dev);
2690 extern void intel_uncore_check_errors(struct drm_device *dev);
2691 extern void intel_uncore_fini(struct drm_device *dev);
2692 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2693 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2694 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2695 enum forcewake_domains domains);
2696 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2697 enum forcewake_domains domains);
2698 /* Like above but the caller must manage the uncore.lock itself.
2699 * Must be used with I915_READ_FW and friends.
2701 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2702 enum forcewake_domains domains);
2703 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2704 enum forcewake_domains domains);
2705 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2706 static inline bool intel_vgpu_active(struct drm_device *dev)
2708 return to_i915(dev)->vgpu.active;
2712 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2716 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2719 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2720 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2722 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2724 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2725 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2726 uint32_t interrupt_mask,
2727 uint32_t enabled_irq_mask);
2728 #define ibx_enable_display_interrupt(dev_priv, bits) \
2729 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2730 #define ibx_disable_display_interrupt(dev_priv, bits) \
2731 ibx_display_interrupt_update((dev_priv), (bits), 0)
2734 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2735 struct drm_file *file_priv);
2736 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2737 struct drm_file *file_priv);
2738 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2739 struct drm_file *file_priv);
2740 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2741 struct drm_file *file_priv);
2742 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2743 struct drm_file *file_priv);
2744 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2745 struct drm_file *file_priv);
2746 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2747 struct drm_file *file_priv);
2748 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2749 struct drm_i915_gem_request *req);
2750 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2751 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2752 struct drm_i915_gem_execbuffer2 *args,
2753 struct list_head *vmas);
2754 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2755 struct drm_file *file_priv);
2756 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2757 struct drm_file *file_priv);
2758 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2759 struct drm_file *file_priv);
2760 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2761 struct drm_file *file);
2762 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2763 struct drm_file *file);
2764 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2765 struct drm_file *file_priv);
2766 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2767 struct drm_file *file_priv);
2768 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2769 struct drm_file *file_priv);
2770 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2771 struct drm_file *file_priv);
2772 int i915_gem_init_userptr(struct drm_device *dev);
2773 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2774 struct drm_file *file);
2775 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2776 struct drm_file *file_priv);
2777 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2778 struct drm_file *file_priv);
2779 void i915_gem_load(struct drm_device *dev);
2780 void *i915_gem_object_alloc(struct drm_device *dev);
2781 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2782 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2783 const struct drm_i915_gem_object_ops *ops);
2784 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2786 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2787 struct drm_device *dev, const void *data, size_t size);
2788 void i915_init_vm(struct drm_i915_private *dev_priv,
2789 struct i915_address_space *vm);
2790 void i915_gem_free_object(struct drm_gem_object *obj);
2791 void i915_gem_vma_destroy(struct i915_vma *vma);
2793 /* Flags used by pin/bind&friends. */
2794 #define PIN_MAPPABLE (1<<0)
2795 #define PIN_NONBLOCK (1<<1)
2796 #define PIN_GLOBAL (1<<2)
2797 #define PIN_OFFSET_BIAS (1<<3)
2798 #define PIN_USER (1<<4)
2799 #define PIN_UPDATE (1<<5)
2800 #define PIN_OFFSET_MASK (~4095)
2802 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2803 struct i915_address_space *vm,
2807 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2808 const struct i915_ggtt_view *view,
2812 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2814 int __must_check i915_vma_unbind(struct i915_vma *vma);
2815 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2816 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2817 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2819 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2820 int *needs_clflush);
2822 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2824 static inline int __sg_page_count(struct scatterlist *sg)
2826 return sg->length >> PAGE_SHIFT;
2829 static inline struct page *
2830 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2832 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2835 if (n < obj->get_page.last) {
2836 obj->get_page.sg = obj->pages->sgl;
2837 obj->get_page.last = 0;
2840 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2841 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2842 if (unlikely(sg_is_chain(obj->get_page.sg)))
2843 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2846 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2849 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2851 BUG_ON(obj->pages == NULL);
2852 obj->pages_pin_count++;
2854 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2856 BUG_ON(obj->pages_pin_count == 0);
2857 obj->pages_pin_count--;
2860 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2861 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2862 struct intel_engine_cs *to,
2863 struct drm_i915_gem_request **to_req);
2864 void i915_vma_move_to_active(struct i915_vma *vma,
2865 struct drm_i915_gem_request *req);
2866 int i915_gem_dumb_create(struct drm_file *file_priv,
2867 struct drm_device *dev,
2868 struct drm_mode_create_dumb *args);
2869 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2870 uint32_t handle, uint64_t *offset);
2872 * Returns true if seq1 is later than seq2.
2875 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2877 return (int32_t)(seq1 - seq2) >= 0;
2880 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2881 bool lazy_coherency)
2885 BUG_ON(req == NULL);
2887 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2889 return i915_seqno_passed(seqno, req->seqno);
2892 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2893 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2895 struct drm_i915_gem_request *
2896 i915_gem_find_active_request(struct intel_engine_cs *ring);
2898 bool i915_gem_retire_requests(struct drm_device *dev);
2899 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2900 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2901 bool interruptible);
2903 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2905 return unlikely(atomic_read(&error->reset_counter)
2906 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2909 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2911 return atomic_read(&error->reset_counter) & I915_WEDGED;
2914 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2916 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2919 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2921 return dev_priv->gpu_error.stop_rings == 0 ||
2922 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2925 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2927 return dev_priv->gpu_error.stop_rings == 0 ||
2928 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2931 void i915_gem_reset(struct drm_device *dev);
2932 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2933 int __must_check i915_gem_init(struct drm_device *dev);
2934 int i915_gem_init_rings(struct drm_device *dev);
2935 int __must_check i915_gem_init_hw(struct drm_device *dev);
2936 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2937 void i915_gem_init_swizzling(struct drm_device *dev);
2938 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2939 int __must_check i915_gpu_idle(struct drm_device *dev);
2940 int __must_check i915_gem_suspend(struct drm_device *dev);
2941 void __i915_add_request(struct drm_i915_gem_request *req,
2942 struct drm_i915_gem_object *batch_obj,
2944 #define i915_add_request(req) \
2945 __i915_add_request(req, NULL, true)
2946 #define i915_add_request_no_flush(req) \
2947 __i915_add_request(req, NULL, false)
2948 int __i915_wait_request(struct drm_i915_gem_request *req,
2949 unsigned reset_counter,
2952 struct intel_rps_client *rps);
2953 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2954 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2956 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2959 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2962 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2964 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2966 struct intel_engine_cs *pipelined,
2967 struct drm_i915_gem_request **pipelined_request,
2968 const struct i915_ggtt_view *view);
2969 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2970 const struct i915_ggtt_view *view);
2971 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2973 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2974 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2977 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2979 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2980 int tiling_mode, bool fenced);
2982 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2983 enum i915_cache_level cache_level);
2985 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2986 struct dma_buf *dma_buf);
2988 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2989 struct drm_gem_object *gem_obj, int flags);
2991 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2992 const struct i915_ggtt_view *view);
2993 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2994 struct i915_address_space *vm);
2996 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2998 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3001 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3002 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3003 const struct i915_ggtt_view *view);
3004 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3005 struct i915_address_space *vm);
3007 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3008 struct i915_address_space *vm);
3010 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3011 struct i915_address_space *vm);
3013 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3014 const struct i915_ggtt_view *view);
3017 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3018 struct i915_address_space *vm);
3020 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3021 const struct i915_ggtt_view *view);
3023 static inline struct i915_vma *
3024 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3026 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3028 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3030 /* Some GGTT VM helpers */
3031 #define i915_obj_to_ggtt(obj) \
3032 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3033 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3035 struct i915_address_space *ggtt =
3036 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3040 static inline struct i915_hw_ppgtt *
3041 i915_vm_to_ppgtt(struct i915_address_space *vm)
3043 WARN_ON(i915_is_ggtt(vm));
3045 return container_of(vm, struct i915_hw_ppgtt, base);
3049 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3051 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3054 static inline unsigned long
3055 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3057 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3060 static inline int __must_check
3061 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3065 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3066 alignment, flags | PIN_GLOBAL);
3070 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3072 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3075 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3076 const struct i915_ggtt_view *view);
3078 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3080 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3083 /* i915_gem_fence.c */
3084 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3085 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3087 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3088 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3090 void i915_gem_restore_fences(struct drm_device *dev);
3092 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3093 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3094 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3096 /* i915_gem_context.c */
3097 int __must_check i915_gem_context_init(struct drm_device *dev);
3098 void i915_gem_context_fini(struct drm_device *dev);
3099 void i915_gem_context_reset(struct drm_device *dev);
3100 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3101 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3102 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3103 int i915_switch_context(struct drm_i915_gem_request *req);
3104 struct intel_context *
3105 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3106 void i915_gem_context_free(struct kref *ctx_ref);
3107 struct drm_i915_gem_object *
3108 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3109 static inline void i915_gem_context_reference(struct intel_context *ctx)
3111 kref_get(&ctx->ref);
3114 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3116 kref_put(&ctx->ref, i915_gem_context_free);
3119 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3121 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3124 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3125 struct drm_file *file);
3126 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3127 struct drm_file *file);
3128 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3129 struct drm_file *file_priv);
3130 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3131 struct drm_file *file_priv);
3133 /* i915_gem_evict.c */
3134 int __must_check i915_gem_evict_something(struct drm_device *dev,
3135 struct i915_address_space *vm,
3138 unsigned cache_level,
3139 unsigned long start,
3142 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3143 int i915_gem_evict_everything(struct drm_device *dev);
3145 /* belongs in i915_gem_gtt.h */
3146 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3148 if (INTEL_INFO(dev)->gen < 6)
3149 intel_gtt_chipset_flush();
3152 /* i915_gem_stolen.c */
3153 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3154 struct drm_mm_node *node, u64 size,
3155 unsigned alignment);
3156 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3157 struct drm_mm_node *node);
3158 int i915_gem_init_stolen(struct drm_device *dev);
3159 void i915_gem_cleanup_stolen(struct drm_device *dev);
3160 struct drm_i915_gem_object *
3161 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3162 struct drm_i915_gem_object *
3163 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3168 /* i915_gem_shrinker.c */
3169 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3172 #define I915_SHRINK_PURGEABLE 0x1
3173 #define I915_SHRINK_UNBOUND 0x2
3174 #define I915_SHRINK_BOUND 0x4
3175 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3176 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3179 /* i915_gem_tiling.c */
3180 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3182 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3184 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3185 obj->tiling_mode != I915_TILING_NONE;
3188 /* i915_gem_debug.c */
3190 int i915_verify_lists(struct drm_device *dev);
3192 #define i915_verify_lists(dev) 0
3195 /* i915_debugfs.c */
3196 int i915_debugfs_init(struct drm_minor *minor);
3197 void i915_debugfs_cleanup(struct drm_minor *minor);
3198 #ifdef CONFIG_DEBUG_FS
3199 int i915_debugfs_connector_add(struct drm_connector *connector);
3200 void intel_display_crc_init(struct drm_device *dev);
3202 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3204 static inline void intel_display_crc_init(struct drm_device *dev) {}
3207 /* i915_gpu_error.c */
3209 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3210 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3211 const struct i915_error_state_file_priv *error);
3212 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3213 struct drm_i915_private *i915,
3214 size_t count, loff_t pos);
3215 static inline void i915_error_state_buf_release(
3216 struct drm_i915_error_state_buf *eb)
3220 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3221 const char *error_msg);
3222 void i915_error_state_get(struct drm_device *dev,
3223 struct i915_error_state_file_priv *error_priv);
3224 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3225 void i915_destroy_error_state(struct drm_device *dev);
3227 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3228 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3230 /* i915_cmd_parser.c */
3231 int i915_cmd_parser_get_version(void);
3232 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3233 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3234 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3235 int i915_parse_cmds(struct intel_engine_cs *ring,
3236 struct drm_i915_gem_object *batch_obj,
3237 struct drm_i915_gem_object *shadow_batch_obj,
3238 u32 batch_start_offset,
3242 /* i915_suspend.c */
3243 extern int i915_save_state(struct drm_device *dev);
3244 extern int i915_restore_state(struct drm_device *dev);
3247 void i915_setup_sysfs(struct drm_device *dev_priv);
3248 void i915_teardown_sysfs(struct drm_device *dev_priv);
3251 extern int intel_setup_gmbus(struct drm_device *dev);
3252 extern void intel_teardown_gmbus(struct drm_device *dev);
3253 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3256 extern struct i2c_adapter *
3257 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3258 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3259 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3260 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3262 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3264 extern void intel_i2c_reset(struct drm_device *dev);
3266 /* intel_opregion.c */
3268 extern int intel_opregion_setup(struct drm_device *dev);
3269 extern void intel_opregion_init(struct drm_device *dev);
3270 extern void intel_opregion_fini(struct drm_device *dev);
3271 extern void intel_opregion_asle_intr(struct drm_device *dev);
3272 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3274 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3277 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3278 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3279 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3280 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3282 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3287 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3295 extern void intel_register_dsm_handler(void);
3296 extern void intel_unregister_dsm_handler(void);
3298 static inline void intel_register_dsm_handler(void) { return; }
3299 static inline void intel_unregister_dsm_handler(void) { return; }
3300 #endif /* CONFIG_ACPI */
3303 extern void intel_modeset_init_hw(struct drm_device *dev);
3304 extern void intel_modeset_init(struct drm_device *dev);
3305 extern void intel_modeset_gem_init(struct drm_device *dev);
3306 extern void intel_modeset_cleanup(struct drm_device *dev);
3307 extern void intel_connector_unregister(struct intel_connector *);
3308 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3309 extern void intel_display_resume(struct drm_device *dev);
3310 extern void i915_redisable_vga(struct drm_device *dev);
3311 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3312 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3313 extern void intel_init_pch_refclk(struct drm_device *dev);
3314 extern void intel_set_rps(struct drm_device *dev, u8 val);
3315 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3317 extern void intel_detect_pch(struct drm_device *dev);
3318 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3319 extern int intel_enable_rc6(const struct drm_device *dev);
3321 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3322 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3323 struct drm_file *file);
3324 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3325 struct drm_file *file);
3328 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3329 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3330 struct intel_overlay_error_state *error);
3332 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3333 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3334 struct drm_device *dev,
3335 struct intel_display_error_state *error);
3337 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3338 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3340 /* intel_sideband.c */
3341 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3342 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3343 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3344 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3345 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3346 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3347 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3348 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3349 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3350 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3351 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3352 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3353 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3354 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3355 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3356 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3357 enum intel_sbi_destination destination);
3358 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3359 enum intel_sbi_destination destination);
3360 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3361 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3363 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3364 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3366 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3367 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3369 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3370 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3371 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3372 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3374 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3375 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3376 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3377 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3379 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3380 * will be implemented using 2 32-bit writes in an arbitrary order with
3381 * an arbitrary delay between them. This can cause the hardware to
3382 * act upon the intermediate value, possibly leading to corruption and
3383 * machine death. You have been warned.
3385 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3386 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3388 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3389 u32 upper, lower, tmp; \
3390 tmp = I915_READ(upper_reg); \
3393 lower = I915_READ(lower_reg); \
3394 tmp = I915_READ(upper_reg); \
3395 } while (upper != tmp); \
3396 (u64)upper << 32 | lower; })
3398 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3399 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3401 /* These are untraced mmio-accessors that are only valid to be used inside
3402 * criticial sections inside IRQ handlers where forcewake is explicitly
3404 * Think twice, and think again, before using these.
3405 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3406 * intel_uncore_forcewake_irqunlock().
3408 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3409 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3410 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3412 /* "Broadcast RGB" property */
3413 #define INTEL_BROADCAST_RGB_AUTO 0
3414 #define INTEL_BROADCAST_RGB_FULL 1
3415 #define INTEL_BROADCAST_RGB_LIMITED 2
3417 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3419 if (IS_VALLEYVIEW(dev))
3420 return VLV_VGACNTRL;
3421 else if (INTEL_INFO(dev)->gen >= 5)
3422 return CPU_VGACNTRL;
3427 static inline void __user *to_user_ptr(u64 address)
3429 return (void __user *)(uintptr_t)address;
3432 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3434 unsigned long j = msecs_to_jiffies(m);
3436 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3439 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3441 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3444 static inline unsigned long
3445 timespec_to_jiffies_timeout(const struct timespec *value)
3447 unsigned long j = timespec_to_jiffies(value);
3449 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3453 * If you need to wait X milliseconds between events A and B, but event B
3454 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3455 * when event A happened, then just before event B you call this function and
3456 * pass the timestamp as the first argument, and X as the second argument.
3459 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3461 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3464 * Don't re-read the value of "jiffies" every time since it may change
3465 * behind our back and break the math.
3467 tmp_jiffies = jiffies;
3468 target_jiffies = timestamp_jiffies +
3469 msecs_to_jiffies_timeout(to_wait_ms);
3471 if (time_after(target_jiffies, tmp_jiffies)) {
3472 remaining_jiffies = target_jiffies - tmp_jiffies;
3473 while (remaining_jiffies)
3475 schedule_timeout_uninterruptible(remaining_jiffies);
3479 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3480 struct drm_i915_gem_request *req)
3482 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3483 i915_gem_request_assign(&ring->trace_irq_req, req);