1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20150117"
61 /* Many gcc seem to no see through this and fall over :( */
63 #define WARN_ON(x) ({ \
64 bool __i915_warn_cond = (x); \
65 if (__builtin_constant_p(__i915_warn_cond)) \
66 BUILD_BUG_ON(__i915_warn_cond); \
67 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
72 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
73 (long) (x), __func__);
75 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
76 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
77 * which may not necessarily be a user visible problem. This will either
78 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
79 * enable distros and users to tailor their preferred amount of i915 abrt
82 #define I915_STATE_WARN(condition, format...) ({ \
83 int __ret_warn_on = !!(condition); \
84 if (unlikely(__ret_warn_on)) { \
85 if (i915.verbose_state_checks) \
90 unlikely(__ret_warn_on); \
93 #define I915_STATE_WARN_ON(condition) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) { \
96 if (i915.verbose_state_checks) \
97 WARN(1, "WARN_ON(" #condition ")\n"); \
99 DRM_ERROR("WARN_ON(" #condition ")\n"); \
101 unlikely(__ret_warn_on); \
110 I915_MAX_PIPES = _PIPE_EDP
112 #define pipe_name(p) ((p) + 'A')
121 #define transcoder_name(t) ((t) + 'A')
124 * This is the maximum (across all platforms) number of planes (primary +
125 * sprites) that can be active at the same time on one pipe.
127 * This value doesn't count the cursor plane.
129 #define I915_MAX_PLANES 3
136 #define plane_name(p) ((p) + 'A')
138 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
148 #define port_name(p) ((p) + 'A')
150 #define I915_NUM_PHYS_VLV 2
162 enum intel_display_power_domain {
166 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
167 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
168 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
169 POWER_DOMAIN_TRANSCODER_A,
170 POWER_DOMAIN_TRANSCODER_B,
171 POWER_DOMAIN_TRANSCODER_C,
172 POWER_DOMAIN_TRANSCODER_EDP,
173 POWER_DOMAIN_PORT_DDI_A_2_LANES,
174 POWER_DOMAIN_PORT_DDI_A_4_LANES,
175 POWER_DOMAIN_PORT_DDI_B_2_LANES,
176 POWER_DOMAIN_PORT_DDI_B_4_LANES,
177 POWER_DOMAIN_PORT_DDI_C_2_LANES,
178 POWER_DOMAIN_PORT_DDI_C_4_LANES,
179 POWER_DOMAIN_PORT_DDI_D_2_LANES,
180 POWER_DOMAIN_PORT_DDI_D_4_LANES,
181 POWER_DOMAIN_PORT_DSI,
182 POWER_DOMAIN_PORT_CRT,
183 POWER_DOMAIN_PORT_OTHER,
192 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
193 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
194 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
195 #define POWER_DOMAIN_TRANSCODER(tran) \
196 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
197 (tran) + POWER_DOMAIN_TRANSCODER_A)
201 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
202 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
212 #define I915_GEM_GPU_DOMAINS \
213 (I915_GEM_DOMAIN_RENDER | \
214 I915_GEM_DOMAIN_SAMPLER | \
215 I915_GEM_DOMAIN_COMMAND | \
216 I915_GEM_DOMAIN_INSTRUCTION | \
217 I915_GEM_DOMAIN_VERTEX)
219 #define for_each_pipe(__dev_priv, __p) \
220 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
221 #define for_each_plane(pipe, p) \
222 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
223 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
225 #define for_each_crtc(dev, crtc) \
226 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
228 #define for_each_intel_crtc(dev, intel_crtc) \
229 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
231 #define for_each_intel_encoder(dev, intel_encoder) \
232 list_for_each_entry(intel_encoder, \
233 &(dev)->mode_config.encoder_list, \
236 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
237 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
238 if ((intel_encoder)->base.crtc == (__crtc))
240 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
241 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
242 if ((intel_connector)->base.encoder == (__encoder))
244 #define for_each_power_domain(domain, mask) \
245 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
246 if ((1 << (domain)) & (mask))
248 struct drm_i915_private;
249 struct i915_mm_struct;
250 struct i915_mmu_object;
253 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
254 /* real shared dpll ids must be >= 0 */
255 DPLL_ID_PCH_PLL_A = 0,
256 DPLL_ID_PCH_PLL_B = 1,
261 DPLL_ID_SKL_DPLL1 = 0,
262 DPLL_ID_SKL_DPLL2 = 1,
263 DPLL_ID_SKL_DPLL3 = 2,
265 #define I915_NUM_PLLS 3
267 struct intel_dpll_hw_state {
279 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
280 * lower part of crtl1 and they get shifted into position when writing
281 * the register. This allows us to easily compare the state to share
285 /* HDMI only, 0 when used for DP */
286 uint32_t cfgcr1, cfgcr2;
289 struct intel_shared_dpll_config {
290 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
291 struct intel_dpll_hw_state hw_state;
294 struct intel_shared_dpll {
295 struct intel_shared_dpll_config config;
296 struct intel_shared_dpll_config *new_config;
298 int active; /* count of number of active CRTCs (i.e. DPMS on) */
299 bool on; /* is the PLL actually active? Disabled during modeset */
301 /* should match the index in the dev_priv->shared_dplls array */
302 enum intel_dpll_id id;
303 /* The mode_set hook is optional and should be used together with the
304 * intel_prepare_shared_dpll function. */
305 void (*mode_set)(struct drm_i915_private *dev_priv,
306 struct intel_shared_dpll *pll);
307 void (*enable)(struct drm_i915_private *dev_priv,
308 struct intel_shared_dpll *pll);
309 void (*disable)(struct drm_i915_private *dev_priv,
310 struct intel_shared_dpll *pll);
311 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
312 struct intel_shared_dpll *pll,
313 struct intel_dpll_hw_state *hw_state);
321 /* Used by dp and fdi links */
322 struct intel_link_m_n {
330 void intel_link_compute_m_n(int bpp, int nlanes,
331 int pixel_clock, int link_clock,
332 struct intel_link_m_n *m_n);
334 /* Interface history:
337 * 1.2: Add Power Management
338 * 1.3: Add vblank support
339 * 1.4: Fix cmdbuffer path, add heap destroy
340 * 1.5: Add vblank pipe configuration
341 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
342 * - Support vertical blank on secondary display pipe
344 #define DRIVER_MAJOR 1
345 #define DRIVER_MINOR 6
346 #define DRIVER_PATCHLEVEL 0
348 #define WATCH_LISTS 0
350 struct opregion_header;
351 struct opregion_acpi;
352 struct opregion_swsci;
353 struct opregion_asle;
355 struct intel_opregion {
356 struct opregion_header __iomem *header;
357 struct opregion_acpi __iomem *acpi;
358 struct opregion_swsci __iomem *swsci;
359 u32 swsci_gbda_sub_functions;
360 u32 swsci_sbcb_sub_functions;
361 struct opregion_asle __iomem *asle;
363 u32 __iomem *lid_state;
364 struct work_struct asle_work;
366 #define OPREGION_SIZE (8*1024)
368 struct intel_overlay;
369 struct intel_overlay_error_state;
371 #define I915_FENCE_REG_NONE -1
372 #define I915_MAX_NUM_FENCES 32
373 /* 32 fences + sign bit for FENCE_REG_NONE */
374 #define I915_MAX_NUM_FENCE_BITS 6
376 struct drm_i915_fence_reg {
377 struct list_head lru_list;
378 struct drm_i915_gem_object *obj;
382 struct sdvo_device_mapping {
391 struct intel_display_error_state;
393 struct drm_i915_error_state {
401 /* Generic register state */
409 u32 error; /* gen6+ */
410 u32 err_int; /* gen7 */
416 u32 extra_instdone[I915_NUM_INSTDONE_REG];
417 u64 fence[I915_MAX_NUM_FENCES];
418 struct intel_overlay_error_state *overlay;
419 struct intel_display_error_state *display;
420 struct drm_i915_error_object *semaphore_obj;
422 struct drm_i915_error_ring {
424 /* Software tracked state */
427 enum intel_ring_hangcheck_action hangcheck_action;
430 /* our own tracking of ring head and tail */
434 u32 semaphore_seqno[I915_NUM_RINGS - 1];
452 u32 rc_psmi; /* sleep state */
453 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
455 struct drm_i915_error_object {
459 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
461 struct drm_i915_error_request {
476 char comm[TASK_COMM_LEN];
477 } ring[I915_NUM_RINGS];
479 struct drm_i915_error_buffer {
486 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
494 } **active_bo, **pinned_bo;
496 u32 *active_bo_count, *pinned_bo_count;
500 struct intel_connector;
501 struct intel_encoder;
502 struct intel_crtc_config;
503 struct intel_plane_config;
508 struct drm_i915_display_funcs {
509 bool (*fbc_enabled)(struct drm_device *dev);
510 void (*enable_fbc)(struct drm_crtc *crtc);
511 void (*disable_fbc)(struct drm_device *dev);
512 int (*get_display_clock_speed)(struct drm_device *dev);
513 int (*get_fifo_size)(struct drm_device *dev, int plane);
515 * find_dpll() - Find the best values for the PLL
516 * @limit: limits for the PLL
517 * @crtc: current CRTC
518 * @target: target frequency in kHz
519 * @refclk: reference clock frequency in kHz
520 * @match_clock: if provided, @best_clock P divider must
521 * match the P divider from @match_clock
522 * used for LVDS downclocking
523 * @best_clock: best PLL values found
525 * Returns true on success, false on failure.
527 bool (*find_dpll)(const struct intel_limit *limit,
528 struct intel_crtc *crtc,
529 int target, int refclk,
530 struct dpll *match_clock,
531 struct dpll *best_clock);
532 void (*update_wm)(struct drm_crtc *crtc);
533 void (*update_sprite_wm)(struct drm_plane *plane,
534 struct drm_crtc *crtc,
535 uint32_t sprite_width, uint32_t sprite_height,
536 int pixel_size, bool enable, bool scaled);
537 void (*modeset_global_resources)(struct drm_device *dev);
538 /* Returns the active state of the crtc, and if the crtc is active,
539 * fills out the pipe-config with the hw state. */
540 bool (*get_pipe_config)(struct intel_crtc *,
541 struct intel_crtc_config *);
542 void (*get_plane_config)(struct intel_crtc *,
543 struct intel_plane_config *);
544 int (*crtc_compute_clock)(struct intel_crtc *crtc);
545 void (*crtc_enable)(struct drm_crtc *crtc);
546 void (*crtc_disable)(struct drm_crtc *crtc);
547 void (*off)(struct drm_crtc *crtc);
548 void (*audio_codec_enable)(struct drm_connector *connector,
549 struct intel_encoder *encoder,
550 struct drm_display_mode *mode);
551 void (*audio_codec_disable)(struct intel_encoder *encoder);
552 void (*fdi_link_train)(struct drm_crtc *crtc);
553 void (*init_clock_gating)(struct drm_device *dev);
554 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
555 struct drm_framebuffer *fb,
556 struct drm_i915_gem_object *obj,
557 struct intel_engine_cs *ring,
559 void (*update_primary_plane)(struct drm_crtc *crtc,
560 struct drm_framebuffer *fb,
562 void (*hpd_irq_setup)(struct drm_device *dev);
563 /* clock updates for mode set */
565 /* render clock increase/decrease */
566 /* display clock increase/decrease */
567 /* pll clock increase/decrease */
569 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
570 uint32_t (*get_backlight)(struct intel_connector *connector);
571 void (*set_backlight)(struct intel_connector *connector,
573 void (*disable_backlight)(struct intel_connector *connector);
574 void (*enable_backlight)(struct intel_connector *connector);
577 struct intel_uncore_funcs {
578 void (*force_wake_get)(struct drm_i915_private *dev_priv,
580 void (*force_wake_put)(struct drm_i915_private *dev_priv,
583 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
584 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
585 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
586 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
588 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
589 uint8_t val, bool trace);
590 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
591 uint16_t val, bool trace);
592 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
593 uint32_t val, bool trace);
594 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
595 uint64_t val, bool trace);
598 struct intel_uncore {
599 spinlock_t lock; /** lock is also taken in irq contexts. */
601 struct intel_uncore_funcs funcs;
604 unsigned forcewake_count;
606 unsigned fw_rendercount;
607 unsigned fw_mediacount;
608 unsigned fw_blittercount;
610 struct timer_list force_wake_timer;
613 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
614 func(is_mobile) sep \
617 func(is_i945gm) sep \
619 func(need_gfx_hws) sep \
621 func(is_pineview) sep \
622 func(is_broadwater) sep \
623 func(is_crestline) sep \
624 func(is_ivybridge) sep \
625 func(is_valleyview) sep \
626 func(is_haswell) sep \
627 func(is_skylake) sep \
628 func(is_preliminary) sep \
630 func(has_pipe_cxsr) sep \
631 func(has_hotplug) sep \
632 func(cursor_needs_physical) sep \
633 func(has_overlay) sep \
634 func(overlay_needs_physical) sep \
635 func(supports_tv) sep \
640 #define DEFINE_FLAG(name) u8 name:1
641 #define SEP_SEMICOLON ;
643 struct intel_device_info {
644 u32 display_mmio_offset;
647 u8 num_sprites[I915_MAX_PIPES];
649 u8 ring_mask; /* Rings supported by the HW */
650 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
651 /* Register offsets for the various display pipes and transcoders */
652 int pipe_offsets[I915_MAX_TRANSCODERS];
653 int trans_offsets[I915_MAX_TRANSCODERS];
654 int palette_offsets[I915_MAX_PIPES];
655 int cursor_offsets[I915_MAX_PIPES];
656 unsigned int eu_total;
662 enum i915_cache_level {
664 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
665 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
666 caches, eg sampler/render caches, and the
667 large Last-Level-Cache. LLC is coherent with
668 the CPU, but L3 is only visible to the GPU. */
669 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
672 struct i915_ctx_hang_stats {
673 /* This context had batch pending when hang was declared */
674 unsigned batch_pending;
676 /* This context had batch active when hang was declared */
677 unsigned batch_active;
679 /* Time when this context was last blamed for a GPU reset */
680 unsigned long guilty_ts;
682 /* If the contexts causes a second GPU hang within this time,
683 * it is permanently banned from submitting any more work.
685 unsigned long ban_period_seconds;
687 /* This context is banned to submit more work */
691 /* This must match up with the value previously used for execbuf2.rsvd1. */
692 #define DEFAULT_CONTEXT_HANDLE 0
694 * struct intel_context - as the name implies, represents a context.
695 * @ref: reference count.
696 * @user_handle: userspace tracking identity for this context.
697 * @remap_slice: l3 row remapping information.
698 * @file_priv: filp associated with this context (NULL for global default
700 * @hang_stats: information about the role of this context in possible GPU
702 * @vm: virtual memory space used by this context.
703 * @legacy_hw_ctx: render context backing object and whether it is correctly
704 * initialized (legacy ring submission mechanism only).
705 * @link: link in the global list of contexts.
707 * Contexts are memory images used by the hardware to store copies of their
710 struct intel_context {
714 struct drm_i915_file_private *file_priv;
715 struct i915_ctx_hang_stats hang_stats;
716 struct i915_hw_ppgtt *ppgtt;
718 /* Legacy ring buffer submission */
720 struct drm_i915_gem_object *rcs_state;
725 bool rcs_initialized;
727 struct drm_i915_gem_object *state;
728 struct intel_ringbuffer *ringbuf;
730 } engine[I915_NUM_RINGS];
732 struct list_head link;
742 struct drm_mm_node compressed_fb;
743 struct drm_mm_node *compressed_llb;
747 /* Tracks whether the HW is actually enabled, not whether the feature is
751 /* On gen8 some rings cannont perform fbc clean operation so for now
752 * we are doing this on SW with mmio.
753 * This variable works in the opposite information direction
754 * of ring->fbc_dirty telling software on frontbuffer tracking
755 * to perform the cache clean on sw side.
757 bool need_sw_cache_clean;
759 struct intel_fbc_work {
760 struct delayed_work work;
761 struct drm_crtc *crtc;
762 struct drm_framebuffer *fb;
766 FBC_OK, /* FBC is enabled */
767 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
768 FBC_NO_OUTPUT, /* no outputs enabled to compress */
769 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
770 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
771 FBC_MODE_TOO_LARGE, /* mode too large for compression */
772 FBC_BAD_PLANE, /* fbc not supported on plane */
773 FBC_NOT_TILED, /* buffer not tiled */
774 FBC_MULTIPLE_PIPES, /* more than one pipe active */
776 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
781 struct intel_connector *connector;
789 struct intel_dp *enabled;
791 struct delayed_work work;
792 unsigned busy_frontbuffer_bits;
797 PCH_NONE = 0, /* No PCH present */
798 PCH_IBX, /* Ibexpeak PCH */
799 PCH_CPT, /* Cougarpoint PCH */
800 PCH_LPT, /* Lynxpoint PCH */
801 PCH_SPT, /* Sunrisepoint PCH */
805 enum intel_sbi_destination {
810 #define QUIRK_PIPEA_FORCE (1<<0)
811 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
812 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
813 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
814 #define QUIRK_PIPEB_FORCE (1<<4)
815 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
818 struct intel_fbc_work;
821 struct i2c_adapter adapter;
825 struct i2c_algo_bit_data bit_algo;
826 struct drm_i915_private *dev_priv;
829 struct i915_suspend_saved_registers {
850 u32 saveTRANS_HTOTAL_A;
851 u32 saveTRANS_HBLANK_A;
852 u32 saveTRANS_HSYNC_A;
853 u32 saveTRANS_VTOTAL_A;
854 u32 saveTRANS_VBLANK_A;
855 u32 saveTRANS_VSYNC_A;
863 u32 savePFIT_PGM_RATIOS;
864 u32 saveBLC_HIST_CTL;
866 u32 saveBLC_PWM_CTL2;
867 u32 saveBLC_CPU_PWM_CTL;
868 u32 saveBLC_CPU_PWM_CTL2;
881 u32 saveTRANS_HTOTAL_B;
882 u32 saveTRANS_HBLANK_B;
883 u32 saveTRANS_HSYNC_B;
884 u32 saveTRANS_VTOTAL_B;
885 u32 saveTRANS_VBLANK_B;
886 u32 saveTRANS_VSYNC_B;
900 u32 savePP_ON_DELAYS;
901 u32 savePP_OFF_DELAYS;
909 u32 savePFIT_CONTROL;
910 u32 save_palette_a[256];
911 u32 save_palette_b[256];
922 u32 saveCACHE_MODE_0;
923 u32 saveMI_ARB_STATE;
934 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
945 u32 savePIPEA_GMCH_DATA_M;
946 u32 savePIPEB_GMCH_DATA_M;
947 u32 savePIPEA_GMCH_DATA_N;
948 u32 savePIPEB_GMCH_DATA_N;
949 u32 savePIPEA_DP_LINK_M;
950 u32 savePIPEB_DP_LINK_M;
951 u32 savePIPEA_DP_LINK_N;
952 u32 savePIPEB_DP_LINK_N;
963 u32 savePCH_DREF_CONTROL;
964 u32 saveDISP_ARB_CTL;
965 u32 savePIPEA_DATA_M1;
966 u32 savePIPEA_DATA_N1;
967 u32 savePIPEA_LINK_M1;
968 u32 savePIPEA_LINK_N1;
969 u32 savePIPEB_DATA_M1;
970 u32 savePIPEB_DATA_N1;
971 u32 savePIPEB_LINK_M1;
972 u32 savePIPEB_LINK_N1;
973 u32 saveMCHBAR_RENDER_STANDBY;
974 u32 savePCH_PORT_HOTPLUG;
978 struct vlv_s0ix_state {
985 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
986 u32 media_max_req_count;
987 u32 gfx_max_req_count;
1013 u32 rp_down_timeout;
1019 /* Display 1 CZ domain */
1024 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1026 /* GT SA CZ domain */
1033 /* Display 2 CZ domain */
1036 u32 clock_gate_dis2;
1039 struct intel_rps_ei {
1045 struct intel_gen6_power_mgmt {
1047 * work, interrupts_enabled and pm_iir are protected by
1048 * dev_priv->irq_lock
1050 struct work_struct work;
1051 bool interrupts_enabled;
1054 /* Frequencies are stored in potentially platform dependent multiples.
1055 * In other words, *_freq needs to be multiplied by X to be interesting.
1056 * Soft limits are those which are used for the dynamic reclocking done
1057 * by the driver (raise frequencies under heavy loads, and lower for
1058 * lighter loads). Hard limits are those imposed by the hardware.
1060 * A distinction is made for overclocking, which is never enabled by
1061 * default, and is considered to be above the hard limit if it's
1064 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1065 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1066 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1067 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1068 u8 min_freq; /* AKA RPn. Minimum frequency */
1069 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1070 u8 rp1_freq; /* "less than" RP0 power/freqency */
1071 u8 rp0_freq; /* Non-overclocked max frequency. */
1074 u32 ei_interrupt_count;
1077 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1080 struct delayed_work delayed_resume_work;
1082 /* manual wa residency calculations */
1083 struct intel_rps_ei up_ei, down_ei;
1086 * Protects RPS/RC6 register access and PCU communication.
1087 * Must be taken after struct_mutex if nested.
1089 struct mutex hw_lock;
1092 /* defined intel_pm.c */
1093 extern spinlock_t mchdev_lock;
1095 struct intel_ilk_power_mgmt {
1103 unsigned long last_time1;
1104 unsigned long chipset_power;
1107 unsigned long gfx_power;
1113 struct drm_i915_gem_object *pwrctx;
1114 struct drm_i915_gem_object *renderctx;
1117 struct drm_i915_private;
1118 struct i915_power_well;
1120 struct i915_power_well_ops {
1122 * Synchronize the well's hw state to match the current sw state, for
1123 * example enable/disable it based on the current refcount. Called
1124 * during driver init and resume time, possibly after first calling
1125 * the enable/disable handlers.
1127 void (*sync_hw)(struct drm_i915_private *dev_priv,
1128 struct i915_power_well *power_well);
1130 * Enable the well and resources that depend on it (for example
1131 * interrupts located on the well). Called after the 0->1 refcount
1134 void (*enable)(struct drm_i915_private *dev_priv,
1135 struct i915_power_well *power_well);
1137 * Disable the well and resources that depend on it. Called after
1138 * the 1->0 refcount transition.
1140 void (*disable)(struct drm_i915_private *dev_priv,
1141 struct i915_power_well *power_well);
1142 /* Returns the hw enabled state. */
1143 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1144 struct i915_power_well *power_well);
1147 /* Power well structure for haswell */
1148 struct i915_power_well {
1151 /* power well enable/disable usage count */
1153 /* cached hw enabled state */
1155 unsigned long domains;
1157 const struct i915_power_well_ops *ops;
1160 struct i915_power_domains {
1162 * Power wells needed for initialization at driver init and suspend
1163 * time are on. They are kept on until after the first modeset.
1167 int power_well_count;
1170 int domain_use_count[POWER_DOMAIN_NUM];
1171 struct i915_power_well *power_wells;
1174 #define MAX_L3_SLICES 2
1175 struct intel_l3_parity {
1176 u32 *remap_info[MAX_L3_SLICES];
1177 struct work_struct error_work;
1181 struct i915_gem_batch_pool {
1182 struct drm_device *dev;
1183 struct list_head cache_list;
1186 struct i915_gem_mm {
1187 /** Memory allocator for GTT stolen memory */
1188 struct drm_mm stolen;
1189 /** List of all objects in gtt_space. Used to restore gtt
1190 * mappings on resume */
1191 struct list_head bound_list;
1193 * List of objects which are not bound to the GTT (thus
1194 * are idle and not used by the GPU) but still have
1195 * (presumably uncached) pages still attached.
1197 struct list_head unbound_list;
1200 * A pool of objects to use as shadow copies of client batch buffers
1201 * when the command parser is enabled. Prevents the client from
1202 * modifying the batch contents after software parsing.
1204 struct i915_gem_batch_pool batch_pool;
1206 /** Usable portion of the GTT for GEM */
1207 unsigned long stolen_base; /* limited to low memory (32-bit) */
1209 /** PPGTT used for aliasing the PPGTT with the GTT */
1210 struct i915_hw_ppgtt *aliasing_ppgtt;
1212 struct notifier_block oom_notifier;
1213 struct shrinker shrinker;
1214 bool shrinker_no_lock_stealing;
1216 /** LRU list of objects with fence regs on them. */
1217 struct list_head fence_list;
1220 * We leave the user IRQ off as much as possible,
1221 * but this means that requests will finish and never
1222 * be retired once the system goes idle. Set a timer to
1223 * fire periodically while the ring is running. When it
1224 * fires, go retire requests.
1226 struct delayed_work retire_work;
1229 * When we detect an idle GPU, we want to turn on
1230 * powersaving features. So once we see that there
1231 * are no more requests outstanding and no more
1232 * arrive within a small period of time, we fire
1233 * off the idle_work.
1235 struct delayed_work idle_work;
1238 * Are we in a non-interruptible section of code like
1244 * Is the GPU currently considered idle, or busy executing userspace
1245 * requests? Whilst idle, we attempt to power down the hardware and
1246 * display clocks. In order to reduce the effect on performance, there
1247 * is a slight delay before we do so.
1251 /* the indicator for dispatch video commands on two BSD rings */
1252 int bsd_ring_dispatch_index;
1254 /** Bit 6 swizzling required for X tiling */
1255 uint32_t bit_6_swizzle_x;
1256 /** Bit 6 swizzling required for Y tiling */
1257 uint32_t bit_6_swizzle_y;
1259 /* accounting, useful for userland debugging */
1260 spinlock_t object_stat_lock;
1261 size_t object_memory;
1265 struct drm_i915_error_state_buf {
1266 struct drm_i915_private *i915;
1275 struct i915_error_state_file_priv {
1276 struct drm_device *dev;
1277 struct drm_i915_error_state *error;
1280 struct i915_gpu_error {
1281 /* For hangcheck timer */
1282 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1283 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1284 /* Hang gpu twice in this window and your context gets banned */
1285 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1287 struct timer_list hangcheck_timer;
1289 /* For reset and error_state handling. */
1291 /* Protected by the above dev->gpu_error.lock. */
1292 struct drm_i915_error_state *first_error;
1293 struct work_struct work;
1296 unsigned long missed_irq_rings;
1299 * State variable controlling the reset flow and count
1301 * This is a counter which gets incremented when reset is triggered,
1302 * and again when reset has been handled. So odd values (lowest bit set)
1303 * means that reset is in progress and even values that
1304 * (reset_counter >> 1):th reset was successfully completed.
1306 * If reset is not completed succesfully, the I915_WEDGE bit is
1307 * set meaning that hardware is terminally sour and there is no
1308 * recovery. All waiters on the reset_queue will be woken when
1311 * This counter is used by the wait_seqno code to notice that reset
1312 * event happened and it needs to restart the entire ioctl (since most
1313 * likely the seqno it waited for won't ever signal anytime soon).
1315 * This is important for lock-free wait paths, where no contended lock
1316 * naturally enforces the correct ordering between the bail-out of the
1317 * waiter and the gpu reset work code.
1319 atomic_t reset_counter;
1321 #define I915_RESET_IN_PROGRESS_FLAG 1
1322 #define I915_WEDGED (1 << 31)
1325 * Waitqueue to signal when the reset has completed. Used by clients
1326 * that wait for dev_priv->mm.wedged to settle.
1328 wait_queue_head_t reset_queue;
1330 /* Userspace knobs for gpu hang simulation;
1331 * combines both a ring mask, and extra flags
1334 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1335 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1337 /* For missed irq/seqno simulation. */
1338 unsigned int test_irq_rings;
1340 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1341 bool reload_in_reset;
1344 enum modeset_restore {
1345 MODESET_ON_LID_OPEN,
1350 struct ddi_vbt_port_info {
1352 * This is an index in the HDMI/DVI DDI buffer translation table.
1353 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1354 * populate this field.
1356 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1357 uint8_t hdmi_level_shift;
1359 uint8_t supports_dvi:1;
1360 uint8_t supports_hdmi:1;
1361 uint8_t supports_dp:1;
1364 enum drrs_support_type {
1365 DRRS_NOT_SUPPORTED = 0,
1366 STATIC_DRRS_SUPPORT = 1,
1367 SEAMLESS_DRRS_SUPPORT = 2
1370 enum psr_lines_to_wait {
1371 PSR_0_LINES_TO_WAIT = 0,
1373 PSR_4_LINES_TO_WAIT,
1377 struct intel_vbt_data {
1378 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1379 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1382 unsigned int int_tv_support:1;
1383 unsigned int lvds_dither:1;
1384 unsigned int lvds_vbt:1;
1385 unsigned int int_crt_support:1;
1386 unsigned int lvds_use_ssc:1;
1387 unsigned int display_clock_mode:1;
1388 unsigned int fdi_rx_polarity_inverted:1;
1389 unsigned int has_mipi:1;
1391 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1393 enum drrs_support_type drrs_type;
1398 int edp_preemphasis;
1400 bool edp_initialized;
1403 struct edp_power_seq edp_pps;
1407 bool require_aux_wakeup;
1409 enum psr_lines_to_wait lines_to_wait;
1410 int tp1_wakeup_time;
1411 int tp2_tp3_wakeup_time;
1417 bool active_low_pwm;
1418 u8 min_brightness; /* min_brightness/255 of max */
1425 struct mipi_config *config;
1426 struct mipi_pps_data *pps;
1430 u8 *sequence[MIPI_SEQ_MAX];
1436 union child_device_config *child_dev;
1438 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1441 enum intel_ddb_partitioning {
1443 INTEL_DDB_PART_5_6, /* IVB+ */
1446 struct intel_wm_level {
1454 struct ilk_wm_values {
1455 uint32_t wm_pipe[3];
1457 uint32_t wm_lp_spr[3];
1458 uint32_t wm_linetime[3];
1460 enum intel_ddb_partitioning partitioning;
1463 struct skl_ddb_entry {
1464 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1467 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1469 return entry->end - entry->start;
1472 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1473 const struct skl_ddb_entry *e2)
1475 if (e1->start == e2->start && e1->end == e2->end)
1481 struct skl_ddb_allocation {
1482 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1483 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1484 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1487 struct skl_wm_values {
1488 bool dirty[I915_MAX_PIPES];
1489 struct skl_ddb_allocation ddb;
1490 uint32_t wm_linetime[I915_MAX_PIPES];
1491 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1492 uint32_t cursor[I915_MAX_PIPES][8];
1493 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1494 uint32_t cursor_trans[I915_MAX_PIPES];
1497 struct skl_wm_level {
1498 bool plane_en[I915_MAX_PLANES];
1500 uint16_t plane_res_b[I915_MAX_PLANES];
1501 uint8_t plane_res_l[I915_MAX_PLANES];
1502 uint16_t cursor_res_b;
1503 uint8_t cursor_res_l;
1507 * This struct helps tracking the state needed for runtime PM, which puts the
1508 * device in PCI D3 state. Notice that when this happens, nothing on the
1509 * graphics device works, even register access, so we don't get interrupts nor
1512 * Every piece of our code that needs to actually touch the hardware needs to
1513 * either call intel_runtime_pm_get or call intel_display_power_get with the
1514 * appropriate power domain.
1516 * Our driver uses the autosuspend delay feature, which means we'll only really
1517 * suspend if we stay with zero refcount for a certain amount of time. The
1518 * default value is currently very conservative (see intel_runtime_pm_enable), but
1519 * it can be changed with the standard runtime PM files from sysfs.
1521 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1522 * goes back to false exactly before we reenable the IRQs. We use this variable
1523 * to check if someone is trying to enable/disable IRQs while they're supposed
1524 * to be disabled. This shouldn't happen and we'll print some error messages in
1527 * For more, read the Documentation/power/runtime_pm.txt.
1529 struct i915_runtime_pm {
1534 enum intel_pipe_crc_source {
1535 INTEL_PIPE_CRC_SOURCE_NONE,
1536 INTEL_PIPE_CRC_SOURCE_PLANE1,
1537 INTEL_PIPE_CRC_SOURCE_PLANE2,
1538 INTEL_PIPE_CRC_SOURCE_PF,
1539 INTEL_PIPE_CRC_SOURCE_PIPE,
1540 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1541 INTEL_PIPE_CRC_SOURCE_TV,
1542 INTEL_PIPE_CRC_SOURCE_DP_B,
1543 INTEL_PIPE_CRC_SOURCE_DP_C,
1544 INTEL_PIPE_CRC_SOURCE_DP_D,
1545 INTEL_PIPE_CRC_SOURCE_AUTO,
1546 INTEL_PIPE_CRC_SOURCE_MAX,
1549 struct intel_pipe_crc_entry {
1554 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1555 struct intel_pipe_crc {
1557 bool opened; /* exclusive access to the result file */
1558 struct intel_pipe_crc_entry *entries;
1559 enum intel_pipe_crc_source source;
1561 wait_queue_head_t wq;
1564 struct i915_frontbuffer_tracking {
1568 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1575 struct i915_wa_reg {
1578 /* bitmask representing WA bits */
1582 #define I915_MAX_WA_REGS 16
1584 struct i915_workarounds {
1585 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1589 struct drm_i915_private {
1590 struct drm_device *dev;
1591 struct kmem_cache *slab;
1593 const struct intel_device_info info;
1595 int relative_constants_mode;
1599 struct intel_uncore uncore;
1601 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1604 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1605 * controller on different i2c buses. */
1606 struct mutex gmbus_mutex;
1609 * Base address of the gmbus and gpio block.
1611 uint32_t gpio_mmio_base;
1613 /* MMIO base address for MIPI regs */
1614 uint32_t mipi_mmio_base;
1616 wait_queue_head_t gmbus_wait_queue;
1618 struct pci_dev *bridge_dev;
1619 struct intel_engine_cs ring[I915_NUM_RINGS];
1620 struct drm_i915_gem_object *semaphore_obj;
1621 uint32_t last_seqno, next_seqno;
1623 struct drm_dma_handle *status_page_dmah;
1624 struct resource mch_res;
1626 /* protects the irq masks */
1627 spinlock_t irq_lock;
1629 /* protects the mmio flip data */
1630 spinlock_t mmio_flip_lock;
1632 bool display_irqs_enabled;
1634 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1635 struct pm_qos_request pm_qos;
1637 /* DPIO indirect register protection */
1638 struct mutex dpio_lock;
1640 /** Cached value of IMR to avoid reads in updating the bitfield */
1643 u32 de_irq_mask[I915_MAX_PIPES];
1648 u32 pipestat_irq_mask[I915_MAX_PIPES];
1650 struct work_struct hotplug_work;
1652 unsigned long hpd_last_jiffies;
1657 HPD_MARK_DISABLED = 2
1659 } hpd_stats[HPD_NUM_PINS];
1661 struct delayed_work hotplug_reenable_work;
1663 struct i915_fbc fbc;
1664 struct i915_drrs drrs;
1665 struct intel_opregion opregion;
1666 struct intel_vbt_data vbt;
1668 bool preserve_bios_swizzle;
1671 struct intel_overlay *overlay;
1673 /* backlight registers and fields in struct intel_panel */
1674 struct mutex backlight_lock;
1677 bool no_aux_handshake;
1679 /* protects panel power sequencer state */
1680 struct mutex pps_mutex;
1682 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1683 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1684 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1686 unsigned int fsb_freq, mem_freq, is_ddr3;
1687 unsigned int vlv_cdclk_freq;
1688 unsigned int hpll_freq;
1691 * wq - Driver workqueue for GEM.
1693 * NOTE: Work items scheduled here are not allowed to grab any modeset
1694 * locks, for otherwise the flushing done in the pageflip code will
1695 * result in deadlocks.
1697 struct workqueue_struct *wq;
1699 /* Display functions */
1700 struct drm_i915_display_funcs display;
1702 /* PCH chipset type */
1703 enum intel_pch pch_type;
1704 unsigned short pch_id;
1706 unsigned long quirks;
1708 enum modeset_restore modeset_restore;
1709 struct mutex modeset_restore_lock;
1711 struct list_head vm_list; /* Global list of all address spaces */
1712 struct i915_gtt gtt; /* VM representing the global address space */
1714 struct i915_gem_mm mm;
1715 DECLARE_HASHTABLE(mm_structs, 7);
1716 struct mutex mm_lock;
1718 /* Kernel Modesetting */
1720 struct sdvo_device_mapping sdvo_mappings[2];
1722 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1723 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1724 wait_queue_head_t pending_flip_queue;
1726 #ifdef CONFIG_DEBUG_FS
1727 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1730 int num_shared_dpll;
1731 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1732 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1734 struct i915_workarounds workarounds;
1736 /* Reclocking support */
1737 bool render_reclock_avail;
1738 bool lvds_downclock_avail;
1739 /* indicates the reduced downclock for LVDS*/
1742 struct i915_frontbuffer_tracking fb_tracking;
1746 bool mchbar_need_disable;
1748 struct intel_l3_parity l3_parity;
1750 /* Cannot be determined by PCIID. You must always read a register. */
1753 /* gen6+ rps state */
1754 struct intel_gen6_power_mgmt rps;
1756 /* ilk-only ips/rps state. Everything in here is protected by the global
1757 * mchdev_lock in intel_pm.c */
1758 struct intel_ilk_power_mgmt ips;
1760 struct i915_power_domains power_domains;
1762 struct i915_psr psr;
1764 struct i915_gpu_error gpu_error;
1766 struct drm_i915_gem_object *vlv_pctx;
1768 #ifdef CONFIG_DRM_I915_FBDEV
1769 /* list of fbdev register on this device */
1770 struct intel_fbdev *fbdev;
1771 struct work_struct fbdev_suspend_work;
1774 struct drm_property *broadcast_rgb_property;
1775 struct drm_property *force_audio_property;
1777 /* hda/i915 audio component */
1778 bool audio_component_registered;
1780 uint32_t hw_context_size;
1781 struct list_head context_list;
1786 struct i915_suspend_saved_registers regfile;
1787 struct vlv_s0ix_state vlv_s0ix_state;
1791 * Raw watermark latency values:
1792 * in 0.1us units for WM0,
1793 * in 0.5us units for WM1+.
1796 uint16_t pri_latency[5];
1798 uint16_t spr_latency[5];
1800 uint16_t cur_latency[5];
1802 * Raw watermark memory latency values
1803 * for SKL for all 8 levels
1806 uint16_t skl_latency[8];
1809 * The skl_wm_values structure is a bit too big for stack
1810 * allocation, so we keep the staging struct where we store
1811 * intermediate results here instead.
1813 struct skl_wm_values skl_results;
1815 /* current hardware state */
1817 struct ilk_wm_values hw;
1818 struct skl_wm_values skl_hw;
1822 struct i915_runtime_pm pm;
1824 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1825 u32 long_hpd_port_mask;
1826 u32 short_hpd_port_mask;
1827 struct work_struct dig_port_work;
1830 * if we get a HPD irq from DP and a HPD irq from non-DP
1831 * the non-DP HPD could block the workqueue on a mode config
1832 * mutex getting, that userspace may have taken. However
1833 * userspace is waiting on the DP workqueue to run which is
1834 * blocked behind the non-DP one.
1836 struct workqueue_struct *dp_wq;
1838 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1840 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1841 struct intel_engine_cs *ring,
1842 struct intel_context *ctx,
1843 struct drm_i915_gem_execbuffer2 *args,
1844 struct list_head *vmas,
1845 struct drm_i915_gem_object *batch_obj,
1846 u64 exec_start, u32 flags);
1847 int (*init_rings)(struct drm_device *dev);
1848 void (*cleanup_ring)(struct intel_engine_cs *ring);
1849 void (*stop_ring)(struct intel_engine_cs *ring);
1852 uint32_t request_uniq;
1855 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1856 * will be rejected. Instead look for a better place.
1860 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1862 return dev->dev_private;
1865 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1867 return to_i915(dev_get_drvdata(dev));
1870 /* Iterate over initialised rings */
1871 #define for_each_ring(ring__, dev_priv__, i__) \
1872 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1873 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1875 enum hdmi_force_audio {
1876 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1877 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1878 HDMI_AUDIO_AUTO, /* trust EDID */
1879 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1882 #define I915_GTT_OFFSET_NONE ((u32)-1)
1884 struct drm_i915_gem_object_ops {
1885 /* Interface between the GEM object and its backing storage.
1886 * get_pages() is called once prior to the use of the associated set
1887 * of pages before to binding them into the GTT, and put_pages() is
1888 * called after we no longer need them. As we expect there to be
1889 * associated cost with migrating pages between the backing storage
1890 * and making them available for the GPU (e.g. clflush), we may hold
1891 * onto the pages after they are no longer referenced by the GPU
1892 * in case they may be used again shortly (for example migrating the
1893 * pages to a different memory domain within the GTT). put_pages()
1894 * will therefore most likely be called when the object itself is
1895 * being released or under memory pressure (where we attempt to
1896 * reap pages for the shrinker).
1898 int (*get_pages)(struct drm_i915_gem_object *);
1899 void (*put_pages)(struct drm_i915_gem_object *);
1900 int (*dmabuf_export)(struct drm_i915_gem_object *);
1901 void (*release)(struct drm_i915_gem_object *);
1905 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1906 * considered to be the frontbuffer for the given plane interface-vise. This
1907 * doesn't mean that the hw necessarily already scans it out, but that any
1908 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1910 * We have one bit per pipe and per scanout plane type.
1912 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1913 #define INTEL_FRONTBUFFER_BITS \
1914 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1915 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1916 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1917 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1918 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1919 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1920 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1921 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1922 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1923 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1924 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1926 struct drm_i915_gem_object {
1927 struct drm_gem_object base;
1929 const struct drm_i915_gem_object_ops *ops;
1931 /** List of VMAs backed by this object */
1932 struct list_head vma_list;
1934 /** Stolen memory for this object, instead of being backed by shmem. */
1935 struct drm_mm_node *stolen;
1936 struct list_head global_list;
1938 struct list_head ring_list;
1939 /** Used in execbuf to temporarily hold a ref */
1940 struct list_head obj_exec_link;
1942 struct list_head batch_pool_list;
1945 * This is set if the object is on the active lists (has pending
1946 * rendering and so a non-zero seqno), and is not set if it i s on
1947 * inactive (ready to be unbound) list.
1949 unsigned int active:1;
1952 * This is set if the object has been written to since last bound
1955 unsigned int dirty:1;
1958 * Fence register bits (if any) for this object. Will be set
1959 * as needed when mapped into the GTT.
1960 * Protected by dev->struct_mutex.
1962 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1965 * Advice: are the backing pages purgeable?
1967 unsigned int madv:2;
1970 * Current tiling mode for the object.
1972 unsigned int tiling_mode:2;
1974 * Whether the tiling parameters for the currently associated fence
1975 * register have changed. Note that for the purposes of tracking
1976 * tiling changes we also treat the unfenced register, the register
1977 * slot that the object occupies whilst it executes a fenced
1978 * command (such as BLT on gen2/3), as a "fence".
1980 unsigned int fence_dirty:1;
1983 * Is the object at the current location in the gtt mappable and
1984 * fenceable? Used to avoid costly recalculations.
1986 unsigned int map_and_fenceable:1;
1989 * Whether the current gtt mapping needs to be mappable (and isn't just
1990 * mappable by accident). Track pin and fault separate for a more
1991 * accurate mappable working set.
1993 unsigned int fault_mappable:1;
1994 unsigned int pin_mappable:1;
1995 unsigned int pin_display:1;
1998 * Is the object to be mapped as read-only to the GPU
1999 * Only honoured if hardware has relevant pte bit
2001 unsigned long gt_ro:1;
2002 unsigned int cache_level:3;
2004 unsigned int has_dma_mapping:1;
2006 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2008 struct sg_table *pages;
2009 int pages_pin_count;
2011 /* prime dma-buf support */
2012 void *dma_buf_vmapping;
2015 /** Breadcrumb of last rendering to the buffer. */
2016 struct drm_i915_gem_request *last_read_req;
2017 struct drm_i915_gem_request *last_write_req;
2018 /** Breadcrumb of last fenced GPU access to the buffer. */
2019 struct drm_i915_gem_request *last_fenced_req;
2021 /** Current tiling stride for the object, if it's tiled. */
2024 /** References from framebuffers, locks out tiling changes. */
2025 unsigned long framebuffer_references;
2027 /** Record of address bit 17 of each page at last unbind. */
2028 unsigned long *bit_17;
2031 /** for phy allocated objects */
2032 struct drm_dma_handle *phys_handle;
2034 struct i915_gem_userptr {
2036 unsigned read_only :1;
2037 unsigned workers :4;
2038 #define I915_GEM_USERPTR_MAX_WORKERS 15
2040 struct i915_mm_struct *mm;
2041 struct i915_mmu_object *mmu_object;
2042 struct work_struct *work;
2046 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2048 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2049 struct drm_i915_gem_object *new,
2050 unsigned frontbuffer_bits);
2053 * Request queue structure.
2055 * The request queue allows us to note sequence numbers that have been emitted
2056 * and may be associated with active buffers to be retired.
2058 * By keeping this list, we can avoid having to do questionable sequence
2059 * number comparisons on buffer last_read|write_seqno. It also allows an
2060 * emission time to be associated with the request for tracking how far ahead
2061 * of the GPU the submission is.
2063 struct drm_i915_gem_request {
2066 /** On Which ring this request was generated */
2067 struct intel_engine_cs *ring;
2069 /** GEM sequence number associated with this request. */
2072 /** Position in the ringbuffer of the start of the request */
2075 /** Position in the ringbuffer of the end of the request */
2078 /** Context related to this request */
2079 struct intel_context *ctx;
2081 /** Batch buffer related to this request if any */
2082 struct drm_i915_gem_object *batch_obj;
2084 /** Time at which this request was emitted, in jiffies. */
2085 unsigned long emitted_jiffies;
2087 /** global list entry for this request */
2088 struct list_head list;
2090 struct drm_i915_file_private *file_priv;
2091 /** file_priv list entry for this request */
2092 struct list_head client_list;
2097 void i915_gem_request_free(struct kref *req_ref);
2099 static inline uint32_t
2100 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2102 return req ? req->seqno : 0;
2105 static inline struct intel_engine_cs *
2106 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2108 return req ? req->ring : NULL;
2112 i915_gem_request_reference(struct drm_i915_gem_request *req)
2114 kref_get(&req->ref);
2118 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2120 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2121 kref_put(&req->ref, i915_gem_request_free);
2124 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2125 struct drm_i915_gem_request *src)
2128 i915_gem_request_reference(src);
2131 i915_gem_request_unreference(*pdst);
2137 * XXX: i915_gem_request_completed should be here but currently needs the
2138 * definition of i915_seqno_passed() which is below. It will be moved in
2139 * a later patch when the call to i915_seqno_passed() is obsoleted...
2142 struct drm_i915_file_private {
2143 struct drm_i915_private *dev_priv;
2144 struct drm_file *file;
2148 struct list_head request_list;
2149 struct delayed_work idle_work;
2151 struct idr context_idr;
2153 atomic_t rps_wait_boost;
2154 struct intel_engine_cs *bsd_ring;
2158 * A command that requires special handling by the command parser.
2160 struct drm_i915_cmd_descriptor {
2162 * Flags describing how the command parser processes the command.
2164 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2165 * a length mask if not set
2166 * CMD_DESC_SKIP: The command is allowed but does not follow the
2167 * standard length encoding for the opcode range in
2169 * CMD_DESC_REJECT: The command is never allowed
2170 * CMD_DESC_REGISTER: The command should be checked against the
2171 * register whitelist for the appropriate ring
2172 * CMD_DESC_MASTER: The command is allowed if the submitting process
2176 #define CMD_DESC_FIXED (1<<0)
2177 #define CMD_DESC_SKIP (1<<1)
2178 #define CMD_DESC_REJECT (1<<2)
2179 #define CMD_DESC_REGISTER (1<<3)
2180 #define CMD_DESC_BITMASK (1<<4)
2181 #define CMD_DESC_MASTER (1<<5)
2184 * The command's unique identification bits and the bitmask to get them.
2185 * This isn't strictly the opcode field as defined in the spec and may
2186 * also include type, subtype, and/or subop fields.
2194 * The command's length. The command is either fixed length (i.e. does
2195 * not include a length field) or has a length field mask. The flag
2196 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2197 * a length mask. All command entries in a command table must include
2198 * length information.
2206 * Describes where to find a register address in the command to check
2207 * against the ring's register whitelist. Only valid if flags has the
2208 * CMD_DESC_REGISTER bit set.
2215 #define MAX_CMD_DESC_BITMASKS 3
2217 * Describes command checks where a particular dword is masked and
2218 * compared against an expected value. If the command does not match
2219 * the expected value, the parser rejects it. Only valid if flags has
2220 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2223 * If the check specifies a non-zero condition_mask then the parser
2224 * only performs the check when the bits specified by condition_mask
2231 u32 condition_offset;
2233 } bits[MAX_CMD_DESC_BITMASKS];
2237 * A table of commands requiring special handling by the command parser.
2239 * Each ring has an array of tables. Each table consists of an array of command
2240 * descriptors, which must be sorted with command opcodes in ascending order.
2242 struct drm_i915_cmd_table {
2243 const struct drm_i915_cmd_descriptor *table;
2247 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2248 #define __I915__(p) ({ \
2249 struct drm_i915_private *__p; \
2250 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2251 __p = (struct drm_i915_private *)p; \
2252 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2253 __p = to_i915((struct drm_device *)p); \
2258 #define INTEL_INFO(p) (&__I915__(p)->info)
2259 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2261 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2262 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2263 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2264 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2265 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2266 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2267 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2268 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2269 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2270 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2271 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2272 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2273 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2274 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2275 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2276 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2277 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2278 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2279 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2280 INTEL_DEVID(dev) == 0x0152 || \
2281 INTEL_DEVID(dev) == 0x015a)
2282 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2283 INTEL_DEVID(dev) == 0x0106 || \
2284 INTEL_DEVID(dev) == 0x010A)
2285 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2286 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2287 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2288 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2289 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2290 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2291 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2292 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2293 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2294 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2295 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2296 (INTEL_DEVID(dev) & 0xf) == 0xe))
2297 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2298 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2299 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2300 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2301 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2302 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2303 /* ULX machines are also considered ULT. */
2304 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2305 INTEL_DEVID(dev) == 0x0A1E)
2306 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2309 * The genX designation typically refers to the render engine, so render
2310 * capability related checks should use IS_GEN, while display and other checks
2311 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2314 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2315 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2316 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2317 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2318 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2319 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2320 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2321 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2323 #define RENDER_RING (1<<RCS)
2324 #define BSD_RING (1<<VCS)
2325 #define BLT_RING (1<<BCS)
2326 #define VEBOX_RING (1<<VECS)
2327 #define BSD2_RING (1<<VCS2)
2328 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2329 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2330 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2331 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2332 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2333 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2334 __I915__(dev)->ellc_size)
2335 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2337 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2338 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2339 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2340 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2342 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2343 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2345 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2346 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2348 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2349 * even when in MSI mode. This results in spurious interrupt warnings if the
2350 * legacy irq no. is shared with another device. The kernel then disables that
2351 * interrupt source and so prevents the other device from working properly.
2353 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2354 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2356 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2357 * rows, which changed the alignment requirements and fence programming.
2359 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2361 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2362 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2363 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2364 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2365 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2367 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2368 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2369 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2371 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2373 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2374 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2375 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2376 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2377 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2378 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2379 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2380 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2382 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2383 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2384 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2385 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2386 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2387 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2388 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2389 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2391 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2392 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2393 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2394 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2395 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2396 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2397 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2399 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2401 /* DPF == dynamic parity feature */
2402 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2403 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2405 #define GT_FREQUENCY_MULTIPLIER 50
2407 #include "i915_trace.h"
2409 extern const struct drm_ioctl_desc i915_ioctls[];
2410 extern int i915_max_ioctl;
2412 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2413 extern int i915_resume_legacy(struct drm_device *dev);
2414 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2415 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2418 struct i915_params {
2420 int panel_ignore_lid;
2421 unsigned int powersave;
2423 unsigned int lvds_downclock;
2424 int lvds_channel_mode;
2426 int vbt_sdvo_panel_type;
2430 int enable_execlists;
2432 unsigned int preliminary_hw_support;
2433 int disable_power_well;
2435 int invert_brightness;
2436 int enable_cmd_parser;
2437 /* leave bools at the end to not create holes */
2438 bool enable_hangcheck;
2440 bool prefault_disable;
2442 bool disable_display;
2443 bool disable_vtd_wa;
2446 bool verbose_state_checks;
2448 extern struct i915_params i915 __read_mostly;
2451 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2452 extern int i915_driver_unload(struct drm_device *);
2453 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2454 extern void i915_driver_lastclose(struct drm_device * dev);
2455 extern void i915_driver_preclose(struct drm_device *dev,
2456 struct drm_file *file);
2457 extern void i915_driver_postclose(struct drm_device *dev,
2458 struct drm_file *file);
2459 extern int i915_driver_device_is_agp(struct drm_device * dev);
2460 #ifdef CONFIG_COMPAT
2461 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2464 extern int intel_gpu_reset(struct drm_device *dev);
2465 extern int i915_reset(struct drm_device *dev);
2466 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2467 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2468 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2469 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2470 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2471 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2474 void i915_queue_hangcheck(struct drm_device *dev);
2476 void i915_handle_error(struct drm_device *dev, bool wedged,
2477 const char *fmt, ...);
2479 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2480 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2481 int intel_irq_install(struct drm_i915_private *dev_priv);
2482 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2484 extern void intel_uncore_sanitize(struct drm_device *dev);
2485 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2486 bool restore_forcewake);
2487 extern void intel_uncore_init(struct drm_device *dev);
2488 extern void intel_uncore_check_errors(struct drm_device *dev);
2489 extern void intel_uncore_fini(struct drm_device *dev);
2490 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2493 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2497 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2500 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2501 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2503 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2505 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2506 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2507 uint32_t interrupt_mask,
2508 uint32_t enabled_irq_mask);
2509 #define ibx_enable_display_interrupt(dev_priv, bits) \
2510 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2511 #define ibx_disable_display_interrupt(dev_priv, bits) \
2512 ibx_display_interrupt_update((dev_priv), (bits), 0)
2515 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2516 struct drm_file *file_priv);
2517 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2518 struct drm_file *file_priv);
2519 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2520 struct drm_file *file_priv);
2521 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2522 struct drm_file *file_priv);
2523 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2524 struct drm_file *file_priv);
2525 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2526 struct drm_file *file_priv);
2527 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2528 struct drm_file *file_priv);
2529 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2530 struct intel_engine_cs *ring);
2531 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2532 struct drm_file *file,
2533 struct intel_engine_cs *ring,
2534 struct drm_i915_gem_object *obj);
2535 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2536 struct drm_file *file,
2537 struct intel_engine_cs *ring,
2538 struct intel_context *ctx,
2539 struct drm_i915_gem_execbuffer2 *args,
2540 struct list_head *vmas,
2541 struct drm_i915_gem_object *batch_obj,
2542 u64 exec_start, u32 flags);
2543 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2544 struct drm_file *file_priv);
2545 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2546 struct drm_file *file_priv);
2547 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2548 struct drm_file *file_priv);
2549 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2550 struct drm_file *file);
2551 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2552 struct drm_file *file);
2553 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2554 struct drm_file *file_priv);
2555 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2556 struct drm_file *file_priv);
2557 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2558 struct drm_file *file_priv);
2559 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2560 struct drm_file *file_priv);
2561 int i915_gem_init_userptr(struct drm_device *dev);
2562 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2563 struct drm_file *file);
2564 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2565 struct drm_file *file_priv);
2566 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2567 struct drm_file *file_priv);
2568 void i915_gem_load(struct drm_device *dev);
2569 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2572 #define I915_SHRINK_PURGEABLE 0x1
2573 #define I915_SHRINK_UNBOUND 0x2
2574 #define I915_SHRINK_BOUND 0x4
2575 void *i915_gem_object_alloc(struct drm_device *dev);
2576 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2577 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2578 const struct drm_i915_gem_object_ops *ops);
2579 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2581 void i915_init_vm(struct drm_i915_private *dev_priv,
2582 struct i915_address_space *vm);
2583 void i915_gem_free_object(struct drm_gem_object *obj);
2584 void i915_gem_vma_destroy(struct i915_vma *vma);
2586 #define PIN_MAPPABLE 0x1
2587 #define PIN_NONBLOCK 0x2
2588 #define PIN_GLOBAL 0x4
2589 #define PIN_OFFSET_BIAS 0x8
2590 #define PIN_OFFSET_MASK (~4095)
2591 int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
2592 struct i915_address_space *vm,
2595 const struct i915_ggtt_view *view);
2597 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2598 struct i915_address_space *vm,
2602 return i915_gem_object_pin_view(obj, vm, alignment, flags,
2603 &i915_ggtt_view_normal);
2606 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2608 int __must_check i915_vma_unbind(struct i915_vma *vma);
2609 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2610 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2611 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2613 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2614 int *needs_clflush);
2616 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2617 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2619 struct sg_page_iter sg_iter;
2621 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2622 return sg_page_iter_page(&sg_iter);
2626 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2628 BUG_ON(obj->pages == NULL);
2629 obj->pages_pin_count++;
2631 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2633 BUG_ON(obj->pages_pin_count == 0);
2634 obj->pages_pin_count--;
2637 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2638 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2639 struct intel_engine_cs *to);
2640 void i915_vma_move_to_active(struct i915_vma *vma,
2641 struct intel_engine_cs *ring);
2642 int i915_gem_dumb_create(struct drm_file *file_priv,
2643 struct drm_device *dev,
2644 struct drm_mode_create_dumb *args);
2645 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2646 uint32_t handle, uint64_t *offset);
2648 * Returns true if seq1 is later than seq2.
2651 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2653 return (int32_t)(seq1 - seq2) >= 0;
2656 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2657 bool lazy_coherency)
2661 BUG_ON(req == NULL);
2663 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2665 return i915_seqno_passed(seqno, req->seqno);
2668 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2669 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2670 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2671 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2673 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2674 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2676 struct drm_i915_gem_request *
2677 i915_gem_find_active_request(struct intel_engine_cs *ring);
2679 bool i915_gem_retire_requests(struct drm_device *dev);
2680 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2681 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2682 bool interruptible);
2683 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2685 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2687 return unlikely(atomic_read(&error->reset_counter)
2688 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2691 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2693 return atomic_read(&error->reset_counter) & I915_WEDGED;
2696 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2698 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2701 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2703 return dev_priv->gpu_error.stop_rings == 0 ||
2704 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2707 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2709 return dev_priv->gpu_error.stop_rings == 0 ||
2710 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2713 void i915_gem_reset(struct drm_device *dev);
2714 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2715 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2716 int __must_check i915_gem_init(struct drm_device *dev);
2717 int i915_gem_init_rings(struct drm_device *dev);
2718 int __must_check i915_gem_init_hw(struct drm_device *dev);
2719 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2720 void i915_gem_init_swizzling(struct drm_device *dev);
2721 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2722 int __must_check i915_gpu_idle(struct drm_device *dev);
2723 int __must_check i915_gem_suspend(struct drm_device *dev);
2724 int __i915_add_request(struct intel_engine_cs *ring,
2725 struct drm_file *file,
2726 struct drm_i915_gem_object *batch_obj);
2727 #define i915_add_request(ring) \
2728 __i915_add_request(ring, NULL, NULL)
2729 int __i915_wait_request(struct drm_i915_gem_request *req,
2730 unsigned reset_counter,
2733 struct drm_i915_file_private *file_priv);
2734 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2735 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2737 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2740 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2742 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2744 struct intel_engine_cs *pipelined);
2745 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2746 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2748 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2749 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2752 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2754 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2755 int tiling_mode, bool fenced);
2757 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2758 enum i915_cache_level cache_level);
2760 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2761 struct dma_buf *dma_buf);
2763 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2764 struct drm_gem_object *gem_obj, int flags);
2766 void i915_gem_restore_fences(struct drm_device *dev);
2768 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
2769 struct i915_address_space *vm,
2770 enum i915_ggtt_view_type view);
2772 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2773 struct i915_address_space *vm)
2775 return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL);
2777 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2778 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
2779 struct i915_address_space *vm,
2780 enum i915_ggtt_view_type view);
2782 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2783 struct i915_address_space *vm)
2785 return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL);
2788 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2789 struct i915_address_space *vm);
2790 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
2791 struct i915_address_space *vm,
2792 const struct i915_ggtt_view *view);
2794 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2795 struct i915_address_space *vm)
2797 return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal);
2801 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj,
2802 struct i915_address_space *vm,
2803 const struct i915_ggtt_view *view);
2807 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2808 struct i915_address_space *vm)
2810 return i915_gem_obj_lookup_or_create_vma_view(obj, vm,
2811 &i915_ggtt_view_normal);
2814 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2815 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2816 struct i915_vma *vma;
2817 list_for_each_entry(vma, &obj->vma_list, vma_link)
2818 if (vma->pin_count > 0)
2823 /* Some GGTT VM helpers */
2824 #define i915_obj_to_ggtt(obj) \
2825 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2826 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2828 struct i915_address_space *ggtt =
2829 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2833 static inline struct i915_hw_ppgtt *
2834 i915_vm_to_ppgtt(struct i915_address_space *vm)
2836 WARN_ON(i915_is_ggtt(vm));
2838 return container_of(vm, struct i915_hw_ppgtt, base);
2842 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2844 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2847 static inline unsigned long
2848 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2850 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2853 static inline unsigned long
2854 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2856 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2859 static inline int __must_check
2860 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2864 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2865 alignment, flags | PIN_GLOBAL);
2869 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2871 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2874 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2876 /* i915_gem_context.c */
2877 int __must_check i915_gem_context_init(struct drm_device *dev);
2878 void i915_gem_context_fini(struct drm_device *dev);
2879 void i915_gem_context_reset(struct drm_device *dev);
2880 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2881 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2882 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2883 int i915_switch_context(struct intel_engine_cs *ring,
2884 struct intel_context *to);
2885 struct intel_context *
2886 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2887 void i915_gem_context_free(struct kref *ctx_ref);
2888 struct drm_i915_gem_object *
2889 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2890 static inline void i915_gem_context_reference(struct intel_context *ctx)
2892 kref_get(&ctx->ref);
2895 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2897 kref_put(&ctx->ref, i915_gem_context_free);
2900 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2902 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2905 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2906 struct drm_file *file);
2907 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2908 struct drm_file *file);
2909 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2910 struct drm_file *file_priv);
2911 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2912 struct drm_file *file_priv);
2914 /* i915_gem_evict.c */
2915 int __must_check i915_gem_evict_something(struct drm_device *dev,
2916 struct i915_address_space *vm,
2919 unsigned cache_level,
2920 unsigned long start,
2923 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2924 int i915_gem_evict_everything(struct drm_device *dev);
2926 /* belongs in i915_gem_gtt.h */
2927 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2929 if (INTEL_INFO(dev)->gen < 6)
2930 intel_gtt_chipset_flush();
2933 /* i915_gem_stolen.c */
2934 int i915_gem_init_stolen(struct drm_device *dev);
2935 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2936 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2937 void i915_gem_cleanup_stolen(struct drm_device *dev);
2938 struct drm_i915_gem_object *
2939 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2940 struct drm_i915_gem_object *
2941 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2946 /* i915_gem_tiling.c */
2947 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2949 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2951 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2952 obj->tiling_mode != I915_TILING_NONE;
2955 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2956 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2957 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2959 /* i915_gem_debug.c */
2961 int i915_verify_lists(struct drm_device *dev);
2963 #define i915_verify_lists(dev) 0
2966 /* i915_debugfs.c */
2967 int i915_debugfs_init(struct drm_minor *minor);
2968 void i915_debugfs_cleanup(struct drm_minor *minor);
2969 #ifdef CONFIG_DEBUG_FS
2970 void intel_display_crc_init(struct drm_device *dev);
2972 static inline void intel_display_crc_init(struct drm_device *dev) {}
2975 /* i915_gpu_error.c */
2977 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2978 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2979 const struct i915_error_state_file_priv *error);
2980 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2981 struct drm_i915_private *i915,
2982 size_t count, loff_t pos);
2983 static inline void i915_error_state_buf_release(
2984 struct drm_i915_error_state_buf *eb)
2988 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2989 const char *error_msg);
2990 void i915_error_state_get(struct drm_device *dev,
2991 struct i915_error_state_file_priv *error_priv);
2992 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2993 void i915_destroy_error_state(struct drm_device *dev);
2995 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2996 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2998 /* i915_gem_batch_pool.c */
2999 void i915_gem_batch_pool_init(struct drm_device *dev,
3000 struct i915_gem_batch_pool *pool);
3001 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
3002 struct drm_i915_gem_object*
3003 i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
3005 /* i915_cmd_parser.c */
3006 int i915_cmd_parser_get_version(void);
3007 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3008 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3009 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3010 int i915_parse_cmds(struct intel_engine_cs *ring,
3011 struct drm_i915_gem_object *batch_obj,
3012 struct drm_i915_gem_object *shadow_batch_obj,
3013 u32 batch_start_offset,
3017 /* i915_suspend.c */
3018 extern int i915_save_state(struct drm_device *dev);
3019 extern int i915_restore_state(struct drm_device *dev);
3022 void i915_save_display_reg(struct drm_device *dev);
3023 void i915_restore_display_reg(struct drm_device *dev);
3026 void i915_setup_sysfs(struct drm_device *dev_priv);
3027 void i915_teardown_sysfs(struct drm_device *dev_priv);
3030 extern int intel_setup_gmbus(struct drm_device *dev);
3031 extern void intel_teardown_gmbus(struct drm_device *dev);
3032 static inline bool intel_gmbus_is_port_valid(unsigned port)
3034 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3037 extern struct i2c_adapter *intel_gmbus_get_adapter(
3038 struct drm_i915_private *dev_priv, unsigned port);
3039 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3040 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3041 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3043 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3045 extern void intel_i2c_reset(struct drm_device *dev);
3047 /* intel_opregion.c */
3049 extern int intel_opregion_setup(struct drm_device *dev);
3050 extern void intel_opregion_init(struct drm_device *dev);
3051 extern void intel_opregion_fini(struct drm_device *dev);
3052 extern void intel_opregion_asle_intr(struct drm_device *dev);
3053 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3055 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3058 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3059 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3060 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3061 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3063 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3068 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3076 extern void intel_register_dsm_handler(void);
3077 extern void intel_unregister_dsm_handler(void);
3079 static inline void intel_register_dsm_handler(void) { return; }
3080 static inline void intel_unregister_dsm_handler(void) { return; }
3081 #endif /* CONFIG_ACPI */
3084 extern void intel_modeset_init_hw(struct drm_device *dev);
3085 extern void intel_modeset_init(struct drm_device *dev);
3086 extern void intel_modeset_gem_init(struct drm_device *dev);
3087 extern void intel_modeset_cleanup(struct drm_device *dev);
3088 extern void intel_connector_unregister(struct intel_connector *);
3089 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3090 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3091 bool force_restore);
3092 extern void i915_redisable_vga(struct drm_device *dev);
3093 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3094 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3095 extern void intel_init_pch_refclk(struct drm_device *dev);
3096 extern void gen6_set_rps(struct drm_device *dev, u8 val);
3097 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
3098 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3100 extern void intel_detect_pch(struct drm_device *dev);
3101 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3102 extern int intel_enable_rc6(const struct drm_device *dev);
3104 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3105 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3106 struct drm_file *file);
3107 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3108 struct drm_file *file);
3110 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
3113 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3114 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3115 struct intel_overlay_error_state *error);
3117 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3118 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3119 struct drm_device *dev,
3120 struct intel_display_error_state *error);
3122 /* On SNB platform, before reading ring registers forcewake bit
3123 * must be set to prevent GT core from power down and stale values being
3126 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
3127 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
3128 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
3130 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3131 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3133 /* intel_sideband.c */
3134 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
3135 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
3136 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3137 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3138 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3139 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3140 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3141 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3142 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3143 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3144 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3145 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3146 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3147 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3148 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3149 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3150 enum intel_sbi_destination destination);
3151 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3152 enum intel_sbi_destination destination);
3153 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3154 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3156 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
3157 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
3159 #define FORCEWAKE_RENDER (1 << 0)
3160 #define FORCEWAKE_MEDIA (1 << 1)
3161 #define FORCEWAKE_BLITTER (1 << 2)
3162 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
3166 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3167 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3169 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3170 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3171 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3172 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3174 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3175 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3176 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3177 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3179 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3180 * will be implemented using 2 32-bit writes in an arbitrary order with
3181 * an arbitrary delay between them. This can cause the hardware to
3182 * act upon the intermediate value, possibly leading to corruption and
3183 * machine death. You have been warned.
3185 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3186 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3188 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3189 u32 upper = I915_READ(upper_reg); \
3190 u32 lower = I915_READ(lower_reg); \
3191 u32 tmp = I915_READ(upper_reg); \
3192 if (upper != tmp) { \
3194 lower = I915_READ(lower_reg); \
3195 WARN_ON(I915_READ(upper_reg) != upper); \
3197 (u64)upper << 32 | lower; })
3199 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3200 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3202 /* "Broadcast RGB" property */
3203 #define INTEL_BROADCAST_RGB_AUTO 0
3204 #define INTEL_BROADCAST_RGB_FULL 1
3205 #define INTEL_BROADCAST_RGB_LIMITED 2
3207 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3209 if (IS_VALLEYVIEW(dev))
3210 return VLV_VGACNTRL;
3211 else if (INTEL_INFO(dev)->gen >= 5)
3212 return CPU_VGACNTRL;
3217 static inline void __user *to_user_ptr(u64 address)
3219 return (void __user *)(uintptr_t)address;
3222 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3224 unsigned long j = msecs_to_jiffies(m);
3226 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3229 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3231 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3234 static inline unsigned long
3235 timespec_to_jiffies_timeout(const struct timespec *value)
3237 unsigned long j = timespec_to_jiffies(value);
3239 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3243 * If you need to wait X milliseconds between events A and B, but event B
3244 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3245 * when event A happened, then just before event B you call this function and
3246 * pass the timestamp as the first argument, and X as the second argument.
3249 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3251 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3254 * Don't re-read the value of "jiffies" every time since it may change
3255 * behind our back and break the math.
3257 tmp_jiffies = jiffies;
3258 target_jiffies = timestamp_jiffies +
3259 msecs_to_jiffies_timeout(to_wait_ms);
3261 if (time_after(target_jiffies, tmp_jiffies)) {
3262 remaining_jiffies = target_jiffies - tmp_jiffies;
3263 while (remaining_jiffies)
3265 schedule_timeout_uninterruptible(remaining_jiffies);
3269 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3270 struct drm_i915_gem_request *req)
3272 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3273 i915_gem_request_assign(&ring->trace_irq_req, req);