1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
87 #define port_name(p) ((p) + 'A')
91 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
92 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
102 #define I915_GEM_GPU_DOMAINS \
103 (I915_GEM_DOMAIN_RENDER | \
104 I915_GEM_DOMAIN_SAMPLER | \
105 I915_GEM_DOMAIN_COMMAND | \
106 I915_GEM_DOMAIN_INSTRUCTION | \
107 I915_GEM_DOMAIN_VERTEX)
109 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
111 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
112 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
113 if ((intel_encoder)->base.crtc == (__crtc))
115 struct intel_pch_pll {
116 int refcount; /* count of number of CRTCs sharing this PLL */
117 int active; /* count of number of active CRTCs (i.e. DPMS on) */
118 bool on; /* is the PLL actually active? Disabled during modeset */
123 #define I915_NUM_PLLS 2
125 /* Used by dp and fdi links */
126 struct intel_link_m_n {
134 void intel_link_compute_m_n(int bpp, int nlanes,
135 int pixel_clock, int link_clock,
136 struct intel_link_m_n *m_n);
138 struct intel_ddi_plls {
144 /* Interface history:
147 * 1.2: Add Power Management
148 * 1.3: Add vblank support
149 * 1.4: Fix cmdbuffer path, add heap destroy
150 * 1.5: Add vblank pipe configuration
151 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
152 * - Support vertical blank on secondary display pipe
154 #define DRIVER_MAJOR 1
155 #define DRIVER_MINOR 6
156 #define DRIVER_PATCHLEVEL 0
158 #define WATCH_COHERENCY 0
159 #define WATCH_LISTS 0
162 #define I915_GEM_PHYS_CURSOR_0 1
163 #define I915_GEM_PHYS_CURSOR_1 2
164 #define I915_GEM_PHYS_OVERLAY_REGS 3
165 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
167 struct drm_i915_gem_phys_object {
169 struct page **page_list;
170 drm_dma_handle_t *handle;
171 struct drm_i915_gem_object *cur_obj;
174 struct opregion_header;
175 struct opregion_acpi;
176 struct opregion_swsci;
177 struct opregion_asle;
178 struct drm_i915_private;
180 struct intel_opregion {
181 struct opregion_header __iomem *header;
182 struct opregion_acpi __iomem *acpi;
183 struct opregion_swsci __iomem *swsci;
184 struct opregion_asle __iomem *asle;
186 u32 __iomem *lid_state;
188 #define OPREGION_SIZE (8*1024)
190 struct intel_overlay;
191 struct intel_overlay_error_state;
193 struct drm_i915_master_private {
194 drm_local_map_t *sarea;
195 struct _drm_i915_sarea *sarea_priv;
197 #define I915_FENCE_REG_NONE -1
198 #define I915_MAX_NUM_FENCES 16
199 /* 16 fences + sign bit for FENCE_REG_NONE */
200 #define I915_MAX_NUM_FENCE_BITS 5
202 struct drm_i915_fence_reg {
203 struct list_head lru_list;
204 struct drm_i915_gem_object *obj;
208 struct sdvo_device_mapping {
217 struct intel_display_error_state;
219 struct drm_i915_error_state {
227 bool waiting[I915_NUM_RINGS];
228 u32 pipestat[I915_MAX_PIPES];
229 u32 tail[I915_NUM_RINGS];
230 u32 head[I915_NUM_RINGS];
231 u32 ctl[I915_NUM_RINGS];
232 u32 ipeir[I915_NUM_RINGS];
233 u32 ipehr[I915_NUM_RINGS];
234 u32 instdone[I915_NUM_RINGS];
235 u32 acthd[I915_NUM_RINGS];
236 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
237 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
238 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
239 /* our own tracking of ring head and tail */
240 u32 cpu_ring_head[I915_NUM_RINGS];
241 u32 cpu_ring_tail[I915_NUM_RINGS];
242 u32 error; /* gen6+ */
243 u32 err_int; /* gen7 */
244 u32 instpm[I915_NUM_RINGS];
245 u32 instps[I915_NUM_RINGS];
246 u32 extra_instdone[I915_NUM_INSTDONE_REG];
247 u32 seqno[I915_NUM_RINGS];
249 u32 fault_reg[I915_NUM_RINGS];
251 u32 faddr[I915_NUM_RINGS];
252 u64 fence[I915_MAX_NUM_FENCES];
254 struct drm_i915_error_ring {
255 struct drm_i915_error_object {
259 } *ringbuffer, *batchbuffer, *ctx;
260 struct drm_i915_error_request {
266 } ring[I915_NUM_RINGS];
267 struct drm_i915_error_buffer {
274 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
281 } *active_bo, *pinned_bo;
282 u32 active_bo_count, pinned_bo_count;
283 struct intel_overlay_error_state *overlay;
284 struct intel_display_error_state *display;
287 struct intel_crtc_config;
289 struct drm_i915_display_funcs {
290 bool (*fbc_enabled)(struct drm_device *dev);
291 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
292 void (*disable_fbc)(struct drm_device *dev);
293 int (*get_display_clock_speed)(struct drm_device *dev);
294 int (*get_fifo_size)(struct drm_device *dev, int plane);
295 void (*update_wm)(struct drm_device *dev);
296 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
297 uint32_t sprite_width, int pixel_size);
298 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
299 struct drm_display_mode *mode);
300 void (*modeset_global_resources)(struct drm_device *dev);
301 int (*crtc_mode_set)(struct drm_crtc *crtc,
303 struct drm_framebuffer *old_fb);
304 void (*crtc_enable)(struct drm_crtc *crtc);
305 void (*crtc_disable)(struct drm_crtc *crtc);
306 void (*off)(struct drm_crtc *crtc);
307 void (*write_eld)(struct drm_connector *connector,
308 struct drm_crtc *crtc);
309 void (*fdi_link_train)(struct drm_crtc *crtc);
310 void (*init_clock_gating)(struct drm_device *dev);
311 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
312 struct drm_framebuffer *fb,
313 struct drm_i915_gem_object *obj);
314 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
316 void (*hpd_irq_setup)(struct drm_device *dev);
317 /* clock updates for mode set */
319 /* render clock increase/decrease */
320 /* display clock increase/decrease */
321 /* pll clock increase/decrease */
324 struct drm_i915_gt_funcs {
325 void (*force_wake_get)(struct drm_i915_private *dev_priv);
326 void (*force_wake_put)(struct drm_i915_private *dev_priv);
329 #define DEV_INFO_FLAGS \
330 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
331 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
332 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
333 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
334 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
335 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
336 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
337 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
338 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
339 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
340 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
341 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
342 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
343 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
344 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
345 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
346 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
347 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
348 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
349 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
350 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
351 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
352 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
353 DEV_INFO_FLAG(has_llc)
355 struct intel_device_info {
356 u32 display_mmio_offset;
376 u8 cursor_needs_physical:1;
378 u8 overlay_needs_physical:1;
385 enum i915_cache_level {
388 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
391 /* The Graphics Translation Table is the way in which GEN hardware translates a
392 * Graphics Virtual Address into a Physical Address. In addition to the normal
393 * collateral associated with any va->pa translations GEN hardware also has a
394 * portion of the GTT which can be mapped by the CPU and remain both coherent
395 * and correct (in cases like swizzling). That region is referred to as GMADR in
399 unsigned long start; /* Start offset of used GTT */
400 size_t total; /* Total size GTT can map */
401 size_t stolen_size; /* Total size of stolen memory */
403 unsigned long mappable_end; /* End offset that we can CPU map */
404 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
405 phys_addr_t mappable_base; /* PA of our GMADR */
407 /** "Graphics Stolen Memory" holds the global PTEs */
411 dma_addr_t scratch_page_dma;
412 struct page *scratch_page;
415 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
416 size_t *stolen, phys_addr_t *mappable_base,
417 unsigned long *mappable_end);
418 void (*gtt_remove)(struct drm_device *dev);
419 void (*gtt_clear_range)(struct drm_device *dev,
420 unsigned int first_entry,
421 unsigned int num_entries);
422 void (*gtt_insert_entries)(struct drm_device *dev,
424 unsigned int pg_start,
425 enum i915_cache_level cache_level);
427 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
429 #define I915_PPGTT_PD_ENTRIES 512
430 #define I915_PPGTT_PT_ENTRIES 1024
431 struct i915_hw_ppgtt {
432 struct drm_device *dev;
433 unsigned num_pd_entries;
434 struct page **pt_pages;
436 dma_addr_t *pt_dma_addr;
437 dma_addr_t scratch_page_dma_addr;
439 /* pte functions, mirroring the interface of the global gtt. */
440 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
441 unsigned int first_entry,
442 unsigned int num_entries);
443 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
445 unsigned int pg_start,
446 enum i915_cache_level cache_level);
447 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
451 /* This must match up with the value previously used for execbuf2.rsvd1. */
452 #define DEFAULT_CONTEXT_ID 0
453 struct i915_hw_context {
456 struct drm_i915_file_private *file_priv;
457 struct intel_ring_buffer *ring;
458 struct drm_i915_gem_object *obj;
462 FBC_NO_OUTPUT, /* no outputs enabled to compress */
463 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
464 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
465 FBC_MODE_TOO_LARGE, /* mode too large for compression */
466 FBC_BAD_PLANE, /* fbc not supported on plane */
467 FBC_NOT_TILED, /* buffer not tiled */
468 FBC_MULTIPLE_PIPES, /* more than one pipe active */
473 PCH_NONE = 0, /* No PCH present */
474 PCH_IBX, /* Ibexpeak PCH */
475 PCH_CPT, /* Cougarpoint PCH */
476 PCH_LPT, /* Lynxpoint PCH */
479 enum intel_sbi_destination {
484 #define QUIRK_PIPEA_FORCE (1<<0)
485 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
486 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
489 struct intel_fbc_work;
492 struct i2c_adapter adapter;
496 struct i2c_algo_bit_data bit_algo;
497 struct drm_i915_private *dev_priv;
500 struct i915_suspend_saved_registers {
521 u32 saveTRANS_HTOTAL_A;
522 u32 saveTRANS_HBLANK_A;
523 u32 saveTRANS_HSYNC_A;
524 u32 saveTRANS_VTOTAL_A;
525 u32 saveTRANS_VBLANK_A;
526 u32 saveTRANS_VSYNC_A;
534 u32 savePFIT_PGM_RATIOS;
535 u32 saveBLC_HIST_CTL;
537 u32 saveBLC_PWM_CTL2;
538 u32 saveBLC_CPU_PWM_CTL;
539 u32 saveBLC_CPU_PWM_CTL2;
552 u32 saveTRANS_HTOTAL_B;
553 u32 saveTRANS_HBLANK_B;
554 u32 saveTRANS_HSYNC_B;
555 u32 saveTRANS_VTOTAL_B;
556 u32 saveTRANS_VBLANK_B;
557 u32 saveTRANS_VSYNC_B;
571 u32 savePP_ON_DELAYS;
572 u32 savePP_OFF_DELAYS;
580 u32 savePFIT_CONTROL;
581 u32 save_palette_a[256];
582 u32 save_palette_b[256];
583 u32 saveDPFC_CB_BASE;
584 u32 saveFBC_CFB_BASE;
587 u32 saveFBC_CONTROL2;
597 u32 saveCACHE_MODE_0;
598 u32 saveMI_ARB_STATE;
609 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
620 u32 savePIPEA_GMCH_DATA_M;
621 u32 savePIPEB_GMCH_DATA_M;
622 u32 savePIPEA_GMCH_DATA_N;
623 u32 savePIPEB_GMCH_DATA_N;
624 u32 savePIPEA_DP_LINK_M;
625 u32 savePIPEB_DP_LINK_M;
626 u32 savePIPEA_DP_LINK_N;
627 u32 savePIPEB_DP_LINK_N;
638 u32 savePCH_DREF_CONTROL;
639 u32 saveDISP_ARB_CTL;
640 u32 savePIPEA_DATA_M1;
641 u32 savePIPEA_DATA_N1;
642 u32 savePIPEA_LINK_M1;
643 u32 savePIPEA_LINK_N1;
644 u32 savePIPEB_DATA_M1;
645 u32 savePIPEB_DATA_N1;
646 u32 savePIPEB_LINK_M1;
647 u32 savePIPEB_LINK_N1;
648 u32 saveMCHBAR_RENDER_STANDBY;
649 u32 savePCH_PORT_HOTPLUG;
652 struct intel_gen6_power_mgmt {
653 struct work_struct work;
655 /* lock - irqsave spinlock that protectects the work_struct and
659 /* The below variables an all the rps hw state are protected by
660 * dev->struct mutext. */
665 struct delayed_work delayed_resume_work;
668 * Protects RPS/RC6 register access and PCU communication.
669 * Must be taken after struct_mutex if nested.
671 struct mutex hw_lock;
674 /* defined intel_pm.c */
675 extern spinlock_t mchdev_lock;
677 struct intel_ilk_power_mgmt {
685 unsigned long last_time1;
686 unsigned long chipset_power;
688 struct timespec last_time2;
689 unsigned long gfx_power;
695 struct drm_i915_gem_object *pwrctx;
696 struct drm_i915_gem_object *renderctx;
699 struct i915_dri1_state {
700 unsigned allow_batchbuffer : 1;
701 u32 __iomem *gfx_hws_cpu_addr;
712 struct intel_l3_parity {
714 struct work_struct error_work;
718 /** Memory allocator for GTT stolen memory */
719 struct drm_mm stolen;
720 /** Memory allocator for GTT */
721 struct drm_mm gtt_space;
722 /** List of all objects in gtt_space. Used to restore gtt
723 * mappings on resume */
724 struct list_head bound_list;
726 * List of objects which are not bound to the GTT (thus
727 * are idle and not used by the GPU) but still have
728 * (presumably uncached) pages still attached.
730 struct list_head unbound_list;
732 /** Usable portion of the GTT for GEM */
733 unsigned long stolen_base; /* limited to low memory (32-bit) */
737 /** PPGTT used for aliasing the PPGTT with the GTT */
738 struct i915_hw_ppgtt *aliasing_ppgtt;
740 struct shrinker inactive_shrinker;
741 bool shrinker_no_lock_stealing;
744 * List of objects currently involved in rendering.
746 * Includes buffers having the contents of their GPU caches
747 * flushed, not necessarily primitives. last_rendering_seqno
748 * represents when the rendering involved will be completed.
750 * A reference is held on the buffer while on this list.
752 struct list_head active_list;
755 * LRU list of objects which are not in the ringbuffer and
756 * are ready to unbind, but are still in the GTT.
758 * last_rendering_seqno is 0 while an object is in this list.
760 * A reference is not held on the buffer while on this list,
761 * as merely being GTT-bound shouldn't prevent its being
762 * freed, and we'll pull it off the list in the free path.
764 struct list_head inactive_list;
766 /** LRU list of objects with fence regs on them. */
767 struct list_head fence_list;
770 * We leave the user IRQ off as much as possible,
771 * but this means that requests will finish and never
772 * be retired once the system goes idle. Set a timer to
773 * fire periodically while the ring is running. When it
774 * fires, go retire requests.
776 struct delayed_work retire_work;
779 * Are we in a non-interruptible section of code like
785 * Flag if the X Server, and thus DRM, is not currently in
786 * control of the device.
788 * This is set between LeaveVT and EnterVT. It needs to be
789 * replaced with a semaphore. It also needs to be
790 * transitioned away from for kernel modesetting.
794 /** Bit 6 swizzling required for X tiling */
795 uint32_t bit_6_swizzle_x;
796 /** Bit 6 swizzling required for Y tiling */
797 uint32_t bit_6_swizzle_y;
799 /* storage for physical objects */
800 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
802 /* accounting, useful for userland debugging */
803 size_t object_memory;
807 struct i915_gpu_error {
808 /* For hangcheck timer */
809 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
810 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
811 struct timer_list hangcheck_timer;
813 uint32_t last_acthd[I915_NUM_RINGS];
814 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
816 /* For reset and error_state handling. */
818 /* Protected by the above dev->gpu_error.lock. */
819 struct drm_i915_error_state *first_error;
820 struct work_struct work;
822 unsigned long last_reset;
825 * State variable and reset counter controlling the reset flow
827 * Upper bits are for the reset counter. This counter is used by the
828 * wait_seqno code to race-free noticed that a reset event happened and
829 * that it needs to restart the entire ioctl (since most likely the
830 * seqno it waited for won't ever signal anytime soon).
832 * This is important for lock-free wait paths, where no contended lock
833 * naturally enforces the correct ordering between the bail-out of the
834 * waiter and the gpu reset work code.
836 * Lowest bit controls the reset state machine: Set means a reset is in
837 * progress. This state will (presuming we don't have any bugs) decay
838 * into either unset (successful reset) or the special WEDGED value (hw
839 * terminally sour). All waiters on the reset_queue will be woken when
842 atomic_t reset_counter;
845 * Special values/flags for reset_counter
847 * Note that the code relies on
848 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
851 #define I915_RESET_IN_PROGRESS_FLAG 1
852 #define I915_WEDGED 0xffffffff
855 * Waitqueue to signal when the reset has completed. Used by clients
856 * that wait for dev_priv->mm.wedged to settle.
858 wait_queue_head_t reset_queue;
860 /* For gpu hang simulation. */
861 unsigned int stop_rings;
864 enum modeset_restore {
870 typedef struct drm_i915_private {
871 struct drm_device *dev;
872 struct kmem_cache *slab;
874 const struct intel_device_info *info;
876 int relative_constants_mode;
880 struct drm_i915_gt_funcs gt;
881 /** gt_fifo_count and the subsequent register write are synchronized
882 * with dev->struct_mutex. */
883 unsigned gt_fifo_count;
884 /** forcewake_count is protected by gt_lock */
885 unsigned forcewake_count;
886 /** gt_lock is also taken in irq contexts. */
889 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
892 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
893 * controller on different i2c buses. */
894 struct mutex gmbus_mutex;
897 * Base address of the gmbus and gpio block.
899 uint32_t gpio_mmio_base;
901 wait_queue_head_t gmbus_wait_queue;
903 struct pci_dev *bridge_dev;
904 struct intel_ring_buffer ring[I915_NUM_RINGS];
905 uint32_t last_seqno, next_seqno;
907 drm_dma_handle_t *status_page_dmah;
908 struct resource mch_res;
910 atomic_t irq_received;
912 /* protects the irq masks */
915 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
916 struct pm_qos_request pm_qos;
918 /* DPIO indirect register protection */
919 struct mutex dpio_lock;
921 /** Cached value of IMR to avoid reads in updating the bitfield */
925 struct work_struct hotplug_work;
926 bool enable_hotplug_processing;
931 unsigned long cfb_size;
933 enum plane cfb_plane;
935 struct intel_fbc_work *fbc_work;
937 struct intel_opregion opregion;
940 struct intel_overlay *overlay;
941 unsigned int sprite_scaling_enabled;
947 struct backlight_device *device;
951 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
952 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
954 /* Feature bits from the VBIOS */
955 unsigned int int_tv_support:1;
956 unsigned int lvds_dither:1;
957 unsigned int lvds_vbt:1;
958 unsigned int int_crt_support:1;
959 unsigned int lvds_use_ssc:1;
960 unsigned int display_clock_mode:1;
962 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
972 struct edp_power_seq pps;
974 bool no_aux_handshake;
977 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
978 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
979 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
981 unsigned int fsb_freq, mem_freq, is_ddr3;
983 struct workqueue_struct *wq;
985 /* Display functions */
986 struct drm_i915_display_funcs display;
988 /* PCH chipset type */
989 enum intel_pch pch_type;
990 unsigned short pch_id;
992 unsigned long quirks;
994 enum modeset_restore modeset_restore;
995 struct mutex modeset_restore_lock;
999 struct i915_gem_mm mm;
1001 /* Kernel Modesetting */
1003 struct sdvo_device_mapping sdvo_mappings[2];
1004 /* indicate whether the LVDS_BORDER should be enabled or not */
1005 unsigned int lvds_border_bits;
1006 /* Panel fitter placement and size for Ironlake+ */
1007 u32 pch_pf_pos, pch_pf_size;
1009 struct drm_crtc *plane_to_crtc_mapping[3];
1010 struct drm_crtc *pipe_to_crtc_mapping[3];
1011 wait_queue_head_t pending_flip_queue;
1013 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
1014 struct intel_ddi_plls ddi_plls;
1016 /* Reclocking support */
1017 bool render_reclock_avail;
1018 bool lvds_downclock_avail;
1019 /* indicates the reduced downclock for LVDS*/
1023 struct child_device_config *child_dev;
1025 bool mchbar_need_disable;
1027 struct intel_l3_parity l3_parity;
1029 /* gen6+ rps state */
1030 struct intel_gen6_power_mgmt rps;
1032 /* ilk-only ips/rps state. Everything in here is protected by the global
1033 * mchdev_lock in intel_pm.c */
1034 struct intel_ilk_power_mgmt ips;
1036 enum no_fbc_reason no_fbc_reason;
1038 struct drm_mm_node *compressed_fb;
1039 struct drm_mm_node *compressed_llb;
1041 struct i915_gpu_error gpu_error;
1043 /* list of fbdev register on this device */
1044 struct intel_fbdev *fbdev;
1047 * The console may be contended at resume, but we don't
1048 * want it to block on it.
1050 struct work_struct console_resume_work;
1052 struct drm_property *broadcast_rgb_property;
1053 struct drm_property *force_audio_property;
1055 bool hw_contexts_disabled;
1056 uint32_t hw_context_size;
1060 struct i915_suspend_saved_registers regfile;
1062 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1064 struct i915_dri1_state dri1;
1065 } drm_i915_private_t;
1067 /* Iterate over initialised rings */
1068 #define for_each_ring(ring__, dev_priv__, i__) \
1069 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1070 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1072 enum hdmi_force_audio {
1073 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1074 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1075 HDMI_AUDIO_AUTO, /* trust EDID */
1076 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1079 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1081 struct drm_i915_gem_object_ops {
1082 /* Interface between the GEM object and its backing storage.
1083 * get_pages() is called once prior to the use of the associated set
1084 * of pages before to binding them into the GTT, and put_pages() is
1085 * called after we no longer need them. As we expect there to be
1086 * associated cost with migrating pages between the backing storage
1087 * and making them available for the GPU (e.g. clflush), we may hold
1088 * onto the pages after they are no longer referenced by the GPU
1089 * in case they may be used again shortly (for example migrating the
1090 * pages to a different memory domain within the GTT). put_pages()
1091 * will therefore most likely be called when the object itself is
1092 * being released or under memory pressure (where we attempt to
1093 * reap pages for the shrinker).
1095 int (*get_pages)(struct drm_i915_gem_object *);
1096 void (*put_pages)(struct drm_i915_gem_object *);
1099 struct drm_i915_gem_object {
1100 struct drm_gem_object base;
1102 const struct drm_i915_gem_object_ops *ops;
1104 /** Current space allocated to this object in the GTT, if any. */
1105 struct drm_mm_node *gtt_space;
1106 /** Stolen memory for this object, instead of being backed by shmem. */
1107 struct drm_mm_node *stolen;
1108 struct list_head gtt_list;
1110 /** This object's place on the active/inactive lists */
1111 struct list_head ring_list;
1112 struct list_head mm_list;
1113 /** This object's place in the batchbuffer or on the eviction list */
1114 struct list_head exec_list;
1117 * This is set if the object is on the active lists (has pending
1118 * rendering and so a non-zero seqno), and is not set if it i s on
1119 * inactive (ready to be unbound) list.
1121 unsigned int active:1;
1124 * This is set if the object has been written to since last bound
1127 unsigned int dirty:1;
1130 * Fence register bits (if any) for this object. Will be set
1131 * as needed when mapped into the GTT.
1132 * Protected by dev->struct_mutex.
1134 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1137 * Advice: are the backing pages purgeable?
1139 unsigned int madv:2;
1142 * Current tiling mode for the object.
1144 unsigned int tiling_mode:2;
1146 * Whether the tiling parameters for the currently associated fence
1147 * register have changed. Note that for the purposes of tracking
1148 * tiling changes we also treat the unfenced register, the register
1149 * slot that the object occupies whilst it executes a fenced
1150 * command (such as BLT on gen2/3), as a "fence".
1152 unsigned int fence_dirty:1;
1154 /** How many users have pinned this object in GTT space. The following
1155 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1156 * (via user_pin_count), execbuffer (objects are not allowed multiple
1157 * times for the same batchbuffer), and the framebuffer code. When
1158 * switching/pageflipping, the framebuffer code has at most two buffers
1161 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1162 * bits with absolutely no headroom. So use 4 bits. */
1163 unsigned int pin_count:4;
1164 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1167 * Is the object at the current location in the gtt mappable and
1168 * fenceable? Used to avoid costly recalculations.
1170 unsigned int map_and_fenceable:1;
1173 * Whether the current gtt mapping needs to be mappable (and isn't just
1174 * mappable by accident). Track pin and fault separate for a more
1175 * accurate mappable working set.
1177 unsigned int fault_mappable:1;
1178 unsigned int pin_mappable:1;
1181 * Is the GPU currently using a fence to access this buffer,
1183 unsigned int pending_fenced_gpu_access:1;
1184 unsigned int fenced_gpu_access:1;
1186 unsigned int cache_level:2;
1188 unsigned int has_aliasing_ppgtt_mapping:1;
1189 unsigned int has_global_gtt_mapping:1;
1190 unsigned int has_dma_mapping:1;
1192 struct sg_table *pages;
1193 int pages_pin_count;
1195 /* prime dma-buf support */
1196 void *dma_buf_vmapping;
1200 * Used for performing relocations during execbuffer insertion.
1202 struct hlist_node exec_node;
1203 unsigned long exec_handle;
1204 struct drm_i915_gem_exec_object2 *exec_entry;
1207 * Current offset of the object in GTT space.
1209 * This is the same as gtt_space->start
1211 uint32_t gtt_offset;
1213 struct intel_ring_buffer *ring;
1215 /** Breadcrumb of last rendering to the buffer. */
1216 uint32_t last_read_seqno;
1217 uint32_t last_write_seqno;
1218 /** Breadcrumb of last fenced GPU access to the buffer. */
1219 uint32_t last_fenced_seqno;
1221 /** Current tiling stride for the object, if it's tiled. */
1224 /** Record of address bit 17 of each page at last unbind. */
1225 unsigned long *bit_17;
1227 /** User space pin count and filp owning the pin */
1228 uint32_t user_pin_count;
1229 struct drm_file *pin_filp;
1231 /** for phy allocated objects */
1232 struct drm_i915_gem_phys_object *phys_obj;
1234 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1236 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1239 * Request queue structure.
1241 * The request queue allows us to note sequence numbers that have been emitted
1242 * and may be associated with active buffers to be retired.
1244 * By keeping this list, we can avoid having to do questionable
1245 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1246 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1248 struct drm_i915_gem_request {
1249 /** On Which ring this request was generated */
1250 struct intel_ring_buffer *ring;
1252 /** GEM sequence number associated with this request. */
1255 /** Postion in the ringbuffer of the end of the request */
1258 /** Time at which this request was emitted, in jiffies. */
1259 unsigned long emitted_jiffies;
1261 /** global list entry for this request */
1262 struct list_head list;
1264 struct drm_i915_file_private *file_priv;
1265 /** file_priv list entry for this request */
1266 struct list_head client_list;
1269 struct drm_i915_file_private {
1272 struct list_head request_list;
1274 struct idr context_idr;
1277 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1279 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1280 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1281 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1282 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1283 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1284 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1285 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1286 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1287 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1288 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1289 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1290 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1291 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1292 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1293 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1294 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1295 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1296 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1297 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1298 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1299 (dev)->pci_device == 0x0152 || \
1300 (dev)->pci_device == 0x015a)
1301 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1302 (dev)->pci_device == 0x0106 || \
1303 (dev)->pci_device == 0x010A)
1304 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1305 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1306 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1307 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1308 ((dev)->pci_device & 0xFF00) == 0x0A00)
1311 * The genX designation typically refers to the render engine, so render
1312 * capability related checks should use IS_GEN, while display and other checks
1313 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1316 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1317 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1318 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1319 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1320 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1321 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1323 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1324 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1325 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1326 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1328 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1329 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1331 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1332 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1334 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1335 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1337 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1338 * rows, which changed the alignment requirements and fence programming.
1340 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1342 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1343 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1344 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1345 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1346 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1347 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1348 /* dsparb controlled by hw only */
1349 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1351 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1352 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1353 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1355 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1357 #define HAS_DDI(dev) (IS_HASWELL(dev))
1358 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1360 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1361 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1362 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1363 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1364 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1365 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1367 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1368 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1369 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1370 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1371 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1373 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1375 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1377 #define GT_FREQUENCY_MULTIPLIER 50
1379 #include "i915_trace.h"
1382 * RC6 is a special power stage which allows the GPU to enter an very
1383 * low-voltage mode when idle, using down to 0V while at this stage. This
1384 * stage is entered automatically when the GPU is idle when RC6 support is
1385 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1387 * There are different RC6 modes available in Intel GPU, which differentiate
1388 * among each other with the latency required to enter and leave RC6 and
1389 * voltage consumed by the GPU in different states.
1391 * The combination of the following flags define which states GPU is allowed
1392 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1393 * RC6pp is deepest RC6. Their support by hardware varies according to the
1394 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1395 * which brings the most power savings; deeper states save more power, but
1396 * require higher latency to switch to and wake up.
1398 #define INTEL_RC6_ENABLE (1<<0)
1399 #define INTEL_RC6p_ENABLE (1<<1)
1400 #define INTEL_RC6pp_ENABLE (1<<2)
1402 extern struct drm_ioctl_desc i915_ioctls[];
1403 extern int i915_max_ioctl;
1404 extern unsigned int i915_fbpercrtc __always_unused;
1405 extern int i915_panel_ignore_lid __read_mostly;
1406 extern unsigned int i915_powersave __read_mostly;
1407 extern int i915_semaphores __read_mostly;
1408 extern unsigned int i915_lvds_downclock __read_mostly;
1409 extern int i915_lvds_channel_mode __read_mostly;
1410 extern int i915_panel_use_ssc __read_mostly;
1411 extern int i915_vbt_sdvo_panel_type __read_mostly;
1412 extern int i915_enable_rc6 __read_mostly;
1413 extern int i915_enable_fbc __read_mostly;
1414 extern bool i915_enable_hangcheck __read_mostly;
1415 extern int i915_enable_ppgtt __read_mostly;
1416 extern unsigned int i915_preliminary_hw_support __read_mostly;
1418 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1419 extern int i915_resume(struct drm_device *dev);
1420 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1421 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1424 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1425 extern void i915_kernel_lost_context(struct drm_device * dev);
1426 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1427 extern int i915_driver_unload(struct drm_device *);
1428 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1429 extern void i915_driver_lastclose(struct drm_device * dev);
1430 extern void i915_driver_preclose(struct drm_device *dev,
1431 struct drm_file *file_priv);
1432 extern void i915_driver_postclose(struct drm_device *dev,
1433 struct drm_file *file_priv);
1434 extern int i915_driver_device_is_agp(struct drm_device * dev);
1435 #ifdef CONFIG_COMPAT
1436 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1439 extern int i915_emit_box(struct drm_device *dev,
1440 struct drm_clip_rect *box,
1442 extern int intel_gpu_reset(struct drm_device *dev);
1443 extern int i915_reset(struct drm_device *dev);
1444 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1445 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1446 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1447 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1449 extern void intel_console_resume(struct work_struct *work);
1452 void i915_hangcheck_elapsed(unsigned long data);
1453 void i915_handle_error(struct drm_device *dev, bool wedged);
1455 extern void intel_irq_init(struct drm_device *dev);
1456 extern void intel_hpd_init(struct drm_device *dev);
1457 extern void intel_gt_init(struct drm_device *dev);
1458 extern void intel_gt_reset(struct drm_device *dev);
1460 void i915_error_state_free(struct kref *error_ref);
1463 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1466 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1468 void intel_enable_asle(struct drm_device *dev);
1470 #ifdef CONFIG_DEBUG_FS
1471 extern void i915_destroy_error_state(struct drm_device *dev);
1473 #define i915_destroy_error_state(x)
1478 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1479 struct drm_file *file_priv);
1480 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1481 struct drm_file *file_priv);
1482 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1483 struct drm_file *file_priv);
1484 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1485 struct drm_file *file_priv);
1486 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1487 struct drm_file *file_priv);
1488 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1489 struct drm_file *file_priv);
1490 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1491 struct drm_file *file_priv);
1492 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1493 struct drm_file *file_priv);
1494 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1495 struct drm_file *file_priv);
1496 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1497 struct drm_file *file_priv);
1498 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1499 struct drm_file *file_priv);
1500 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1501 struct drm_file *file_priv);
1502 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1503 struct drm_file *file_priv);
1504 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1505 struct drm_file *file);
1506 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1507 struct drm_file *file);
1508 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1509 struct drm_file *file_priv);
1510 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1511 struct drm_file *file_priv);
1512 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1513 struct drm_file *file_priv);
1514 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1515 struct drm_file *file_priv);
1516 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1517 struct drm_file *file_priv);
1518 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1519 struct drm_file *file_priv);
1520 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1521 struct drm_file *file_priv);
1522 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1523 struct drm_file *file_priv);
1524 void i915_gem_load(struct drm_device *dev);
1525 void *i915_gem_object_alloc(struct drm_device *dev);
1526 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1527 int i915_gem_init_object(struct drm_gem_object *obj);
1528 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1529 const struct drm_i915_gem_object_ops *ops);
1530 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1532 void i915_gem_free_object(struct drm_gem_object *obj);
1534 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1536 bool map_and_fenceable,
1538 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1539 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1540 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1541 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1542 void i915_gem_lastclose(struct drm_device *dev);
1544 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1545 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1547 struct sg_page_iter sg_iter;
1549 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1550 return sg_page_iter_page(&sg_iter);
1554 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1556 BUG_ON(obj->pages == NULL);
1557 obj->pages_pin_count++;
1559 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1561 BUG_ON(obj->pages_pin_count == 0);
1562 obj->pages_pin_count--;
1565 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1566 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1567 struct intel_ring_buffer *to);
1568 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1569 struct intel_ring_buffer *ring);
1571 int i915_gem_dumb_create(struct drm_file *file_priv,
1572 struct drm_device *dev,
1573 struct drm_mode_create_dumb *args);
1574 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1575 uint32_t handle, uint64_t *offset);
1576 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1579 * Returns true if seq1 is later than seq2.
1582 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1584 return (int32_t)(seq1 - seq2) >= 0;
1587 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1588 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1589 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1590 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1593 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1595 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1596 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1597 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1604 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1606 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1607 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1608 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1612 void i915_gem_retire_requests(struct drm_device *dev);
1613 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1614 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1615 bool interruptible);
1616 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1618 return unlikely(atomic_read(&error->reset_counter)
1619 & I915_RESET_IN_PROGRESS_FLAG);
1622 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1624 return atomic_read(&error->reset_counter) == I915_WEDGED;
1627 void i915_gem_reset(struct drm_device *dev);
1628 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1629 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1630 uint32_t read_domains,
1631 uint32_t write_domain);
1632 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1633 int __must_check i915_gem_init(struct drm_device *dev);
1634 int __must_check i915_gem_init_hw(struct drm_device *dev);
1635 void i915_gem_l3_remap(struct drm_device *dev);
1636 void i915_gem_init_swizzling(struct drm_device *dev);
1637 void i915_gem_init_ppgtt(struct drm_device *dev);
1638 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1639 int __must_check i915_gpu_idle(struct drm_device *dev);
1640 int __must_check i915_gem_idle(struct drm_device *dev);
1641 int i915_add_request(struct intel_ring_buffer *ring,
1642 struct drm_file *file,
1644 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1646 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1648 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1651 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1653 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1655 struct intel_ring_buffer *pipelined);
1656 int i915_gem_attach_phys_object(struct drm_device *dev,
1657 struct drm_i915_gem_object *obj,
1660 void i915_gem_detach_phys_object(struct drm_device *dev,
1661 struct drm_i915_gem_object *obj);
1662 void i915_gem_free_all_phys_object(struct drm_device *dev);
1663 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1666 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1668 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1669 int tiling_mode, bool fenced);
1671 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1672 enum i915_cache_level cache_level);
1674 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1675 struct dma_buf *dma_buf);
1677 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1678 struct drm_gem_object *gem_obj, int flags);
1680 /* i915_gem_context.c */
1681 void i915_gem_context_init(struct drm_device *dev);
1682 void i915_gem_context_fini(struct drm_device *dev);
1683 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1684 int i915_switch_context(struct intel_ring_buffer *ring,
1685 struct drm_file *file, int to_id);
1686 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1687 struct drm_file *file);
1688 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1689 struct drm_file *file);
1691 /* i915_gem_gtt.c */
1692 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1693 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1694 struct drm_i915_gem_object *obj,
1695 enum i915_cache_level cache_level);
1696 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1697 struct drm_i915_gem_object *obj);
1699 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1700 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1701 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1702 enum i915_cache_level cache_level);
1703 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1704 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1705 void i915_gem_init_global_gtt(struct drm_device *dev);
1706 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1707 unsigned long mappable_end, unsigned long end);
1708 int i915_gem_gtt_init(struct drm_device *dev);
1709 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1711 if (INTEL_INFO(dev)->gen < 6)
1712 intel_gtt_chipset_flush();
1716 /* i915_gem_evict.c */
1717 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1719 unsigned cache_level,
1722 int i915_gem_evict_everything(struct drm_device *dev);
1724 /* i915_gem_stolen.c */
1725 int i915_gem_init_stolen(struct drm_device *dev);
1726 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1727 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1728 void i915_gem_cleanup_stolen(struct drm_device *dev);
1729 struct drm_i915_gem_object *
1730 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1731 struct drm_i915_gem_object *
1732 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1736 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1738 /* i915_gem_tiling.c */
1739 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1741 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1743 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1744 obj->tiling_mode != I915_TILING_NONE;
1747 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1748 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1749 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1751 /* i915_gem_debug.c */
1752 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1753 const char *where, uint32_t mark);
1755 int i915_verify_lists(struct drm_device *dev);
1757 #define i915_verify_lists(dev) 0
1759 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1761 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1762 const char *where, uint32_t mark);
1764 /* i915_debugfs.c */
1765 int i915_debugfs_init(struct drm_minor *minor);
1766 void i915_debugfs_cleanup(struct drm_minor *minor);
1768 /* i915_suspend.c */
1769 extern int i915_save_state(struct drm_device *dev);
1770 extern int i915_restore_state(struct drm_device *dev);
1773 void i915_save_display_reg(struct drm_device *dev);
1774 void i915_restore_display_reg(struct drm_device *dev);
1777 void i915_setup_sysfs(struct drm_device *dev_priv);
1778 void i915_teardown_sysfs(struct drm_device *dev_priv);
1781 extern int intel_setup_gmbus(struct drm_device *dev);
1782 extern void intel_teardown_gmbus(struct drm_device *dev);
1783 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1785 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1788 extern struct i2c_adapter *intel_gmbus_get_adapter(
1789 struct drm_i915_private *dev_priv, unsigned port);
1790 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1791 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1792 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1794 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1796 extern void intel_i2c_reset(struct drm_device *dev);
1798 /* intel_opregion.c */
1799 extern int intel_opregion_setup(struct drm_device *dev);
1801 extern void intel_opregion_init(struct drm_device *dev);
1802 extern void intel_opregion_fini(struct drm_device *dev);
1803 extern void intel_opregion_asle_intr(struct drm_device *dev);
1804 extern void intel_opregion_gse_intr(struct drm_device *dev);
1805 extern void intel_opregion_enable_asle(struct drm_device *dev);
1807 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1808 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1809 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1810 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1811 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1816 extern void intel_register_dsm_handler(void);
1817 extern void intel_unregister_dsm_handler(void);
1819 static inline void intel_register_dsm_handler(void) { return; }
1820 static inline void intel_unregister_dsm_handler(void) { return; }
1821 #endif /* CONFIG_ACPI */
1824 extern void intel_modeset_init_hw(struct drm_device *dev);
1825 extern void intel_modeset_init(struct drm_device *dev);
1826 extern void intel_modeset_gem_init(struct drm_device *dev);
1827 extern void intel_modeset_cleanup(struct drm_device *dev);
1828 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1829 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1830 bool force_restore);
1831 extern void i915_redisable_vga(struct drm_device *dev);
1832 extern bool intel_fbc_enabled(struct drm_device *dev);
1833 extern void intel_disable_fbc(struct drm_device *dev);
1834 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1835 extern void intel_init_pch_refclk(struct drm_device *dev);
1836 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1837 extern void intel_detect_pch(struct drm_device *dev);
1838 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1839 extern int intel_enable_rc6(const struct drm_device *dev);
1841 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1842 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *file);
1846 #ifdef CONFIG_DEBUG_FS
1847 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1848 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1850 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1851 extern void intel_display_print_error_state(struct seq_file *m,
1852 struct drm_device *dev,
1853 struct intel_display_error_state *error);
1856 /* On SNB platform, before reading ring registers forcewake bit
1857 * must be set to prevent GT core from power down and stale values being
1860 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1861 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1862 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1864 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1865 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1867 #define __i915_read(x, y) \
1868 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1876 #define __i915_write(x, y) \
1877 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1885 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1886 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1888 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1889 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1890 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1891 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1893 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1894 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1895 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1896 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1898 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1899 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1901 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1902 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1904 /* "Broadcast RGB" property */
1905 #define INTEL_BROADCAST_RGB_AUTO 0
1906 #define INTEL_BROADCAST_RGB_FULL 1
1907 #define INTEL_BROADCAST_RGB_LIMITED 2
1909 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1911 if (HAS_PCH_SPLIT(dev))
1912 return CPU_VGACNTRL;
1913 else if (IS_VALLEYVIEW(dev))
1914 return VLV_VGACNTRL;
1919 static inline void __user *to_user_ptr(u64 address)
1921 return (void __user *)(uintptr_t)address;