1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150423"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_crtc(dev, intel_crtc) \
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
244 #define for_each_intel_encoder(dev, intel_encoder) \
245 list_for_each_entry(intel_encoder, \
246 &(dev)->mode_config.encoder_list, \
249 #define for_each_intel_connector(dev, intel_connector) \
250 list_for_each_entry(intel_connector, \
251 &dev->mode_config.connector_list, \
254 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
255 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
256 if ((intel_encoder)->base.crtc == (__crtc))
258 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
259 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
260 if ((intel_connector)->base.encoder == (__encoder))
262 #define for_each_power_domain(domain, mask) \
263 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
264 if ((1 << (domain)) & (mask))
266 struct drm_i915_private;
267 struct i915_mm_struct;
268 struct i915_mmu_object;
271 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
272 /* real shared dpll ids must be >= 0 */
273 DPLL_ID_PCH_PLL_A = 0,
274 DPLL_ID_PCH_PLL_B = 1,
279 DPLL_ID_SKL_DPLL1 = 0,
280 DPLL_ID_SKL_DPLL2 = 1,
281 DPLL_ID_SKL_DPLL3 = 2,
283 #define I915_NUM_PLLS 3
285 struct intel_dpll_hw_state {
297 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
298 * lower part of ctrl1 and they get shifted into position when writing
299 * the register. This allows us to easily compare the state to share
303 /* HDMI only, 0 when used for DP */
304 uint32_t cfgcr1, cfgcr2;
307 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
310 struct intel_shared_dpll_config {
311 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
312 struct intel_dpll_hw_state hw_state;
315 struct intel_shared_dpll {
316 struct intel_shared_dpll_config config;
317 struct intel_shared_dpll_config *new_config;
319 int active; /* count of number of active CRTCs (i.e. DPMS on) */
320 bool on; /* is the PLL actually active? Disabled during modeset */
322 /* should match the index in the dev_priv->shared_dplls array */
323 enum intel_dpll_id id;
324 /* The mode_set hook is optional and should be used together with the
325 * intel_prepare_shared_dpll function. */
326 void (*mode_set)(struct drm_i915_private *dev_priv,
327 struct intel_shared_dpll *pll);
328 void (*enable)(struct drm_i915_private *dev_priv,
329 struct intel_shared_dpll *pll);
330 void (*disable)(struct drm_i915_private *dev_priv,
331 struct intel_shared_dpll *pll);
332 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
333 struct intel_shared_dpll *pll,
334 struct intel_dpll_hw_state *hw_state);
342 /* Used by dp and fdi links */
343 struct intel_link_m_n {
351 void intel_link_compute_m_n(int bpp, int nlanes,
352 int pixel_clock, int link_clock,
353 struct intel_link_m_n *m_n);
355 /* Interface history:
358 * 1.2: Add Power Management
359 * 1.3: Add vblank support
360 * 1.4: Fix cmdbuffer path, add heap destroy
361 * 1.5: Add vblank pipe configuration
362 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
363 * - Support vertical blank on secondary display pipe
365 #define DRIVER_MAJOR 1
366 #define DRIVER_MINOR 6
367 #define DRIVER_PATCHLEVEL 0
369 #define WATCH_LISTS 0
371 struct opregion_header;
372 struct opregion_acpi;
373 struct opregion_swsci;
374 struct opregion_asle;
376 struct intel_opregion {
377 struct opregion_header __iomem *header;
378 struct opregion_acpi __iomem *acpi;
379 struct opregion_swsci __iomem *swsci;
380 u32 swsci_gbda_sub_functions;
381 u32 swsci_sbcb_sub_functions;
382 struct opregion_asle __iomem *asle;
384 u32 __iomem *lid_state;
385 struct work_struct asle_work;
387 #define OPREGION_SIZE (8*1024)
389 struct intel_overlay;
390 struct intel_overlay_error_state;
392 #define I915_FENCE_REG_NONE -1
393 #define I915_MAX_NUM_FENCES 32
394 /* 32 fences + sign bit for FENCE_REG_NONE */
395 #define I915_MAX_NUM_FENCE_BITS 6
397 struct drm_i915_fence_reg {
398 struct list_head lru_list;
399 struct drm_i915_gem_object *obj;
403 struct sdvo_device_mapping {
412 struct intel_display_error_state;
414 struct drm_i915_error_state {
422 /* Generic register state */
430 u32 error; /* gen6+ */
431 u32 err_int; /* gen7 */
432 u32 fault_data0; /* gen8, gen9 */
433 u32 fault_data1; /* gen8, gen9 */
439 u32 extra_instdone[I915_NUM_INSTDONE_REG];
440 u64 fence[I915_MAX_NUM_FENCES];
441 struct intel_overlay_error_state *overlay;
442 struct intel_display_error_state *display;
443 struct drm_i915_error_object *semaphore_obj;
445 struct drm_i915_error_ring {
447 /* Software tracked state */
450 enum intel_ring_hangcheck_action hangcheck_action;
453 /* our own tracking of ring head and tail */
457 u32 semaphore_seqno[I915_NUM_RINGS - 1];
476 u32 rc_psmi; /* sleep state */
477 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
479 struct drm_i915_error_object {
483 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
485 struct drm_i915_error_request {
500 char comm[TASK_COMM_LEN];
501 } ring[I915_NUM_RINGS];
503 struct drm_i915_error_buffer {
510 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
518 } **active_bo, **pinned_bo;
520 u32 *active_bo_count, *pinned_bo_count;
524 struct intel_connector;
525 struct intel_encoder;
526 struct intel_crtc_state;
527 struct intel_initial_plane_config;
532 struct drm_i915_display_funcs {
533 bool (*fbc_enabled)(struct drm_device *dev);
534 void (*enable_fbc)(struct drm_crtc *crtc);
535 void (*disable_fbc)(struct drm_device *dev);
536 int (*get_display_clock_speed)(struct drm_device *dev);
537 int (*get_fifo_size)(struct drm_device *dev, int plane);
539 * find_dpll() - Find the best values for the PLL
540 * @limit: limits for the PLL
541 * @crtc: current CRTC
542 * @target: target frequency in kHz
543 * @refclk: reference clock frequency in kHz
544 * @match_clock: if provided, @best_clock P divider must
545 * match the P divider from @match_clock
546 * used for LVDS downclocking
547 * @best_clock: best PLL values found
549 * Returns true on success, false on failure.
551 bool (*find_dpll)(const struct intel_limit *limit,
552 struct intel_crtc_state *crtc_state,
553 int target, int refclk,
554 struct dpll *match_clock,
555 struct dpll *best_clock);
556 void (*update_wm)(struct drm_crtc *crtc);
557 void (*update_sprite_wm)(struct drm_plane *plane,
558 struct drm_crtc *crtc,
559 uint32_t sprite_width, uint32_t sprite_height,
560 int pixel_size, bool enable, bool scaled);
561 void (*modeset_global_resources)(struct drm_atomic_state *state);
562 /* Returns the active state of the crtc, and if the crtc is active,
563 * fills out the pipe-config with the hw state. */
564 bool (*get_pipe_config)(struct intel_crtc *,
565 struct intel_crtc_state *);
566 void (*get_initial_plane_config)(struct intel_crtc *,
567 struct intel_initial_plane_config *);
568 int (*crtc_compute_clock)(struct intel_crtc *crtc,
569 struct intel_crtc_state *crtc_state);
570 void (*crtc_enable)(struct drm_crtc *crtc);
571 void (*crtc_disable)(struct drm_crtc *crtc);
572 void (*off)(struct drm_crtc *crtc);
573 void (*audio_codec_enable)(struct drm_connector *connector,
574 struct intel_encoder *encoder,
575 struct drm_display_mode *mode);
576 void (*audio_codec_disable)(struct intel_encoder *encoder);
577 void (*fdi_link_train)(struct drm_crtc *crtc);
578 void (*init_clock_gating)(struct drm_device *dev);
579 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
580 struct drm_framebuffer *fb,
581 struct drm_i915_gem_object *obj,
582 struct intel_engine_cs *ring,
584 void (*update_primary_plane)(struct drm_crtc *crtc,
585 struct drm_framebuffer *fb,
587 void (*hpd_irq_setup)(struct drm_device *dev);
588 /* clock updates for mode set */
590 /* render clock increase/decrease */
591 /* display clock increase/decrease */
592 /* pll clock increase/decrease */
594 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
595 uint32_t (*get_backlight)(struct intel_connector *connector);
596 void (*set_backlight)(struct intel_connector *connector,
598 void (*disable_backlight)(struct intel_connector *connector);
599 void (*enable_backlight)(struct intel_connector *connector);
602 enum forcewake_domain_id {
603 FW_DOMAIN_ID_RENDER = 0,
604 FW_DOMAIN_ID_BLITTER,
610 enum forcewake_domains {
611 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
612 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
613 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
614 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
619 struct intel_uncore_funcs {
620 void (*force_wake_get)(struct drm_i915_private *dev_priv,
621 enum forcewake_domains domains);
622 void (*force_wake_put)(struct drm_i915_private *dev_priv,
623 enum forcewake_domains domains);
625 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
626 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
627 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
628 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
630 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
631 uint8_t val, bool trace);
632 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
633 uint16_t val, bool trace);
634 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
635 uint32_t val, bool trace);
636 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
637 uint64_t val, bool trace);
640 struct intel_uncore {
641 spinlock_t lock; /** lock is also taken in irq contexts. */
643 struct intel_uncore_funcs funcs;
646 enum forcewake_domains fw_domains;
648 struct intel_uncore_forcewake_domain {
649 struct drm_i915_private *i915;
650 enum forcewake_domain_id id;
652 struct timer_list timer;
659 } fw_domain[FW_DOMAIN_ID_COUNT];
662 /* Iterate over initialised fw domains */
663 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
664 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
665 (i__) < FW_DOMAIN_ID_COUNT; \
666 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
667 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
669 #define for_each_fw_domain(domain__, dev_priv__, i__) \
670 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
673 FW_UNINITIALIZED = 0,
681 uint32_t dmc_fw_size;
683 uint32_t mmioaddr[8];
684 uint32_t mmiodata[8];
685 enum csr_state state;
688 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
689 func(is_mobile) sep \
692 func(is_i945gm) sep \
694 func(need_gfx_hws) sep \
696 func(is_pineview) sep \
697 func(is_broadwater) sep \
698 func(is_crestline) sep \
699 func(is_ivybridge) sep \
700 func(is_valleyview) sep \
701 func(is_haswell) sep \
702 func(is_skylake) sep \
703 func(is_preliminary) sep \
705 func(has_pipe_cxsr) sep \
706 func(has_hotplug) sep \
707 func(cursor_needs_physical) sep \
708 func(has_overlay) sep \
709 func(overlay_needs_physical) sep \
710 func(supports_tv) sep \
715 #define DEFINE_FLAG(name) u8 name:1
716 #define SEP_SEMICOLON ;
718 struct intel_device_info {
719 u32 display_mmio_offset;
722 u8 num_sprites[I915_MAX_PIPES];
724 u8 ring_mask; /* Rings supported by the HW */
725 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
726 /* Register offsets for the various display pipes and transcoders */
727 int pipe_offsets[I915_MAX_TRANSCODERS];
728 int trans_offsets[I915_MAX_TRANSCODERS];
729 int palette_offsets[I915_MAX_PIPES];
730 int cursor_offsets[I915_MAX_PIPES];
732 /* Slice/subslice/EU info */
735 u8 subslice_per_slice;
738 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
741 u8 has_subslice_pg:1;
748 enum i915_cache_level {
750 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
751 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
752 caches, eg sampler/render caches, and the
753 large Last-Level-Cache. LLC is coherent with
754 the CPU, but L3 is only visible to the GPU. */
755 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
758 struct i915_ctx_hang_stats {
759 /* This context had batch pending when hang was declared */
760 unsigned batch_pending;
762 /* This context had batch active when hang was declared */
763 unsigned batch_active;
765 /* Time when this context was last blamed for a GPU reset */
766 unsigned long guilty_ts;
768 /* If the contexts causes a second GPU hang within this time,
769 * it is permanently banned from submitting any more work.
771 unsigned long ban_period_seconds;
773 /* This context is banned to submit more work */
777 /* This must match up with the value previously used for execbuf2.rsvd1. */
778 #define DEFAULT_CONTEXT_HANDLE 0
780 * struct intel_context - as the name implies, represents a context.
781 * @ref: reference count.
782 * @user_handle: userspace tracking identity for this context.
783 * @remap_slice: l3 row remapping information.
784 * @file_priv: filp associated with this context (NULL for global default
786 * @hang_stats: information about the role of this context in possible GPU
788 * @ppgtt: virtual memory space used by this context.
789 * @legacy_hw_ctx: render context backing object and whether it is correctly
790 * initialized (legacy ring submission mechanism only).
791 * @link: link in the global list of contexts.
793 * Contexts are memory images used by the hardware to store copies of their
796 struct intel_context {
800 struct drm_i915_file_private *file_priv;
801 struct i915_ctx_hang_stats hang_stats;
802 struct i915_hw_ppgtt *ppgtt;
804 /* Legacy ring buffer submission */
806 struct drm_i915_gem_object *rcs_state;
811 bool rcs_initialized;
813 struct drm_i915_gem_object *state;
814 struct intel_ringbuffer *ringbuf;
816 } engine[I915_NUM_RINGS];
818 struct list_head link;
829 unsigned long uncompressed_size;
832 unsigned int possible_framebuffer_bits;
833 unsigned int busy_bits;
834 struct intel_crtc *crtc;
837 struct drm_mm_node compressed_fb;
838 struct drm_mm_node *compressed_llb;
842 /* Tracks whether the HW is actually enabled, not whether the feature is
846 struct intel_fbc_work {
847 struct delayed_work work;
848 struct drm_crtc *crtc;
849 struct drm_framebuffer *fb;
853 FBC_OK, /* FBC is enabled */
854 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
855 FBC_NO_OUTPUT, /* no outputs enabled to compress */
856 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
857 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
858 FBC_MODE_TOO_LARGE, /* mode too large for compression */
859 FBC_BAD_PLANE, /* fbc not supported on plane */
860 FBC_NOT_TILED, /* buffer not tiled */
861 FBC_MULTIPLE_PIPES, /* more than one pipe active */
863 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
868 * HIGH_RR is the highest eDP panel refresh rate read from EDID
869 * LOW_RR is the lowest eDP panel refresh rate found from EDID
870 * parsing for same resolution.
872 enum drrs_refresh_rate_type {
875 DRRS_MAX_RR, /* RR count */
878 enum drrs_support_type {
879 DRRS_NOT_SUPPORTED = 0,
880 STATIC_DRRS_SUPPORT = 1,
881 SEAMLESS_DRRS_SUPPORT = 2
887 struct delayed_work work;
889 unsigned busy_frontbuffer_bits;
890 enum drrs_refresh_rate_type refresh_rate_type;
891 enum drrs_support_type type;
898 struct intel_dp *enabled;
900 struct delayed_work work;
901 unsigned busy_frontbuffer_bits;
907 PCH_NONE = 0, /* No PCH present */
908 PCH_IBX, /* Ibexpeak PCH */
909 PCH_CPT, /* Cougarpoint PCH */
910 PCH_LPT, /* Lynxpoint PCH */
911 PCH_SPT, /* Sunrisepoint PCH */
915 enum intel_sbi_destination {
920 #define QUIRK_PIPEA_FORCE (1<<0)
921 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
922 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
923 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
924 #define QUIRK_PIPEB_FORCE (1<<4)
925 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
928 struct intel_fbc_work;
931 struct i2c_adapter adapter;
935 struct i2c_algo_bit_data bit_algo;
936 struct drm_i915_private *dev_priv;
939 struct i915_suspend_saved_registers {
942 u32 savePP_ON_DELAYS;
943 u32 savePP_OFF_DELAYS;
949 u32 saveCACHE_MODE_0;
950 u32 saveMI_ARB_STATE;
954 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
955 u32 savePCH_PORT_HOTPLUG;
959 struct vlv_s0ix_state {
966 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
967 u32 media_max_req_count;
968 u32 gfx_max_req_count;
1000 /* Display 1 CZ domain */
1005 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1007 /* GT SA CZ domain */
1014 /* Display 2 CZ domain */
1018 u32 clock_gate_dis2;
1021 struct intel_rps_ei {
1027 struct intel_gen6_power_mgmt {
1029 * work, interrupts_enabled and pm_iir are protected by
1030 * dev_priv->irq_lock
1032 struct work_struct work;
1033 bool interrupts_enabled;
1036 /* Frequencies are stored in potentially platform dependent multiples.
1037 * In other words, *_freq needs to be multiplied by X to be interesting.
1038 * Soft limits are those which are used for the dynamic reclocking done
1039 * by the driver (raise frequencies under heavy loads, and lower for
1040 * lighter loads). Hard limits are those imposed by the hardware.
1042 * A distinction is made for overclocking, which is never enabled by
1043 * default, and is considered to be above the hard limit if it's
1046 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1047 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1048 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1049 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1050 u8 min_freq; /* AKA RPn. Minimum frequency */
1051 u8 idle_freq; /* Frequency to request when we are idle */
1052 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1053 u8 rp1_freq; /* "less than" RP0 power/freqency */
1054 u8 rp0_freq; /* Non-overclocked max frequency. */
1057 u8 up_threshold; /* Current %busy required to uplock */
1058 u8 down_threshold; /* Current %busy required to downclock */
1061 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1064 struct delayed_work delayed_resume_work;
1065 struct list_head clients;
1068 /* manual wa residency calculations */
1069 struct intel_rps_ei up_ei, down_ei;
1072 * Protects RPS/RC6 register access and PCU communication.
1073 * Must be taken after struct_mutex if nested.
1075 struct mutex hw_lock;
1078 /* defined intel_pm.c */
1079 extern spinlock_t mchdev_lock;
1081 struct intel_ilk_power_mgmt {
1089 unsigned long last_time1;
1090 unsigned long chipset_power;
1093 unsigned long gfx_power;
1100 struct drm_i915_private;
1101 struct i915_power_well;
1103 struct i915_power_well_ops {
1105 * Synchronize the well's hw state to match the current sw state, for
1106 * example enable/disable it based on the current refcount. Called
1107 * during driver init and resume time, possibly after first calling
1108 * the enable/disable handlers.
1110 void (*sync_hw)(struct drm_i915_private *dev_priv,
1111 struct i915_power_well *power_well);
1113 * Enable the well and resources that depend on it (for example
1114 * interrupts located on the well). Called after the 0->1 refcount
1117 void (*enable)(struct drm_i915_private *dev_priv,
1118 struct i915_power_well *power_well);
1120 * Disable the well and resources that depend on it. Called after
1121 * the 1->0 refcount transition.
1123 void (*disable)(struct drm_i915_private *dev_priv,
1124 struct i915_power_well *power_well);
1125 /* Returns the hw enabled state. */
1126 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1127 struct i915_power_well *power_well);
1130 /* Power well structure for haswell */
1131 struct i915_power_well {
1134 /* power well enable/disable usage count */
1136 /* cached hw enabled state */
1138 unsigned long domains;
1140 const struct i915_power_well_ops *ops;
1143 struct i915_power_domains {
1145 * Power wells needed for initialization at driver init and suspend
1146 * time are on. They are kept on until after the first modeset.
1150 int power_well_count;
1153 int domain_use_count[POWER_DOMAIN_NUM];
1154 struct i915_power_well *power_wells;
1157 #define MAX_L3_SLICES 2
1158 struct intel_l3_parity {
1159 u32 *remap_info[MAX_L3_SLICES];
1160 struct work_struct error_work;
1164 struct i915_gem_mm {
1165 /** Memory allocator for GTT stolen memory */
1166 struct drm_mm stolen;
1167 /** List of all objects in gtt_space. Used to restore gtt
1168 * mappings on resume */
1169 struct list_head bound_list;
1171 * List of objects which are not bound to the GTT (thus
1172 * are idle and not used by the GPU) but still have
1173 * (presumably uncached) pages still attached.
1175 struct list_head unbound_list;
1177 /** Usable portion of the GTT for GEM */
1178 unsigned long stolen_base; /* limited to low memory (32-bit) */
1180 /** PPGTT used for aliasing the PPGTT with the GTT */
1181 struct i915_hw_ppgtt *aliasing_ppgtt;
1183 struct notifier_block oom_notifier;
1184 struct shrinker shrinker;
1185 bool shrinker_no_lock_stealing;
1187 /** LRU list of objects with fence regs on them. */
1188 struct list_head fence_list;
1191 * We leave the user IRQ off as much as possible,
1192 * but this means that requests will finish and never
1193 * be retired once the system goes idle. Set a timer to
1194 * fire periodically while the ring is running. When it
1195 * fires, go retire requests.
1197 struct delayed_work retire_work;
1200 * When we detect an idle GPU, we want to turn on
1201 * powersaving features. So once we see that there
1202 * are no more requests outstanding and no more
1203 * arrive within a small period of time, we fire
1204 * off the idle_work.
1206 struct delayed_work idle_work;
1209 * Are we in a non-interruptible section of code like
1215 * Is the GPU currently considered idle, or busy executing userspace
1216 * requests? Whilst idle, we attempt to power down the hardware and
1217 * display clocks. In order to reduce the effect on performance, there
1218 * is a slight delay before we do so.
1222 /* the indicator for dispatch video commands on two BSD rings */
1223 int bsd_ring_dispatch_index;
1225 /** Bit 6 swizzling required for X tiling */
1226 uint32_t bit_6_swizzle_x;
1227 /** Bit 6 swizzling required for Y tiling */
1228 uint32_t bit_6_swizzle_y;
1230 /* accounting, useful for userland debugging */
1231 spinlock_t object_stat_lock;
1232 size_t object_memory;
1236 struct drm_i915_error_state_buf {
1237 struct drm_i915_private *i915;
1246 struct i915_error_state_file_priv {
1247 struct drm_device *dev;
1248 struct drm_i915_error_state *error;
1251 struct i915_gpu_error {
1252 /* For hangcheck timer */
1253 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1254 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1255 /* Hang gpu twice in this window and your context gets banned */
1256 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1258 struct workqueue_struct *hangcheck_wq;
1259 struct delayed_work hangcheck_work;
1261 /* For reset and error_state handling. */
1263 /* Protected by the above dev->gpu_error.lock. */
1264 struct drm_i915_error_state *first_error;
1266 unsigned long missed_irq_rings;
1269 * State variable controlling the reset flow and count
1271 * This is a counter which gets incremented when reset is triggered,
1272 * and again when reset has been handled. So odd values (lowest bit set)
1273 * means that reset is in progress and even values that
1274 * (reset_counter >> 1):th reset was successfully completed.
1276 * If reset is not completed succesfully, the I915_WEDGE bit is
1277 * set meaning that hardware is terminally sour and there is no
1278 * recovery. All waiters on the reset_queue will be woken when
1281 * This counter is used by the wait_seqno code to notice that reset
1282 * event happened and it needs to restart the entire ioctl (since most
1283 * likely the seqno it waited for won't ever signal anytime soon).
1285 * This is important for lock-free wait paths, where no contended lock
1286 * naturally enforces the correct ordering between the bail-out of the
1287 * waiter and the gpu reset work code.
1289 atomic_t reset_counter;
1291 #define I915_RESET_IN_PROGRESS_FLAG 1
1292 #define I915_WEDGED (1 << 31)
1295 * Waitqueue to signal when the reset has completed. Used by clients
1296 * that wait for dev_priv->mm.wedged to settle.
1298 wait_queue_head_t reset_queue;
1300 /* Userspace knobs for gpu hang simulation;
1301 * combines both a ring mask, and extra flags
1304 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1305 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1307 /* For missed irq/seqno simulation. */
1308 unsigned int test_irq_rings;
1310 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1311 bool reload_in_reset;
1314 enum modeset_restore {
1315 MODESET_ON_LID_OPEN,
1320 struct ddi_vbt_port_info {
1322 * This is an index in the HDMI/DVI DDI buffer translation table.
1323 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1324 * populate this field.
1326 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1327 uint8_t hdmi_level_shift;
1329 uint8_t supports_dvi:1;
1330 uint8_t supports_hdmi:1;
1331 uint8_t supports_dp:1;
1334 enum psr_lines_to_wait {
1335 PSR_0_LINES_TO_WAIT = 0,
1337 PSR_4_LINES_TO_WAIT,
1341 struct intel_vbt_data {
1342 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1343 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1346 unsigned int int_tv_support:1;
1347 unsigned int lvds_dither:1;
1348 unsigned int lvds_vbt:1;
1349 unsigned int int_crt_support:1;
1350 unsigned int lvds_use_ssc:1;
1351 unsigned int display_clock_mode:1;
1352 unsigned int fdi_rx_polarity_inverted:1;
1353 unsigned int has_mipi:1;
1355 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1357 enum drrs_support_type drrs_type;
1362 int edp_preemphasis;
1364 bool edp_initialized;
1367 struct edp_power_seq edp_pps;
1371 bool require_aux_wakeup;
1373 enum psr_lines_to_wait lines_to_wait;
1374 int tp1_wakeup_time;
1375 int tp2_tp3_wakeup_time;
1381 bool active_low_pwm;
1382 u8 min_brightness; /* min_brightness/255 of max */
1389 struct mipi_config *config;
1390 struct mipi_pps_data *pps;
1394 u8 *sequence[MIPI_SEQ_MAX];
1400 union child_device_config *child_dev;
1402 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1405 enum intel_ddb_partitioning {
1407 INTEL_DDB_PART_5_6, /* IVB+ */
1410 struct intel_wm_level {
1418 struct ilk_wm_values {
1419 uint32_t wm_pipe[3];
1421 uint32_t wm_lp_spr[3];
1422 uint32_t wm_linetime[3];
1424 enum intel_ddb_partitioning partitioning;
1427 struct vlv_wm_values {
1446 struct skl_ddb_entry {
1447 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1450 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1452 return entry->end - entry->start;
1455 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1456 const struct skl_ddb_entry *e2)
1458 if (e1->start == e2->start && e1->end == e2->end)
1464 struct skl_ddb_allocation {
1465 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1466 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1467 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1470 struct skl_wm_values {
1471 bool dirty[I915_MAX_PIPES];
1472 struct skl_ddb_allocation ddb;
1473 uint32_t wm_linetime[I915_MAX_PIPES];
1474 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1475 uint32_t cursor[I915_MAX_PIPES][8];
1476 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1477 uint32_t cursor_trans[I915_MAX_PIPES];
1480 struct skl_wm_level {
1481 bool plane_en[I915_MAX_PLANES];
1483 uint16_t plane_res_b[I915_MAX_PLANES];
1484 uint8_t plane_res_l[I915_MAX_PLANES];
1485 uint16_t cursor_res_b;
1486 uint8_t cursor_res_l;
1490 * This struct helps tracking the state needed for runtime PM, which puts the
1491 * device in PCI D3 state. Notice that when this happens, nothing on the
1492 * graphics device works, even register access, so we don't get interrupts nor
1495 * Every piece of our code that needs to actually touch the hardware needs to
1496 * either call intel_runtime_pm_get or call intel_display_power_get with the
1497 * appropriate power domain.
1499 * Our driver uses the autosuspend delay feature, which means we'll only really
1500 * suspend if we stay with zero refcount for a certain amount of time. The
1501 * default value is currently very conservative (see intel_runtime_pm_enable), but
1502 * it can be changed with the standard runtime PM files from sysfs.
1504 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1505 * goes back to false exactly before we reenable the IRQs. We use this variable
1506 * to check if someone is trying to enable/disable IRQs while they're supposed
1507 * to be disabled. This shouldn't happen and we'll print some error messages in
1510 * For more, read the Documentation/power/runtime_pm.txt.
1512 struct i915_runtime_pm {
1517 enum intel_pipe_crc_source {
1518 INTEL_PIPE_CRC_SOURCE_NONE,
1519 INTEL_PIPE_CRC_SOURCE_PLANE1,
1520 INTEL_PIPE_CRC_SOURCE_PLANE2,
1521 INTEL_PIPE_CRC_SOURCE_PF,
1522 INTEL_PIPE_CRC_SOURCE_PIPE,
1523 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1524 INTEL_PIPE_CRC_SOURCE_TV,
1525 INTEL_PIPE_CRC_SOURCE_DP_B,
1526 INTEL_PIPE_CRC_SOURCE_DP_C,
1527 INTEL_PIPE_CRC_SOURCE_DP_D,
1528 INTEL_PIPE_CRC_SOURCE_AUTO,
1529 INTEL_PIPE_CRC_SOURCE_MAX,
1532 struct intel_pipe_crc_entry {
1537 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1538 struct intel_pipe_crc {
1540 bool opened; /* exclusive access to the result file */
1541 struct intel_pipe_crc_entry *entries;
1542 enum intel_pipe_crc_source source;
1544 wait_queue_head_t wq;
1547 struct i915_frontbuffer_tracking {
1551 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1558 struct i915_wa_reg {
1561 /* bitmask representing WA bits */
1565 #define I915_MAX_WA_REGS 16
1567 struct i915_workarounds {
1568 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1572 struct i915_virtual_gpu {
1576 struct drm_i915_private {
1577 struct drm_device *dev;
1578 struct kmem_cache *objects;
1579 struct kmem_cache *vmas;
1580 struct kmem_cache *requests;
1582 const struct intel_device_info info;
1584 int relative_constants_mode;
1588 struct intel_uncore uncore;
1590 struct i915_virtual_gpu vgpu;
1592 struct intel_csr csr;
1594 /* Display CSR-related protection */
1595 struct mutex csr_lock;
1597 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1599 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1600 * controller on different i2c buses. */
1601 struct mutex gmbus_mutex;
1604 * Base address of the gmbus and gpio block.
1606 uint32_t gpio_mmio_base;
1608 /* MMIO base address for MIPI regs */
1609 uint32_t mipi_mmio_base;
1611 wait_queue_head_t gmbus_wait_queue;
1613 struct pci_dev *bridge_dev;
1614 struct intel_engine_cs ring[I915_NUM_RINGS];
1615 struct drm_i915_gem_object *semaphore_obj;
1616 uint32_t last_seqno, next_seqno;
1618 struct drm_dma_handle *status_page_dmah;
1619 struct resource mch_res;
1621 /* protects the irq masks */
1622 spinlock_t irq_lock;
1624 /* protects the mmio flip data */
1625 spinlock_t mmio_flip_lock;
1627 bool display_irqs_enabled;
1629 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1630 struct pm_qos_request pm_qos;
1632 /* DPIO indirect register protection */
1633 struct mutex dpio_lock;
1635 /** Cached value of IMR to avoid reads in updating the bitfield */
1638 u32 de_irq_mask[I915_MAX_PIPES];
1643 u32 pipestat_irq_mask[I915_MAX_PIPES];
1645 struct work_struct hotplug_work;
1647 unsigned long hpd_last_jiffies;
1652 HPD_MARK_DISABLED = 2
1654 } hpd_stats[HPD_NUM_PINS];
1656 struct delayed_work hotplug_reenable_work;
1658 struct i915_fbc fbc;
1659 struct i915_drrs drrs;
1660 struct intel_opregion opregion;
1661 struct intel_vbt_data vbt;
1663 bool preserve_bios_swizzle;
1666 struct intel_overlay *overlay;
1668 /* backlight registers and fields in struct intel_panel */
1669 struct mutex backlight_lock;
1672 bool no_aux_handshake;
1674 /* protects panel power sequencer state */
1675 struct mutex pps_mutex;
1677 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1678 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1679 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1681 unsigned int fsb_freq, mem_freq, is_ddr3;
1682 unsigned int cdclk_freq;
1683 unsigned int hpll_freq;
1686 * wq - Driver workqueue for GEM.
1688 * NOTE: Work items scheduled here are not allowed to grab any modeset
1689 * locks, for otherwise the flushing done in the pageflip code will
1690 * result in deadlocks.
1692 struct workqueue_struct *wq;
1694 /* Display functions */
1695 struct drm_i915_display_funcs display;
1697 /* PCH chipset type */
1698 enum intel_pch pch_type;
1699 unsigned short pch_id;
1701 unsigned long quirks;
1703 enum modeset_restore modeset_restore;
1704 struct mutex modeset_restore_lock;
1706 struct list_head vm_list; /* Global list of all address spaces */
1707 struct i915_gtt gtt; /* VM representing the global address space */
1709 struct i915_gem_mm mm;
1710 DECLARE_HASHTABLE(mm_structs, 7);
1711 struct mutex mm_lock;
1713 /* Kernel Modesetting */
1715 struct sdvo_device_mapping sdvo_mappings[2];
1717 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1718 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1719 wait_queue_head_t pending_flip_queue;
1721 #ifdef CONFIG_DEBUG_FS
1722 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1725 int num_shared_dpll;
1726 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1727 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1729 struct i915_workarounds workarounds;
1731 /* Reclocking support */
1732 bool render_reclock_avail;
1733 bool lvds_downclock_avail;
1734 /* indicates the reduced downclock for LVDS*/
1737 struct i915_frontbuffer_tracking fb_tracking;
1741 bool mchbar_need_disable;
1743 struct intel_l3_parity l3_parity;
1745 /* Cannot be determined by PCIID. You must always read a register. */
1748 /* gen6+ rps state */
1749 struct intel_gen6_power_mgmt rps;
1751 /* ilk-only ips/rps state. Everything in here is protected by the global
1752 * mchdev_lock in intel_pm.c */
1753 struct intel_ilk_power_mgmt ips;
1755 struct i915_power_domains power_domains;
1757 struct i915_psr psr;
1759 struct i915_gpu_error gpu_error;
1761 struct drm_i915_gem_object *vlv_pctx;
1763 #ifdef CONFIG_DRM_I915_FBDEV
1764 /* list of fbdev register on this device */
1765 struct intel_fbdev *fbdev;
1766 struct work_struct fbdev_suspend_work;
1769 struct drm_property *broadcast_rgb_property;
1770 struct drm_property *force_audio_property;
1772 /* hda/i915 audio component */
1773 bool audio_component_registered;
1775 uint32_t hw_context_size;
1776 struct list_head context_list;
1781 struct i915_suspend_saved_registers regfile;
1782 struct vlv_s0ix_state vlv_s0ix_state;
1786 * Raw watermark latency values:
1787 * in 0.1us units for WM0,
1788 * in 0.5us units for WM1+.
1791 uint16_t pri_latency[5];
1793 uint16_t spr_latency[5];
1795 uint16_t cur_latency[5];
1797 * Raw watermark memory latency values
1798 * for SKL for all 8 levels
1801 uint16_t skl_latency[8];
1804 * The skl_wm_values structure is a bit too big for stack
1805 * allocation, so we keep the staging struct where we store
1806 * intermediate results here instead.
1808 struct skl_wm_values skl_results;
1810 /* current hardware state */
1812 struct ilk_wm_values hw;
1813 struct skl_wm_values skl_hw;
1814 struct vlv_wm_values vlv;
1818 struct i915_runtime_pm pm;
1820 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1821 u32 long_hpd_port_mask;
1822 u32 short_hpd_port_mask;
1823 struct work_struct dig_port_work;
1826 * if we get a HPD irq from DP and a HPD irq from non-DP
1827 * the non-DP HPD could block the workqueue on a mode config
1828 * mutex getting, that userspace may have taken. However
1829 * userspace is waiting on the DP workqueue to run which is
1830 * blocked behind the non-DP one.
1832 struct workqueue_struct *dp_wq;
1834 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1836 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1837 struct intel_engine_cs *ring,
1838 struct intel_context *ctx,
1839 struct drm_i915_gem_execbuffer2 *args,
1840 struct list_head *vmas,
1841 struct drm_i915_gem_object *batch_obj,
1842 u64 exec_start, u32 flags);
1843 int (*init_rings)(struct drm_device *dev);
1844 void (*cleanup_ring)(struct intel_engine_cs *ring);
1845 void (*stop_ring)(struct intel_engine_cs *ring);
1848 bool edp_low_vswing;
1851 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1852 * will be rejected. Instead look for a better place.
1856 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1858 return dev->dev_private;
1861 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1863 return to_i915(dev_get_drvdata(dev));
1866 /* Iterate over initialised rings */
1867 #define for_each_ring(ring__, dev_priv__, i__) \
1868 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1869 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1871 enum hdmi_force_audio {
1872 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1873 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1874 HDMI_AUDIO_AUTO, /* trust EDID */
1875 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1878 #define I915_GTT_OFFSET_NONE ((u32)-1)
1880 struct drm_i915_gem_object_ops {
1881 /* Interface between the GEM object and its backing storage.
1882 * get_pages() is called once prior to the use of the associated set
1883 * of pages before to binding them into the GTT, and put_pages() is
1884 * called after we no longer need them. As we expect there to be
1885 * associated cost with migrating pages between the backing storage
1886 * and making them available for the GPU (e.g. clflush), we may hold
1887 * onto the pages after they are no longer referenced by the GPU
1888 * in case they may be used again shortly (for example migrating the
1889 * pages to a different memory domain within the GTT). put_pages()
1890 * will therefore most likely be called when the object itself is
1891 * being released or under memory pressure (where we attempt to
1892 * reap pages for the shrinker).
1894 int (*get_pages)(struct drm_i915_gem_object *);
1895 void (*put_pages)(struct drm_i915_gem_object *);
1896 int (*dmabuf_export)(struct drm_i915_gem_object *);
1897 void (*release)(struct drm_i915_gem_object *);
1901 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1902 * considered to be the frontbuffer for the given plane interface-vise. This
1903 * doesn't mean that the hw necessarily already scans it out, but that any
1904 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1906 * We have one bit per pipe and per scanout plane type.
1908 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1909 #define INTEL_FRONTBUFFER_BITS \
1910 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1911 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1912 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1913 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1914 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1915 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1916 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1917 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1918 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1919 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1920 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1922 struct drm_i915_gem_object {
1923 struct drm_gem_object base;
1925 const struct drm_i915_gem_object_ops *ops;
1927 /** List of VMAs backed by this object */
1928 struct list_head vma_list;
1930 /** Stolen memory for this object, instead of being backed by shmem. */
1931 struct drm_mm_node *stolen;
1932 struct list_head global_list;
1934 struct list_head ring_list;
1935 /** Used in execbuf to temporarily hold a ref */
1936 struct list_head obj_exec_link;
1938 struct list_head batch_pool_link;
1941 * This is set if the object is on the active lists (has pending
1942 * rendering and so a non-zero seqno), and is not set if it i s on
1943 * inactive (ready to be unbound) list.
1945 unsigned int active:1;
1948 * This is set if the object has been written to since last bound
1951 unsigned int dirty:1;
1954 * Fence register bits (if any) for this object. Will be set
1955 * as needed when mapped into the GTT.
1956 * Protected by dev->struct_mutex.
1958 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1961 * Advice: are the backing pages purgeable?
1963 unsigned int madv:2;
1966 * Current tiling mode for the object.
1968 unsigned int tiling_mode:2;
1970 * Whether the tiling parameters for the currently associated fence
1971 * register have changed. Note that for the purposes of tracking
1972 * tiling changes we also treat the unfenced register, the register
1973 * slot that the object occupies whilst it executes a fenced
1974 * command (such as BLT on gen2/3), as a "fence".
1976 unsigned int fence_dirty:1;
1979 * Is the object at the current location in the gtt mappable and
1980 * fenceable? Used to avoid costly recalculations.
1982 unsigned int map_and_fenceable:1;
1985 * Whether the current gtt mapping needs to be mappable (and isn't just
1986 * mappable by accident). Track pin and fault separate for a more
1987 * accurate mappable working set.
1989 unsigned int fault_mappable:1;
1992 * Is the object to be mapped as read-only to the GPU
1993 * Only honoured if hardware has relevant pte bit
1995 unsigned long gt_ro:1;
1996 unsigned int cache_level:3;
1997 unsigned int cache_dirty:1;
1999 unsigned int has_dma_mapping:1;
2001 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2003 unsigned int pin_display;
2005 struct sg_table *pages;
2006 int pages_pin_count;
2008 struct scatterlist *sg;
2012 /* prime dma-buf support */
2013 void *dma_buf_vmapping;
2016 /** Breadcrumb of last rendering to the buffer. */
2017 struct drm_i915_gem_request *last_read_req;
2018 struct drm_i915_gem_request *last_write_req;
2019 /** Breadcrumb of last fenced GPU access to the buffer. */
2020 struct drm_i915_gem_request *last_fenced_req;
2022 /** Current tiling stride for the object, if it's tiled. */
2025 /** References from framebuffers, locks out tiling changes. */
2026 unsigned long framebuffer_references;
2028 /** Record of address bit 17 of each page at last unbind. */
2029 unsigned long *bit_17;
2032 /** for phy allocated objects */
2033 struct drm_dma_handle *phys_handle;
2035 struct i915_gem_userptr {
2037 unsigned read_only :1;
2038 unsigned workers :4;
2039 #define I915_GEM_USERPTR_MAX_WORKERS 15
2041 struct i915_mm_struct *mm;
2042 struct i915_mmu_object *mmu_object;
2043 struct work_struct *work;
2047 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2049 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2050 struct drm_i915_gem_object *new,
2051 unsigned frontbuffer_bits);
2054 * Request queue structure.
2056 * The request queue allows us to note sequence numbers that have been emitted
2057 * and may be associated with active buffers to be retired.
2059 * By keeping this list, we can avoid having to do questionable sequence
2060 * number comparisons on buffer last_read|write_seqno. It also allows an
2061 * emission time to be associated with the request for tracking how far ahead
2062 * of the GPU the submission is.
2064 * The requests are reference counted, so upon creation they should have an
2065 * initial reference taken using kref_init
2067 struct drm_i915_gem_request {
2070 /** On Which ring this request was generated */
2071 struct drm_i915_private *i915;
2072 struct intel_engine_cs *ring;
2074 /** GEM sequence number associated with this request. */
2077 /** Position in the ringbuffer of the start of the request */
2081 * Position in the ringbuffer of the start of the postfix.
2082 * This is required to calculate the maximum available ringbuffer
2083 * space without overwriting the postfix.
2087 /** Position in the ringbuffer of the end of the whole request */
2091 * Context and ring buffer related to this request
2092 * Contexts are refcounted, so when this request is associated with a
2093 * context, we must increment the context's refcount, to guarantee that
2094 * it persists while any request is linked to it. Requests themselves
2095 * are also refcounted, so the request will only be freed when the last
2096 * reference to it is dismissed, and the code in
2097 * i915_gem_request_free() will then decrement the refcount on the
2100 struct intel_context *ctx;
2101 struct intel_ringbuffer *ringbuf;
2103 /** Batch buffer related to this request if any */
2104 struct drm_i915_gem_object *batch_obj;
2106 /** Time at which this request was emitted, in jiffies. */
2107 unsigned long emitted_jiffies;
2109 /** global list entry for this request */
2110 struct list_head list;
2112 struct drm_i915_file_private *file_priv;
2113 /** file_priv list entry for this request */
2114 struct list_head client_list;
2116 /** process identifier submitting this request */
2120 * The ELSP only accepts two elements at a time, so we queue
2121 * context/tail pairs on a given queue (ring->execlist_queue) until the
2122 * hardware is available. The queue serves a double purpose: we also use
2123 * it to keep track of the up to 2 contexts currently in the hardware
2124 * (usually one in execution and the other queued up by the GPU): We
2125 * only remove elements from the head of the queue when the hardware
2126 * informs us that an element has been completed.
2128 * All accesses to the queue are mediated by a spinlock
2129 * (ring->execlist_lock).
2132 /** Execlist link in the submission queue.*/
2133 struct list_head execlist_link;
2135 /** Execlists no. of times this request has been sent to the ELSP */
2140 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2141 struct intel_context *ctx);
2142 void i915_gem_request_free(struct kref *req_ref);
2144 static inline uint32_t
2145 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2147 return req ? req->seqno : 0;
2150 static inline struct intel_engine_cs *
2151 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2153 return req ? req->ring : NULL;
2157 i915_gem_request_reference(struct drm_i915_gem_request *req)
2159 kref_get(&req->ref);
2163 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2165 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2166 kref_put(&req->ref, i915_gem_request_free);
2170 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2172 struct drm_device *dev;
2177 dev = req->ring->dev;
2178 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2179 mutex_unlock(&dev->struct_mutex);
2182 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2183 struct drm_i915_gem_request *src)
2186 i915_gem_request_reference(src);
2189 i915_gem_request_unreference(*pdst);
2195 * XXX: i915_gem_request_completed should be here but currently needs the
2196 * definition of i915_seqno_passed() which is below. It will be moved in
2197 * a later patch when the call to i915_seqno_passed() is obsoleted...
2200 struct drm_i915_file_private {
2201 struct drm_i915_private *dev_priv;
2202 struct drm_file *file;
2206 struct list_head request_list;
2208 struct idr context_idr;
2210 struct list_head rps_boost;
2211 struct intel_engine_cs *bsd_ring;
2213 unsigned rps_boosts;
2217 * A command that requires special handling by the command parser.
2219 struct drm_i915_cmd_descriptor {
2221 * Flags describing how the command parser processes the command.
2223 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2224 * a length mask if not set
2225 * CMD_DESC_SKIP: The command is allowed but does not follow the
2226 * standard length encoding for the opcode range in
2228 * CMD_DESC_REJECT: The command is never allowed
2229 * CMD_DESC_REGISTER: The command should be checked against the
2230 * register whitelist for the appropriate ring
2231 * CMD_DESC_MASTER: The command is allowed if the submitting process
2235 #define CMD_DESC_FIXED (1<<0)
2236 #define CMD_DESC_SKIP (1<<1)
2237 #define CMD_DESC_REJECT (1<<2)
2238 #define CMD_DESC_REGISTER (1<<3)
2239 #define CMD_DESC_BITMASK (1<<4)
2240 #define CMD_DESC_MASTER (1<<5)
2243 * The command's unique identification bits and the bitmask to get them.
2244 * This isn't strictly the opcode field as defined in the spec and may
2245 * also include type, subtype, and/or subop fields.
2253 * The command's length. The command is either fixed length (i.e. does
2254 * not include a length field) or has a length field mask. The flag
2255 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2256 * a length mask. All command entries in a command table must include
2257 * length information.
2265 * Describes where to find a register address in the command to check
2266 * against the ring's register whitelist. Only valid if flags has the
2267 * CMD_DESC_REGISTER bit set.
2274 #define MAX_CMD_DESC_BITMASKS 3
2276 * Describes command checks where a particular dword is masked and
2277 * compared against an expected value. If the command does not match
2278 * the expected value, the parser rejects it. Only valid if flags has
2279 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2282 * If the check specifies a non-zero condition_mask then the parser
2283 * only performs the check when the bits specified by condition_mask
2290 u32 condition_offset;
2292 } bits[MAX_CMD_DESC_BITMASKS];
2296 * A table of commands requiring special handling by the command parser.
2298 * Each ring has an array of tables. Each table consists of an array of command
2299 * descriptors, which must be sorted with command opcodes in ascending order.
2301 struct drm_i915_cmd_table {
2302 const struct drm_i915_cmd_descriptor *table;
2306 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2307 #define __I915__(p) ({ \
2308 struct drm_i915_private *__p; \
2309 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2310 __p = (struct drm_i915_private *)p; \
2311 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2312 __p = to_i915((struct drm_device *)p); \
2317 #define INTEL_INFO(p) (&__I915__(p)->info)
2318 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2319 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2321 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2322 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2323 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2324 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2325 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2326 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2327 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2328 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2329 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2330 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2331 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2332 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2333 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2334 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2335 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2336 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2337 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2338 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2339 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2340 INTEL_DEVID(dev) == 0x0152 || \
2341 INTEL_DEVID(dev) == 0x015a)
2342 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2343 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2344 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2345 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2346 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2347 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2348 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2349 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2350 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2351 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2352 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2353 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2354 (INTEL_DEVID(dev) & 0xf) == 0xe))
2355 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2356 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2357 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2358 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2359 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2360 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2361 /* ULX machines are also considered ULT. */
2362 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2363 INTEL_DEVID(dev) == 0x0A1E)
2364 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2366 #define SKL_REVID_A0 (0x0)
2367 #define SKL_REVID_B0 (0x1)
2368 #define SKL_REVID_C0 (0x2)
2369 #define SKL_REVID_D0 (0x3)
2370 #define SKL_REVID_E0 (0x4)
2372 #define BXT_REVID_A0 (0x0)
2373 #define BXT_REVID_B0 (0x3)
2374 #define BXT_REVID_C0 (0x6)
2377 * The genX designation typically refers to the render engine, so render
2378 * capability related checks should use IS_GEN, while display and other checks
2379 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2382 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2383 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2384 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2385 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2386 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2387 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2388 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2389 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2391 #define RENDER_RING (1<<RCS)
2392 #define BSD_RING (1<<VCS)
2393 #define BLT_RING (1<<BCS)
2394 #define VEBOX_RING (1<<VECS)
2395 #define BSD2_RING (1<<VCS2)
2396 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2397 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2398 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2399 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2400 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2401 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2402 __I915__(dev)->ellc_size)
2403 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2405 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2406 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2407 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2408 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2410 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2411 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2413 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2414 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2416 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2417 * even when in MSI mode. This results in spurious interrupt warnings if the
2418 * legacy irq no. is shared with another device. The kernel then disables that
2419 * interrupt source and so prevents the other device from working properly.
2421 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2422 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2424 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2425 * rows, which changed the alignment requirements and fence programming.
2427 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2429 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2430 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2431 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2432 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2433 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2435 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2436 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2437 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2439 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2441 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2442 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2443 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2444 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2446 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2447 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2449 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2450 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2452 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2454 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2455 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2456 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2457 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2458 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2459 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2460 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2461 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2463 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2464 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2465 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2466 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2467 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2468 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2469 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2471 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2473 /* DPF == dynamic parity feature */
2474 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2475 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2477 #define GT_FREQUENCY_MULTIPLIER 50
2478 #define GEN9_FREQ_SCALER 3
2480 #include "i915_trace.h"
2482 extern const struct drm_ioctl_desc i915_ioctls[];
2483 extern int i915_max_ioctl;
2485 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2486 extern int i915_resume_legacy(struct drm_device *dev);
2489 struct i915_params {
2491 int panel_ignore_lid;
2493 unsigned int lvds_downclock;
2494 int lvds_channel_mode;
2496 int vbt_sdvo_panel_type;
2500 int enable_execlists;
2502 unsigned int preliminary_hw_support;
2503 int disable_power_well;
2505 int invert_brightness;
2506 int enable_cmd_parser;
2507 /* leave bools at the end to not create holes */
2508 bool enable_hangcheck;
2510 bool prefault_disable;
2511 bool load_detect_test;
2513 bool disable_display;
2514 bool disable_vtd_wa;
2517 bool verbose_state_checks;
2518 bool nuclear_pageflip;
2521 extern struct i915_params i915 __read_mostly;
2524 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2525 extern int i915_driver_unload(struct drm_device *);
2526 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2527 extern void i915_driver_lastclose(struct drm_device * dev);
2528 extern void i915_driver_preclose(struct drm_device *dev,
2529 struct drm_file *file);
2530 extern void i915_driver_postclose(struct drm_device *dev,
2531 struct drm_file *file);
2532 extern int i915_driver_device_is_agp(struct drm_device * dev);
2533 #ifdef CONFIG_COMPAT
2534 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2537 extern int intel_gpu_reset(struct drm_device *dev);
2538 extern int i915_reset(struct drm_device *dev);
2539 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2540 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2541 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2542 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2543 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2544 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2545 void i915_firmware_load_error_print(const char *fw_path, int err);
2548 void i915_queue_hangcheck(struct drm_device *dev);
2550 void i915_handle_error(struct drm_device *dev, bool wedged,
2551 const char *fmt, ...);
2553 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2554 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2555 int intel_irq_install(struct drm_i915_private *dev_priv);
2556 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2558 extern void intel_uncore_sanitize(struct drm_device *dev);
2559 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2560 bool restore_forcewake);
2561 extern void intel_uncore_init(struct drm_device *dev);
2562 extern void intel_uncore_check_errors(struct drm_device *dev);
2563 extern void intel_uncore_fini(struct drm_device *dev);
2564 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2565 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2566 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2567 enum forcewake_domains domains);
2568 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2569 enum forcewake_domains domains);
2570 /* Like above but the caller must manage the uncore.lock itself.
2571 * Must be used with I915_READ_FW and friends.
2573 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2574 enum forcewake_domains domains);
2575 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2576 enum forcewake_domains domains);
2577 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2578 static inline bool intel_vgpu_active(struct drm_device *dev)
2580 return to_i915(dev)->vgpu.active;
2584 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2588 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2591 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2592 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2594 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2596 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2597 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2598 uint32_t interrupt_mask,
2599 uint32_t enabled_irq_mask);
2600 #define ibx_enable_display_interrupt(dev_priv, bits) \
2601 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2602 #define ibx_disable_display_interrupt(dev_priv, bits) \
2603 ibx_display_interrupt_update((dev_priv), (bits), 0)
2606 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2607 struct drm_file *file_priv);
2608 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2609 struct drm_file *file_priv);
2610 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2611 struct drm_file *file_priv);
2612 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2613 struct drm_file *file_priv);
2614 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2615 struct drm_file *file_priv);
2616 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2617 struct drm_file *file_priv);
2618 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2619 struct drm_file *file_priv);
2620 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2621 struct intel_engine_cs *ring);
2622 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2623 struct drm_file *file,
2624 struct intel_engine_cs *ring,
2625 struct drm_i915_gem_object *obj);
2626 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2627 struct drm_file *file,
2628 struct intel_engine_cs *ring,
2629 struct intel_context *ctx,
2630 struct drm_i915_gem_execbuffer2 *args,
2631 struct list_head *vmas,
2632 struct drm_i915_gem_object *batch_obj,
2633 u64 exec_start, u32 flags);
2634 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2635 struct drm_file *file_priv);
2636 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2637 struct drm_file *file_priv);
2638 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2639 struct drm_file *file_priv);
2640 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2641 struct drm_file *file);
2642 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2643 struct drm_file *file);
2644 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2645 struct drm_file *file_priv);
2646 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2647 struct drm_file *file_priv);
2648 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2649 struct drm_file *file_priv);
2650 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2651 struct drm_file *file_priv);
2652 int i915_gem_init_userptr(struct drm_device *dev);
2653 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2654 struct drm_file *file);
2655 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2656 struct drm_file *file_priv);
2657 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2658 struct drm_file *file_priv);
2659 void i915_gem_load(struct drm_device *dev);
2660 void *i915_gem_object_alloc(struct drm_device *dev);
2661 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2662 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2663 const struct drm_i915_gem_object_ops *ops);
2664 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2666 void i915_init_vm(struct drm_i915_private *dev_priv,
2667 struct i915_address_space *vm);
2668 void i915_gem_free_object(struct drm_gem_object *obj);
2669 void i915_gem_vma_destroy(struct i915_vma *vma);
2671 /* Flags used by pin/bind&friends. */
2672 #define PIN_MAPPABLE (1<<0)
2673 #define PIN_NONBLOCK (1<<1)
2674 #define PIN_GLOBAL (1<<2)
2675 #define PIN_OFFSET_BIAS (1<<3)
2676 #define PIN_USER (1<<4)
2677 #define PIN_UPDATE (1<<5)
2678 #define PIN_OFFSET_MASK (~4095)
2680 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2681 struct i915_address_space *vm,
2685 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2686 const struct i915_ggtt_view *view,
2690 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2692 int __must_check i915_vma_unbind(struct i915_vma *vma);
2693 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2694 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2695 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2697 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2698 int *needs_clflush);
2700 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2702 static inline int __sg_page_count(struct scatterlist *sg)
2704 return sg->length >> PAGE_SHIFT;
2707 static inline struct page *
2708 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2710 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2713 if (n < obj->get_page.last) {
2714 obj->get_page.sg = obj->pages->sgl;
2715 obj->get_page.last = 0;
2718 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2719 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2720 if (unlikely(sg_is_chain(obj->get_page.sg)))
2721 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2724 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2727 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2729 BUG_ON(obj->pages == NULL);
2730 obj->pages_pin_count++;
2732 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2734 BUG_ON(obj->pages_pin_count == 0);
2735 obj->pages_pin_count--;
2738 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2739 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2740 struct intel_engine_cs *to);
2741 void i915_vma_move_to_active(struct i915_vma *vma,
2742 struct intel_engine_cs *ring);
2743 int i915_gem_dumb_create(struct drm_file *file_priv,
2744 struct drm_device *dev,
2745 struct drm_mode_create_dumb *args);
2746 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2747 uint32_t handle, uint64_t *offset);
2749 * Returns true if seq1 is later than seq2.
2752 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2754 return (int32_t)(seq1 - seq2) >= 0;
2757 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2758 bool lazy_coherency)
2762 BUG_ON(req == NULL);
2764 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2766 return i915_seqno_passed(seqno, req->seqno);
2769 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2770 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2771 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2772 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2774 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2775 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2777 struct drm_i915_gem_request *
2778 i915_gem_find_active_request(struct intel_engine_cs *ring);
2780 bool i915_gem_retire_requests(struct drm_device *dev);
2781 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2782 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2783 bool interruptible);
2784 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2786 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2788 return unlikely(atomic_read(&error->reset_counter)
2789 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2792 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2794 return atomic_read(&error->reset_counter) & I915_WEDGED;
2797 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2799 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2802 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2804 return dev_priv->gpu_error.stop_rings == 0 ||
2805 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2808 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2810 return dev_priv->gpu_error.stop_rings == 0 ||
2811 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2814 void i915_gem_reset(struct drm_device *dev);
2815 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2816 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2817 int __must_check i915_gem_init(struct drm_device *dev);
2818 int i915_gem_init_rings(struct drm_device *dev);
2819 int __must_check i915_gem_init_hw(struct drm_device *dev);
2820 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2821 void i915_gem_init_swizzling(struct drm_device *dev);
2822 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2823 int __must_check i915_gpu_idle(struct drm_device *dev);
2824 int __must_check i915_gem_suspend(struct drm_device *dev);
2825 int __i915_add_request(struct intel_engine_cs *ring,
2826 struct drm_file *file,
2827 struct drm_i915_gem_object *batch_obj);
2828 #define i915_add_request(ring) \
2829 __i915_add_request(ring, NULL, NULL)
2830 int __i915_wait_request(struct drm_i915_gem_request *req,
2831 unsigned reset_counter,
2834 struct drm_i915_file_private *file_priv);
2835 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2836 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2838 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2841 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2843 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2845 struct intel_engine_cs *pipelined,
2846 const struct i915_ggtt_view *view);
2847 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2848 const struct i915_ggtt_view *view);
2849 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2851 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2852 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2855 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2857 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2858 int tiling_mode, bool fenced);
2860 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2861 enum i915_cache_level cache_level);
2863 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2864 struct dma_buf *dma_buf);
2866 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2867 struct drm_gem_object *gem_obj, int flags);
2869 void i915_gem_restore_fences(struct drm_device *dev);
2872 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2873 const struct i915_ggtt_view *view);
2875 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2876 struct i915_address_space *vm);
2877 static inline unsigned long
2878 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2880 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2883 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2884 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2885 const struct i915_ggtt_view *view);
2886 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2887 struct i915_address_space *vm);
2889 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2890 struct i915_address_space *vm);
2892 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2893 struct i915_address_space *vm);
2895 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2896 const struct i915_ggtt_view *view);
2899 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2900 struct i915_address_space *vm);
2902 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2903 const struct i915_ggtt_view *view);
2905 static inline struct i915_vma *
2906 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2908 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2910 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2912 /* Some GGTT VM helpers */
2913 #define i915_obj_to_ggtt(obj) \
2914 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2915 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2917 struct i915_address_space *ggtt =
2918 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2922 static inline struct i915_hw_ppgtt *
2923 i915_vm_to_ppgtt(struct i915_address_space *vm)
2925 WARN_ON(i915_is_ggtt(vm));
2927 return container_of(vm, struct i915_hw_ppgtt, base);
2931 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2933 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2936 static inline unsigned long
2937 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2939 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2942 static inline int __must_check
2943 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2947 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2948 alignment, flags | PIN_GLOBAL);
2952 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2954 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2957 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2958 const struct i915_ggtt_view *view);
2960 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2962 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2965 /* i915_gem_context.c */
2966 int __must_check i915_gem_context_init(struct drm_device *dev);
2967 void i915_gem_context_fini(struct drm_device *dev);
2968 void i915_gem_context_reset(struct drm_device *dev);
2969 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2970 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2971 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2972 int i915_switch_context(struct intel_engine_cs *ring,
2973 struct intel_context *to);
2974 struct intel_context *
2975 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2976 void i915_gem_context_free(struct kref *ctx_ref);
2977 struct drm_i915_gem_object *
2978 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2979 static inline void i915_gem_context_reference(struct intel_context *ctx)
2981 kref_get(&ctx->ref);
2984 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2986 kref_put(&ctx->ref, i915_gem_context_free);
2989 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2991 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2994 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2995 struct drm_file *file);
2996 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2997 struct drm_file *file);
2998 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2999 struct drm_file *file_priv);
3000 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3001 struct drm_file *file_priv);
3003 /* i915_gem_evict.c */
3004 int __must_check i915_gem_evict_something(struct drm_device *dev,
3005 struct i915_address_space *vm,
3008 unsigned cache_level,
3009 unsigned long start,
3012 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3013 int i915_gem_evict_everything(struct drm_device *dev);
3015 /* belongs in i915_gem_gtt.h */
3016 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3018 if (INTEL_INFO(dev)->gen < 6)
3019 intel_gtt_chipset_flush();
3022 /* i915_gem_stolen.c */
3023 int i915_gem_init_stolen(struct drm_device *dev);
3024 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
3025 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3026 void i915_gem_cleanup_stolen(struct drm_device *dev);
3027 struct drm_i915_gem_object *
3028 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3029 struct drm_i915_gem_object *
3030 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3035 /* i915_gem_shrinker.c */
3036 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3039 #define I915_SHRINK_PURGEABLE 0x1
3040 #define I915_SHRINK_UNBOUND 0x2
3041 #define I915_SHRINK_BOUND 0x4
3042 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3043 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3046 /* i915_gem_tiling.c */
3047 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3049 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3051 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3052 obj->tiling_mode != I915_TILING_NONE;
3055 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3056 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3057 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3059 /* i915_gem_debug.c */
3061 int i915_verify_lists(struct drm_device *dev);
3063 #define i915_verify_lists(dev) 0
3066 /* i915_debugfs.c */
3067 int i915_debugfs_init(struct drm_minor *minor);
3068 void i915_debugfs_cleanup(struct drm_minor *minor);
3069 #ifdef CONFIG_DEBUG_FS
3070 int i915_debugfs_connector_add(struct drm_connector *connector);
3071 void intel_display_crc_init(struct drm_device *dev);
3073 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3074 static inline void intel_display_crc_init(struct drm_device *dev) {}
3077 /* i915_gpu_error.c */
3079 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3080 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3081 const struct i915_error_state_file_priv *error);
3082 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3083 struct drm_i915_private *i915,
3084 size_t count, loff_t pos);
3085 static inline void i915_error_state_buf_release(
3086 struct drm_i915_error_state_buf *eb)
3090 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3091 const char *error_msg);
3092 void i915_error_state_get(struct drm_device *dev,
3093 struct i915_error_state_file_priv *error_priv);
3094 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3095 void i915_destroy_error_state(struct drm_device *dev);
3097 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3098 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3100 /* i915_cmd_parser.c */
3101 int i915_cmd_parser_get_version(void);
3102 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3103 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3104 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3105 int i915_parse_cmds(struct intel_engine_cs *ring,
3106 struct drm_i915_gem_object *batch_obj,
3107 struct drm_i915_gem_object *shadow_batch_obj,
3108 u32 batch_start_offset,
3112 /* i915_suspend.c */
3113 extern int i915_save_state(struct drm_device *dev);
3114 extern int i915_restore_state(struct drm_device *dev);
3117 void i915_setup_sysfs(struct drm_device *dev_priv);
3118 void i915_teardown_sysfs(struct drm_device *dev_priv);
3121 extern int intel_setup_gmbus(struct drm_device *dev);
3122 extern void intel_teardown_gmbus(struct drm_device *dev);
3123 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3126 extern struct i2c_adapter *
3127 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3128 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3129 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3130 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3132 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3134 extern void intel_i2c_reset(struct drm_device *dev);
3136 /* intel_opregion.c */
3138 extern int intel_opregion_setup(struct drm_device *dev);
3139 extern void intel_opregion_init(struct drm_device *dev);
3140 extern void intel_opregion_fini(struct drm_device *dev);
3141 extern void intel_opregion_asle_intr(struct drm_device *dev);
3142 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3144 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3147 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3148 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3149 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3150 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3152 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3157 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3165 extern void intel_register_dsm_handler(void);
3166 extern void intel_unregister_dsm_handler(void);
3168 static inline void intel_register_dsm_handler(void) { return; }
3169 static inline void intel_unregister_dsm_handler(void) { return; }
3170 #endif /* CONFIG_ACPI */
3173 extern void intel_modeset_init_hw(struct drm_device *dev);
3174 extern void intel_modeset_init(struct drm_device *dev);
3175 extern void intel_modeset_gem_init(struct drm_device *dev);
3176 extern void intel_modeset_cleanup(struct drm_device *dev);
3177 extern void intel_connector_unregister(struct intel_connector *);
3178 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3179 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3180 bool force_restore);
3181 extern void i915_redisable_vga(struct drm_device *dev);
3182 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3183 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3184 extern void intel_init_pch_refclk(struct drm_device *dev);
3185 extern void intel_set_rps(struct drm_device *dev, u8 val);
3186 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3188 extern void intel_detect_pch(struct drm_device *dev);
3189 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3190 extern int intel_enable_rc6(const struct drm_device *dev);
3192 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3193 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3194 struct drm_file *file);
3195 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3196 struct drm_file *file);
3199 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3200 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3201 struct intel_overlay_error_state *error);
3203 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3204 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3205 struct drm_device *dev,
3206 struct intel_display_error_state *error);
3208 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3209 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3211 /* intel_sideband.c */
3212 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3213 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3214 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3215 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3216 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3217 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3218 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3219 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3220 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3221 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3222 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3223 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3224 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3225 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3226 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3227 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3228 enum intel_sbi_destination destination);
3229 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3230 enum intel_sbi_destination destination);
3231 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3232 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3234 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3235 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3237 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3238 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3240 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3241 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3242 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3243 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3245 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3246 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3247 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3248 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3250 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3251 * will be implemented using 2 32-bit writes in an arbitrary order with
3252 * an arbitrary delay between them. This can cause the hardware to
3253 * act upon the intermediate value, possibly leading to corruption and
3254 * machine death. You have been warned.
3256 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3257 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3259 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3260 u32 upper = I915_READ(upper_reg); \
3261 u32 lower = I915_READ(lower_reg); \
3262 u32 tmp = I915_READ(upper_reg); \
3263 if (upper != tmp) { \
3265 lower = I915_READ(lower_reg); \
3266 WARN_ON(I915_READ(upper_reg) != upper); \
3268 (u64)upper << 32 | lower; })
3270 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3271 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3273 /* These are untraced mmio-accessors that are only valid to be used inside
3274 * criticial sections inside IRQ handlers where forcewake is explicitly
3276 * Think twice, and think again, before using these.
3277 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3278 * intel_uncore_forcewake_irqunlock().
3280 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3281 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3282 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3284 /* "Broadcast RGB" property */
3285 #define INTEL_BROADCAST_RGB_AUTO 0
3286 #define INTEL_BROADCAST_RGB_FULL 1
3287 #define INTEL_BROADCAST_RGB_LIMITED 2
3289 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3291 if (IS_VALLEYVIEW(dev))
3292 return VLV_VGACNTRL;
3293 else if (INTEL_INFO(dev)->gen >= 5)
3294 return CPU_VGACNTRL;
3299 static inline void __user *to_user_ptr(u64 address)
3301 return (void __user *)(uintptr_t)address;
3304 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3306 unsigned long j = msecs_to_jiffies(m);
3308 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3311 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3313 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3316 static inline unsigned long
3317 timespec_to_jiffies_timeout(const struct timespec *value)
3319 unsigned long j = timespec_to_jiffies(value);
3321 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3325 * If you need to wait X milliseconds between events A and B, but event B
3326 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3327 * when event A happened, then just before event B you call this function and
3328 * pass the timestamp as the first argument, and X as the second argument.
3331 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3333 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3336 * Don't re-read the value of "jiffies" every time since it may change
3337 * behind our back and break the math.
3339 tmp_jiffies = jiffies;
3340 target_jiffies = timestamp_jiffies +
3341 msecs_to_jiffies_timeout(to_wait_ms);
3343 if (time_after(target_jiffies, tmp_jiffies)) {
3344 remaining_jiffies = target_jiffies - tmp_jiffies;
3345 while (remaining_jiffies)
3347 schedule_timeout_uninterruptible(remaining_jiffies);
3351 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3352 struct drm_i915_gem_request *req)
3354 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3355 i915_gem_request_assign(&ring->trace_irq_req, req);