1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/backlight.h>
41 /* General customization:
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
56 #define pipe_name(p) ((p) + 'A')
63 #define plane_name(p) ((p) + 'A')
65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
79 #define DRIVER_MAJOR 1
80 #define DRIVER_MINOR 6
81 #define DRIVER_PATCHLEVEL 0
83 #define WATCH_COHERENCY 0
86 #define I915_GEM_PHYS_CURSOR_0 1
87 #define I915_GEM_PHYS_CURSOR_1 2
88 #define I915_GEM_PHYS_OVERLAY_REGS 3
89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91 struct drm_i915_gem_phys_object {
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
99 struct mem_block *next;
100 struct mem_block *prev;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
110 struct drm_i915_private;
112 struct intel_opregion {
113 struct opregion_header *header;
114 struct opregion_acpi *acpi;
115 struct opregion_swsci *swsci;
116 struct opregion_asle *asle;
118 u32 __iomem *lid_state;
120 #define OPREGION_SIZE (8*1024)
122 struct intel_overlay;
123 struct intel_overlay_error_state;
125 struct drm_i915_master_private {
126 drm_local_map_t *sarea;
127 struct _drm_i915_sarea *sarea_priv;
129 #define I915_FENCE_REG_NONE -1
130 #define I915_MAX_NUM_FENCES 16
131 /* 16 fences + sign bit for FENCE_REG_NONE */
132 #define I915_MAX_NUM_FENCE_BITS 5
134 struct drm_i915_fence_reg {
135 struct list_head lru_list;
136 struct drm_i915_gem_object *obj;
137 uint32_t setup_seqno;
140 struct sdvo_device_mapping {
149 struct intel_display_error_state;
151 struct drm_i915_error_state {
154 u32 pipestat[I915_MAX_PIPES];
159 u32 error; /* gen6+ */
160 u32 bcs_acthd; /* gen6+ blt engine */
165 u32 vcs_acthd; /* gen6+ bsd engine */
175 u64 fence[I915_MAX_NUM_FENCES];
177 struct drm_i915_error_object {
181 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
182 struct drm_i915_error_buffer {
189 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
196 } *active_bo, *pinned_bo;
197 u32 active_bo_count, pinned_bo_count;
198 struct intel_overlay_error_state *overlay;
199 struct intel_display_error_state *display;
202 struct drm_i915_display_funcs {
203 void (*dpms)(struct drm_crtc *crtc, int mode);
204 bool (*fbc_enabled)(struct drm_device *dev);
205 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
206 void (*disable_fbc)(struct drm_device *dev);
207 int (*get_display_clock_speed)(struct drm_device *dev);
208 int (*get_fifo_size)(struct drm_device *dev, int plane);
209 void (*update_wm)(struct drm_device *dev);
210 int (*crtc_mode_set)(struct drm_crtc *crtc,
211 struct drm_display_mode *mode,
212 struct drm_display_mode *adjusted_mode,
214 struct drm_framebuffer *old_fb);
215 void (*write_eld)(struct drm_connector *connector,
216 struct drm_crtc *crtc);
217 void (*fdi_link_train)(struct drm_crtc *crtc);
218 void (*init_clock_gating)(struct drm_device *dev);
219 void (*init_pch_clock_gating)(struct drm_device *dev);
220 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
221 struct drm_framebuffer *fb,
222 struct drm_i915_gem_object *obj);
223 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
225 void (*force_wake_get)(struct drm_i915_private *dev_priv);
226 void (*force_wake_put)(struct drm_i915_private *dev_priv);
227 /* clock updates for mode set */
229 /* render clock increase/decrease */
230 /* display clock increase/decrease */
231 /* pll clock increase/decrease */
234 struct intel_device_info {
250 u8 cursor_needs_physical:1;
252 u8 overlay_needs_physical:1;
259 FBC_NO_OUTPUT, /* no outputs enabled to compress */
260 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
261 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
262 FBC_MODE_TOO_LARGE, /* mode too large for compression */
263 FBC_BAD_PLANE, /* fbc not supported on plane */
264 FBC_NOT_TILED, /* buffer not tiled */
265 FBC_MULTIPLE_PIPES, /* more than one pipe active */
270 PCH_IBX, /* Ibexpeak PCH */
271 PCH_CPT, /* Cougarpoint PCH */
274 #define QUIRK_PIPEA_FORCE (1<<0)
275 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
278 struct intel_fbc_work;
280 typedef struct drm_i915_private {
281 struct drm_device *dev;
283 const struct intel_device_info *info;
286 int relative_constants_mode;
292 struct i2c_adapter adapter;
293 struct i2c_adapter *force_bit;
297 struct pci_dev *bridge_dev;
298 struct intel_ring_buffer ring[I915_NUM_RINGS];
301 drm_dma_handle_t *status_page_dmah;
303 drm_local_map_t hws_map;
304 struct drm_i915_gem_object *pwrctx;
305 struct drm_i915_gem_object *renderctx;
307 struct resource mch_res;
315 atomic_t irq_received;
317 /* protects the irq masks */
319 /** Cached value of IMR to avoid reads in updating the bitfield */
325 u32 hotplug_supported_mask;
326 struct work_struct hotplug_work;
328 int tex_lru_log_granularity;
329 int allow_batchbuffer;
330 struct mem_block *agp_heap;
331 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
335 /* For hangcheck timer */
336 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
337 struct timer_list hangcheck_timer;
340 uint32_t last_acthd_bsd;
341 uint32_t last_acthd_blt;
342 uint32_t last_instdone;
343 uint32_t last_instdone1;
345 unsigned long cfb_size;
347 enum plane cfb_plane;
349 struct intel_fbc_work *fbc_work;
351 struct intel_opregion opregion;
354 struct intel_overlay *overlay;
357 int backlight_level; /* restore backlight to this value */
358 bool backlight_enabled;
359 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
360 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
362 /* Feature bits from the VBIOS */
363 unsigned int int_tv_support:1;
364 unsigned int lvds_dither:1;
365 unsigned int lvds_vbt:1;
366 unsigned int int_crt_support:1;
367 unsigned int lvds_use_ssc:1;
368 unsigned int display_clock_mode:1;
379 struct edp_power_seq pps;
381 bool no_aux_handshake;
383 struct notifier_block lid_notifier;
386 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
387 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
388 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
390 unsigned int fsb_freq, mem_freq, is_ddr3;
392 spinlock_t error_lock;
393 struct drm_i915_error_state *first_error;
394 struct work_struct error_work;
395 struct completion error_completion;
396 struct workqueue_struct *wq;
398 /* Display functions */
399 struct drm_i915_display_funcs display;
401 /* PCH chipset type */
402 enum intel_pch pch_type;
404 unsigned long quirks;
429 u32 saveTRANS_HTOTAL_A;
430 u32 saveTRANS_HBLANK_A;
431 u32 saveTRANS_HSYNC_A;
432 u32 saveTRANS_VTOTAL_A;
433 u32 saveTRANS_VBLANK_A;
434 u32 saveTRANS_VSYNC_A;
442 u32 savePFIT_PGM_RATIOS;
443 u32 saveBLC_HIST_CTL;
445 u32 saveBLC_PWM_CTL2;
446 u32 saveBLC_CPU_PWM_CTL;
447 u32 saveBLC_CPU_PWM_CTL2;
460 u32 saveTRANS_HTOTAL_B;
461 u32 saveTRANS_HBLANK_B;
462 u32 saveTRANS_HSYNC_B;
463 u32 saveTRANS_VTOTAL_B;
464 u32 saveTRANS_VBLANK_B;
465 u32 saveTRANS_VSYNC_B;
479 u32 savePP_ON_DELAYS;
480 u32 savePP_OFF_DELAYS;
488 u32 savePFIT_CONTROL;
489 u32 save_palette_a[256];
490 u32 save_palette_b[256];
491 u32 saveDPFC_CB_BASE;
492 u32 saveFBC_CFB_BASE;
495 u32 saveFBC_CONTROL2;
505 u32 saveCACHE_MODE_0;
506 u32 saveMI_ARB_STATE;
517 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
528 u32 savePIPEA_GMCH_DATA_M;
529 u32 savePIPEB_GMCH_DATA_M;
530 u32 savePIPEA_GMCH_DATA_N;
531 u32 savePIPEB_GMCH_DATA_N;
532 u32 savePIPEA_DP_LINK_M;
533 u32 savePIPEB_DP_LINK_M;
534 u32 savePIPEA_DP_LINK_N;
535 u32 savePIPEB_DP_LINK_N;
546 u32 savePCH_DREF_CONTROL;
547 u32 saveDISP_ARB_CTL;
548 u32 savePIPEA_DATA_M1;
549 u32 savePIPEA_DATA_N1;
550 u32 savePIPEA_LINK_M1;
551 u32 savePIPEA_LINK_N1;
552 u32 savePIPEB_DATA_M1;
553 u32 savePIPEB_DATA_N1;
554 u32 savePIPEB_LINK_M1;
555 u32 savePIPEB_LINK_N1;
556 u32 saveMCHBAR_RENDER_STANDBY;
557 u32 savePCH_PORT_HOTPLUG;
560 /** Bridge to intel-gtt-ko */
561 const struct intel_gtt *gtt;
562 /** Memory allocator for GTT stolen memory */
563 struct drm_mm stolen;
564 /** Memory allocator for GTT */
565 struct drm_mm gtt_space;
566 /** List of all objects in gtt_space. Used to restore gtt
567 * mappings on resume */
568 struct list_head gtt_list;
570 /** Usable portion of the GTT for GEM */
571 unsigned long gtt_start;
572 unsigned long gtt_mappable_end;
573 unsigned long gtt_end;
575 struct io_mapping *gtt_mapping;
578 struct shrinker inactive_shrinker;
581 * List of objects currently involved in rendering.
583 * Includes buffers having the contents of their GPU caches
584 * flushed, not necessarily primitives. last_rendering_seqno
585 * represents when the rendering involved will be completed.
587 * A reference is held on the buffer while on this list.
589 struct list_head active_list;
592 * List of objects which are not in the ringbuffer but which
593 * still have a write_domain which needs to be flushed before
596 * last_rendering_seqno is 0 while an object is in this list.
598 * A reference is held on the buffer while on this list.
600 struct list_head flushing_list;
603 * LRU list of objects which are not in the ringbuffer and
604 * are ready to unbind, but are still in the GTT.
606 * last_rendering_seqno is 0 while an object is in this list.
608 * A reference is not held on the buffer while on this list,
609 * as merely being GTT-bound shouldn't prevent its being
610 * freed, and we'll pull it off the list in the free path.
612 struct list_head inactive_list;
615 * LRU list of objects which are not in the ringbuffer but
616 * are still pinned in the GTT.
618 struct list_head pinned_list;
620 /** LRU list of objects with fence regs on them. */
621 struct list_head fence_list;
624 * List of objects currently pending being freed.
626 * These objects are no longer in use, but due to a signal
627 * we were prevented from freeing them at the appointed time.
629 struct list_head deferred_free_list;
632 * We leave the user IRQ off as much as possible,
633 * but this means that requests will finish and never
634 * be retired once the system goes idle. Set a timer to
635 * fire periodically while the ring is running. When it
636 * fires, go retire requests.
638 struct delayed_work retire_work;
641 * Are we in a non-interruptible section of code like
647 * Flag if the X Server, and thus DRM, is not currently in
648 * control of the device.
650 * This is set between LeaveVT and EnterVT. It needs to be
651 * replaced with a semaphore. It also needs to be
652 * transitioned away from for kernel modesetting.
657 * Flag if the hardware appears to be wedged.
659 * This is set when attempts to idle the device timeout.
660 * It prevents command submission from occurring and makes
661 * every pending request fail
665 /** Bit 6 swizzling required for X tiling */
666 uint32_t bit_6_swizzle_x;
667 /** Bit 6 swizzling required for Y tiling */
668 uint32_t bit_6_swizzle_y;
670 /* storage for physical objects */
671 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
673 /* accounting, useful for userland debugging */
675 size_t mappable_gtt_total;
676 size_t object_memory;
679 struct sdvo_device_mapping sdvo_mappings[2];
680 /* indicate whether the LVDS_BORDER should be enabled or not */
681 unsigned int lvds_border_bits;
682 /* Panel fitter placement and size for Ironlake+ */
683 u32 pch_pf_pos, pch_pf_size;
685 struct drm_crtc *plane_to_crtc_mapping[3];
686 struct drm_crtc *pipe_to_crtc_mapping[3];
687 wait_queue_head_t pending_flip_queue;
688 bool flip_pending_is_done;
690 /* Reclocking support */
691 bool render_reclock_avail;
692 bool lvds_downclock_avail;
693 /* indicates the reduced downclock for LVDS*/
695 struct work_struct idle_work;
696 struct timer_list idle_timer;
700 struct child_device_config *child_dev;
701 struct drm_connector *int_lvds_connector;
702 struct drm_connector *int_edp_connector;
704 bool mchbar_need_disable;
706 struct work_struct rps_work;
717 unsigned long last_time1;
718 unsigned long chipset_power;
720 struct timespec last_time2;
721 unsigned long gfx_power;
725 spinlock_t *mchdev_lock;
727 enum no_fbc_reason no_fbc_reason;
729 struct drm_mm_node *compressed_fb;
730 struct drm_mm_node *compressed_llb;
732 unsigned long last_gpu_reset;
734 /* list of fbdev register on this device */
735 struct intel_fbdev *fbdev;
737 struct backlight_device *backlight;
739 struct drm_property *broadcast_rgb_property;
740 struct drm_property *force_audio_property;
742 atomic_t forcewake_count;
743 } drm_i915_private_t;
745 enum i915_cache_level {
748 I915_CACHE_LLC_MLC, /* gen6+ */
751 struct drm_i915_gem_object {
752 struct drm_gem_object base;
754 /** Current space allocated to this object in the GTT, if any. */
755 struct drm_mm_node *gtt_space;
756 struct list_head gtt_list;
758 /** This object's place on the active/flushing/inactive lists */
759 struct list_head ring_list;
760 struct list_head mm_list;
761 /** This object's place on GPU write list */
762 struct list_head gpu_write_list;
763 /** This object's place in the batchbuffer or on the eviction list */
764 struct list_head exec_list;
767 * This is set if the object is on the active or flushing lists
768 * (has pending rendering), and is not set if it's on inactive (ready
771 unsigned int active:1;
774 * This is set if the object has been written to since last bound
777 unsigned int dirty:1;
780 * This is set if the object has been written to since the last
783 unsigned int pending_gpu_write:1;
786 * Fence register bits (if any) for this object. Will be set
787 * as needed when mapped into the GTT.
788 * Protected by dev->struct_mutex.
790 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
793 * Advice: are the backing pages purgeable?
798 * Current tiling mode for the object.
800 unsigned int tiling_mode:2;
801 unsigned int tiling_changed:1;
803 /** How many users have pinned this object in GTT space. The following
804 * users can each hold at most one reference: pwrite/pread, pin_ioctl
805 * (via user_pin_count), execbuffer (objects are not allowed multiple
806 * times for the same batchbuffer), and the framebuffer code. When
807 * switching/pageflipping, the framebuffer code has at most two buffers
810 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
811 * bits with absolutely no headroom. So use 4 bits. */
812 unsigned int pin_count:4;
813 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
816 * Is the object at the current location in the gtt mappable and
817 * fenceable? Used to avoid costly recalculations.
819 unsigned int map_and_fenceable:1;
822 * Whether the current gtt mapping needs to be mappable (and isn't just
823 * mappable by accident). Track pin and fault separate for a more
824 * accurate mappable working set.
826 unsigned int fault_mappable:1;
827 unsigned int pin_mappable:1;
830 * Is the GPU currently using a fence to access this buffer,
832 unsigned int pending_fenced_gpu_access:1;
833 unsigned int fenced_gpu_access:1;
835 unsigned int cache_level:2;
842 struct scatterlist *sg_list;
846 * Used for performing relocations during execbuffer insertion.
848 struct hlist_node exec_node;
849 unsigned long exec_handle;
850 struct drm_i915_gem_exec_object2 *exec_entry;
853 * Current offset of the object in GTT space.
855 * This is the same as gtt_space->start
859 /** Breadcrumb of last rendering to the buffer. */
860 uint32_t last_rendering_seqno;
861 struct intel_ring_buffer *ring;
863 /** Breadcrumb of last fenced GPU access to the buffer. */
864 uint32_t last_fenced_seqno;
865 struct intel_ring_buffer *last_fenced_ring;
867 /** Current tiling stride for the object, if it's tiled. */
870 /** Record of address bit 17 of each page at last unbind. */
871 unsigned long *bit_17;
875 * If present, while GEM_DOMAIN_CPU is in the read domain this array
876 * flags which individual pages are valid.
878 uint8_t *page_cpu_valid;
880 /** User space pin count and filp owning the pin */
881 uint32_t user_pin_count;
882 struct drm_file *pin_filp;
884 /** for phy allocated objects */
885 struct drm_i915_gem_phys_object *phys_obj;
888 * Number of crtcs where this object is currently the fb, but
889 * will be page flipped away on the next vblank. When it
890 * reaches 0, dev_priv->pending_flip_queue will be woken up.
892 atomic_t pending_flip;
895 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
898 * Request queue structure.
900 * The request queue allows us to note sequence numbers that have been emitted
901 * and may be associated with active buffers to be retired.
903 * By keeping this list, we can avoid having to do questionable
904 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
905 * an emission time with seqnos for tracking how far ahead of the GPU we are.
907 struct drm_i915_gem_request {
908 /** On Which ring this request was generated */
909 struct intel_ring_buffer *ring;
911 /** GEM sequence number associated with this request. */
914 /** Time at which this request was emitted, in jiffies. */
915 unsigned long emitted_jiffies;
917 /** global list entry for this request */
918 struct list_head list;
920 struct drm_i915_file_private *file_priv;
921 /** file_priv list entry for this request */
922 struct list_head client_list;
925 struct drm_i915_file_private {
927 struct spinlock lock;
928 struct list_head request_list;
932 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
934 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
935 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
936 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
937 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
938 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
939 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
940 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
941 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
942 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
943 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
944 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
945 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
946 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
947 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
948 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
949 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
950 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
951 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
952 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
953 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
956 * The genX designation typically refers to the render engine, so render
957 * capability related checks should use IS_GEN, while display and other checks
958 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
961 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
962 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
963 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
964 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
965 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
966 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
968 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
969 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
970 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
972 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
973 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
975 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
976 * rows, which changed the alignment requirements and fence programming.
978 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
980 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
981 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
982 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
983 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
984 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
985 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
986 /* dsparb controlled by hw only */
987 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
989 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
990 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
991 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
993 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
994 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
996 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
997 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
998 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1000 #include "i915_trace.h"
1002 extern struct drm_ioctl_desc i915_ioctls[];
1003 extern int i915_max_ioctl;
1004 extern unsigned int i915_fbpercrtc __always_unused;
1005 extern int i915_panel_ignore_lid __read_mostly;
1006 extern unsigned int i915_powersave __read_mostly;
1007 extern int i915_semaphores __read_mostly;
1008 extern unsigned int i915_lvds_downclock __read_mostly;
1009 extern int i915_panel_use_ssc __read_mostly;
1010 extern int i915_vbt_sdvo_panel_type __read_mostly;
1011 extern int i915_enable_rc6 __read_mostly;
1012 extern int i915_enable_fbc __read_mostly;
1013 extern bool i915_enable_hangcheck __read_mostly;
1015 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1016 extern int i915_resume(struct drm_device *dev);
1017 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1018 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1021 extern void i915_kernel_lost_context(struct drm_device * dev);
1022 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1023 extern int i915_driver_unload(struct drm_device *);
1024 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1025 extern void i915_driver_lastclose(struct drm_device * dev);
1026 extern void i915_driver_preclose(struct drm_device *dev,
1027 struct drm_file *file_priv);
1028 extern void i915_driver_postclose(struct drm_device *dev,
1029 struct drm_file *file_priv);
1030 extern int i915_driver_device_is_agp(struct drm_device * dev);
1031 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1033 extern int i915_emit_box(struct drm_device *dev,
1034 struct drm_clip_rect *box,
1036 extern int i915_reset(struct drm_device *dev, u8 flags);
1037 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1038 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1039 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1040 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1044 void i915_hangcheck_elapsed(unsigned long data);
1045 void i915_handle_error(struct drm_device *dev, bool wedged);
1046 extern int i915_irq_emit(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1048 extern int i915_irq_wait(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv);
1051 extern void intel_irq_init(struct drm_device *dev);
1053 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv);
1055 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1056 struct drm_file *file_priv);
1057 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1058 struct drm_file *file_priv);
1061 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1064 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1066 void intel_enable_asle(struct drm_device *dev);
1068 #ifdef CONFIG_DEBUG_FS
1069 extern void i915_destroy_error_state(struct drm_device *dev);
1071 #define i915_destroy_error_state(x)
1076 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078 extern int i915_mem_free(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv);
1080 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1084 extern void i915_mem_takedown(struct mem_block **heap);
1085 extern void i915_mem_release(struct drm_device * dev,
1086 struct drm_file *file_priv, struct mem_block *heap);
1088 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv);
1096 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv);
1098 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv);
1102 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv);
1104 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1105 struct drm_file *file_priv);
1106 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv);
1108 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1109 struct drm_file *file_priv);
1110 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1111 struct drm_file *file_priv);
1112 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv);
1114 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv);
1116 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1117 struct drm_file *file_priv);
1118 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv);
1120 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1121 struct drm_file *file_priv);
1122 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1123 struct drm_file *file_priv);
1124 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1125 struct drm_file *file_priv);
1126 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128 void i915_gem_load(struct drm_device *dev);
1129 int i915_gem_init_object(struct drm_gem_object *obj);
1130 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1131 uint32_t invalidate_domains,
1132 uint32_t flush_domains);
1133 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1135 void i915_gem_free_object(struct drm_gem_object *obj);
1136 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1138 bool map_and_fenceable);
1139 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1140 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1141 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1142 void i915_gem_lastclose(struct drm_device *dev);
1144 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1145 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1146 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1147 struct intel_ring_buffer *ring,
1150 int i915_gem_dumb_create(struct drm_file *file_priv,
1151 struct drm_device *dev,
1152 struct drm_mode_create_dumb *args);
1153 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1154 uint32_t handle, uint64_t *offset);
1155 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1158 * Returns true if seq1 is later than seq2.
1161 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1163 return (int32_t)(seq1 - seq2) >= 0;
1167 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1169 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1170 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1173 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1174 struct intel_ring_buffer *pipelined);
1175 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1177 void i915_gem_retire_requests(struct drm_device *dev);
1178 void i915_gem_reset(struct drm_device *dev);
1179 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1180 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1181 uint32_t read_domains,
1182 uint32_t write_domain);
1183 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1184 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1185 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1186 void i915_gem_do_init(struct drm_device *dev,
1187 unsigned long start,
1188 unsigned long mappable_end,
1190 int __must_check i915_gpu_idle(struct drm_device *dev);
1191 int __must_check i915_gem_idle(struct drm_device *dev);
1192 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1193 struct drm_file *file,
1194 struct drm_i915_gem_request *request);
1195 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1197 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1199 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1202 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1204 struct intel_ring_buffer *pipelined);
1205 int i915_gem_attach_phys_object(struct drm_device *dev,
1206 struct drm_i915_gem_object *obj,
1209 void i915_gem_detach_phys_object(struct drm_device *dev,
1210 struct drm_i915_gem_object *obj);
1211 void i915_gem_free_all_phys_object(struct drm_device *dev);
1212 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1215 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1219 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1220 enum i915_cache_level cache_level);
1222 /* i915_gem_gtt.c */
1223 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1224 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1225 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1226 enum i915_cache_level cache_level);
1227 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1229 /* i915_gem_evict.c */
1230 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1231 unsigned alignment, bool mappable);
1232 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1233 bool purgeable_only);
1234 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1235 bool purgeable_only);
1237 /* i915_gem_tiling.c */
1238 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1239 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1240 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1242 /* i915_gem_debug.c */
1243 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1244 const char *where, uint32_t mark);
1246 int i915_verify_lists(struct drm_device *dev);
1248 #define i915_verify_lists(dev) 0
1250 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1252 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1253 const char *where, uint32_t mark);
1255 /* i915_debugfs.c */
1256 int i915_debugfs_init(struct drm_minor *minor);
1257 void i915_debugfs_cleanup(struct drm_minor *minor);
1259 /* i915_suspend.c */
1260 extern int i915_save_state(struct drm_device *dev);
1261 extern int i915_restore_state(struct drm_device *dev);
1263 /* i915_suspend.c */
1264 extern int i915_save_state(struct drm_device *dev);
1265 extern int i915_restore_state(struct drm_device *dev);
1268 extern int intel_setup_gmbus(struct drm_device *dev);
1269 extern void intel_teardown_gmbus(struct drm_device *dev);
1270 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1271 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1272 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1274 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1276 extern void intel_i2c_reset(struct drm_device *dev);
1278 /* intel_opregion.c */
1279 extern int intel_opregion_setup(struct drm_device *dev);
1281 extern void intel_opregion_init(struct drm_device *dev);
1282 extern void intel_opregion_fini(struct drm_device *dev);
1283 extern void intel_opregion_asle_intr(struct drm_device *dev);
1284 extern void intel_opregion_gse_intr(struct drm_device *dev);
1285 extern void intel_opregion_enable_asle(struct drm_device *dev);
1287 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1288 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1289 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1290 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1291 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1296 extern void intel_register_dsm_handler(void);
1297 extern void intel_unregister_dsm_handler(void);
1299 static inline void intel_register_dsm_handler(void) { return; }
1300 static inline void intel_unregister_dsm_handler(void) { return; }
1301 #endif /* CONFIG_ACPI */
1304 extern void intel_modeset_init(struct drm_device *dev);
1305 extern void intel_modeset_gem_init(struct drm_device *dev);
1306 extern void intel_modeset_cleanup(struct drm_device *dev);
1307 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1308 extern bool intel_fbc_enabled(struct drm_device *dev);
1309 extern void intel_disable_fbc(struct drm_device *dev);
1310 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1311 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1312 extern void ironlake_enable_rc6(struct drm_device *dev);
1313 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1314 extern void intel_detect_pch(struct drm_device *dev);
1315 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1317 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1318 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1319 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1320 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1323 #ifdef CONFIG_DEBUG_FS
1324 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1325 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1327 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1328 extern void intel_display_print_error_state(struct seq_file *m,
1329 struct drm_device *dev,
1330 struct intel_display_error_state *error);
1333 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1335 #define BEGIN_LP_RING(n) \
1336 intel_ring_begin(LP_RING(dev_priv), (n))
1338 #define OUT_RING(x) \
1339 intel_ring_emit(LP_RING(dev_priv), x)
1341 #define ADVANCE_LP_RING() \
1342 intel_ring_advance(LP_RING(dev_priv))
1345 * Lock test for when it's just for synchronization of ring access.
1347 * In that case, we don't need to do it when GEM is initialized as nobody else
1348 * has access to the ring.
1350 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1351 if (LP_RING(dev->dev_private)->obj == NULL) \
1352 LOCK_TEST_WITH_RETURN(dev, file); \
1355 /* On SNB platform, before reading ring registers forcewake bit
1356 * must be set to prevent GT core from power down and stale values being
1359 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1360 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1361 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1363 /* We give fast paths for the really cool registers */
1364 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1365 (((dev_priv)->info->gen >= 6) && \
1366 ((reg) < 0x40000) && \
1367 ((reg) != FORCEWAKE))
1369 #define __i915_read(x, y) \
1370 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1378 #define __i915_write(x, y) \
1379 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1387 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1388 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1390 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1391 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1392 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1393 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1395 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1396 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1397 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1398 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1400 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1401 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1403 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1404 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)