2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static int i915_gem_phys_pwrite(struct drm_device *dev,
51 struct drm_i915_gem_object *obj,
52 struct drm_i915_gem_pwrite *args,
53 struct drm_file *file);
55 static void i915_gem_write_fence(struct drm_device *dev, int reg,
56 struct drm_i915_gem_object *obj);
57 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
58 struct drm_i915_fence_reg *fence,
61 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
62 struct shrink_control *sc);
63 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
64 struct shrink_control *sc);
65 static int i915_gem_shrinker_oom(struct notifier_block *nb,
68 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
69 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
71 static bool cpu_cache_is_coherent(struct drm_device *dev,
72 enum i915_cache_level level)
74 return HAS_LLC(dev) || level != I915_CACHE_NONE;
77 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
79 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
82 return obj->pin_display;
85 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
88 i915_gem_release_mmap(obj);
90 /* As we do not have an associated fence register, we will force
91 * a tiling change if we ever need to acquire one.
93 obj->fence_dirty = false;
94 obj->fence_reg = I915_FENCE_REG_NONE;
97 /* some bookkeeping */
98 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
101 spin_lock(&dev_priv->mm.object_stat_lock);
102 dev_priv->mm.object_count++;
103 dev_priv->mm.object_memory += size;
104 spin_unlock(&dev_priv->mm.object_stat_lock);
107 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
110 spin_lock(&dev_priv->mm.object_stat_lock);
111 dev_priv->mm.object_count--;
112 dev_priv->mm.object_memory -= size;
113 spin_unlock(&dev_priv->mm.object_stat_lock);
117 i915_gem_wait_for_error(struct i915_gpu_error *error)
121 #define EXIT_COND (!i915_reset_in_progress(error) || \
122 i915_terminally_wedged(error))
127 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
128 * userspace. If it takes that long something really bad is going on and
129 * we should simply try to bail out and fail as gracefully as possible.
131 ret = wait_event_interruptible_timeout(error->reset_queue,
135 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
137 } else if (ret < 0) {
145 int i915_mutex_lock_interruptible(struct drm_device *dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
158 WARN_ON(i915_verify_lists(dev));
163 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
165 return i915_gem_obj_bound_any(obj) && !obj->active;
169 i915_gem_init_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_init *args = data;
175 if (drm_core_check_feature(dev, DRIVER_MODESET))
178 if (args->gtt_start >= args->gtt_end ||
179 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
182 /* GEM with user mode setting was never supported on ilk and later. */
183 if (INTEL_INFO(dev)->gen >= 5)
186 mutex_lock(&dev->struct_mutex);
187 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
189 dev_priv->gtt.mappable_end = args->gtt_end;
190 mutex_unlock(&dev->struct_mutex);
196 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_i915_gem_get_aperture *args = data;
201 struct drm_i915_gem_object *obj;
205 mutex_lock(&dev->struct_mutex);
206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
207 if (i915_gem_obj_is_pinned(obj))
208 pinned += i915_gem_obj_ggtt_size(obj);
209 mutex_unlock(&dev->struct_mutex);
211 args->aper_size = dev_priv->gtt.base.total;
212 args->aper_available_size = args->aper_size - pinned;
217 void *i915_gem_object_alloc(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
223 void i915_gem_object_free(struct drm_i915_gem_object *obj)
225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
226 kmem_cache_free(dev_priv->slab, obj);
230 i915_gem_create(struct drm_file *file,
231 struct drm_device *dev,
235 struct drm_i915_gem_object *obj;
239 size = roundup(size, PAGE_SIZE);
243 /* Allocate the new object */
244 obj = i915_gem_alloc_object(dev, size);
248 ret = drm_gem_handle_create(file, &obj->base, &handle);
249 /* drop reference from allocate - handle holds it now */
250 drm_gem_object_unreference_unlocked(&obj->base);
259 i915_gem_dumb_create(struct drm_file *file,
260 struct drm_device *dev,
261 struct drm_mode_create_dumb *args)
263 /* have to work out size/pitch and return them */
264 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
265 args->size = args->pitch * args->height;
266 return i915_gem_create(file, dev,
267 args->size, &args->handle);
271 * Creates a new mm object and returns a handle to it.
274 i915_gem_create_ioctl(struct drm_device *dev, void *data,
275 struct drm_file *file)
277 struct drm_i915_gem_create *args = data;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
284 __copy_to_user_swizzled(char __user *cpu_vaddr,
285 const char *gpu_vaddr, int gpu_offset,
288 int ret, cpu_offset = 0;
291 int cacheline_end = ALIGN(gpu_offset + 1, 64);
292 int this_length = min(cacheline_end - gpu_offset, length);
293 int swizzled_gpu_offset = gpu_offset ^ 64;
295 ret = __copy_to_user(cpu_vaddr + cpu_offset,
296 gpu_vaddr + swizzled_gpu_offset,
301 cpu_offset += this_length;
302 gpu_offset += this_length;
303 length -= this_length;
310 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
311 const char __user *cpu_vaddr,
314 int ret, cpu_offset = 0;
317 int cacheline_end = ALIGN(gpu_offset + 1, 64);
318 int this_length = min(cacheline_end - gpu_offset, length);
319 int swizzled_gpu_offset = gpu_offset ^ 64;
321 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
322 cpu_vaddr + cpu_offset,
327 cpu_offset += this_length;
328 gpu_offset += this_length;
329 length -= this_length;
336 * Pins the specified object's pages and synchronizes the object with
337 * GPU accesses. Sets needs_clflush to non-zero if the caller should
338 * flush the object from the CPU cache.
340 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
350 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
351 /* If we're not in the cpu read domain, set ourself into the gtt
352 * read domain and manually flush cachelines (if required). This
353 * optimizes for the case when the gpu will dirty the data
354 * anyway again before the next pread happens. */
355 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
357 ret = i915_gem_object_wait_rendering(obj, true);
361 i915_gem_object_retire(obj);
364 ret = i915_gem_object_get_pages(obj);
368 i915_gem_object_pin_pages(obj);
373 /* Per-page copy function for the shmem pread fastpath.
374 * Flushes invalid cachelines before reading the target if
375 * needs_clflush is set. */
377 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
378 char __user *user_data,
379 bool page_do_bit17_swizzling, bool needs_clflush)
384 if (unlikely(page_do_bit17_swizzling))
387 vaddr = kmap_atomic(page);
389 drm_clflush_virt_range(vaddr + shmem_page_offset,
391 ret = __copy_to_user_inatomic(user_data,
392 vaddr + shmem_page_offset,
394 kunmap_atomic(vaddr);
396 return ret ? -EFAULT : 0;
400 shmem_clflush_swizzled_range(char *addr, unsigned long length,
403 if (unlikely(swizzled)) {
404 unsigned long start = (unsigned long) addr;
405 unsigned long end = (unsigned long) addr + length;
407 /* For swizzling simply ensure that we always flush both
408 * channels. Lame, but simple and it works. Swizzled
409 * pwrite/pread is far from a hotpath - current userspace
410 * doesn't use it at all. */
411 start = round_down(start, 128);
412 end = round_up(end, 128);
414 drm_clflush_virt_range((void *)start, end - start);
416 drm_clflush_virt_range(addr, length);
421 /* Only difference to the fast-path function is that this can handle bit17
422 * and uses non-atomic copy and kmap functions. */
424 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
425 char __user *user_data,
426 bool page_do_bit17_swizzling, bool needs_clflush)
433 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
435 page_do_bit17_swizzling);
437 if (page_do_bit17_swizzling)
438 ret = __copy_to_user_swizzled(user_data,
439 vaddr, shmem_page_offset,
442 ret = __copy_to_user(user_data,
443 vaddr + shmem_page_offset,
447 return ret ? - EFAULT : 0;
451 i915_gem_shmem_pread(struct drm_device *dev,
452 struct drm_i915_gem_object *obj,
453 struct drm_i915_gem_pread *args,
454 struct drm_file *file)
456 char __user *user_data;
459 int shmem_page_offset, page_length, ret = 0;
460 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
462 int needs_clflush = 0;
463 struct sg_page_iter sg_iter;
465 user_data = to_user_ptr(args->data_ptr);
468 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
470 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
474 offset = args->offset;
476 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
477 offset >> PAGE_SHIFT) {
478 struct page *page = sg_page_iter_page(&sg_iter);
483 /* Operation in this page
485 * shmem_page_offset = offset within page in shmem file
486 * page_length = bytes to copy for this page
488 shmem_page_offset = offset_in_page(offset);
489 page_length = remain;
490 if ((shmem_page_offset + page_length) > PAGE_SIZE)
491 page_length = PAGE_SIZE - shmem_page_offset;
493 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
494 (page_to_phys(page) & (1 << 17)) != 0;
496 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
497 user_data, page_do_bit17_swizzling,
502 mutex_unlock(&dev->struct_mutex);
504 if (likely(!i915.prefault_disable) && !prefaulted) {
505 ret = fault_in_multipages_writeable(user_data, remain);
506 /* Userspace is tricking us, but we've already clobbered
507 * its pages with the prefault and promised to write the
508 * data up to the first fault. Hence ignore any errors
509 * and just continue. */
514 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
515 user_data, page_do_bit17_swizzling,
518 mutex_lock(&dev->struct_mutex);
524 remain -= page_length;
525 user_data += page_length;
526 offset += page_length;
530 i915_gem_object_unpin_pages(obj);
536 * Reads data from the object referenced by handle.
538 * On error, the contents of *data are undefined.
541 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
542 struct drm_file *file)
544 struct drm_i915_gem_pread *args = data;
545 struct drm_i915_gem_object *obj;
551 if (!access_ok(VERIFY_WRITE,
552 to_user_ptr(args->data_ptr),
556 ret = i915_mutex_lock_interruptible(dev);
560 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
561 if (&obj->base == NULL) {
566 /* Bounds check source. */
567 if (args->offset > obj->base.size ||
568 args->size > obj->base.size - args->offset) {
573 /* prime objects have no backing filp to GEM pread/pwrite
576 if (!obj->base.filp) {
581 trace_i915_gem_object_pread(obj, args->offset, args->size);
583 ret = i915_gem_shmem_pread(dev, obj, args, file);
586 drm_gem_object_unreference(&obj->base);
588 mutex_unlock(&dev->struct_mutex);
592 /* This is the fast write path which cannot handle
593 * page faults in the source data
597 fast_user_write(struct io_mapping *mapping,
598 loff_t page_base, int page_offset,
599 char __user *user_data,
602 void __iomem *vaddr_atomic;
604 unsigned long unwritten;
606 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
607 /* We can use the cpu mem copy function because this is X86. */
608 vaddr = (void __force*)vaddr_atomic + page_offset;
609 unwritten = __copy_from_user_inatomic_nocache(vaddr,
611 io_mapping_unmap_atomic(vaddr_atomic);
616 * This is the fast pwrite path, where we copy the data directly from the
617 * user into the GTT, uncached.
620 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
621 struct drm_i915_gem_object *obj,
622 struct drm_i915_gem_pwrite *args,
623 struct drm_file *file)
625 struct drm_i915_private *dev_priv = dev->dev_private;
627 loff_t offset, page_base;
628 char __user *user_data;
629 int page_offset, page_length, ret;
631 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
635 ret = i915_gem_object_set_to_gtt_domain(obj, true);
639 ret = i915_gem_object_put_fence(obj);
643 user_data = to_user_ptr(args->data_ptr);
646 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
649 /* Operation in this page
651 * page_base = page offset within aperture
652 * page_offset = offset within page
653 * page_length = bytes to copy for this page
655 page_base = offset & PAGE_MASK;
656 page_offset = offset_in_page(offset);
657 page_length = remain;
658 if ((page_offset + remain) > PAGE_SIZE)
659 page_length = PAGE_SIZE - page_offset;
661 /* If we get a fault while copying data, then (presumably) our
662 * source page isn't available. Return the error and we'll
663 * retry in the slow path.
665 if (fast_user_write(dev_priv->gtt.mappable, page_base,
666 page_offset, user_data, page_length)) {
671 remain -= page_length;
672 user_data += page_length;
673 offset += page_length;
677 i915_gem_object_ggtt_unpin(obj);
682 /* Per-page copy function for the shmem pwrite fastpath.
683 * Flushes invalid cachelines before writing to the target if
684 * needs_clflush_before is set and flushes out any written cachelines after
685 * writing if needs_clflush is set. */
687 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
688 char __user *user_data,
689 bool page_do_bit17_swizzling,
690 bool needs_clflush_before,
691 bool needs_clflush_after)
696 if (unlikely(page_do_bit17_swizzling))
699 vaddr = kmap_atomic(page);
700 if (needs_clflush_before)
701 drm_clflush_virt_range(vaddr + shmem_page_offset,
703 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
704 user_data, page_length);
705 if (needs_clflush_after)
706 drm_clflush_virt_range(vaddr + shmem_page_offset,
708 kunmap_atomic(vaddr);
710 return ret ? -EFAULT : 0;
713 /* Only difference to the fast-path function is that this can handle bit17
714 * and uses non-atomic copy and kmap functions. */
716 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
717 char __user *user_data,
718 bool page_do_bit17_swizzling,
719 bool needs_clflush_before,
720 bool needs_clflush_after)
726 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
727 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
729 page_do_bit17_swizzling);
730 if (page_do_bit17_swizzling)
731 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
735 ret = __copy_from_user(vaddr + shmem_page_offset,
738 if (needs_clflush_after)
739 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
741 page_do_bit17_swizzling);
744 return ret ? -EFAULT : 0;
748 i915_gem_shmem_pwrite(struct drm_device *dev,
749 struct drm_i915_gem_object *obj,
750 struct drm_i915_gem_pwrite *args,
751 struct drm_file *file)
755 char __user *user_data;
756 int shmem_page_offset, page_length, ret = 0;
757 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
758 int hit_slowpath = 0;
759 int needs_clflush_after = 0;
760 int needs_clflush_before = 0;
761 struct sg_page_iter sg_iter;
763 user_data = to_user_ptr(args->data_ptr);
766 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
768 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
769 /* If we're not in the cpu write domain, set ourself into the gtt
770 * write domain and manually flush cachelines (if required). This
771 * optimizes for the case when the gpu will use the data
772 * right away and we therefore have to clflush anyway. */
773 needs_clflush_after = cpu_write_needs_clflush(obj);
774 ret = i915_gem_object_wait_rendering(obj, false);
778 i915_gem_object_retire(obj);
780 /* Same trick applies to invalidate partially written cachelines read
782 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
783 needs_clflush_before =
784 !cpu_cache_is_coherent(dev, obj->cache_level);
786 ret = i915_gem_object_get_pages(obj);
790 i915_gem_object_pin_pages(obj);
792 offset = args->offset;
795 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
796 offset >> PAGE_SHIFT) {
797 struct page *page = sg_page_iter_page(&sg_iter);
798 int partial_cacheline_write;
803 /* Operation in this page
805 * shmem_page_offset = offset within page in shmem file
806 * page_length = bytes to copy for this page
808 shmem_page_offset = offset_in_page(offset);
810 page_length = remain;
811 if ((shmem_page_offset + page_length) > PAGE_SIZE)
812 page_length = PAGE_SIZE - shmem_page_offset;
814 /* If we don't overwrite a cacheline completely we need to be
815 * careful to have up-to-date data by first clflushing. Don't
816 * overcomplicate things and flush the entire patch. */
817 partial_cacheline_write = needs_clflush_before &&
818 ((shmem_page_offset | page_length)
819 & (boot_cpu_data.x86_clflush_size - 1));
821 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
822 (page_to_phys(page) & (1 << 17)) != 0;
824 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
825 user_data, page_do_bit17_swizzling,
826 partial_cacheline_write,
827 needs_clflush_after);
832 mutex_unlock(&dev->struct_mutex);
833 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
834 user_data, page_do_bit17_swizzling,
835 partial_cacheline_write,
836 needs_clflush_after);
838 mutex_lock(&dev->struct_mutex);
844 remain -= page_length;
845 user_data += page_length;
846 offset += page_length;
850 i915_gem_object_unpin_pages(obj);
854 * Fixup: Flush cpu caches in case we didn't flush the dirty
855 * cachelines in-line while writing and the object moved
856 * out of the cpu write domain while we've dropped the lock.
858 if (!needs_clflush_after &&
859 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
860 if (i915_gem_clflush_object(obj, obj->pin_display))
861 i915_gem_chipset_flush(dev);
865 if (needs_clflush_after)
866 i915_gem_chipset_flush(dev);
872 * Writes data to the object referenced by handle.
874 * On error, the contents of the buffer that were to be modified are undefined.
877 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file)
880 struct drm_i915_gem_pwrite *args = data;
881 struct drm_i915_gem_object *obj;
887 if (!access_ok(VERIFY_READ,
888 to_user_ptr(args->data_ptr),
892 if (likely(!i915.prefault_disable)) {
893 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
899 ret = i915_mutex_lock_interruptible(dev);
903 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
904 if (&obj->base == NULL) {
909 /* Bounds check destination. */
910 if (args->offset > obj->base.size ||
911 args->size > obj->base.size - args->offset) {
916 /* prime objects have no backing filp to GEM pread/pwrite
919 if (!obj->base.filp) {
924 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
927 /* We can only do the GTT pwrite on untiled buffers, as otherwise
928 * it would end up going through the fenced access, and we'll get
929 * different detiling behavior between reading and writing.
930 * pread/pwrite currently are reading and writing from the CPU
931 * perspective, requiring manual detiling by the client.
934 ret = i915_gem_phys_pwrite(dev, obj, args, file);
938 if (obj->tiling_mode == I915_TILING_NONE &&
939 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
940 cpu_write_needs_clflush(obj)) {
941 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
942 /* Note that the gtt paths might fail with non-page-backed user
943 * pointers (e.g. gtt mappings when moving data between
944 * textures). Fallback to the shmem path in that case. */
947 if (ret == -EFAULT || ret == -ENOSPC)
948 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
951 drm_gem_object_unreference(&obj->base);
953 mutex_unlock(&dev->struct_mutex);
958 i915_gem_check_wedge(struct i915_gpu_error *error,
961 if (i915_reset_in_progress(error)) {
962 /* Non-interruptible callers can't handle -EAGAIN, hence return
963 * -EIO unconditionally for these. */
967 /* Recovery complete, but the reset failed ... */
968 if (i915_terminally_wedged(error))
978 * Compare seqno against outstanding lazy request. Emit a request if they are
982 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
986 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
989 if (seqno == ring->outstanding_lazy_seqno)
990 ret = i915_add_request(ring, NULL);
995 static void fake_irq(unsigned long data)
997 wake_up_process((struct task_struct *)data);
1000 static bool missed_irq(struct drm_i915_private *dev_priv,
1001 struct intel_engine_cs *ring)
1003 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1006 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1008 if (file_priv == NULL)
1011 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1015 * __wait_seqno - wait until execution of seqno has finished
1016 * @ring: the ring expected to report seqno
1018 * @reset_counter: reset sequence associated with the given seqno
1019 * @interruptible: do an interruptible wait (normally yes)
1020 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1022 * Note: It is of utmost importance that the passed in seqno and reset_counter
1023 * values have been read by the caller in an smp safe manner. Where read-side
1024 * locks are involved, it is sufficient to read the reset_counter before
1025 * unlocking the lock that protects the seqno. For lockless tricks, the
1026 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1029 * Returns 0 if the seqno was found within the alloted time. Else returns the
1030 * errno with remaining time filled in timeout argument.
1032 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1033 unsigned reset_counter,
1035 struct timespec *timeout,
1036 struct drm_i915_file_private *file_priv)
1038 struct drm_device *dev = ring->dev;
1039 struct drm_i915_private *dev_priv = dev->dev_private;
1040 const bool irq_test_in_progress =
1041 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1042 struct timespec before, now;
1044 unsigned long timeout_expire;
1047 WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1049 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1052 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1054 if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1055 gen6_rps_boost(dev_priv);
1057 mod_delayed_work(dev_priv->wq,
1058 &file_priv->mm.idle_work,
1059 msecs_to_jiffies(100));
1062 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1065 /* Record current time in case interrupted by signal, or wedged */
1066 trace_i915_gem_request_wait_begin(ring, seqno);
1067 getrawmonotonic(&before);
1069 struct timer_list timer;
1071 prepare_to_wait(&ring->irq_queue, &wait,
1072 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1074 /* We need to check whether any gpu reset happened in between
1075 * the caller grabbing the seqno and now ... */
1076 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1077 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1078 * is truely gone. */
1079 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1085 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1090 if (interruptible && signal_pending(current)) {
1095 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1100 timer.function = NULL;
1101 if (timeout || missed_irq(dev_priv, ring)) {
1102 unsigned long expire;
1104 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1105 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1106 mod_timer(&timer, expire);
1111 if (timer.function) {
1112 del_singleshot_timer_sync(&timer);
1113 destroy_timer_on_stack(&timer);
1116 getrawmonotonic(&now);
1117 trace_i915_gem_request_wait_end(ring, seqno);
1119 if (!irq_test_in_progress)
1120 ring->irq_put(ring);
1122 finish_wait(&ring->irq_queue, &wait);
1125 struct timespec sleep_time = timespec_sub(now, before);
1126 *timeout = timespec_sub(*timeout, sleep_time);
1127 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1128 set_normalized_timespec(timeout, 0, 0);
1135 * Waits for a sequence number to be signaled, and cleans up the
1136 * request and object lists appropriately for that event.
1139 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1141 struct drm_device *dev = ring->dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 bool interruptible = dev_priv->mm.interruptible;
1146 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1149 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1153 ret = i915_gem_check_olr(ring, seqno);
1157 return __wait_seqno(ring, seqno,
1158 atomic_read(&dev_priv->gpu_error.reset_counter),
1159 interruptible, NULL, NULL);
1163 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1164 struct intel_engine_cs *ring)
1169 /* Manually manage the write flush as we may have not yet
1170 * retired the buffer.
1172 * Note that the last_write_seqno is always the earlier of
1173 * the two (read/write) seqno, so if we haved successfully waited,
1174 * we know we have passed the last write.
1176 obj->last_write_seqno = 0;
1182 * Ensures that all rendering to the object has completed and the object is
1183 * safe to unbind from the GTT or access from the CPU.
1185 static __must_check int
1186 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1189 struct intel_engine_cs *ring = obj->ring;
1193 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1197 ret = i915_wait_seqno(ring, seqno);
1201 return i915_gem_object_wait_rendering__tail(obj, ring);
1204 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1205 * as the object state may change during this call.
1207 static __must_check int
1208 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1209 struct drm_i915_file_private *file_priv,
1212 struct drm_device *dev = obj->base.dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 struct intel_engine_cs *ring = obj->ring;
1215 unsigned reset_counter;
1219 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1220 BUG_ON(!dev_priv->mm.interruptible);
1222 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1226 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1230 ret = i915_gem_check_olr(ring, seqno);
1234 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1235 mutex_unlock(&dev->struct_mutex);
1236 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1237 mutex_lock(&dev->struct_mutex);
1241 return i915_gem_object_wait_rendering__tail(obj, ring);
1245 * Called when user space prepares to use an object with the CPU, either
1246 * through the mmap ioctl's mapping or a GTT mapping.
1249 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1250 struct drm_file *file)
1252 struct drm_i915_gem_set_domain *args = data;
1253 struct drm_i915_gem_object *obj;
1254 uint32_t read_domains = args->read_domains;
1255 uint32_t write_domain = args->write_domain;
1258 /* Only handle setting domains to types used by the CPU. */
1259 if (write_domain & I915_GEM_GPU_DOMAINS)
1262 if (read_domains & I915_GEM_GPU_DOMAINS)
1265 /* Having something in the write domain implies it's in the read
1266 * domain, and only that read domain. Enforce that in the request.
1268 if (write_domain != 0 && read_domains != write_domain)
1271 ret = i915_mutex_lock_interruptible(dev);
1275 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1276 if (&obj->base == NULL) {
1281 /* Try to flush the object off the GPU without holding the lock.
1282 * We will repeat the flush holding the lock in the normal manner
1283 * to catch cases where we are gazumped.
1285 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1291 if (read_domains & I915_GEM_DOMAIN_GTT) {
1292 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1294 /* Silently promote "you're not bound, there was nothing to do"
1295 * to success, since the client was just asking us to
1296 * make sure everything was done.
1301 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1305 drm_gem_object_unreference(&obj->base);
1307 mutex_unlock(&dev->struct_mutex);
1312 * Called when user space has done writes to this buffer
1315 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *file)
1318 struct drm_i915_gem_sw_finish *args = data;
1319 struct drm_i915_gem_object *obj;
1322 ret = i915_mutex_lock_interruptible(dev);
1326 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1327 if (&obj->base == NULL) {
1332 /* Pinned buffers may be scanout, so flush the cache */
1333 if (obj->pin_display)
1334 i915_gem_object_flush_cpu_write_domain(obj, true);
1336 drm_gem_object_unreference(&obj->base);
1338 mutex_unlock(&dev->struct_mutex);
1343 * Maps the contents of an object, returning the address it is mapped
1346 * While the mapping holds a reference on the contents of the object, it doesn't
1347 * imply a ref on the object itself.
1350 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1351 struct drm_file *file)
1353 struct drm_i915_gem_mmap *args = data;
1354 struct drm_gem_object *obj;
1357 obj = drm_gem_object_lookup(dev, file, args->handle);
1361 /* prime objects have no backing filp to GEM mmap
1365 drm_gem_object_unreference_unlocked(obj);
1369 addr = vm_mmap(obj->filp, 0, args->size,
1370 PROT_READ | PROT_WRITE, MAP_SHARED,
1372 drm_gem_object_unreference_unlocked(obj);
1373 if (IS_ERR((void *)addr))
1376 args->addr_ptr = (uint64_t) addr;
1382 * i915_gem_fault - fault a page into the GTT
1383 * vma: VMA in question
1386 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1387 * from userspace. The fault handler takes care of binding the object to
1388 * the GTT (if needed), allocating and programming a fence register (again,
1389 * only if needed based on whether the old reg is still valid or the object
1390 * is tiled) and inserting a new PTE into the faulting process.
1392 * Note that the faulting process may involve evicting existing objects
1393 * from the GTT and/or fence registers to make room. So performance may
1394 * suffer if the GTT working set is large or there are few fence registers
1397 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1399 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1400 struct drm_device *dev = obj->base.dev;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 pgoff_t page_offset;
1405 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1407 intel_runtime_pm_get(dev_priv);
1409 /* We don't use vmf->pgoff since that has the fake offset */
1410 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1413 ret = i915_mutex_lock_interruptible(dev);
1417 trace_i915_gem_object_fault(obj, page_offset, true, write);
1419 /* Try to flush the object off the GPU first without holding the lock.
1420 * Upon reacquiring the lock, we will perform our sanity checks and then
1421 * repeat the flush holding the lock in the normal manner to catch cases
1422 * where we are gazumped.
1424 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1428 /* Access to snoopable pages through the GTT is incoherent. */
1429 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1434 /* Now bind it into the GTT if needed */
1435 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1439 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1443 ret = i915_gem_object_get_fence(obj);
1447 obj->fault_mappable = true;
1449 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1453 /* Finally, remap it using the new GTT offset */
1454 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1456 i915_gem_object_ggtt_unpin(obj);
1458 mutex_unlock(&dev->struct_mutex);
1462 /* If this -EIO is due to a gpu hang, give the reset code a
1463 * chance to clean up the mess. Otherwise return the proper
1465 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1466 ret = VM_FAULT_SIGBUS;
1471 * EAGAIN means the gpu is hung and we'll wait for the error
1472 * handler to reset everything when re-faulting in
1473 * i915_mutex_lock_interruptible.
1480 * EBUSY is ok: this just means that another thread
1481 * already did the job.
1483 ret = VM_FAULT_NOPAGE;
1490 ret = VM_FAULT_SIGBUS;
1493 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1494 ret = VM_FAULT_SIGBUS;
1498 intel_runtime_pm_put(dev_priv);
1502 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1504 struct i915_vma *vma;
1507 * Only the global gtt is relevant for gtt memory mappings, so restrict
1508 * list traversal to objects bound into the global address space. Note
1509 * that the active list should be empty, but better safe than sorry.
1511 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1512 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1513 i915_gem_release_mmap(vma->obj);
1514 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1515 i915_gem_release_mmap(vma->obj);
1519 * i915_gem_release_mmap - remove physical page mappings
1520 * @obj: obj in question
1522 * Preserve the reservation of the mmapping with the DRM core code, but
1523 * relinquish ownership of the pages back to the system.
1525 * It is vital that we remove the page mapping if we have mapped a tiled
1526 * object through the GTT and then lose the fence register due to
1527 * resource pressure. Similarly if the object has been moved out of the
1528 * aperture, than pages mapped into userspace must be revoked. Removing the
1529 * mapping will then trigger a page fault on the next user access, allowing
1530 * fixup by i915_gem_fault().
1533 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1535 if (!obj->fault_mappable)
1538 drm_vma_node_unmap(&obj->base.vma_node,
1539 obj->base.dev->anon_inode->i_mapping);
1540 obj->fault_mappable = false;
1544 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1548 if (INTEL_INFO(dev)->gen >= 4 ||
1549 tiling_mode == I915_TILING_NONE)
1552 /* Previous chips need a power-of-two fence region when tiling */
1553 if (INTEL_INFO(dev)->gen == 3)
1554 gtt_size = 1024*1024;
1556 gtt_size = 512*1024;
1558 while (gtt_size < size)
1565 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1566 * @obj: object to check
1568 * Return the required GTT alignment for an object, taking into account
1569 * potential fence register mapping.
1572 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1573 int tiling_mode, bool fenced)
1576 * Minimum alignment is 4k (GTT page size), but might be greater
1577 * if a fence register is needed for the object.
1579 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1580 tiling_mode == I915_TILING_NONE)
1584 * Previous chips need to be aligned to the size of the smallest
1585 * fence register that can contain the object.
1587 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1590 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1592 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1595 if (drm_vma_node_has_offset(&obj->base.vma_node))
1598 dev_priv->mm.shrinker_no_lock_stealing = true;
1600 ret = drm_gem_create_mmap_offset(&obj->base);
1604 /* Badly fragmented mmap space? The only way we can recover
1605 * space is by destroying unwanted objects. We can't randomly release
1606 * mmap_offsets as userspace expects them to be persistent for the
1607 * lifetime of the objects. The closest we can is to release the
1608 * offsets on purgeable objects by truncating it and marking it purged,
1609 * which prevents userspace from ever using that object again.
1611 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1612 ret = drm_gem_create_mmap_offset(&obj->base);
1616 i915_gem_shrink_all(dev_priv);
1617 ret = drm_gem_create_mmap_offset(&obj->base);
1619 dev_priv->mm.shrinker_no_lock_stealing = false;
1624 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1626 drm_gem_free_mmap_offset(&obj->base);
1630 i915_gem_mmap_gtt(struct drm_file *file,
1631 struct drm_device *dev,
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636 struct drm_i915_gem_object *obj;
1639 ret = i915_mutex_lock_interruptible(dev);
1643 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1644 if (&obj->base == NULL) {
1649 if (obj->base.size > dev_priv->gtt.mappable_end) {
1654 if (obj->madv != I915_MADV_WILLNEED) {
1655 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1660 ret = i915_gem_object_create_mmap_offset(obj);
1664 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1667 drm_gem_object_unreference(&obj->base);
1669 mutex_unlock(&dev->struct_mutex);
1674 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1676 * @data: GTT mapping ioctl data
1677 * @file: GEM object info
1679 * Simply returns the fake offset to userspace so it can mmap it.
1680 * The mmap call will end up in drm_gem_mmap(), which will set things
1681 * up so we can get faults in the handler above.
1683 * The fault handler will take care of binding the object into the GTT
1684 * (since it may have been evicted to make room for something), allocating
1685 * a fence register, and mapping the appropriate aperture address into
1689 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1690 struct drm_file *file)
1692 struct drm_i915_gem_mmap_gtt *args = data;
1694 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1698 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1700 return obj->madv == I915_MADV_DONTNEED;
1703 /* Immediately discard the backing storage */
1705 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1707 i915_gem_object_free_mmap_offset(obj);
1709 if (obj->base.filp == NULL)
1712 /* Our goal here is to return as much of the memory as
1713 * is possible back to the system as we are called from OOM.
1714 * To do this we must instruct the shmfs to drop all of its
1715 * backing pages, *now*.
1717 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1718 obj->madv = __I915_MADV_PURGED;
1721 /* Try to discard unwanted pages */
1723 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1725 struct address_space *mapping;
1727 switch (obj->madv) {
1728 case I915_MADV_DONTNEED:
1729 i915_gem_object_truncate(obj);
1730 case __I915_MADV_PURGED:
1734 if (obj->base.filp == NULL)
1737 mapping = file_inode(obj->base.filp)->i_mapping,
1738 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1742 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1744 struct sg_page_iter sg_iter;
1747 BUG_ON(obj->madv == __I915_MADV_PURGED);
1749 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1751 /* In the event of a disaster, abandon all caches and
1752 * hope for the best.
1754 WARN_ON(ret != -EIO);
1755 i915_gem_clflush_object(obj, true);
1756 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1759 if (i915_gem_object_needs_bit17_swizzle(obj))
1760 i915_gem_object_save_bit_17_swizzle(obj);
1762 if (obj->madv == I915_MADV_DONTNEED)
1765 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1766 struct page *page = sg_page_iter_page(&sg_iter);
1769 set_page_dirty(page);
1771 if (obj->madv == I915_MADV_WILLNEED)
1772 mark_page_accessed(page);
1774 page_cache_release(page);
1778 sg_free_table(obj->pages);
1783 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1785 const struct drm_i915_gem_object_ops *ops = obj->ops;
1787 if (obj->pages == NULL)
1790 if (obj->pages_pin_count)
1793 BUG_ON(i915_gem_obj_bound_any(obj));
1795 /* ->put_pages might need to allocate memory for the bit17 swizzle
1796 * array, hence protect them from being reaped by removing them from gtt
1798 list_del(&obj->global_list);
1800 ops->put_pages(obj);
1803 i915_gem_object_invalidate(obj);
1808 static unsigned long
1809 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1810 bool purgeable_only)
1812 struct list_head still_in_list;
1813 struct drm_i915_gem_object *obj;
1814 unsigned long count = 0;
1817 * As we may completely rewrite the (un)bound list whilst unbinding
1818 * (due to retiring requests) we have to strictly process only
1819 * one element of the list at the time, and recheck the list
1820 * on every iteration.
1822 * In particular, we must hold a reference whilst removing the
1823 * object as we may end up waiting for and/or retiring the objects.
1824 * This might release the final reference (held by the active list)
1825 * and result in the object being freed from under us. This is
1826 * similar to the precautions the eviction code must take whilst
1829 * Also note that although these lists do not hold a reference to
1830 * the object we can safely grab one here: The final object
1831 * unreferencing and the bound_list are both protected by the
1832 * dev->struct_mutex and so we won't ever be able to observe an
1833 * object on the bound_list with a reference count equals 0.
1835 INIT_LIST_HEAD(&still_in_list);
1836 while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1837 obj = list_first_entry(&dev_priv->mm.unbound_list,
1838 typeof(*obj), global_list);
1839 list_move_tail(&obj->global_list, &still_in_list);
1841 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1844 drm_gem_object_reference(&obj->base);
1846 if (i915_gem_object_put_pages(obj) == 0)
1847 count += obj->base.size >> PAGE_SHIFT;
1849 drm_gem_object_unreference(&obj->base);
1851 list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1853 INIT_LIST_HEAD(&still_in_list);
1854 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1855 struct i915_vma *vma, *v;
1857 obj = list_first_entry(&dev_priv->mm.bound_list,
1858 typeof(*obj), global_list);
1859 list_move_tail(&obj->global_list, &still_in_list);
1861 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1864 drm_gem_object_reference(&obj->base);
1866 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1867 if (i915_vma_unbind(vma))
1870 if (i915_gem_object_put_pages(obj) == 0)
1871 count += obj->base.size >> PAGE_SHIFT;
1873 drm_gem_object_unreference(&obj->base);
1875 list_splice(&still_in_list, &dev_priv->mm.bound_list);
1880 static unsigned long
1881 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1883 return __i915_gem_shrink(dev_priv, target, true);
1886 static unsigned long
1887 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1889 i915_gem_evict_everything(dev_priv->dev);
1890 return __i915_gem_shrink(dev_priv, LONG_MAX, false);
1894 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1896 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1898 struct address_space *mapping;
1899 struct sg_table *st;
1900 struct scatterlist *sg;
1901 struct sg_page_iter sg_iter;
1903 unsigned long last_pfn = 0; /* suppress gcc warning */
1906 /* Assert that the object is not currently in any GPU domain. As it
1907 * wasn't in the GTT, there shouldn't be any way it could have been in
1910 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1911 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1913 st = kmalloc(sizeof(*st), GFP_KERNEL);
1917 page_count = obj->base.size / PAGE_SIZE;
1918 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1923 /* Get the list of pages out of our struct file. They'll be pinned
1924 * at this point until we release them.
1926 * Fail silently without starting the shrinker
1928 mapping = file_inode(obj->base.filp)->i_mapping;
1929 gfp = mapping_gfp_mask(mapping);
1930 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1931 gfp &= ~(__GFP_IO | __GFP_WAIT);
1934 for (i = 0; i < page_count; i++) {
1935 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1937 i915_gem_purge(dev_priv, page_count);
1938 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1941 /* We've tried hard to allocate the memory by reaping
1942 * our own buffer, now let the real VM do its job and
1943 * go down in flames if truly OOM.
1945 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1946 gfp |= __GFP_IO | __GFP_WAIT;
1948 i915_gem_shrink_all(dev_priv);
1949 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1953 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1954 gfp &= ~(__GFP_IO | __GFP_WAIT);
1956 #ifdef CONFIG_SWIOTLB
1957 if (swiotlb_nr_tbl()) {
1959 sg_set_page(sg, page, PAGE_SIZE, 0);
1964 if (!i || page_to_pfn(page) != last_pfn + 1) {
1968 sg_set_page(sg, page, PAGE_SIZE, 0);
1970 sg->length += PAGE_SIZE;
1972 last_pfn = page_to_pfn(page);
1974 /* Check that the i965g/gm workaround works. */
1975 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1977 #ifdef CONFIG_SWIOTLB
1978 if (!swiotlb_nr_tbl())
1983 if (i915_gem_object_needs_bit17_swizzle(obj))
1984 i915_gem_object_do_bit_17_swizzle(obj);
1990 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1991 page_cache_release(sg_page_iter_page(&sg_iter));
1995 /* shmemfs first checks if there is enough memory to allocate the page
1996 * and reports ENOSPC should there be insufficient, along with the usual
1997 * ENOMEM for a genuine allocation failure.
1999 * We use ENOSPC in our driver to mean that we have run out of aperture
2000 * space and so want to translate the error from shmemfs back to our
2001 * usual understanding of ENOMEM.
2003 if (PTR_ERR(page) == -ENOSPC)
2006 return PTR_ERR(page);
2009 /* Ensure that the associated pages are gathered from the backing storage
2010 * and pinned into our object. i915_gem_object_get_pages() may be called
2011 * multiple times before they are released by a single call to
2012 * i915_gem_object_put_pages() - once the pages are no longer referenced
2013 * either as a result of memory pressure (reaping pages under the shrinker)
2014 * or as the object is itself released.
2017 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2019 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2020 const struct drm_i915_gem_object_ops *ops = obj->ops;
2026 if (obj->madv != I915_MADV_WILLNEED) {
2027 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2031 BUG_ON(obj->pages_pin_count);
2033 ret = ops->get_pages(obj);
2037 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2042 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2043 struct intel_engine_cs *ring)
2045 struct drm_device *dev = obj->base.dev;
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 u32 seqno = intel_ring_get_seqno(ring);
2049 BUG_ON(ring == NULL);
2050 if (obj->ring != ring && obj->last_write_seqno) {
2051 /* Keep the seqno relative to the current ring */
2052 obj->last_write_seqno = seqno;
2056 /* Add a reference if we're newly entering the active list. */
2058 drm_gem_object_reference(&obj->base);
2062 list_move_tail(&obj->ring_list, &ring->active_list);
2064 obj->last_read_seqno = seqno;
2066 if (obj->fenced_gpu_access) {
2067 obj->last_fenced_seqno = seqno;
2069 /* Bump MRU to take account of the delayed flush */
2070 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2071 struct drm_i915_fence_reg *reg;
2073 reg = &dev_priv->fence_regs[obj->fence_reg];
2074 list_move_tail(®->lru_list,
2075 &dev_priv->mm.fence_list);
2080 void i915_vma_move_to_active(struct i915_vma *vma,
2081 struct intel_engine_cs *ring)
2083 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2084 return i915_gem_object_move_to_active(vma->obj, ring);
2088 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2090 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2091 struct i915_address_space *vm;
2092 struct i915_vma *vma;
2094 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2095 BUG_ON(!obj->active);
2097 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2098 vma = i915_gem_obj_to_vma(obj, vm);
2099 if (vma && !list_empty(&vma->mm_list))
2100 list_move_tail(&vma->mm_list, &vm->inactive_list);
2103 list_del_init(&obj->ring_list);
2106 obj->last_read_seqno = 0;
2107 obj->last_write_seqno = 0;
2108 obj->base.write_domain = 0;
2110 obj->last_fenced_seqno = 0;
2111 obj->fenced_gpu_access = false;
2114 drm_gem_object_unreference(&obj->base);
2116 WARN_ON(i915_verify_lists(dev));
2120 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2122 struct intel_engine_cs *ring = obj->ring;
2127 if (i915_seqno_passed(ring->get_seqno(ring, true),
2128 obj->last_read_seqno))
2129 i915_gem_object_move_to_inactive(obj);
2133 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_engine_cs *ring;
2139 /* Carefully retire all requests without writing to the rings */
2140 for_each_ring(ring, dev_priv, i) {
2141 ret = intel_ring_idle(ring);
2145 i915_gem_retire_requests(dev);
2147 /* Finally reset hw state */
2148 for_each_ring(ring, dev_priv, i) {
2149 intel_ring_init_seqno(ring, seqno);
2151 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2152 ring->semaphore.sync_seqno[j] = 0;
2158 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2166 /* HWS page needs to be set less than what we
2167 * will inject to ring
2169 ret = i915_gem_init_seqno(dev, seqno - 1);
2173 /* Carefully set the last_seqno value so that wrap
2174 * detection still works
2176 dev_priv->next_seqno = seqno;
2177 dev_priv->last_seqno = seqno - 1;
2178 if (dev_priv->last_seqno == 0)
2179 dev_priv->last_seqno--;
2185 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2187 struct drm_i915_private *dev_priv = dev->dev_private;
2189 /* reserve 0 for non-seqno */
2190 if (dev_priv->next_seqno == 0) {
2191 int ret = i915_gem_init_seqno(dev, 0);
2195 dev_priv->next_seqno = 1;
2198 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2202 int __i915_add_request(struct intel_engine_cs *ring,
2203 struct drm_file *file,
2204 struct drm_i915_gem_object *obj,
2207 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2208 struct drm_i915_gem_request *request;
2209 u32 request_ring_position, request_start;
2212 request_start = intel_ring_get_tail(ring);
2214 * Emit any outstanding flushes - execbuf can fail to emit the flush
2215 * after having emitted the batchbuffer command. Hence we need to fix
2216 * things up similar to emitting the lazy request. The difference here
2217 * is that the flush _must_ happen before the next request, no matter
2220 ret = intel_ring_flush_all_caches(ring);
2224 request = ring->preallocated_lazy_request;
2225 if (WARN_ON(request == NULL))
2228 /* Record the position of the start of the request so that
2229 * should we detect the updated seqno part-way through the
2230 * GPU processing the request, we never over-estimate the
2231 * position of the head.
2233 request_ring_position = intel_ring_get_tail(ring);
2235 ret = ring->add_request(ring);
2239 request->seqno = intel_ring_get_seqno(ring);
2240 request->ring = ring;
2241 request->head = request_start;
2242 request->tail = request_ring_position;
2244 /* Whilst this request exists, batch_obj will be on the
2245 * active_list, and so will hold the active reference. Only when this
2246 * request is retired will the the batch_obj be moved onto the
2247 * inactive_list and lose its active reference. Hence we do not need
2248 * to explicitly hold another reference here.
2250 request->batch_obj = obj;
2252 /* Hold a reference to the current context so that we can inspect
2253 * it later in case a hangcheck error event fires.
2255 request->ctx = ring->last_context;
2257 i915_gem_context_reference(request->ctx);
2259 request->emitted_jiffies = jiffies;
2260 list_add_tail(&request->list, &ring->request_list);
2261 request->file_priv = NULL;
2264 struct drm_i915_file_private *file_priv = file->driver_priv;
2266 spin_lock(&file_priv->mm.lock);
2267 request->file_priv = file_priv;
2268 list_add_tail(&request->client_list,
2269 &file_priv->mm.request_list);
2270 spin_unlock(&file_priv->mm.lock);
2273 trace_i915_gem_request_add(ring, request->seqno);
2274 ring->outstanding_lazy_seqno = 0;
2275 ring->preallocated_lazy_request = NULL;
2277 if (!dev_priv->ums.mm_suspended) {
2278 i915_queue_hangcheck(ring->dev);
2280 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2281 queue_delayed_work(dev_priv->wq,
2282 &dev_priv->mm.retire_work,
2283 round_jiffies_up_relative(HZ));
2284 intel_mark_busy(dev_priv->dev);
2288 *out_seqno = request->seqno;
2293 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2295 struct drm_i915_file_private *file_priv = request->file_priv;
2300 spin_lock(&file_priv->mm.lock);
2301 list_del(&request->client_list);
2302 request->file_priv = NULL;
2303 spin_unlock(&file_priv->mm.lock);
2306 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2307 const struct i915_hw_context *ctx)
2309 unsigned long elapsed;
2311 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2313 if (ctx->hang_stats.banned)
2316 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2317 if (!i915_gem_context_is_default(ctx)) {
2318 DRM_DEBUG("context hanging too fast, banning!\n");
2320 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2321 if (i915_stop_ring_allow_warn(dev_priv))
2322 DRM_ERROR("gpu hanging too fast, banning!\n");
2330 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2331 struct i915_hw_context *ctx,
2334 struct i915_ctx_hang_stats *hs;
2339 hs = &ctx->hang_stats;
2342 hs->banned = i915_context_is_banned(dev_priv, ctx);
2344 hs->guilty_ts = get_seconds();
2346 hs->batch_pending++;
2350 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2352 list_del(&request->list);
2353 i915_gem_request_remove_from_client(request);
2356 i915_gem_context_unreference(request->ctx);
2361 struct drm_i915_gem_request *
2362 i915_gem_find_active_request(struct intel_engine_cs *ring)
2364 struct drm_i915_gem_request *request;
2365 u32 completed_seqno;
2367 completed_seqno = ring->get_seqno(ring, false);
2369 list_for_each_entry(request, &ring->request_list, list) {
2370 if (i915_seqno_passed(completed_seqno, request->seqno))
2379 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2380 struct intel_engine_cs *ring)
2382 struct drm_i915_gem_request *request;
2385 request = i915_gem_find_active_request(ring);
2387 if (request == NULL)
2390 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2392 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2394 list_for_each_entry_continue(request, &ring->request_list, list)
2395 i915_set_reset_status(dev_priv, request->ctx, false);
2398 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2399 struct intel_engine_cs *ring)
2401 while (!list_empty(&ring->active_list)) {
2402 struct drm_i915_gem_object *obj;
2404 obj = list_first_entry(&ring->active_list,
2405 struct drm_i915_gem_object,
2408 i915_gem_object_move_to_inactive(obj);
2412 * We must free the requests after all the corresponding objects have
2413 * been moved off active lists. Which is the same order as the normal
2414 * retire_requests function does. This is important if object hold
2415 * implicit references on things like e.g. ppgtt address spaces through
2418 while (!list_empty(&ring->request_list)) {
2419 struct drm_i915_gem_request *request;
2421 request = list_first_entry(&ring->request_list,
2422 struct drm_i915_gem_request,
2425 i915_gem_free_request(request);
2428 /* These may not have been flush before the reset, do so now */
2429 kfree(ring->preallocated_lazy_request);
2430 ring->preallocated_lazy_request = NULL;
2431 ring->outstanding_lazy_seqno = 0;
2434 void i915_gem_restore_fences(struct drm_device *dev)
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2439 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2440 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2443 * Commit delayed tiling changes if we have an object still
2444 * attached to the fence, otherwise just clear the fence.
2447 i915_gem_object_update_fence(reg->obj, reg,
2448 reg->obj->tiling_mode);
2450 i915_gem_write_fence(dev, i, NULL);
2455 void i915_gem_reset(struct drm_device *dev)
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458 struct intel_engine_cs *ring;
2462 * Before we free the objects from the requests, we need to inspect
2463 * them for finding the guilty party. As the requests only borrow
2464 * their reference to the objects, the inspection must be done first.
2466 for_each_ring(ring, dev_priv, i)
2467 i915_gem_reset_ring_status(dev_priv, ring);
2469 for_each_ring(ring, dev_priv, i)
2470 i915_gem_reset_ring_cleanup(dev_priv, ring);
2472 i915_gem_context_reset(dev);
2474 i915_gem_restore_fences(dev);
2478 * This function clears the request list as sequence numbers are passed.
2481 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2485 if (list_empty(&ring->request_list))
2488 WARN_ON(i915_verify_lists(ring->dev));
2490 seqno = ring->get_seqno(ring, true);
2492 /* Move any buffers on the active list that are no longer referenced
2493 * by the ringbuffer to the flushing/inactive lists as appropriate,
2494 * before we free the context associated with the requests.
2496 while (!list_empty(&ring->active_list)) {
2497 struct drm_i915_gem_object *obj;
2499 obj = list_first_entry(&ring->active_list,
2500 struct drm_i915_gem_object,
2503 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2506 i915_gem_object_move_to_inactive(obj);
2510 while (!list_empty(&ring->request_list)) {
2511 struct drm_i915_gem_request *request;
2513 request = list_first_entry(&ring->request_list,
2514 struct drm_i915_gem_request,
2517 if (!i915_seqno_passed(seqno, request->seqno))
2520 trace_i915_gem_request_retire(ring, request->seqno);
2521 /* We know the GPU must have read the request to have
2522 * sent us the seqno + interrupt, so use the position
2523 * of tail of the request to update the last known position
2526 ring->last_retired_head = request->tail;
2528 i915_gem_free_request(request);
2531 if (unlikely(ring->trace_irq_seqno &&
2532 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2533 ring->irq_put(ring);
2534 ring->trace_irq_seqno = 0;
2537 WARN_ON(i915_verify_lists(ring->dev));
2541 i915_gem_retire_requests(struct drm_device *dev)
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544 struct intel_engine_cs *ring;
2548 for_each_ring(ring, dev_priv, i) {
2549 i915_gem_retire_requests_ring(ring);
2550 idle &= list_empty(&ring->request_list);
2554 mod_delayed_work(dev_priv->wq,
2555 &dev_priv->mm.idle_work,
2556 msecs_to_jiffies(100));
2562 i915_gem_retire_work_handler(struct work_struct *work)
2564 struct drm_i915_private *dev_priv =
2565 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2566 struct drm_device *dev = dev_priv->dev;
2569 /* Come back later if the device is busy... */
2571 if (mutex_trylock(&dev->struct_mutex)) {
2572 idle = i915_gem_retire_requests(dev);
2573 mutex_unlock(&dev->struct_mutex);
2576 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2577 round_jiffies_up_relative(HZ));
2581 i915_gem_idle_work_handler(struct work_struct *work)
2583 struct drm_i915_private *dev_priv =
2584 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2586 intel_mark_idle(dev_priv->dev);
2590 * Ensures that an object will eventually get non-busy by flushing any required
2591 * write domains, emitting any outstanding lazy request and retiring and
2592 * completed requests.
2595 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2600 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2604 i915_gem_retire_requests_ring(obj->ring);
2611 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2612 * @DRM_IOCTL_ARGS: standard ioctl arguments
2614 * Returns 0 if successful, else an error is returned with the remaining time in
2615 * the timeout parameter.
2616 * -ETIME: object is still busy after timeout
2617 * -ERESTARTSYS: signal interrupted the wait
2618 * -ENONENT: object doesn't exist
2619 * Also possible, but rare:
2620 * -EAGAIN: GPU wedged
2622 * -ENODEV: Internal IRQ fail
2623 * -E?: The add request failed
2625 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2626 * non-zero timeout parameter the wait ioctl will wait for the given number of
2627 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2628 * without holding struct_mutex the object may become re-busied before this
2629 * function completes. A similar but shorter * race condition exists in the busy
2633 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct drm_i915_gem_wait *args = data;
2637 struct drm_i915_gem_object *obj;
2638 struct intel_engine_cs *ring = NULL;
2639 struct timespec timeout_stack, *timeout = NULL;
2640 unsigned reset_counter;
2644 if (args->timeout_ns >= 0) {
2645 timeout_stack = ns_to_timespec(args->timeout_ns);
2646 timeout = &timeout_stack;
2649 ret = i915_mutex_lock_interruptible(dev);
2653 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2654 if (&obj->base == NULL) {
2655 mutex_unlock(&dev->struct_mutex);
2659 /* Need to make sure the object gets inactive eventually. */
2660 ret = i915_gem_object_flush_active(obj);
2665 seqno = obj->last_read_seqno;
2672 /* Do this after OLR check to make sure we make forward progress polling
2673 * on this IOCTL with a 0 timeout (like busy ioctl)
2675 if (!args->timeout_ns) {
2680 drm_gem_object_unreference(&obj->base);
2681 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2682 mutex_unlock(&dev->struct_mutex);
2684 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2686 args->timeout_ns = timespec_to_ns(timeout);
2690 drm_gem_object_unreference(&obj->base);
2691 mutex_unlock(&dev->struct_mutex);
2696 * i915_gem_object_sync - sync an object to a ring.
2698 * @obj: object which may be in use on another ring.
2699 * @to: ring we wish to use the object on. May be NULL.
2701 * This code is meant to abstract object synchronization with the GPU.
2702 * Calling with NULL implies synchronizing the object with the CPU
2703 * rather than a particular GPU ring.
2705 * Returns 0 if successful, else propagates up the lower layer error.
2708 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2709 struct intel_engine_cs *to)
2711 struct intel_engine_cs *from = obj->ring;
2715 if (from == NULL || to == from)
2718 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2719 return i915_gem_object_wait_rendering(obj, false);
2721 idx = intel_ring_sync_index(from, to);
2723 seqno = obj->last_read_seqno;
2724 if (seqno <= from->semaphore.sync_seqno[idx])
2727 ret = i915_gem_check_olr(obj->ring, seqno);
2731 trace_i915_gem_ring_sync_to(from, to, seqno);
2732 ret = to->semaphore.sync_to(to, from, seqno);
2734 /* We use last_read_seqno because sync_to()
2735 * might have just caused seqno wrap under
2738 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2743 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2745 u32 old_write_domain, old_read_domains;
2747 /* Force a pagefault for domain tracking on next user access */
2748 i915_gem_release_mmap(obj);
2750 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2753 /* Wait for any direct GTT access to complete */
2756 old_read_domains = obj->base.read_domains;
2757 old_write_domain = obj->base.write_domain;
2759 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2760 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2762 trace_i915_gem_object_change_domain(obj,
2767 int i915_vma_unbind(struct i915_vma *vma)
2769 struct drm_i915_gem_object *obj = vma->obj;
2770 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2773 if (list_empty(&vma->vma_link))
2776 if (!drm_mm_node_allocated(&vma->node)) {
2777 i915_gem_vma_destroy(vma);
2784 BUG_ON(obj->pages == NULL);
2786 ret = i915_gem_object_finish_gpu(obj);
2789 /* Continue on if we fail due to EIO, the GPU is hung so we
2790 * should be safe and we need to cleanup or else we might
2791 * cause memory corruption through use-after-free.
2794 if (i915_is_ggtt(vma->vm)) {
2795 i915_gem_object_finish_gtt(obj);
2797 /* release the fence reg _after_ flushing */
2798 ret = i915_gem_object_put_fence(obj);
2803 trace_i915_vma_unbind(vma);
2805 vma->unbind_vma(vma);
2807 i915_gem_gtt_finish_object(obj);
2809 list_del_init(&vma->mm_list);
2810 /* Avoid an unnecessary call to unbind on rebind. */
2811 if (i915_is_ggtt(vma->vm))
2812 obj->map_and_fenceable = true;
2814 drm_mm_remove_node(&vma->node);
2815 i915_gem_vma_destroy(vma);
2817 /* Since the unbound list is global, only move to that list if
2818 * no more VMAs exist. */
2819 if (list_empty(&obj->vma_list))
2820 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2822 /* And finally now the object is completely decoupled from this vma,
2823 * we can drop its hold on the backing storage and allow it to be
2824 * reaped by the shrinker.
2826 i915_gem_object_unpin_pages(obj);
2831 int i915_gpu_idle(struct drm_device *dev)
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 struct intel_engine_cs *ring;
2837 /* Flush everything onto the inactive list. */
2838 for_each_ring(ring, dev_priv, i) {
2839 ret = i915_switch_context(ring, ring->default_context);
2843 ret = intel_ring_idle(ring);
2851 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2852 struct drm_i915_gem_object *obj)
2854 struct drm_i915_private *dev_priv = dev->dev_private;
2856 int fence_pitch_shift;
2858 if (INTEL_INFO(dev)->gen >= 6) {
2859 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2860 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2862 fence_reg = FENCE_REG_965_0;
2863 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2866 fence_reg += reg * 8;
2868 /* To w/a incoherency with non-atomic 64-bit register updates,
2869 * we split the 64-bit update into two 32-bit writes. In order
2870 * for a partial fence not to be evaluated between writes, we
2871 * precede the update with write to turn off the fence register,
2872 * and only enable the fence as the last step.
2874 * For extra levels of paranoia, we make sure each step lands
2875 * before applying the next step.
2877 I915_WRITE(fence_reg, 0);
2878 POSTING_READ(fence_reg);
2881 u32 size = i915_gem_obj_ggtt_size(obj);
2884 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2886 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2887 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2888 if (obj->tiling_mode == I915_TILING_Y)
2889 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2890 val |= I965_FENCE_REG_VALID;
2892 I915_WRITE(fence_reg + 4, val >> 32);
2893 POSTING_READ(fence_reg + 4);
2895 I915_WRITE(fence_reg + 0, val);
2896 POSTING_READ(fence_reg);
2898 I915_WRITE(fence_reg + 4, 0);
2899 POSTING_READ(fence_reg + 4);
2903 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2904 struct drm_i915_gem_object *obj)
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2910 u32 size = i915_gem_obj_ggtt_size(obj);
2914 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2915 (size & -size) != size ||
2916 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2917 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2918 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2920 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2925 /* Note: pitch better be a power of two tile widths */
2926 pitch_val = obj->stride / tile_width;
2927 pitch_val = ffs(pitch_val) - 1;
2929 val = i915_gem_obj_ggtt_offset(obj);
2930 if (obj->tiling_mode == I915_TILING_Y)
2931 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2932 val |= I915_FENCE_SIZE_BITS(size);
2933 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2934 val |= I830_FENCE_REG_VALID;
2939 reg = FENCE_REG_830_0 + reg * 4;
2941 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2943 I915_WRITE(reg, val);
2947 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2948 struct drm_i915_gem_object *obj)
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2954 u32 size = i915_gem_obj_ggtt_size(obj);
2957 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2958 (size & -size) != size ||
2959 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2960 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2961 i915_gem_obj_ggtt_offset(obj), size);
2963 pitch_val = obj->stride / 128;
2964 pitch_val = ffs(pitch_val) - 1;
2966 val = i915_gem_obj_ggtt_offset(obj);
2967 if (obj->tiling_mode == I915_TILING_Y)
2968 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2969 val |= I830_FENCE_SIZE_BITS(size);
2970 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2971 val |= I830_FENCE_REG_VALID;
2975 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2976 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2979 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2981 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2984 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2985 struct drm_i915_gem_object *obj)
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2989 /* Ensure that all CPU reads are completed before installing a fence
2990 * and all writes before removing the fence.
2992 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2995 WARN(obj && (!obj->stride || !obj->tiling_mode),
2996 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2997 obj->stride, obj->tiling_mode);
2999 switch (INTEL_INFO(dev)->gen) {
3004 case 4: i965_write_fence_reg(dev, reg, obj); break;
3005 case 3: i915_write_fence_reg(dev, reg, obj); break;
3006 case 2: i830_write_fence_reg(dev, reg, obj); break;
3010 /* And similarly be paranoid that no direct access to this region
3011 * is reordered to before the fence is installed.
3013 if (i915_gem_object_needs_mb(obj))
3017 static inline int fence_number(struct drm_i915_private *dev_priv,
3018 struct drm_i915_fence_reg *fence)
3020 return fence - dev_priv->fence_regs;
3023 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3024 struct drm_i915_fence_reg *fence,
3027 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3028 int reg = fence_number(dev_priv, fence);
3030 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3033 obj->fence_reg = reg;
3035 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3037 obj->fence_reg = I915_FENCE_REG_NONE;
3039 list_del_init(&fence->lru_list);
3041 obj->fence_dirty = false;
3045 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3047 if (obj->last_fenced_seqno) {
3048 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3052 obj->last_fenced_seqno = 0;
3055 obj->fenced_gpu_access = false;
3060 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3062 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3063 struct drm_i915_fence_reg *fence;
3066 ret = i915_gem_object_wait_fence(obj);
3070 if (obj->fence_reg == I915_FENCE_REG_NONE)
3073 fence = &dev_priv->fence_regs[obj->fence_reg];
3075 if (WARN_ON(fence->pin_count))
3078 i915_gem_object_fence_lost(obj);
3079 i915_gem_object_update_fence(obj, fence, false);
3084 static struct drm_i915_fence_reg *
3085 i915_find_fence_reg(struct drm_device *dev)
3087 struct drm_i915_private *dev_priv = dev->dev_private;
3088 struct drm_i915_fence_reg *reg, *avail;
3091 /* First try to find a free reg */
3093 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3094 reg = &dev_priv->fence_regs[i];
3098 if (!reg->pin_count)
3105 /* None available, try to steal one or wait for a user to finish */
3106 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3114 /* Wait for completion of pending flips which consume fences */
3115 if (intel_has_pending_fb_unpin(dev))
3116 return ERR_PTR(-EAGAIN);
3118 return ERR_PTR(-EDEADLK);
3122 * i915_gem_object_get_fence - set up fencing for an object
3123 * @obj: object to map through a fence reg
3125 * When mapping objects through the GTT, userspace wants to be able to write
3126 * to them without having to worry about swizzling if the object is tiled.
3127 * This function walks the fence regs looking for a free one for @obj,
3128 * stealing one if it can't find any.
3130 * It then sets up the reg based on the object's properties: address, pitch
3131 * and tiling format.
3133 * For an untiled surface, this removes any existing fence.
3136 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3138 struct drm_device *dev = obj->base.dev;
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 bool enable = obj->tiling_mode != I915_TILING_NONE;
3141 struct drm_i915_fence_reg *reg;
3144 /* Have we updated the tiling parameters upon the object and so
3145 * will need to serialise the write to the associated fence register?
3147 if (obj->fence_dirty) {
3148 ret = i915_gem_object_wait_fence(obj);
3153 /* Just update our place in the LRU if our fence is getting reused. */
3154 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3155 reg = &dev_priv->fence_regs[obj->fence_reg];
3156 if (!obj->fence_dirty) {
3157 list_move_tail(®->lru_list,
3158 &dev_priv->mm.fence_list);
3161 } else if (enable) {
3162 reg = i915_find_fence_reg(dev);
3164 return PTR_ERR(reg);
3167 struct drm_i915_gem_object *old = reg->obj;
3169 ret = i915_gem_object_wait_fence(old);
3173 i915_gem_object_fence_lost(old);
3178 i915_gem_object_update_fence(obj, reg, enable);
3183 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3184 struct drm_mm_node *gtt_space,
3185 unsigned long cache_level)
3187 struct drm_mm_node *other;
3189 /* On non-LLC machines we have to be careful when putting differing
3190 * types of snoopable memory together to avoid the prefetcher
3191 * crossing memory domains and dying.
3196 if (!drm_mm_node_allocated(gtt_space))
3199 if (list_empty(>t_space->node_list))
3202 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3203 if (other->allocated && !other->hole_follows && other->color != cache_level)
3206 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3207 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3213 static void i915_gem_verify_gtt(struct drm_device *dev)
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 struct drm_i915_gem_object *obj;
3220 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3221 if (obj->gtt_space == NULL) {
3222 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3227 if (obj->cache_level != obj->gtt_space->color) {
3228 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3229 i915_gem_obj_ggtt_offset(obj),
3230 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3232 obj->gtt_space->color);
3237 if (!i915_gem_valid_gtt_space(dev,
3239 obj->cache_level)) {
3240 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3241 i915_gem_obj_ggtt_offset(obj),
3242 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3254 * Finds free space in the GTT aperture and binds the object there.
3256 static struct i915_vma *
3257 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3258 struct i915_address_space *vm,
3262 struct drm_device *dev = obj->base.dev;
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 u32 size, fence_size, fence_alignment, unfenced_alignment;
3266 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3267 struct i915_vma *vma;
3270 fence_size = i915_gem_get_gtt_size(dev,
3273 fence_alignment = i915_gem_get_gtt_alignment(dev,
3275 obj->tiling_mode, true);
3276 unfenced_alignment =
3277 i915_gem_get_gtt_alignment(dev,
3279 obj->tiling_mode, false);
3282 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3284 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3285 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3286 return ERR_PTR(-EINVAL);
3289 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3291 /* If the object is bigger than the entire aperture, reject it early
3292 * before evicting everything in a vain attempt to find space.
3294 if (obj->base.size > gtt_max) {
3295 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3297 flags & PIN_MAPPABLE ? "mappable" : "total",
3299 return ERR_PTR(-E2BIG);
3302 ret = i915_gem_object_get_pages(obj);
3304 return ERR_PTR(ret);
3306 i915_gem_object_pin_pages(obj);
3308 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3313 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3315 obj->cache_level, 0, gtt_max,
3316 DRM_MM_SEARCH_DEFAULT,
3317 DRM_MM_CREATE_DEFAULT);
3319 ret = i915_gem_evict_something(dev, vm, size, alignment,
3320 obj->cache_level, flags);
3326 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3327 obj->cache_level))) {
3329 goto err_remove_node;
3332 ret = i915_gem_gtt_prepare_object(obj);
3334 goto err_remove_node;
3336 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3337 list_add_tail(&vma->mm_list, &vm->inactive_list);
3339 if (i915_is_ggtt(vm)) {
3340 bool mappable, fenceable;
3342 fenceable = (vma->node.size == fence_size &&
3343 (vma->node.start & (fence_alignment - 1)) == 0);
3345 mappable = (vma->node.start + obj->base.size <=
3346 dev_priv->gtt.mappable_end);
3348 obj->map_and_fenceable = mappable && fenceable;
3351 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3353 trace_i915_vma_bind(vma, flags);
3354 vma->bind_vma(vma, obj->cache_level,
3355 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3357 i915_gem_verify_gtt(dev);
3361 drm_mm_remove_node(&vma->node);
3363 i915_gem_vma_destroy(vma);
3366 i915_gem_object_unpin_pages(obj);
3371 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3374 /* If we don't have a page list set up, then we're not pinned
3375 * to GPU, and we can ignore the cache flush because it'll happen
3376 * again at bind time.
3378 if (obj->pages == NULL)
3382 * Stolen memory is always coherent with the GPU as it is explicitly
3383 * marked as wc by the system, or the system is cache-coherent.
3388 /* If the GPU is snooping the contents of the CPU cache,
3389 * we do not need to manually clear the CPU cache lines. However,
3390 * the caches are only snooped when the render cache is
3391 * flushed/invalidated. As we always have to emit invalidations
3392 * and flushes when moving into and out of the RENDER domain, correct
3393 * snooping behaviour occurs naturally as the result of our domain
3396 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3399 trace_i915_gem_object_clflush(obj);
3400 drm_clflush_sg(obj->pages);
3405 /** Flushes the GTT write domain for the object if it's dirty. */
3407 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3409 uint32_t old_write_domain;
3411 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3414 /* No actual flushing is required for the GTT write domain. Writes
3415 * to it immediately go to main memory as far as we know, so there's
3416 * no chipset flush. It also doesn't land in render cache.
3418 * However, we do have to enforce the order so that all writes through
3419 * the GTT land before any writes to the device, such as updates to
3424 old_write_domain = obj->base.write_domain;
3425 obj->base.write_domain = 0;
3427 trace_i915_gem_object_change_domain(obj,
3428 obj->base.read_domains,
3432 /** Flushes the CPU write domain for the object if it's dirty. */
3434 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3437 uint32_t old_write_domain;
3439 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3442 if (i915_gem_clflush_object(obj, force))
3443 i915_gem_chipset_flush(obj->base.dev);
3445 old_write_domain = obj->base.write_domain;
3446 obj->base.write_domain = 0;
3448 trace_i915_gem_object_change_domain(obj,
3449 obj->base.read_domains,
3454 * Moves a single object to the GTT read, and possibly write domain.
3456 * This function returns when the move is complete, including waiting on
3460 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3462 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3463 uint32_t old_write_domain, old_read_domains;
3466 /* Not valid to be called on unbound objects. */
3467 if (!i915_gem_obj_bound_any(obj))
3470 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3473 ret = i915_gem_object_wait_rendering(obj, !write);
3477 i915_gem_object_retire(obj);
3478 i915_gem_object_flush_cpu_write_domain(obj, false);
3480 /* Serialise direct access to this object with the barriers for
3481 * coherent writes from the GPU, by effectively invalidating the
3482 * GTT domain upon first access.
3484 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3487 old_write_domain = obj->base.write_domain;
3488 old_read_domains = obj->base.read_domains;
3490 /* It should now be out of any other write domains, and we can update
3491 * the domain values for our changes.
3493 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3494 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3496 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3497 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3501 trace_i915_gem_object_change_domain(obj,
3505 /* And bump the LRU for this access */
3506 if (i915_gem_object_is_inactive(obj)) {
3507 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3509 list_move_tail(&vma->mm_list,
3510 &dev_priv->gtt.base.inactive_list);
3517 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3518 enum i915_cache_level cache_level)
3520 struct drm_device *dev = obj->base.dev;
3521 struct i915_vma *vma, *next;
3524 if (obj->cache_level == cache_level)
3527 if (i915_gem_obj_is_pinned(obj)) {
3528 DRM_DEBUG("can not change the cache level of pinned objects\n");
3532 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3533 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3534 ret = i915_vma_unbind(vma);
3540 if (i915_gem_obj_bound_any(obj)) {
3541 ret = i915_gem_object_finish_gpu(obj);
3545 i915_gem_object_finish_gtt(obj);
3547 /* Before SandyBridge, you could not use tiling or fence
3548 * registers with snooped memory, so relinquish any fences
3549 * currently pointing to our region in the aperture.
3551 if (INTEL_INFO(dev)->gen < 6) {
3552 ret = i915_gem_object_put_fence(obj);
3557 list_for_each_entry(vma, &obj->vma_list, vma_link)
3558 if (drm_mm_node_allocated(&vma->node))
3559 vma->bind_vma(vma, cache_level,
3560 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3563 list_for_each_entry(vma, &obj->vma_list, vma_link)
3564 vma->node.color = cache_level;
3565 obj->cache_level = cache_level;
3567 if (cpu_write_needs_clflush(obj)) {
3568 u32 old_read_domains, old_write_domain;
3570 /* If we're coming from LLC cached, then we haven't
3571 * actually been tracking whether the data is in the
3572 * CPU cache or not, since we only allow one bit set
3573 * in obj->write_domain and have been skipping the clflushes.
3574 * Just set it to the CPU cache for now.
3576 i915_gem_object_retire(obj);
3577 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3579 old_read_domains = obj->base.read_domains;
3580 old_write_domain = obj->base.write_domain;
3582 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3583 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3585 trace_i915_gem_object_change_domain(obj,
3590 i915_gem_verify_gtt(dev);
3594 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3595 struct drm_file *file)
3597 struct drm_i915_gem_caching *args = data;
3598 struct drm_i915_gem_object *obj;
3601 ret = i915_mutex_lock_interruptible(dev);
3605 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3606 if (&obj->base == NULL) {
3611 switch (obj->cache_level) {
3612 case I915_CACHE_LLC:
3613 case I915_CACHE_L3_LLC:
3614 args->caching = I915_CACHING_CACHED;
3618 args->caching = I915_CACHING_DISPLAY;
3622 args->caching = I915_CACHING_NONE;
3626 drm_gem_object_unreference(&obj->base);
3628 mutex_unlock(&dev->struct_mutex);
3632 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3633 struct drm_file *file)
3635 struct drm_i915_gem_caching *args = data;
3636 struct drm_i915_gem_object *obj;
3637 enum i915_cache_level level;
3640 switch (args->caching) {
3641 case I915_CACHING_NONE:
3642 level = I915_CACHE_NONE;
3644 case I915_CACHING_CACHED:
3645 level = I915_CACHE_LLC;
3647 case I915_CACHING_DISPLAY:
3648 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3654 ret = i915_mutex_lock_interruptible(dev);
3658 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3659 if (&obj->base == NULL) {
3664 ret = i915_gem_object_set_cache_level(obj, level);
3666 drm_gem_object_unreference(&obj->base);
3668 mutex_unlock(&dev->struct_mutex);
3672 static bool is_pin_display(struct drm_i915_gem_object *obj)
3674 struct i915_vma *vma;
3676 if (list_empty(&obj->vma_list))
3679 vma = i915_gem_obj_to_ggtt(obj);
3683 /* There are 3 sources that pin objects:
3684 * 1. The display engine (scanouts, sprites, cursors);
3685 * 2. Reservations for execbuffer;
3688 * We can ignore reservations as we hold the struct_mutex and
3689 * are only called outside of the reservation path. The user
3690 * can only increment pin_count once, and so if after
3691 * subtracting the potential reference by the user, any pin_count
3692 * remains, it must be due to another use by the display engine.
3694 return vma->pin_count - !!obj->user_pin_count;
3698 * Prepare buffer for display plane (scanout, cursors, etc).
3699 * Can be called from an uninterruptible phase (modesetting) and allows
3700 * any flushes to be pipelined (for pageflips).
3703 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3705 struct intel_engine_cs *pipelined)
3707 u32 old_read_domains, old_write_domain;
3708 bool was_pin_display;
3711 if (pipelined != obj->ring) {
3712 ret = i915_gem_object_sync(obj, pipelined);
3717 /* Mark the pin_display early so that we account for the
3718 * display coherency whilst setting up the cache domains.
3720 was_pin_display = obj->pin_display;
3721 obj->pin_display = true;
3723 /* The display engine is not coherent with the LLC cache on gen6. As
3724 * a result, we make sure that the pinning that is about to occur is
3725 * done with uncached PTEs. This is lowest common denominator for all
3728 * However for gen6+, we could do better by using the GFDT bit instead
3729 * of uncaching, which would allow us to flush all the LLC-cached data
3730 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3732 ret = i915_gem_object_set_cache_level(obj,
3733 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3735 goto err_unpin_display;
3737 /* As the user may map the buffer once pinned in the display plane
3738 * (e.g. libkms for the bootup splash), we have to ensure that we
3739 * always use map_and_fenceable for all scanout buffers.
3741 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3743 goto err_unpin_display;
3745 i915_gem_object_flush_cpu_write_domain(obj, true);
3747 old_write_domain = obj->base.write_domain;
3748 old_read_domains = obj->base.read_domains;
3750 /* It should now be out of any other write domains, and we can update
3751 * the domain values for our changes.
3753 obj->base.write_domain = 0;
3754 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3756 trace_i915_gem_object_change_domain(obj,
3763 WARN_ON(was_pin_display != is_pin_display(obj));
3764 obj->pin_display = was_pin_display;
3769 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3771 i915_gem_object_ggtt_unpin(obj);
3772 obj->pin_display = is_pin_display(obj);
3776 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3780 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3783 ret = i915_gem_object_wait_rendering(obj, false);
3787 /* Ensure that we invalidate the GPU's caches and TLBs. */
3788 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3793 * Moves a single object to the CPU read, and possibly write domain.
3795 * This function returns when the move is complete, including waiting on
3799 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3801 uint32_t old_write_domain, old_read_domains;
3804 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3807 ret = i915_gem_object_wait_rendering(obj, !write);
3811 i915_gem_object_retire(obj);
3812 i915_gem_object_flush_gtt_write_domain(obj);
3814 old_write_domain = obj->base.write_domain;
3815 old_read_domains = obj->base.read_domains;
3817 /* Flush the CPU cache if it's still invalid. */
3818 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3819 i915_gem_clflush_object(obj, false);
3821 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3824 /* It should now be out of any other write domains, and we can update
3825 * the domain values for our changes.
3827 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3829 /* If we're writing through the CPU, then the GPU read domains will
3830 * need to be invalidated at next use.
3833 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3834 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3837 trace_i915_gem_object_change_domain(obj,
3844 /* Throttle our rendering by waiting until the ring has completed our requests
3845 * emitted over 20 msec ago.
3847 * Note that if we were to use the current jiffies each time around the loop,
3848 * we wouldn't escape the function with any frames outstanding if the time to
3849 * render a frame was over 20ms.
3851 * This should get us reasonable parallelism between CPU and GPU but also
3852 * relatively low latency when blocking on a particular request to finish.
3855 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 struct drm_i915_file_private *file_priv = file->driver_priv;
3859 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3860 struct drm_i915_gem_request *request;
3861 struct intel_engine_cs *ring = NULL;
3862 unsigned reset_counter;
3866 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3870 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3874 spin_lock(&file_priv->mm.lock);
3875 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3876 if (time_after_eq(request->emitted_jiffies, recent_enough))
3879 ring = request->ring;
3880 seqno = request->seqno;
3882 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3883 spin_unlock(&file_priv->mm.lock);
3888 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3890 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3896 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3897 struct i915_address_space *vm,
3901 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3902 struct i915_vma *vma;
3905 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
3908 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
3911 vma = i915_gem_obj_to_vma(obj, vm);
3913 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3917 vma->node.start & (alignment - 1)) ||
3918 (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) {
3919 WARN(vma->pin_count,
3920 "bo is already pinned with incorrect alignment:"
3921 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3922 " obj->map_and_fenceable=%d\n",
3923 i915_gem_obj_offset(obj, vm), alignment,
3924 flags & PIN_MAPPABLE,
3925 obj->map_and_fenceable);
3926 ret = i915_vma_unbind(vma);
3934 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
3935 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
3937 return PTR_ERR(vma);
3940 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
3941 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
3944 if (flags & PIN_MAPPABLE)
3945 obj->pin_mappable |= true;
3951 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3953 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3956 BUG_ON(vma->pin_count == 0);
3957 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3959 if (--vma->pin_count == 0)
3960 obj->pin_mappable = false;
3964 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
3966 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3967 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3968 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
3970 WARN_ON(!ggtt_vma ||
3971 dev_priv->fence_regs[obj->fence_reg].pin_count >
3972 ggtt_vma->pin_count);
3973 dev_priv->fence_regs[obj->fence_reg].pin_count++;
3980 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
3982 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3983 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3984 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
3985 dev_priv->fence_regs[obj->fence_reg].pin_count--;
3990 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3991 struct drm_file *file)
3993 struct drm_i915_gem_pin *args = data;
3994 struct drm_i915_gem_object *obj;
3997 if (INTEL_INFO(dev)->gen >= 6)
4000 ret = i915_mutex_lock_interruptible(dev);
4004 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4005 if (&obj->base == NULL) {
4010 if (obj->madv != I915_MADV_WILLNEED) {
4011 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4016 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4017 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4023 if (obj->user_pin_count == ULONG_MAX) {
4028 if (obj->user_pin_count == 0) {
4029 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4034 obj->user_pin_count++;
4035 obj->pin_filp = file;
4037 args->offset = i915_gem_obj_ggtt_offset(obj);
4039 drm_gem_object_unreference(&obj->base);
4041 mutex_unlock(&dev->struct_mutex);
4046 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4047 struct drm_file *file)
4049 struct drm_i915_gem_pin *args = data;
4050 struct drm_i915_gem_object *obj;
4053 ret = i915_mutex_lock_interruptible(dev);
4057 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4058 if (&obj->base == NULL) {
4063 if (obj->pin_filp != file) {
4064 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4069 obj->user_pin_count--;
4070 if (obj->user_pin_count == 0) {
4071 obj->pin_filp = NULL;
4072 i915_gem_object_ggtt_unpin(obj);
4076 drm_gem_object_unreference(&obj->base);
4078 mutex_unlock(&dev->struct_mutex);
4083 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4084 struct drm_file *file)
4086 struct drm_i915_gem_busy *args = data;
4087 struct drm_i915_gem_object *obj;
4090 ret = i915_mutex_lock_interruptible(dev);
4094 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4095 if (&obj->base == NULL) {
4100 /* Count all active objects as busy, even if they are currently not used
4101 * by the gpu. Users of this interface expect objects to eventually
4102 * become non-busy without any further actions, therefore emit any
4103 * necessary flushes here.
4105 ret = i915_gem_object_flush_active(obj);
4107 args->busy = obj->active;
4109 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4110 args->busy |= intel_ring_flag(obj->ring) << 16;
4113 drm_gem_object_unreference(&obj->base);
4115 mutex_unlock(&dev->struct_mutex);
4120 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4121 struct drm_file *file_priv)
4123 return i915_gem_ring_throttle(dev, file_priv);
4127 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4128 struct drm_file *file_priv)
4130 struct drm_i915_gem_madvise *args = data;
4131 struct drm_i915_gem_object *obj;
4134 switch (args->madv) {
4135 case I915_MADV_DONTNEED:
4136 case I915_MADV_WILLNEED:
4142 ret = i915_mutex_lock_interruptible(dev);
4146 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4147 if (&obj->base == NULL) {
4152 if (i915_gem_obj_is_pinned(obj)) {
4157 if (obj->madv != __I915_MADV_PURGED)
4158 obj->madv = args->madv;
4160 /* if the object is no longer attached, discard its backing storage */
4161 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4162 i915_gem_object_truncate(obj);
4164 args->retained = obj->madv != __I915_MADV_PURGED;
4167 drm_gem_object_unreference(&obj->base);
4169 mutex_unlock(&dev->struct_mutex);
4173 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4174 const struct drm_i915_gem_object_ops *ops)
4176 INIT_LIST_HEAD(&obj->global_list);
4177 INIT_LIST_HEAD(&obj->ring_list);
4178 INIT_LIST_HEAD(&obj->obj_exec_link);
4179 INIT_LIST_HEAD(&obj->vma_list);
4183 obj->fence_reg = I915_FENCE_REG_NONE;
4184 obj->madv = I915_MADV_WILLNEED;
4185 /* Avoid an unnecessary call to unbind on the first bind. */
4186 obj->map_and_fenceable = true;
4188 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4191 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4192 .get_pages = i915_gem_object_get_pages_gtt,
4193 .put_pages = i915_gem_object_put_pages_gtt,
4196 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4199 struct drm_i915_gem_object *obj;
4200 struct address_space *mapping;
4203 obj = i915_gem_object_alloc(dev);
4207 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4208 i915_gem_object_free(obj);
4212 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4213 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4214 /* 965gm cannot relocate objects above 4GiB. */
4215 mask &= ~__GFP_HIGHMEM;
4216 mask |= __GFP_DMA32;
4219 mapping = file_inode(obj->base.filp)->i_mapping;
4220 mapping_set_gfp_mask(mapping, mask);
4222 i915_gem_object_init(obj, &i915_gem_object_ops);
4224 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4225 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4228 /* On some devices, we can have the GPU use the LLC (the CPU
4229 * cache) for about a 10% performance improvement
4230 * compared to uncached. Graphics requests other than
4231 * display scanout are coherent with the CPU in
4232 * accessing this cache. This means in this mode we
4233 * don't need to clflush on the CPU side, and on the
4234 * GPU side we only need to flush internal caches to
4235 * get data visible to the CPU.
4237 * However, we maintain the display planes as UC, and so
4238 * need to rebind when first used as such.
4240 obj->cache_level = I915_CACHE_LLC;
4242 obj->cache_level = I915_CACHE_NONE;
4244 trace_i915_gem_object_create(obj);
4249 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4251 /* If we are the last user of the backing storage (be it shmemfs
4252 * pages or stolen etc), we know that the pages are going to be
4253 * immediately released. In this case, we can then skip copying
4254 * back the contents from the GPU.
4257 if (obj->madv != I915_MADV_WILLNEED)
4260 if (obj->base.filp == NULL)
4263 /* At first glance, this looks racy, but then again so would be
4264 * userspace racing mmap against close. However, the first external
4265 * reference to the filp can only be obtained through the
4266 * i915_gem_mmap_ioctl() which safeguards us against the user
4267 * acquiring such a reference whilst we are in the middle of
4268 * freeing the object.
4270 return atomic_long_read(&obj->base.filp->f_count) == 1;
4273 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4275 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4276 struct drm_device *dev = obj->base.dev;
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278 struct i915_vma *vma, *next;
4280 intel_runtime_pm_get(dev_priv);
4282 trace_i915_gem_object_destroy(obj);
4285 i915_gem_detach_phys_object(dev, obj);
4287 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4291 ret = i915_vma_unbind(vma);
4292 if (WARN_ON(ret == -ERESTARTSYS)) {
4293 bool was_interruptible;
4295 was_interruptible = dev_priv->mm.interruptible;
4296 dev_priv->mm.interruptible = false;
4298 WARN_ON(i915_vma_unbind(vma));
4300 dev_priv->mm.interruptible = was_interruptible;
4304 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4305 * before progressing. */
4307 i915_gem_object_unpin_pages(obj);
4309 if (WARN_ON(obj->pages_pin_count))
4310 obj->pages_pin_count = 0;
4311 if (discard_backing_storage(obj))
4312 obj->madv = I915_MADV_DONTNEED;
4313 i915_gem_object_put_pages(obj);
4314 i915_gem_object_free_mmap_offset(obj);
4315 i915_gem_object_release_stolen(obj);
4319 if (obj->base.import_attach)
4320 drm_prime_gem_destroy(&obj->base, NULL);
4322 if (obj->ops->release)
4323 obj->ops->release(obj);
4325 drm_gem_object_release(&obj->base);
4326 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4329 i915_gem_object_free(obj);
4331 intel_runtime_pm_put(dev_priv);
4334 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4335 struct i915_address_space *vm)
4337 struct i915_vma *vma;
4338 list_for_each_entry(vma, &obj->vma_list, vma_link)
4345 void i915_gem_vma_destroy(struct i915_vma *vma)
4347 WARN_ON(vma->node.allocated);
4349 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4350 if (!list_empty(&vma->exec_list))
4353 list_del(&vma->vma_link);
4359 i915_gem_stop_ringbuffers(struct drm_device *dev)
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 struct intel_engine_cs *ring;
4365 for_each_ring(ring, dev_priv, i)
4366 intel_stop_ring_buffer(ring);
4370 i915_gem_suspend(struct drm_device *dev)
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4375 mutex_lock(&dev->struct_mutex);
4376 if (dev_priv->ums.mm_suspended)
4379 ret = i915_gpu_idle(dev);
4383 i915_gem_retire_requests(dev);
4385 /* Under UMS, be paranoid and evict. */
4386 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4387 i915_gem_evict_everything(dev);
4389 i915_kernel_lost_context(dev);
4390 i915_gem_stop_ringbuffers(dev);
4392 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4393 * We need to replace this with a semaphore, or something.
4394 * And not confound ums.mm_suspended!
4396 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4398 mutex_unlock(&dev->struct_mutex);
4400 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4401 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4402 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4407 mutex_unlock(&dev->struct_mutex);
4411 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4413 struct drm_device *dev = ring->dev;
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4416 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4419 if (!HAS_L3_DPF(dev) || !remap_info)
4422 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4427 * Note: We do not worry about the concurrent register cacheline hang
4428 * here because no other code should access these registers other than
4429 * at initialization time.
4431 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4432 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4433 intel_ring_emit(ring, reg_base + i);
4434 intel_ring_emit(ring, remap_info[i/4]);
4437 intel_ring_advance(ring);
4442 void i915_gem_init_swizzling(struct drm_device *dev)
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4446 if (INTEL_INFO(dev)->gen < 5 ||
4447 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4450 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4451 DISP_TILE_SURFACE_SWIZZLING);
4456 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4458 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4459 else if (IS_GEN7(dev))
4460 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4461 else if (IS_GEN8(dev))
4462 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4468 intel_enable_blt(struct drm_device *dev)
4473 /* The blitter was dysfunctional on early prototypes */
4474 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4475 DRM_INFO("BLT not supported on this pre-production hardware;"
4476 " graphics performance will be degraded.\n");
4483 static int i915_gem_init_rings(struct drm_device *dev)
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4488 ret = intel_init_render_ring_buffer(dev);
4493 ret = intel_init_bsd_ring_buffer(dev);
4495 goto cleanup_render_ring;
4498 if (intel_enable_blt(dev)) {
4499 ret = intel_init_blt_ring_buffer(dev);
4501 goto cleanup_bsd_ring;
4504 if (HAS_VEBOX(dev)) {
4505 ret = intel_init_vebox_ring_buffer(dev);
4507 goto cleanup_blt_ring;
4510 if (HAS_BSD2(dev)) {
4511 ret = intel_init_bsd2_ring_buffer(dev);
4513 goto cleanup_vebox_ring;
4516 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4518 goto cleanup_bsd2_ring;
4523 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4525 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4527 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4529 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4530 cleanup_render_ring:
4531 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4537 i915_gem_init_hw(struct drm_device *dev)
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4542 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4545 if (dev_priv->ellc_size)
4546 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4548 if (IS_HASWELL(dev))
4549 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4550 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4552 if (HAS_PCH_NOP(dev)) {
4553 if (IS_IVYBRIDGE(dev)) {
4554 u32 temp = I915_READ(GEN7_MSG_CTL);
4555 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4556 I915_WRITE(GEN7_MSG_CTL, temp);
4557 } else if (INTEL_INFO(dev)->gen >= 7) {
4558 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4559 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4560 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4564 i915_gem_init_swizzling(dev);
4566 ret = i915_gem_init_rings(dev);
4570 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4571 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4574 * XXX: Contexts should only be initialized once. Doing a switch to the
4575 * default context switch however is something we'd like to do after
4576 * reset or thaw (the latter may not actually be necessary for HW, but
4577 * goes with our code better). Context switching requires rings (for
4578 * the do_switch), but before enabling PPGTT. So don't move this.
4580 ret = i915_gem_context_enable(dev_priv);
4581 if (ret && ret != -EIO) {
4582 DRM_ERROR("Context enable failed %d\n", ret);
4583 i915_gem_cleanup_ringbuffer(dev);
4589 int i915_gem_init(struct drm_device *dev)
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4594 mutex_lock(&dev->struct_mutex);
4596 if (IS_VALLEYVIEW(dev)) {
4597 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4598 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4599 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4600 VLV_GTLC_ALLOWWAKEACK), 10))
4601 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4604 i915_gem_init_userptr(dev);
4605 i915_gem_init_global_gtt(dev);
4607 ret = i915_gem_context_init(dev);
4609 mutex_unlock(&dev->struct_mutex);
4613 ret = i915_gem_init_hw(dev);
4615 /* Allow ring initialisation to fail by marking the GPU as
4616 * wedged. But we only want to do this where the GPU is angry,
4617 * for all other failure, such as an allocation failure, bail.
4619 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4620 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4623 mutex_unlock(&dev->struct_mutex);
4625 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4626 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4627 dev_priv->dri1.allow_batchbuffer = 1;
4632 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 struct intel_engine_cs *ring;
4638 for_each_ring(ring, dev_priv, i)
4639 intel_cleanup_ring_buffer(ring);
4643 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4644 struct drm_file *file_priv)
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4649 if (drm_core_check_feature(dev, DRIVER_MODESET))
4652 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4653 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4654 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4657 mutex_lock(&dev->struct_mutex);
4658 dev_priv->ums.mm_suspended = 0;
4660 ret = i915_gem_init_hw(dev);
4662 mutex_unlock(&dev->struct_mutex);
4666 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4668 ret = drm_irq_install(dev, dev->pdev->irq);
4670 goto cleanup_ringbuffer;
4671 mutex_unlock(&dev->struct_mutex);
4676 i915_gem_cleanup_ringbuffer(dev);
4677 dev_priv->ums.mm_suspended = 1;
4678 mutex_unlock(&dev->struct_mutex);
4684 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4685 struct drm_file *file_priv)
4687 if (drm_core_check_feature(dev, DRIVER_MODESET))
4690 mutex_lock(&dev->struct_mutex);
4691 drm_irq_uninstall(dev);
4692 mutex_unlock(&dev->struct_mutex);
4694 return i915_gem_suspend(dev);
4698 i915_gem_lastclose(struct drm_device *dev)
4702 if (drm_core_check_feature(dev, DRIVER_MODESET))
4705 ret = i915_gem_suspend(dev);
4707 DRM_ERROR("failed to idle hardware: %d\n", ret);
4711 init_ring_lists(struct intel_engine_cs *ring)
4713 INIT_LIST_HEAD(&ring->active_list);
4714 INIT_LIST_HEAD(&ring->request_list);
4717 void i915_init_vm(struct drm_i915_private *dev_priv,
4718 struct i915_address_space *vm)
4720 if (!i915_is_ggtt(vm))
4721 drm_mm_init(&vm->mm, vm->start, vm->total);
4722 vm->dev = dev_priv->dev;
4723 INIT_LIST_HEAD(&vm->active_list);
4724 INIT_LIST_HEAD(&vm->inactive_list);
4725 INIT_LIST_HEAD(&vm->global_link);
4726 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4730 i915_gem_load(struct drm_device *dev)
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4736 kmem_cache_create("i915_gem_object",
4737 sizeof(struct drm_i915_gem_object), 0,
4741 INIT_LIST_HEAD(&dev_priv->vm_list);
4742 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4744 INIT_LIST_HEAD(&dev_priv->context_list);
4745 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4746 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4747 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4748 for (i = 0; i < I915_NUM_RINGS; i++)
4749 init_ring_lists(&dev_priv->ring[i]);
4750 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4751 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4752 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4753 i915_gem_retire_work_handler);
4754 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4755 i915_gem_idle_work_handler);
4756 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4758 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4760 I915_WRITE(MI_ARB_STATE,
4761 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4764 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4766 /* Old X drivers will take 0-2 for front, back, depth buffers */
4767 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4768 dev_priv->fence_reg_start = 3;
4770 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4771 dev_priv->num_fence_regs = 32;
4772 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4773 dev_priv->num_fence_regs = 16;
4775 dev_priv->num_fence_regs = 8;
4777 /* Initialize fence registers to zero */
4778 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4779 i915_gem_restore_fences(dev);
4781 i915_gem_detect_bit_6_swizzle(dev);
4782 init_waitqueue_head(&dev_priv->pending_flip_queue);
4784 dev_priv->mm.interruptible = true;
4786 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4787 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4788 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4789 register_shrinker(&dev_priv->mm.shrinker);
4791 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4792 register_oom_notifier(&dev_priv->mm.oom_notifier);
4796 * Create a physically contiguous memory object for this object
4797 * e.g. for cursor + overlay regs
4799 static int i915_gem_init_phys_object(struct drm_device *dev,
4800 int id, int size, int align)
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct drm_i915_gem_phys_object *phys_obj;
4806 if (dev_priv->mm.phys_objs[id - 1] || !size)
4809 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4815 phys_obj->handle = drm_pci_alloc(dev, size, align);
4816 if (!phys_obj->handle) {
4821 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4824 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4832 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 struct drm_i915_gem_phys_object *phys_obj;
4837 if (!dev_priv->mm.phys_objs[id - 1])
4840 phys_obj = dev_priv->mm.phys_objs[id - 1];
4841 if (phys_obj->cur_obj) {
4842 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4846 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4848 drm_pci_free(dev, phys_obj->handle);
4850 dev_priv->mm.phys_objs[id - 1] = NULL;
4853 void i915_gem_free_all_phys_object(struct drm_device *dev)
4857 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4858 i915_gem_free_phys_object(dev, i);
4861 void i915_gem_detach_phys_object(struct drm_device *dev,
4862 struct drm_i915_gem_object *obj)
4864 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4871 vaddr = obj->phys_obj->handle->vaddr;
4873 page_count = obj->base.size / PAGE_SIZE;
4874 for (i = 0; i < page_count; i++) {
4875 struct page *page = shmem_read_mapping_page(mapping, i);
4876 if (!IS_ERR(page)) {
4877 char *dst = kmap_atomic(page);
4878 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4881 drm_clflush_pages(&page, 1);
4883 set_page_dirty(page);
4884 mark_page_accessed(page);
4885 page_cache_release(page);
4888 i915_gem_chipset_flush(dev);
4890 obj->phys_obj->cur_obj = NULL;
4891 obj->phys_obj = NULL;
4895 i915_gem_attach_phys_object(struct drm_device *dev,
4896 struct drm_i915_gem_object *obj,
4900 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4906 if (id > I915_MAX_PHYS_OBJECT)
4909 if (obj->phys_obj) {
4910 if (obj->phys_obj->id == id)
4912 i915_gem_detach_phys_object(dev, obj);
4915 /* create a new object */
4916 if (!dev_priv->mm.phys_objs[id - 1]) {
4917 ret = i915_gem_init_phys_object(dev, id,
4918 obj->base.size, align);
4920 DRM_ERROR("failed to init phys object %d size: %zu\n",
4921 id, obj->base.size);
4926 /* bind to the object */
4927 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4928 obj->phys_obj->cur_obj = obj;
4930 page_count = obj->base.size / PAGE_SIZE;
4932 for (i = 0; i < page_count; i++) {
4936 page = shmem_read_mapping_page(mapping, i);
4938 return PTR_ERR(page);
4940 src = kmap_atomic(page);
4941 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4942 memcpy(dst, src, PAGE_SIZE);
4945 mark_page_accessed(page);
4946 page_cache_release(page);
4953 i915_gem_phys_pwrite(struct drm_device *dev,
4954 struct drm_i915_gem_object *obj,
4955 struct drm_i915_gem_pwrite *args,
4956 struct drm_file *file_priv)
4958 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4959 char __user *user_data = to_user_ptr(args->data_ptr);
4961 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4962 unsigned long unwritten;
4964 /* The physical object once assigned is fixed for the lifetime
4965 * of the obj, so we can safely drop the lock and continue
4968 mutex_unlock(&dev->struct_mutex);
4969 unwritten = copy_from_user(vaddr, user_data, args->size);
4970 mutex_lock(&dev->struct_mutex);
4975 i915_gem_chipset_flush(dev);
4979 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4981 struct drm_i915_file_private *file_priv = file->driver_priv;
4983 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4985 /* Clean up our request list when the client is going away, so that
4986 * later retire_requests won't dereference our soon-to-be-gone
4989 spin_lock(&file_priv->mm.lock);
4990 while (!list_empty(&file_priv->mm.request_list)) {
4991 struct drm_i915_gem_request *request;
4993 request = list_first_entry(&file_priv->mm.request_list,
4994 struct drm_i915_gem_request,
4996 list_del(&request->client_list);
4997 request->file_priv = NULL;
4999 spin_unlock(&file_priv->mm.lock);
5003 i915_gem_file_idle_work_handler(struct work_struct *work)
5005 struct drm_i915_file_private *file_priv =
5006 container_of(work, typeof(*file_priv), mm.idle_work.work);
5008 atomic_set(&file_priv->rps_wait_boost, false);
5011 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5013 struct drm_i915_file_private *file_priv;
5016 DRM_DEBUG_DRIVER("\n");
5018 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5022 file->driver_priv = file_priv;
5023 file_priv->dev_priv = dev->dev_private;
5024 file_priv->file = file;
5026 spin_lock_init(&file_priv->mm.lock);
5027 INIT_LIST_HEAD(&file_priv->mm.request_list);
5028 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5029 i915_gem_file_idle_work_handler);
5031 ret = i915_gem_context_open(dev, file);
5038 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5040 if (!mutex_is_locked(mutex))
5043 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5044 return mutex->owner == task;
5046 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5051 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5053 if (!mutex_trylock(&dev->struct_mutex)) {
5054 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5057 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5067 static int num_vma_bound(struct drm_i915_gem_object *obj)
5069 struct i915_vma *vma;
5072 list_for_each_entry(vma, &obj->vma_list, vma_link)
5073 if (drm_mm_node_allocated(&vma->node))
5079 static unsigned long
5080 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5082 struct drm_i915_private *dev_priv =
5083 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5084 struct drm_device *dev = dev_priv->dev;
5085 struct drm_i915_gem_object *obj;
5086 unsigned long count;
5089 if (!i915_gem_shrinker_lock(dev, &unlock))
5093 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5094 if (obj->pages_pin_count == 0)
5095 count += obj->base.size >> PAGE_SHIFT;
5097 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5098 if (!i915_gem_obj_is_pinned(obj) &&
5099 obj->pages_pin_count == num_vma_bound(obj))
5100 count += obj->base.size >> PAGE_SHIFT;
5104 mutex_unlock(&dev->struct_mutex);
5109 /* All the new VM stuff */
5110 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5111 struct i915_address_space *vm)
5113 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5114 struct i915_vma *vma;
5116 if (!dev_priv->mm.aliasing_ppgtt ||
5117 vm == &dev_priv->mm.aliasing_ppgtt->base)
5118 vm = &dev_priv->gtt.base;
5120 BUG_ON(list_empty(&o->vma_list));
5121 list_for_each_entry(vma, &o->vma_list, vma_link) {
5123 return vma->node.start;
5129 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5130 struct i915_address_space *vm)
5132 struct i915_vma *vma;
5134 list_for_each_entry(vma, &o->vma_list, vma_link)
5135 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5141 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5143 struct i915_vma *vma;
5145 list_for_each_entry(vma, &o->vma_list, vma_link)
5146 if (drm_mm_node_allocated(&vma->node))
5152 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5153 struct i915_address_space *vm)
5155 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5156 struct i915_vma *vma;
5158 if (!dev_priv->mm.aliasing_ppgtt ||
5159 vm == &dev_priv->mm.aliasing_ppgtt->base)
5160 vm = &dev_priv->gtt.base;
5162 BUG_ON(list_empty(&o->vma_list));
5164 list_for_each_entry(vma, &o->vma_list, vma_link)
5166 return vma->node.size;
5171 static unsigned long
5172 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5174 struct drm_i915_private *dev_priv =
5175 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5176 struct drm_device *dev = dev_priv->dev;
5177 unsigned long freed;
5180 if (!i915_gem_shrinker_lock(dev, &unlock))
5183 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5184 if (freed < sc->nr_to_scan)
5185 freed += __i915_gem_shrink(dev_priv,
5186 sc->nr_to_scan - freed,
5189 mutex_unlock(&dev->struct_mutex);
5195 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5197 struct drm_i915_private *dev_priv =
5198 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5199 struct drm_device *dev = dev_priv->dev;
5200 struct drm_i915_gem_object *obj;
5201 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5202 unsigned long pinned, bound, unbound, freed;
5203 bool was_interruptible;
5206 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout)
5207 schedule_timeout_killable(1);
5209 pr_err("Unable to purge GPU memory due lock contention.\n");
5213 was_interruptible = dev_priv->mm.interruptible;
5214 dev_priv->mm.interruptible = false;
5216 freed = i915_gem_shrink_all(dev_priv);
5218 dev_priv->mm.interruptible = was_interruptible;
5220 /* Because we may be allocating inside our own driver, we cannot
5221 * assert that there are no objects with pinned pages that are not
5222 * being pointed to by hardware.
5224 unbound = bound = pinned = 0;
5225 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5226 if (!obj->base.filp) /* not backed by a freeable object */
5229 if (obj->pages_pin_count)
5230 pinned += obj->base.size;
5232 unbound += obj->base.size;
5234 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5235 if (!obj->base.filp)
5238 if (obj->pages_pin_count)
5239 pinned += obj->base.size;
5241 bound += obj->base.size;
5245 mutex_unlock(&dev->struct_mutex);
5247 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5249 if (unbound || bound)
5250 pr_err("%lu and %lu bytes still available in the "
5251 "bound and unbound GPU page lists.\n",
5254 *(unsigned long *)ptr += freed;
5258 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5260 struct i915_vma *vma;
5262 /* This WARN has probably outlived its usefulness (callers already
5263 * WARN if they don't find the GGTT vma they expect). When removing,
5264 * remember to remove the pre-check in is_pin_display() as well */
5265 if (WARN_ON(list_empty(&obj->vma_list)))
5268 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5269 if (vma->vm != obj_to_ggtt(obj))