2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_get_aperture *args = data;
168 struct drm_i915_gem_object *obj;
172 mutex_lock(&dev->struct_mutex);
173 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
174 if (i915_gem_obj_is_pinned(obj))
175 pinned += i915_gem_obj_ggtt_size(obj);
176 mutex_unlock(&dev->struct_mutex);
178 args->aper_size = dev_priv->gtt.base.total;
179 args->aper_available_size = args->aper_size - pinned;
185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
187 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
188 char *vaddr = obj->phys_handle->vaddr;
190 struct scatterlist *sg;
193 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
196 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
200 page = shmem_read_mapping_page(mapping, i);
202 return PTR_ERR(page);
204 src = kmap_atomic(page);
205 memcpy(vaddr, src, PAGE_SIZE);
206 drm_clflush_virt_range(vaddr, PAGE_SIZE);
209 page_cache_release(page);
213 i915_gem_chipset_flush(obj->base.dev);
215 st = kmalloc(sizeof(*st), GFP_KERNEL);
219 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
226 sg->length = obj->base.size;
228 sg_dma_address(sg) = obj->phys_handle->busaddr;
229 sg_dma_len(sg) = obj->base.size;
232 obj->has_dma_mapping = true;
237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
241 BUG_ON(obj->madv == __I915_MADV_PURGED);
243 ret = i915_gem_object_set_to_cpu_domain(obj, true);
245 /* In the event of a disaster, abandon all caches and
248 WARN_ON(ret != -EIO);
249 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
252 if (obj->madv == I915_MADV_DONTNEED)
256 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
257 char *vaddr = obj->phys_handle->vaddr;
260 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
264 page = shmem_read_mapping_page(mapping, i);
268 dst = kmap_atomic(page);
269 drm_clflush_virt_range(vaddr, PAGE_SIZE);
270 memcpy(dst, vaddr, PAGE_SIZE);
273 set_page_dirty(page);
274 if (obj->madv == I915_MADV_WILLNEED)
275 mark_page_accessed(page);
276 page_cache_release(page);
282 sg_free_table(obj->pages);
285 obj->has_dma_mapping = false;
289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
291 drm_pci_free(obj->base.dev, obj->phys_handle);
294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
295 .get_pages = i915_gem_object_get_pages_phys,
296 .put_pages = i915_gem_object_put_pages_phys,
297 .release = i915_gem_object_release_phys,
301 drop_pages(struct drm_i915_gem_object *obj)
303 struct i915_vma *vma, *next;
306 drm_gem_object_reference(&obj->base);
307 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
308 if (i915_vma_unbind(vma))
311 ret = i915_gem_object_put_pages(obj);
312 drm_gem_object_unreference(&obj->base);
318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
321 drm_dma_handle_t *phys;
324 if (obj->phys_handle) {
325 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
331 if (obj->madv != I915_MADV_WILLNEED)
334 if (obj->base.filp == NULL)
337 ret = drop_pages(obj);
341 /* create a new object */
342 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
346 obj->phys_handle = phys;
347 obj->ops = &i915_gem_phys_ops;
349 return i915_gem_object_get_pages(obj);
353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
354 struct drm_i915_gem_pwrite *args,
355 struct drm_file *file_priv)
357 struct drm_device *dev = obj->base.dev;
358 void *vaddr = obj->phys_handle->vaddr + args->offset;
359 char __user *user_data = to_user_ptr(args->data_ptr);
362 /* We manually control the domain here and pretend that it
363 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
365 ret = i915_gem_object_wait_rendering(obj, false);
369 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
370 unsigned long unwritten;
372 /* The physical object once assigned is fixed for the lifetime
373 * of the obj, so we can safely drop the lock and continue
376 mutex_unlock(&dev->struct_mutex);
377 unwritten = copy_from_user(vaddr, user_data, args->size);
378 mutex_lock(&dev->struct_mutex);
383 drm_clflush_virt_range(vaddr, args->size);
384 i915_gem_chipset_flush(dev);
388 void *i915_gem_object_alloc(struct drm_device *dev)
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
396 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
397 kmem_cache_free(dev_priv->slab, obj);
401 i915_gem_create(struct drm_file *file,
402 struct drm_device *dev,
406 struct drm_i915_gem_object *obj;
410 size = roundup(size, PAGE_SIZE);
414 /* Allocate the new object */
415 obj = i915_gem_alloc_object(dev, size);
419 ret = drm_gem_handle_create(file, &obj->base, &handle);
420 /* drop reference from allocate - handle holds it now */
421 drm_gem_object_unreference_unlocked(&obj->base);
430 i915_gem_dumb_create(struct drm_file *file,
431 struct drm_device *dev,
432 struct drm_mode_create_dumb *args)
434 /* have to work out size/pitch and return them */
435 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
436 args->size = args->pitch * args->height;
437 return i915_gem_create(file, dev,
438 args->size, &args->handle);
442 * Creates a new mm object and returns a handle to it.
445 i915_gem_create_ioctl(struct drm_device *dev, void *data,
446 struct drm_file *file)
448 struct drm_i915_gem_create *args = data;
450 return i915_gem_create(file, dev,
451 args->size, &args->handle);
455 __copy_to_user_swizzled(char __user *cpu_vaddr,
456 const char *gpu_vaddr, int gpu_offset,
459 int ret, cpu_offset = 0;
462 int cacheline_end = ALIGN(gpu_offset + 1, 64);
463 int this_length = min(cacheline_end - gpu_offset, length);
464 int swizzled_gpu_offset = gpu_offset ^ 64;
466 ret = __copy_to_user(cpu_vaddr + cpu_offset,
467 gpu_vaddr + swizzled_gpu_offset,
472 cpu_offset += this_length;
473 gpu_offset += this_length;
474 length -= this_length;
481 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
482 const char __user *cpu_vaddr,
485 int ret, cpu_offset = 0;
488 int cacheline_end = ALIGN(gpu_offset + 1, 64);
489 int this_length = min(cacheline_end - gpu_offset, length);
490 int swizzled_gpu_offset = gpu_offset ^ 64;
492 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
493 cpu_vaddr + cpu_offset,
498 cpu_offset += this_length;
499 gpu_offset += this_length;
500 length -= this_length;
507 * Pins the specified object's pages and synchronizes the object with
508 * GPU accesses. Sets needs_clflush to non-zero if the caller should
509 * flush the object from the CPU cache.
511 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
521 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
522 /* If we're not in the cpu read domain, set ourself into the gtt
523 * read domain and manually flush cachelines (if required). This
524 * optimizes for the case when the gpu will dirty the data
525 * anyway again before the next pread happens. */
526 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
528 ret = i915_gem_object_wait_rendering(obj, true);
532 i915_gem_object_retire(obj);
535 ret = i915_gem_object_get_pages(obj);
539 i915_gem_object_pin_pages(obj);
544 /* Per-page copy function for the shmem pread fastpath.
545 * Flushes invalid cachelines before reading the target if
546 * needs_clflush is set. */
548 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
549 char __user *user_data,
550 bool page_do_bit17_swizzling, bool needs_clflush)
555 if (unlikely(page_do_bit17_swizzling))
558 vaddr = kmap_atomic(page);
560 drm_clflush_virt_range(vaddr + shmem_page_offset,
562 ret = __copy_to_user_inatomic(user_data,
563 vaddr + shmem_page_offset,
565 kunmap_atomic(vaddr);
567 return ret ? -EFAULT : 0;
571 shmem_clflush_swizzled_range(char *addr, unsigned long length,
574 if (unlikely(swizzled)) {
575 unsigned long start = (unsigned long) addr;
576 unsigned long end = (unsigned long) addr + length;
578 /* For swizzling simply ensure that we always flush both
579 * channels. Lame, but simple and it works. Swizzled
580 * pwrite/pread is far from a hotpath - current userspace
581 * doesn't use it at all. */
582 start = round_down(start, 128);
583 end = round_up(end, 128);
585 drm_clflush_virt_range((void *)start, end - start);
587 drm_clflush_virt_range(addr, length);
592 /* Only difference to the fast-path function is that this can handle bit17
593 * and uses non-atomic copy and kmap functions. */
595 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
596 char __user *user_data,
597 bool page_do_bit17_swizzling, bool needs_clflush)
604 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
606 page_do_bit17_swizzling);
608 if (page_do_bit17_swizzling)
609 ret = __copy_to_user_swizzled(user_data,
610 vaddr, shmem_page_offset,
613 ret = __copy_to_user(user_data,
614 vaddr + shmem_page_offset,
618 return ret ? - EFAULT : 0;
622 i915_gem_shmem_pread(struct drm_device *dev,
623 struct drm_i915_gem_object *obj,
624 struct drm_i915_gem_pread *args,
625 struct drm_file *file)
627 char __user *user_data;
630 int shmem_page_offset, page_length, ret = 0;
631 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
633 int needs_clflush = 0;
634 struct sg_page_iter sg_iter;
636 user_data = to_user_ptr(args->data_ptr);
639 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
641 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
645 offset = args->offset;
647 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
648 offset >> PAGE_SHIFT) {
649 struct page *page = sg_page_iter_page(&sg_iter);
654 /* Operation in this page
656 * shmem_page_offset = offset within page in shmem file
657 * page_length = bytes to copy for this page
659 shmem_page_offset = offset_in_page(offset);
660 page_length = remain;
661 if ((shmem_page_offset + page_length) > PAGE_SIZE)
662 page_length = PAGE_SIZE - shmem_page_offset;
664 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
665 (page_to_phys(page) & (1 << 17)) != 0;
667 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
668 user_data, page_do_bit17_swizzling,
673 mutex_unlock(&dev->struct_mutex);
675 if (likely(!i915.prefault_disable) && !prefaulted) {
676 ret = fault_in_multipages_writeable(user_data, remain);
677 /* Userspace is tricking us, but we've already clobbered
678 * its pages with the prefault and promised to write the
679 * data up to the first fault. Hence ignore any errors
680 * and just continue. */
685 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
686 user_data, page_do_bit17_swizzling,
689 mutex_lock(&dev->struct_mutex);
695 remain -= page_length;
696 user_data += page_length;
697 offset += page_length;
701 i915_gem_object_unpin_pages(obj);
707 * Reads data from the object referenced by handle.
709 * On error, the contents of *data are undefined.
712 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *file)
715 struct drm_i915_gem_pread *args = data;
716 struct drm_i915_gem_object *obj;
722 if (!access_ok(VERIFY_WRITE,
723 to_user_ptr(args->data_ptr),
727 ret = i915_mutex_lock_interruptible(dev);
731 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
732 if (&obj->base == NULL) {
737 /* Bounds check source. */
738 if (args->offset > obj->base.size ||
739 args->size > obj->base.size - args->offset) {
744 /* prime objects have no backing filp to GEM pread/pwrite
747 if (!obj->base.filp) {
752 trace_i915_gem_object_pread(obj, args->offset, args->size);
754 ret = i915_gem_shmem_pread(dev, obj, args, file);
757 drm_gem_object_unreference(&obj->base);
759 mutex_unlock(&dev->struct_mutex);
763 /* This is the fast write path which cannot handle
764 * page faults in the source data
768 fast_user_write(struct io_mapping *mapping,
769 loff_t page_base, int page_offset,
770 char __user *user_data,
773 void __iomem *vaddr_atomic;
775 unsigned long unwritten;
777 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
778 /* We can use the cpu mem copy function because this is X86. */
779 vaddr = (void __force*)vaddr_atomic + page_offset;
780 unwritten = __copy_from_user_inatomic_nocache(vaddr,
782 io_mapping_unmap_atomic(vaddr_atomic);
787 * This is the fast pwrite path, where we copy the data directly from the
788 * user into the GTT, uncached.
791 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
792 struct drm_i915_gem_object *obj,
793 struct drm_i915_gem_pwrite *args,
794 struct drm_file *file)
796 struct drm_i915_private *dev_priv = dev->dev_private;
798 loff_t offset, page_base;
799 char __user *user_data;
800 int page_offset, page_length, ret;
802 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
806 ret = i915_gem_object_set_to_gtt_domain(obj, true);
810 ret = i915_gem_object_put_fence(obj);
814 user_data = to_user_ptr(args->data_ptr);
817 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
820 /* Operation in this page
822 * page_base = page offset within aperture
823 * page_offset = offset within page
824 * page_length = bytes to copy for this page
826 page_base = offset & PAGE_MASK;
827 page_offset = offset_in_page(offset);
828 page_length = remain;
829 if ((page_offset + remain) > PAGE_SIZE)
830 page_length = PAGE_SIZE - page_offset;
832 /* If we get a fault while copying data, then (presumably) our
833 * source page isn't available. Return the error and we'll
834 * retry in the slow path.
836 if (fast_user_write(dev_priv->gtt.mappable, page_base,
837 page_offset, user_data, page_length)) {
842 remain -= page_length;
843 user_data += page_length;
844 offset += page_length;
848 i915_gem_object_ggtt_unpin(obj);
853 /* Per-page copy function for the shmem pwrite fastpath.
854 * Flushes invalid cachelines before writing to the target if
855 * needs_clflush_before is set and flushes out any written cachelines after
856 * writing if needs_clflush is set. */
858 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
859 char __user *user_data,
860 bool page_do_bit17_swizzling,
861 bool needs_clflush_before,
862 bool needs_clflush_after)
867 if (unlikely(page_do_bit17_swizzling))
870 vaddr = kmap_atomic(page);
871 if (needs_clflush_before)
872 drm_clflush_virt_range(vaddr + shmem_page_offset,
874 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
875 user_data, page_length);
876 if (needs_clflush_after)
877 drm_clflush_virt_range(vaddr + shmem_page_offset,
879 kunmap_atomic(vaddr);
881 return ret ? -EFAULT : 0;
884 /* Only difference to the fast-path function is that this can handle bit17
885 * and uses non-atomic copy and kmap functions. */
887 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
888 char __user *user_data,
889 bool page_do_bit17_swizzling,
890 bool needs_clflush_before,
891 bool needs_clflush_after)
897 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
898 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
900 page_do_bit17_swizzling);
901 if (page_do_bit17_swizzling)
902 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
906 ret = __copy_from_user(vaddr + shmem_page_offset,
909 if (needs_clflush_after)
910 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
912 page_do_bit17_swizzling);
915 return ret ? -EFAULT : 0;
919 i915_gem_shmem_pwrite(struct drm_device *dev,
920 struct drm_i915_gem_object *obj,
921 struct drm_i915_gem_pwrite *args,
922 struct drm_file *file)
926 char __user *user_data;
927 int shmem_page_offset, page_length, ret = 0;
928 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
929 int hit_slowpath = 0;
930 int needs_clflush_after = 0;
931 int needs_clflush_before = 0;
932 struct sg_page_iter sg_iter;
934 user_data = to_user_ptr(args->data_ptr);
937 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
939 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
940 /* If we're not in the cpu write domain, set ourself into the gtt
941 * write domain and manually flush cachelines (if required). This
942 * optimizes for the case when the gpu will use the data
943 * right away and we therefore have to clflush anyway. */
944 needs_clflush_after = cpu_write_needs_clflush(obj);
945 ret = i915_gem_object_wait_rendering(obj, false);
949 i915_gem_object_retire(obj);
951 /* Same trick applies to invalidate partially written cachelines read
953 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
954 needs_clflush_before =
955 !cpu_cache_is_coherent(dev, obj->cache_level);
957 ret = i915_gem_object_get_pages(obj);
961 i915_gem_object_pin_pages(obj);
963 offset = args->offset;
966 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
967 offset >> PAGE_SHIFT) {
968 struct page *page = sg_page_iter_page(&sg_iter);
969 int partial_cacheline_write;
974 /* Operation in this page
976 * shmem_page_offset = offset within page in shmem file
977 * page_length = bytes to copy for this page
979 shmem_page_offset = offset_in_page(offset);
981 page_length = remain;
982 if ((shmem_page_offset + page_length) > PAGE_SIZE)
983 page_length = PAGE_SIZE - shmem_page_offset;
985 /* If we don't overwrite a cacheline completely we need to be
986 * careful to have up-to-date data by first clflushing. Don't
987 * overcomplicate things and flush the entire patch. */
988 partial_cacheline_write = needs_clflush_before &&
989 ((shmem_page_offset | page_length)
990 & (boot_cpu_data.x86_clflush_size - 1));
992 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
993 (page_to_phys(page) & (1 << 17)) != 0;
995 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
996 user_data, page_do_bit17_swizzling,
997 partial_cacheline_write,
998 needs_clflush_after);
1003 mutex_unlock(&dev->struct_mutex);
1004 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1005 user_data, page_do_bit17_swizzling,
1006 partial_cacheline_write,
1007 needs_clflush_after);
1009 mutex_lock(&dev->struct_mutex);
1015 remain -= page_length;
1016 user_data += page_length;
1017 offset += page_length;
1021 i915_gem_object_unpin_pages(obj);
1025 * Fixup: Flush cpu caches in case we didn't flush the dirty
1026 * cachelines in-line while writing and the object moved
1027 * out of the cpu write domain while we've dropped the lock.
1029 if (!needs_clflush_after &&
1030 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1031 if (i915_gem_clflush_object(obj, obj->pin_display))
1032 i915_gem_chipset_flush(dev);
1036 if (needs_clflush_after)
1037 i915_gem_chipset_flush(dev);
1043 * Writes data to the object referenced by handle.
1045 * On error, the contents of the buffer that were to be modified are undefined.
1048 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1049 struct drm_file *file)
1051 struct drm_i915_gem_pwrite *args = data;
1052 struct drm_i915_gem_object *obj;
1055 if (args->size == 0)
1058 if (!access_ok(VERIFY_READ,
1059 to_user_ptr(args->data_ptr),
1063 if (likely(!i915.prefault_disable)) {
1064 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1070 ret = i915_mutex_lock_interruptible(dev);
1074 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1075 if (&obj->base == NULL) {
1080 /* Bounds check destination. */
1081 if (args->offset > obj->base.size ||
1082 args->size > obj->base.size - args->offset) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj->base.filp) {
1095 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj->tiling_mode == I915_TILING_NONE &&
1105 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1106 cpu_write_needs_clflush(obj)) {
1107 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret == -EFAULT || ret == -ENOSPC) {
1114 if (obj->phys_handle)
1115 ret = i915_gem_phys_pwrite(obj, args, file);
1117 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1121 drm_gem_object_unreference(&obj->base);
1123 mutex_unlock(&dev->struct_mutex);
1128 i915_gem_check_wedge(struct i915_gpu_error *error,
1131 if (i915_reset_in_progress(error)) {
1132 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133 * -EIO unconditionally for these. */
1137 /* Recovery complete, but the reset failed ... */
1138 if (i915_terminally_wedged(error))
1142 * Check if GPU Reset is in progress - we need intel_ring_begin
1143 * to work properly to reinit the hw state while the gpu is
1144 * still marked as reset-in-progress. Handle this with a flag.
1146 if (!error->reload_in_reset)
1154 * Compare seqno against outstanding lazy request. Emit a request if they are
1158 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1162 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1165 if (seqno == ring->outstanding_lazy_seqno)
1166 ret = i915_add_request(ring, NULL);
1171 static void fake_irq(unsigned long data)
1173 wake_up_process((struct task_struct *)data);
1176 static bool missed_irq(struct drm_i915_private *dev_priv,
1177 struct intel_engine_cs *ring)
1179 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1182 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1184 if (file_priv == NULL)
1187 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1191 * __i915_wait_seqno - wait until execution of seqno has finished
1192 * @ring: the ring expected to report seqno
1194 * @reset_counter: reset sequence associated with the given seqno
1195 * @interruptible: do an interruptible wait (normally yes)
1196 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1198 * Note: It is of utmost importance that the passed in seqno and reset_counter
1199 * values have been read by the caller in an smp safe manner. Where read-side
1200 * locks are involved, it is sufficient to read the reset_counter before
1201 * unlocking the lock that protects the seqno. For lockless tricks, the
1202 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1205 * Returns 0 if the seqno was found within the alloted time. Else returns the
1206 * errno with remaining time filled in timeout argument.
1208 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1209 unsigned reset_counter,
1212 struct drm_i915_file_private *file_priv)
1214 struct drm_device *dev = ring->dev;
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 const bool irq_test_in_progress =
1217 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1219 unsigned long timeout_expire;
1223 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1225 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1228 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1230 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1231 gen6_rps_boost(dev_priv);
1233 mod_delayed_work(dev_priv->wq,
1234 &file_priv->mm.idle_work,
1235 msecs_to_jiffies(100));
1238 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1241 /* Record current time in case interrupted by signal, or wedged */
1242 trace_i915_gem_request_wait_begin(ring, seqno);
1243 before = ktime_get_raw_ns();
1245 struct timer_list timer;
1247 prepare_to_wait(&ring->irq_queue, &wait,
1248 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1250 /* We need to check whether any gpu reset happened in between
1251 * the caller grabbing the seqno and now ... */
1252 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1253 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1254 * is truely gone. */
1255 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1261 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1266 if (interruptible && signal_pending(current)) {
1271 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1276 timer.function = NULL;
1277 if (timeout || missed_irq(dev_priv, ring)) {
1278 unsigned long expire;
1280 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1281 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1282 mod_timer(&timer, expire);
1287 if (timer.function) {
1288 del_singleshot_timer_sync(&timer);
1289 destroy_timer_on_stack(&timer);
1292 now = ktime_get_raw_ns();
1293 trace_i915_gem_request_wait_end(ring, seqno);
1295 if (!irq_test_in_progress)
1296 ring->irq_put(ring);
1298 finish_wait(&ring->irq_queue, &wait);
1301 s64 tres = *timeout - (now - before);
1303 *timeout = tres < 0 ? 0 : tres;
1310 * Waits for a sequence number to be signaled, and cleans up the
1311 * request and object lists appropriately for that event.
1314 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1316 struct drm_device *dev = ring->dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 bool interruptible = dev_priv->mm.interruptible;
1319 unsigned reset_counter;
1322 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1325 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1329 ret = i915_gem_check_olr(ring, seqno);
1333 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1334 return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
1339 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1344 /* Manually manage the write flush as we may have not yet
1345 * retired the buffer.
1347 * Note that the last_write_seqno is always the earlier of
1348 * the two (read/write) seqno, so if we haved successfully waited,
1349 * we know we have passed the last write.
1351 obj->last_write_seqno = 0;
1357 * Ensures that all rendering to the object has completed and the object is
1358 * safe to unbind from the GTT or access from the CPU.
1360 static __must_check int
1361 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1364 struct intel_engine_cs *ring = obj->ring;
1368 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1372 ret = i915_wait_seqno(ring, seqno);
1376 return i915_gem_object_wait_rendering__tail(obj);
1379 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1380 * as the object state may change during this call.
1382 static __must_check int
1383 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1384 struct drm_i915_file_private *file_priv,
1387 struct drm_device *dev = obj->base.dev;
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 struct intel_engine_cs *ring = obj->ring;
1390 unsigned reset_counter;
1394 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1395 BUG_ON(!dev_priv->mm.interruptible);
1397 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1401 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1405 ret = i915_gem_check_olr(ring, seqno);
1409 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1410 mutex_unlock(&dev->struct_mutex);
1411 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
1413 mutex_lock(&dev->struct_mutex);
1417 return i915_gem_object_wait_rendering__tail(obj);
1421 * Called when user space prepares to use an object with the CPU, either
1422 * through the mmap ioctl's mapping or a GTT mapping.
1425 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1426 struct drm_file *file)
1428 struct drm_i915_gem_set_domain *args = data;
1429 struct drm_i915_gem_object *obj;
1430 uint32_t read_domains = args->read_domains;
1431 uint32_t write_domain = args->write_domain;
1434 /* Only handle setting domains to types used by the CPU. */
1435 if (write_domain & I915_GEM_GPU_DOMAINS)
1438 if (read_domains & I915_GEM_GPU_DOMAINS)
1441 /* Having something in the write domain implies it's in the read
1442 * domain, and only that read domain. Enforce that in the request.
1444 if (write_domain != 0 && read_domains != write_domain)
1447 ret = i915_mutex_lock_interruptible(dev);
1451 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1452 if (&obj->base == NULL) {
1457 /* Try to flush the object off the GPU without holding the lock.
1458 * We will repeat the flush holding the lock in the normal manner
1459 * to catch cases where we are gazumped.
1461 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1467 if (read_domains & I915_GEM_DOMAIN_GTT) {
1468 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1470 /* Silently promote "you're not bound, there was nothing to do"
1471 * to success, since the client was just asking us to
1472 * make sure everything was done.
1477 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1481 drm_gem_object_unreference(&obj->base);
1483 mutex_unlock(&dev->struct_mutex);
1488 * Called when user space has done writes to this buffer
1491 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1492 struct drm_file *file)
1494 struct drm_i915_gem_sw_finish *args = data;
1495 struct drm_i915_gem_object *obj;
1498 ret = i915_mutex_lock_interruptible(dev);
1502 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1503 if (&obj->base == NULL) {
1508 /* Pinned buffers may be scanout, so flush the cache */
1509 if (obj->pin_display)
1510 i915_gem_object_flush_cpu_write_domain(obj, true);
1512 drm_gem_object_unreference(&obj->base);
1514 mutex_unlock(&dev->struct_mutex);
1519 * Maps the contents of an object, returning the address it is mapped
1522 * While the mapping holds a reference on the contents of the object, it doesn't
1523 * imply a ref on the object itself.
1527 * DRM driver writers who look a this function as an example for how to do GEM
1528 * mmap support, please don't implement mmap support like here. The modern way
1529 * to implement DRM mmap support is with an mmap offset ioctl (like
1530 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1531 * That way debug tooling like valgrind will understand what's going on, hiding
1532 * the mmap call in a driver private ioctl will break that. The i915 driver only
1533 * does cpu mmaps this way because we didn't know better.
1536 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1537 struct drm_file *file)
1539 struct drm_i915_gem_mmap *args = data;
1540 struct drm_gem_object *obj;
1543 obj = drm_gem_object_lookup(dev, file, args->handle);
1547 /* prime objects have no backing filp to GEM mmap
1551 drm_gem_object_unreference_unlocked(obj);
1555 addr = vm_mmap(obj->filp, 0, args->size,
1556 PROT_READ | PROT_WRITE, MAP_SHARED,
1558 drm_gem_object_unreference_unlocked(obj);
1559 if (IS_ERR((void *)addr))
1562 args->addr_ptr = (uint64_t) addr;
1568 * i915_gem_fault - fault a page into the GTT
1569 * vma: VMA in question
1572 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1573 * from userspace. The fault handler takes care of binding the object to
1574 * the GTT (if needed), allocating and programming a fence register (again,
1575 * only if needed based on whether the old reg is still valid or the object
1576 * is tiled) and inserting a new PTE into the faulting process.
1578 * Note that the faulting process may involve evicting existing objects
1579 * from the GTT and/or fence registers to make room. So performance may
1580 * suffer if the GTT working set is large or there are few fence registers
1583 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1585 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1586 struct drm_device *dev = obj->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 pgoff_t page_offset;
1591 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1593 intel_runtime_pm_get(dev_priv);
1595 /* We don't use vmf->pgoff since that has the fake offset */
1596 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1599 ret = i915_mutex_lock_interruptible(dev);
1603 trace_i915_gem_object_fault(obj, page_offset, true, write);
1605 /* Try to flush the object off the GPU first without holding the lock.
1606 * Upon reacquiring the lock, we will perform our sanity checks and then
1607 * repeat the flush holding the lock in the normal manner to catch cases
1608 * where we are gazumped.
1610 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1614 /* Access to snoopable pages through the GTT is incoherent. */
1615 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1620 /* Now bind it into the GTT if needed */
1621 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1625 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1629 ret = i915_gem_object_get_fence(obj);
1633 /* Finally, remap it using the new GTT offset */
1634 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1637 if (!obj->fault_mappable) {
1638 unsigned long size = min_t(unsigned long,
1639 vma->vm_end - vma->vm_start,
1643 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1644 ret = vm_insert_pfn(vma,
1645 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1651 obj->fault_mappable = true;
1653 ret = vm_insert_pfn(vma,
1654 (unsigned long)vmf->virtual_address,
1657 i915_gem_object_ggtt_unpin(obj);
1659 mutex_unlock(&dev->struct_mutex);
1664 * We eat errors when the gpu is terminally wedged to avoid
1665 * userspace unduly crashing (gl has no provisions for mmaps to
1666 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1667 * and so needs to be reported.
1669 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1670 ret = VM_FAULT_SIGBUS;
1675 * EAGAIN means the gpu is hung and we'll wait for the error
1676 * handler to reset everything when re-faulting in
1677 * i915_mutex_lock_interruptible.
1684 * EBUSY is ok: this just means that another thread
1685 * already did the job.
1687 ret = VM_FAULT_NOPAGE;
1694 ret = VM_FAULT_SIGBUS;
1697 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1698 ret = VM_FAULT_SIGBUS;
1702 intel_runtime_pm_put(dev_priv);
1707 * i915_gem_release_mmap - remove physical page mappings
1708 * @obj: obj in question
1710 * Preserve the reservation of the mmapping with the DRM core code, but
1711 * relinquish ownership of the pages back to the system.
1713 * It is vital that we remove the page mapping if we have mapped a tiled
1714 * object through the GTT and then lose the fence register due to
1715 * resource pressure. Similarly if the object has been moved out of the
1716 * aperture, than pages mapped into userspace must be revoked. Removing the
1717 * mapping will then trigger a page fault on the next user access, allowing
1718 * fixup by i915_gem_fault().
1721 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1723 if (!obj->fault_mappable)
1726 drm_vma_node_unmap(&obj->base.vma_node,
1727 obj->base.dev->anon_inode->i_mapping);
1728 obj->fault_mappable = false;
1732 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1734 struct drm_i915_gem_object *obj;
1736 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1737 i915_gem_release_mmap(obj);
1741 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1745 if (INTEL_INFO(dev)->gen >= 4 ||
1746 tiling_mode == I915_TILING_NONE)
1749 /* Previous chips need a power-of-two fence region when tiling */
1750 if (INTEL_INFO(dev)->gen == 3)
1751 gtt_size = 1024*1024;
1753 gtt_size = 512*1024;
1755 while (gtt_size < size)
1762 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1763 * @obj: object to check
1765 * Return the required GTT alignment for an object, taking into account
1766 * potential fence register mapping.
1769 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1770 int tiling_mode, bool fenced)
1773 * Minimum alignment is 4k (GTT page size), but might be greater
1774 * if a fence register is needed for the object.
1776 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1777 tiling_mode == I915_TILING_NONE)
1781 * Previous chips need to be aligned to the size of the smallest
1782 * fence register that can contain the object.
1784 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1787 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1789 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1792 if (drm_vma_node_has_offset(&obj->base.vma_node))
1795 dev_priv->mm.shrinker_no_lock_stealing = true;
1797 ret = drm_gem_create_mmap_offset(&obj->base);
1801 /* Badly fragmented mmap space? The only way we can recover
1802 * space is by destroying unwanted objects. We can't randomly release
1803 * mmap_offsets as userspace expects them to be persistent for the
1804 * lifetime of the objects. The closest we can is to release the
1805 * offsets on purgeable objects by truncating it and marking it purged,
1806 * which prevents userspace from ever using that object again.
1808 i915_gem_shrink(dev_priv,
1809 obj->base.size >> PAGE_SHIFT,
1811 I915_SHRINK_UNBOUND |
1812 I915_SHRINK_PURGEABLE);
1813 ret = drm_gem_create_mmap_offset(&obj->base);
1817 i915_gem_shrink_all(dev_priv);
1818 ret = drm_gem_create_mmap_offset(&obj->base);
1820 dev_priv->mm.shrinker_no_lock_stealing = false;
1825 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1827 drm_gem_free_mmap_offset(&obj->base);
1831 i915_gem_mmap_gtt(struct drm_file *file,
1832 struct drm_device *dev,
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct drm_i915_gem_object *obj;
1840 ret = i915_mutex_lock_interruptible(dev);
1844 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1845 if (&obj->base == NULL) {
1850 if (obj->base.size > dev_priv->gtt.mappable_end) {
1855 if (obj->madv != I915_MADV_WILLNEED) {
1856 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1861 ret = i915_gem_object_create_mmap_offset(obj);
1865 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1868 drm_gem_object_unreference(&obj->base);
1870 mutex_unlock(&dev->struct_mutex);
1875 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1877 * @data: GTT mapping ioctl data
1878 * @file: GEM object info
1880 * Simply returns the fake offset to userspace so it can mmap it.
1881 * The mmap call will end up in drm_gem_mmap(), which will set things
1882 * up so we can get faults in the handler above.
1884 * The fault handler will take care of binding the object into the GTT
1885 * (since it may have been evicted to make room for something), allocating
1886 * a fence register, and mapping the appropriate aperture address into
1890 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1891 struct drm_file *file)
1893 struct drm_i915_gem_mmap_gtt *args = data;
1895 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1899 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1901 return obj->madv == I915_MADV_DONTNEED;
1904 /* Immediately discard the backing storage */
1906 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1908 i915_gem_object_free_mmap_offset(obj);
1910 if (obj->base.filp == NULL)
1913 /* Our goal here is to return as much of the memory as
1914 * is possible back to the system as we are called from OOM.
1915 * To do this we must instruct the shmfs to drop all of its
1916 * backing pages, *now*.
1918 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1919 obj->madv = __I915_MADV_PURGED;
1922 /* Try to discard unwanted pages */
1924 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1926 struct address_space *mapping;
1928 switch (obj->madv) {
1929 case I915_MADV_DONTNEED:
1930 i915_gem_object_truncate(obj);
1931 case __I915_MADV_PURGED:
1935 if (obj->base.filp == NULL)
1938 mapping = file_inode(obj->base.filp)->i_mapping,
1939 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1943 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1945 struct sg_page_iter sg_iter;
1948 BUG_ON(obj->madv == __I915_MADV_PURGED);
1950 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1952 /* In the event of a disaster, abandon all caches and
1953 * hope for the best.
1955 WARN_ON(ret != -EIO);
1956 i915_gem_clflush_object(obj, true);
1957 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1960 if (i915_gem_object_needs_bit17_swizzle(obj))
1961 i915_gem_object_save_bit_17_swizzle(obj);
1963 if (obj->madv == I915_MADV_DONTNEED)
1966 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1967 struct page *page = sg_page_iter_page(&sg_iter);
1970 set_page_dirty(page);
1972 if (obj->madv == I915_MADV_WILLNEED)
1973 mark_page_accessed(page);
1975 page_cache_release(page);
1979 sg_free_table(obj->pages);
1984 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1986 const struct drm_i915_gem_object_ops *ops = obj->ops;
1988 if (obj->pages == NULL)
1991 if (obj->pages_pin_count)
1994 BUG_ON(i915_gem_obj_bound_any(obj));
1996 /* ->put_pages might need to allocate memory for the bit17 swizzle
1997 * array, hence protect them from being reaped by removing them from gtt
1999 list_del(&obj->global_list);
2001 ops->put_pages(obj);
2004 i915_gem_object_invalidate(obj);
2010 i915_gem_shrink(struct drm_i915_private *dev_priv,
2011 long target, unsigned flags)
2014 struct list_head *list;
2017 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2018 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2021 unsigned long count = 0;
2024 * As we may completely rewrite the (un)bound list whilst unbinding
2025 * (due to retiring requests) we have to strictly process only
2026 * one element of the list at the time, and recheck the list
2027 * on every iteration.
2029 * In particular, we must hold a reference whilst removing the
2030 * object as we may end up waiting for and/or retiring the objects.
2031 * This might release the final reference (held by the active list)
2032 * and result in the object being freed from under us. This is
2033 * similar to the precautions the eviction code must take whilst
2036 * Also note that although these lists do not hold a reference to
2037 * the object we can safely grab one here: The final object
2038 * unreferencing and the bound_list are both protected by the
2039 * dev->struct_mutex and so we won't ever be able to observe an
2040 * object on the bound_list with a reference count equals 0.
2042 for (phase = phases; phase->list; phase++) {
2043 struct list_head still_in_list;
2045 if ((flags & phase->bit) == 0)
2048 INIT_LIST_HEAD(&still_in_list);
2049 while (count < target && !list_empty(phase->list)) {
2050 struct drm_i915_gem_object *obj;
2051 struct i915_vma *vma, *v;
2053 obj = list_first_entry(phase->list,
2054 typeof(*obj), global_list);
2055 list_move_tail(&obj->global_list, &still_in_list);
2057 if (flags & I915_SHRINK_PURGEABLE &&
2058 !i915_gem_object_is_purgeable(obj))
2061 drm_gem_object_reference(&obj->base);
2063 /* For the unbound phase, this should be a no-op! */
2064 list_for_each_entry_safe(vma, v,
2065 &obj->vma_list, vma_link)
2066 if (i915_vma_unbind(vma))
2069 if (i915_gem_object_put_pages(obj) == 0)
2070 count += obj->base.size >> PAGE_SHIFT;
2072 drm_gem_object_unreference(&obj->base);
2074 list_splice(&still_in_list, phase->list);
2080 static unsigned long
2081 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2083 i915_gem_evict_everything(dev_priv->dev);
2084 return i915_gem_shrink(dev_priv, LONG_MAX,
2085 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2089 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2091 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2093 struct address_space *mapping;
2094 struct sg_table *st;
2095 struct scatterlist *sg;
2096 struct sg_page_iter sg_iter;
2098 unsigned long last_pfn = 0; /* suppress gcc warning */
2101 /* Assert that the object is not currently in any GPU domain. As it
2102 * wasn't in the GTT, there shouldn't be any way it could have been in
2105 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2106 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2108 st = kmalloc(sizeof(*st), GFP_KERNEL);
2112 page_count = obj->base.size / PAGE_SIZE;
2113 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2118 /* Get the list of pages out of our struct file. They'll be pinned
2119 * at this point until we release them.
2121 * Fail silently without starting the shrinker
2123 mapping = file_inode(obj->base.filp)->i_mapping;
2124 gfp = mapping_gfp_mask(mapping);
2125 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2126 gfp &= ~(__GFP_IO | __GFP_WAIT);
2129 for (i = 0; i < page_count; i++) {
2130 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2132 i915_gem_shrink(dev_priv,
2135 I915_SHRINK_UNBOUND |
2136 I915_SHRINK_PURGEABLE);
2137 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2140 /* We've tried hard to allocate the memory by reaping
2141 * our own buffer, now let the real VM do its job and
2142 * go down in flames if truly OOM.
2144 i915_gem_shrink_all(dev_priv);
2145 page = shmem_read_mapping_page(mapping, i);
2149 #ifdef CONFIG_SWIOTLB
2150 if (swiotlb_nr_tbl()) {
2152 sg_set_page(sg, page, PAGE_SIZE, 0);
2157 if (!i || page_to_pfn(page) != last_pfn + 1) {
2161 sg_set_page(sg, page, PAGE_SIZE, 0);
2163 sg->length += PAGE_SIZE;
2165 last_pfn = page_to_pfn(page);
2167 /* Check that the i965g/gm workaround works. */
2168 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2170 #ifdef CONFIG_SWIOTLB
2171 if (!swiotlb_nr_tbl())
2176 if (i915_gem_object_needs_bit17_swizzle(obj))
2177 i915_gem_object_do_bit_17_swizzle(obj);
2179 if (obj->tiling_mode != I915_TILING_NONE &&
2180 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2181 i915_gem_object_pin_pages(obj);
2187 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2188 page_cache_release(sg_page_iter_page(&sg_iter));
2192 /* shmemfs first checks if there is enough memory to allocate the page
2193 * and reports ENOSPC should there be insufficient, along with the usual
2194 * ENOMEM for a genuine allocation failure.
2196 * We use ENOSPC in our driver to mean that we have run out of aperture
2197 * space and so want to translate the error from shmemfs back to our
2198 * usual understanding of ENOMEM.
2200 if (PTR_ERR(page) == -ENOSPC)
2203 return PTR_ERR(page);
2206 /* Ensure that the associated pages are gathered from the backing storage
2207 * and pinned into our object. i915_gem_object_get_pages() may be called
2208 * multiple times before they are released by a single call to
2209 * i915_gem_object_put_pages() - once the pages are no longer referenced
2210 * either as a result of memory pressure (reaping pages under the shrinker)
2211 * or as the object is itself released.
2214 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2216 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2217 const struct drm_i915_gem_object_ops *ops = obj->ops;
2223 if (obj->madv != I915_MADV_WILLNEED) {
2224 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2228 BUG_ON(obj->pages_pin_count);
2230 ret = ops->get_pages(obj);
2234 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2239 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2240 struct intel_engine_cs *ring)
2242 u32 seqno = intel_ring_get_seqno(ring);
2244 BUG_ON(ring == NULL);
2245 if (obj->ring != ring && obj->last_write_seqno) {
2246 /* Keep the seqno relative to the current ring */
2247 obj->last_write_seqno = seqno;
2251 /* Add a reference if we're newly entering the active list. */
2253 drm_gem_object_reference(&obj->base);
2257 list_move_tail(&obj->ring_list, &ring->active_list);
2259 obj->last_read_seqno = seqno;
2262 void i915_vma_move_to_active(struct i915_vma *vma,
2263 struct intel_engine_cs *ring)
2265 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2266 return i915_gem_object_move_to_active(vma->obj, ring);
2270 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2272 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2273 struct i915_address_space *vm;
2274 struct i915_vma *vma;
2276 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2277 BUG_ON(!obj->active);
2279 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2280 vma = i915_gem_obj_to_vma(obj, vm);
2281 if (vma && !list_empty(&vma->mm_list))
2282 list_move_tail(&vma->mm_list, &vm->inactive_list);
2285 intel_fb_obj_flush(obj, true);
2287 list_del_init(&obj->ring_list);
2290 obj->last_read_seqno = 0;
2291 obj->last_write_seqno = 0;
2292 obj->base.write_domain = 0;
2294 obj->last_fenced_seqno = 0;
2297 drm_gem_object_unreference(&obj->base);
2299 WARN_ON(i915_verify_lists(dev));
2303 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2305 struct intel_engine_cs *ring = obj->ring;
2310 if (i915_seqno_passed(ring->get_seqno(ring, true),
2311 obj->last_read_seqno))
2312 i915_gem_object_move_to_inactive(obj);
2316 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_engine_cs *ring;
2322 /* Carefully retire all requests without writing to the rings */
2323 for_each_ring(ring, dev_priv, i) {
2324 ret = intel_ring_idle(ring);
2328 i915_gem_retire_requests(dev);
2330 /* Finally reset hw state */
2331 for_each_ring(ring, dev_priv, i) {
2332 intel_ring_init_seqno(ring, seqno);
2334 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2335 ring->semaphore.sync_seqno[j] = 0;
2341 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2349 /* HWS page needs to be set less than what we
2350 * will inject to ring
2352 ret = i915_gem_init_seqno(dev, seqno - 1);
2356 /* Carefully set the last_seqno value so that wrap
2357 * detection still works
2359 dev_priv->next_seqno = seqno;
2360 dev_priv->last_seqno = seqno - 1;
2361 if (dev_priv->last_seqno == 0)
2362 dev_priv->last_seqno--;
2368 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2372 /* reserve 0 for non-seqno */
2373 if (dev_priv->next_seqno == 0) {
2374 int ret = i915_gem_init_seqno(dev, 0);
2378 dev_priv->next_seqno = 1;
2381 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2385 int __i915_add_request(struct intel_engine_cs *ring,
2386 struct drm_file *file,
2387 struct drm_i915_gem_object *obj,
2390 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2391 struct drm_i915_gem_request *request;
2392 struct intel_ringbuffer *ringbuf;
2393 u32 request_ring_position, request_start;
2396 request = ring->preallocated_lazy_request;
2397 if (WARN_ON(request == NULL))
2400 if (i915.enable_execlists) {
2401 struct intel_context *ctx = request->ctx;
2402 ringbuf = ctx->engine[ring->id].ringbuf;
2404 ringbuf = ring->buffer;
2406 request_start = intel_ring_get_tail(ringbuf);
2408 * Emit any outstanding flushes - execbuf can fail to emit the flush
2409 * after having emitted the batchbuffer command. Hence we need to fix
2410 * things up similar to emitting the lazy request. The difference here
2411 * is that the flush _must_ happen before the next request, no matter
2414 if (i915.enable_execlists) {
2415 ret = logical_ring_flush_all_caches(ringbuf);
2419 ret = intel_ring_flush_all_caches(ring);
2424 /* Record the position of the start of the request so that
2425 * should we detect the updated seqno part-way through the
2426 * GPU processing the request, we never over-estimate the
2427 * position of the head.
2429 request_ring_position = intel_ring_get_tail(ringbuf);
2431 if (i915.enable_execlists) {
2432 ret = ring->emit_request(ringbuf);
2436 ret = ring->add_request(ring);
2441 request->seqno = intel_ring_get_seqno(ring);
2442 request->ring = ring;
2443 request->head = request_start;
2444 request->tail = request_ring_position;
2446 /* Whilst this request exists, batch_obj will be on the
2447 * active_list, and so will hold the active reference. Only when this
2448 * request is retired will the the batch_obj be moved onto the
2449 * inactive_list and lose its active reference. Hence we do not need
2450 * to explicitly hold another reference here.
2452 request->batch_obj = obj;
2454 if (!i915.enable_execlists) {
2455 /* Hold a reference to the current context so that we can inspect
2456 * it later in case a hangcheck error event fires.
2458 request->ctx = ring->last_context;
2460 i915_gem_context_reference(request->ctx);
2463 request->emitted_jiffies = jiffies;
2464 list_add_tail(&request->list, &ring->request_list);
2465 request->file_priv = NULL;
2468 struct drm_i915_file_private *file_priv = file->driver_priv;
2470 spin_lock(&file_priv->mm.lock);
2471 request->file_priv = file_priv;
2472 list_add_tail(&request->client_list,
2473 &file_priv->mm.request_list);
2474 spin_unlock(&file_priv->mm.lock);
2477 trace_i915_gem_request_add(ring, request->seqno);
2478 ring->outstanding_lazy_seqno = 0;
2479 ring->preallocated_lazy_request = NULL;
2481 i915_queue_hangcheck(ring->dev);
2483 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2484 queue_delayed_work(dev_priv->wq,
2485 &dev_priv->mm.retire_work,
2486 round_jiffies_up_relative(HZ));
2487 intel_mark_busy(dev_priv->dev);
2490 *out_seqno = request->seqno;
2495 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2497 struct drm_i915_file_private *file_priv = request->file_priv;
2502 spin_lock(&file_priv->mm.lock);
2503 list_del(&request->client_list);
2504 request->file_priv = NULL;
2505 spin_unlock(&file_priv->mm.lock);
2508 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2509 const struct intel_context *ctx)
2511 unsigned long elapsed;
2513 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2515 if (ctx->hang_stats.banned)
2518 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2519 if (!i915_gem_context_is_default(ctx)) {
2520 DRM_DEBUG("context hanging too fast, banning!\n");
2522 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2523 if (i915_stop_ring_allow_warn(dev_priv))
2524 DRM_ERROR("gpu hanging too fast, banning!\n");
2532 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2533 struct intel_context *ctx,
2536 struct i915_ctx_hang_stats *hs;
2541 hs = &ctx->hang_stats;
2544 hs->banned = i915_context_is_banned(dev_priv, ctx);
2546 hs->guilty_ts = get_seconds();
2548 hs->batch_pending++;
2552 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2554 struct intel_context *ctx = request->ctx;
2556 list_del(&request->list);
2557 i915_gem_request_remove_from_client(request);
2559 if (i915.enable_execlists && ctx) {
2560 struct intel_engine_cs *ring = request->ring;
2562 if (ctx != ring->default_context)
2563 intel_lr_context_unpin(ring, ctx);
2564 i915_gem_context_unreference(ctx);
2569 struct drm_i915_gem_request *
2570 i915_gem_find_active_request(struct intel_engine_cs *ring)
2572 struct drm_i915_gem_request *request;
2573 u32 completed_seqno;
2575 completed_seqno = ring->get_seqno(ring, false);
2577 list_for_each_entry(request, &ring->request_list, list) {
2578 if (i915_seqno_passed(completed_seqno, request->seqno))
2587 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2588 struct intel_engine_cs *ring)
2590 struct drm_i915_gem_request *request;
2593 request = i915_gem_find_active_request(ring);
2595 if (request == NULL)
2598 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2600 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2602 list_for_each_entry_continue(request, &ring->request_list, list)
2603 i915_set_reset_status(dev_priv, request->ctx, false);
2606 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2607 struct intel_engine_cs *ring)
2609 while (!list_empty(&ring->active_list)) {
2610 struct drm_i915_gem_object *obj;
2612 obj = list_first_entry(&ring->active_list,
2613 struct drm_i915_gem_object,
2616 i915_gem_object_move_to_inactive(obj);
2620 * Clear the execlists queue up before freeing the requests, as those
2621 * are the ones that keep the context and ringbuffer backing objects
2624 while (!list_empty(&ring->execlist_queue)) {
2625 struct intel_ctx_submit_request *submit_req;
2627 submit_req = list_first_entry(&ring->execlist_queue,
2628 struct intel_ctx_submit_request,
2630 list_del(&submit_req->execlist_link);
2631 intel_runtime_pm_put(dev_priv);
2632 i915_gem_context_unreference(submit_req->ctx);
2637 * We must free the requests after all the corresponding objects have
2638 * been moved off active lists. Which is the same order as the normal
2639 * retire_requests function does. This is important if object hold
2640 * implicit references on things like e.g. ppgtt address spaces through
2643 while (!list_empty(&ring->request_list)) {
2644 struct drm_i915_gem_request *request;
2646 request = list_first_entry(&ring->request_list,
2647 struct drm_i915_gem_request,
2650 i915_gem_free_request(request);
2653 /* These may not have been flush before the reset, do so now */
2654 kfree(ring->preallocated_lazy_request);
2655 ring->preallocated_lazy_request = NULL;
2656 ring->outstanding_lazy_seqno = 0;
2659 void i915_gem_restore_fences(struct drm_device *dev)
2661 struct drm_i915_private *dev_priv = dev->dev_private;
2664 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2665 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2668 * Commit delayed tiling changes if we have an object still
2669 * attached to the fence, otherwise just clear the fence.
2672 i915_gem_object_update_fence(reg->obj, reg,
2673 reg->obj->tiling_mode);
2675 i915_gem_write_fence(dev, i, NULL);
2680 void i915_gem_reset(struct drm_device *dev)
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_engine_cs *ring;
2687 * Before we free the objects from the requests, we need to inspect
2688 * them for finding the guilty party. As the requests only borrow
2689 * their reference to the objects, the inspection must be done first.
2691 for_each_ring(ring, dev_priv, i)
2692 i915_gem_reset_ring_status(dev_priv, ring);
2694 for_each_ring(ring, dev_priv, i)
2695 i915_gem_reset_ring_cleanup(dev_priv, ring);
2697 i915_gem_context_reset(dev);
2699 i915_gem_restore_fences(dev);
2703 * This function clears the request list as sequence numbers are passed.
2706 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2710 if (list_empty(&ring->request_list))
2713 WARN_ON(i915_verify_lists(ring->dev));
2715 seqno = ring->get_seqno(ring, true);
2717 /* Move any buffers on the active list that are no longer referenced
2718 * by the ringbuffer to the flushing/inactive lists as appropriate,
2719 * before we free the context associated with the requests.
2721 while (!list_empty(&ring->active_list)) {
2722 struct drm_i915_gem_object *obj;
2724 obj = list_first_entry(&ring->active_list,
2725 struct drm_i915_gem_object,
2728 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2731 i915_gem_object_move_to_inactive(obj);
2735 while (!list_empty(&ring->request_list)) {
2736 struct drm_i915_gem_request *request;
2737 struct intel_ringbuffer *ringbuf;
2739 request = list_first_entry(&ring->request_list,
2740 struct drm_i915_gem_request,
2743 if (!i915_seqno_passed(seqno, request->seqno))
2746 trace_i915_gem_request_retire(ring, request->seqno);
2748 /* This is one of the few common intersection points
2749 * between legacy ringbuffer submission and execlists:
2750 * we need to tell them apart in order to find the correct
2751 * ringbuffer to which the request belongs to.
2753 if (i915.enable_execlists) {
2754 struct intel_context *ctx = request->ctx;
2755 ringbuf = ctx->engine[ring->id].ringbuf;
2757 ringbuf = ring->buffer;
2759 /* We know the GPU must have read the request to have
2760 * sent us the seqno + interrupt, so use the position
2761 * of tail of the request to update the last known position
2764 ringbuf->last_retired_head = request->tail;
2766 i915_gem_free_request(request);
2769 if (unlikely(ring->trace_irq_seqno &&
2770 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2771 ring->irq_put(ring);
2772 ring->trace_irq_seqno = 0;
2775 WARN_ON(i915_verify_lists(ring->dev));
2779 i915_gem_retire_requests(struct drm_device *dev)
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_engine_cs *ring;
2786 for_each_ring(ring, dev_priv, i) {
2787 i915_gem_retire_requests_ring(ring);
2788 idle &= list_empty(&ring->request_list);
2789 if (i915.enable_execlists) {
2790 unsigned long flags;
2792 spin_lock_irqsave(&ring->execlist_lock, flags);
2793 idle &= list_empty(&ring->execlist_queue);
2794 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2796 intel_execlists_retire_requests(ring);
2801 mod_delayed_work(dev_priv->wq,
2802 &dev_priv->mm.idle_work,
2803 msecs_to_jiffies(100));
2809 i915_gem_retire_work_handler(struct work_struct *work)
2811 struct drm_i915_private *dev_priv =
2812 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2813 struct drm_device *dev = dev_priv->dev;
2816 /* Come back later if the device is busy... */
2818 if (mutex_trylock(&dev->struct_mutex)) {
2819 idle = i915_gem_retire_requests(dev);
2820 mutex_unlock(&dev->struct_mutex);
2823 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2824 round_jiffies_up_relative(HZ));
2828 i915_gem_idle_work_handler(struct work_struct *work)
2830 struct drm_i915_private *dev_priv =
2831 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2833 intel_mark_idle(dev_priv->dev);
2837 * Ensures that an object will eventually get non-busy by flushing any required
2838 * write domains, emitting any outstanding lazy request and retiring and
2839 * completed requests.
2842 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2847 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2851 i915_gem_retire_requests_ring(obj->ring);
2858 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2859 * @DRM_IOCTL_ARGS: standard ioctl arguments
2861 * Returns 0 if successful, else an error is returned with the remaining time in
2862 * the timeout parameter.
2863 * -ETIME: object is still busy after timeout
2864 * -ERESTARTSYS: signal interrupted the wait
2865 * -ENONENT: object doesn't exist
2866 * Also possible, but rare:
2867 * -EAGAIN: GPU wedged
2869 * -ENODEV: Internal IRQ fail
2870 * -E?: The add request failed
2872 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2873 * non-zero timeout parameter the wait ioctl will wait for the given number of
2874 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2875 * without holding struct_mutex the object may become re-busied before this
2876 * function completes. A similar but shorter * race condition exists in the busy
2880 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct drm_i915_gem_wait *args = data;
2884 struct drm_i915_gem_object *obj;
2885 struct intel_engine_cs *ring = NULL;
2886 unsigned reset_counter;
2890 if (args->flags != 0)
2893 ret = i915_mutex_lock_interruptible(dev);
2897 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2898 if (&obj->base == NULL) {
2899 mutex_unlock(&dev->struct_mutex);
2903 /* Need to make sure the object gets inactive eventually. */
2904 ret = i915_gem_object_flush_active(obj);
2909 seqno = obj->last_read_seqno;
2916 /* Do this after OLR check to make sure we make forward progress polling
2917 * on this IOCTL with a timeout <=0 (like busy ioctl)
2919 if (args->timeout_ns <= 0) {
2924 drm_gem_object_unreference(&obj->base);
2925 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2926 mutex_unlock(&dev->struct_mutex);
2928 return __i915_wait_seqno(ring, seqno, reset_counter, true,
2929 &args->timeout_ns, file->driver_priv);
2932 drm_gem_object_unreference(&obj->base);
2933 mutex_unlock(&dev->struct_mutex);
2938 * i915_gem_object_sync - sync an object to a ring.
2940 * @obj: object which may be in use on another ring.
2941 * @to: ring we wish to use the object on. May be NULL.
2943 * This code is meant to abstract object synchronization with the GPU.
2944 * Calling with NULL implies synchronizing the object with the CPU
2945 * rather than a particular GPU ring.
2947 * Returns 0 if successful, else propagates up the lower layer error.
2950 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2951 struct intel_engine_cs *to)
2953 struct intel_engine_cs *from = obj->ring;
2957 if (from == NULL || to == from)
2960 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2961 return i915_gem_object_wait_rendering(obj, false);
2963 idx = intel_ring_sync_index(from, to);
2965 seqno = obj->last_read_seqno;
2966 /* Optimization: Avoid semaphore sync when we are sure we already
2967 * waited for an object with higher seqno */
2968 if (seqno <= from->semaphore.sync_seqno[idx])
2971 ret = i915_gem_check_olr(obj->ring, seqno);
2975 trace_i915_gem_ring_sync_to(from, to, seqno);
2976 ret = to->semaphore.sync_to(to, from, seqno);
2978 /* We use last_read_seqno because sync_to()
2979 * might have just caused seqno wrap under
2982 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2987 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2989 u32 old_write_domain, old_read_domains;
2991 /* Force a pagefault for domain tracking on next user access */
2992 i915_gem_release_mmap(obj);
2994 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2997 /* Wait for any direct GTT access to complete */
3000 old_read_domains = obj->base.read_domains;
3001 old_write_domain = obj->base.write_domain;
3003 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3004 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3006 trace_i915_gem_object_change_domain(obj,
3011 int i915_vma_unbind(struct i915_vma *vma)
3013 struct drm_i915_gem_object *obj = vma->obj;
3014 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3017 if (list_empty(&vma->vma_link))
3020 if (!drm_mm_node_allocated(&vma->node)) {
3021 i915_gem_vma_destroy(vma);
3028 BUG_ON(obj->pages == NULL);
3030 ret = i915_gem_object_finish_gpu(obj);
3033 /* Continue on if we fail due to EIO, the GPU is hung so we
3034 * should be safe and we need to cleanup or else we might
3035 * cause memory corruption through use-after-free.
3038 /* Throw away the active reference before moving to the unbound list */
3039 i915_gem_object_retire(obj);
3041 if (i915_is_ggtt(vma->vm)) {
3042 i915_gem_object_finish_gtt(obj);
3044 /* release the fence reg _after_ flushing */
3045 ret = i915_gem_object_put_fence(obj);
3050 trace_i915_vma_unbind(vma);
3052 vma->unbind_vma(vma);
3054 list_del_init(&vma->mm_list);
3055 if (i915_is_ggtt(vma->vm))
3056 obj->map_and_fenceable = false;
3058 drm_mm_remove_node(&vma->node);
3059 i915_gem_vma_destroy(vma);
3061 /* Since the unbound list is global, only move to that list if
3062 * no more VMAs exist. */
3063 if (list_empty(&obj->vma_list)) {
3064 i915_gem_gtt_finish_object(obj);
3065 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3068 /* And finally now the object is completely decoupled from this vma,
3069 * we can drop its hold on the backing storage and allow it to be
3070 * reaped by the shrinker.
3072 i915_gem_object_unpin_pages(obj);
3077 int i915_gpu_idle(struct drm_device *dev)
3079 struct drm_i915_private *dev_priv = dev->dev_private;
3080 struct intel_engine_cs *ring;
3083 /* Flush everything onto the inactive list. */
3084 for_each_ring(ring, dev_priv, i) {
3085 if (!i915.enable_execlists) {
3086 ret = i915_switch_context(ring, ring->default_context);
3091 ret = intel_ring_idle(ring);
3099 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3100 struct drm_i915_gem_object *obj)
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3104 int fence_pitch_shift;
3106 if (INTEL_INFO(dev)->gen >= 6) {
3107 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3108 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3110 fence_reg = FENCE_REG_965_0;
3111 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3114 fence_reg += reg * 8;
3116 /* To w/a incoherency with non-atomic 64-bit register updates,
3117 * we split the 64-bit update into two 32-bit writes. In order
3118 * for a partial fence not to be evaluated between writes, we
3119 * precede the update with write to turn off the fence register,
3120 * and only enable the fence as the last step.
3122 * For extra levels of paranoia, we make sure each step lands
3123 * before applying the next step.
3125 I915_WRITE(fence_reg, 0);
3126 POSTING_READ(fence_reg);
3129 u32 size = i915_gem_obj_ggtt_size(obj);
3132 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3134 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3135 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3136 if (obj->tiling_mode == I915_TILING_Y)
3137 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3138 val |= I965_FENCE_REG_VALID;
3140 I915_WRITE(fence_reg + 4, val >> 32);
3141 POSTING_READ(fence_reg + 4);
3143 I915_WRITE(fence_reg + 0, val);
3144 POSTING_READ(fence_reg);
3146 I915_WRITE(fence_reg + 4, 0);
3147 POSTING_READ(fence_reg + 4);
3151 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3152 struct drm_i915_gem_object *obj)
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3158 u32 size = i915_gem_obj_ggtt_size(obj);
3162 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3163 (size & -size) != size ||
3164 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3165 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3166 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3168 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3173 /* Note: pitch better be a power of two tile widths */
3174 pitch_val = obj->stride / tile_width;
3175 pitch_val = ffs(pitch_val) - 1;
3177 val = i915_gem_obj_ggtt_offset(obj);
3178 if (obj->tiling_mode == I915_TILING_Y)
3179 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3180 val |= I915_FENCE_SIZE_BITS(size);
3181 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3182 val |= I830_FENCE_REG_VALID;
3187 reg = FENCE_REG_830_0 + reg * 4;
3189 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3191 I915_WRITE(reg, val);
3195 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3196 struct drm_i915_gem_object *obj)
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3202 u32 size = i915_gem_obj_ggtt_size(obj);
3205 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3206 (size & -size) != size ||
3207 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3208 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3209 i915_gem_obj_ggtt_offset(obj), size);
3211 pitch_val = obj->stride / 128;
3212 pitch_val = ffs(pitch_val) - 1;
3214 val = i915_gem_obj_ggtt_offset(obj);
3215 if (obj->tiling_mode == I915_TILING_Y)
3216 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3217 val |= I830_FENCE_SIZE_BITS(size);
3218 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3219 val |= I830_FENCE_REG_VALID;
3223 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3224 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3227 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3229 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3232 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3233 struct drm_i915_gem_object *obj)
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3237 /* Ensure that all CPU reads are completed before installing a fence
3238 * and all writes before removing the fence.
3240 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3243 WARN(obj && (!obj->stride || !obj->tiling_mode),
3244 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3245 obj->stride, obj->tiling_mode);
3247 switch (INTEL_INFO(dev)->gen) {
3253 case 4: i965_write_fence_reg(dev, reg, obj); break;
3254 case 3: i915_write_fence_reg(dev, reg, obj); break;
3255 case 2: i830_write_fence_reg(dev, reg, obj); break;
3259 /* And similarly be paranoid that no direct access to this region
3260 * is reordered to before the fence is installed.
3262 if (i915_gem_object_needs_mb(obj))
3266 static inline int fence_number(struct drm_i915_private *dev_priv,
3267 struct drm_i915_fence_reg *fence)
3269 return fence - dev_priv->fence_regs;
3272 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3273 struct drm_i915_fence_reg *fence,
3276 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3277 int reg = fence_number(dev_priv, fence);
3279 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3282 obj->fence_reg = reg;
3284 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3286 obj->fence_reg = I915_FENCE_REG_NONE;
3288 list_del_init(&fence->lru_list);
3290 obj->fence_dirty = false;
3294 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3296 if (obj->last_fenced_seqno) {
3297 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3301 obj->last_fenced_seqno = 0;
3308 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3310 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3311 struct drm_i915_fence_reg *fence;
3314 ret = i915_gem_object_wait_fence(obj);
3318 if (obj->fence_reg == I915_FENCE_REG_NONE)
3321 fence = &dev_priv->fence_regs[obj->fence_reg];
3323 if (WARN_ON(fence->pin_count))
3326 i915_gem_object_fence_lost(obj);
3327 i915_gem_object_update_fence(obj, fence, false);
3332 static struct drm_i915_fence_reg *
3333 i915_find_fence_reg(struct drm_device *dev)
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct drm_i915_fence_reg *reg, *avail;
3339 /* First try to find a free reg */
3341 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3342 reg = &dev_priv->fence_regs[i];
3346 if (!reg->pin_count)
3353 /* None available, try to steal one or wait for a user to finish */
3354 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3362 /* Wait for completion of pending flips which consume fences */
3363 if (intel_has_pending_fb_unpin(dev))
3364 return ERR_PTR(-EAGAIN);
3366 return ERR_PTR(-EDEADLK);
3370 * i915_gem_object_get_fence - set up fencing for an object
3371 * @obj: object to map through a fence reg
3373 * When mapping objects through the GTT, userspace wants to be able to write
3374 * to them without having to worry about swizzling if the object is tiled.
3375 * This function walks the fence regs looking for a free one for @obj,
3376 * stealing one if it can't find any.
3378 * It then sets up the reg based on the object's properties: address, pitch
3379 * and tiling format.
3381 * For an untiled surface, this removes any existing fence.
3384 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3386 struct drm_device *dev = obj->base.dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 bool enable = obj->tiling_mode != I915_TILING_NONE;
3389 struct drm_i915_fence_reg *reg;
3392 /* Have we updated the tiling parameters upon the object and so
3393 * will need to serialise the write to the associated fence register?
3395 if (obj->fence_dirty) {
3396 ret = i915_gem_object_wait_fence(obj);
3401 /* Just update our place in the LRU if our fence is getting reused. */
3402 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3403 reg = &dev_priv->fence_regs[obj->fence_reg];
3404 if (!obj->fence_dirty) {
3405 list_move_tail(®->lru_list,
3406 &dev_priv->mm.fence_list);
3409 } else if (enable) {
3410 if (WARN_ON(!obj->map_and_fenceable))
3413 reg = i915_find_fence_reg(dev);
3415 return PTR_ERR(reg);
3418 struct drm_i915_gem_object *old = reg->obj;
3420 ret = i915_gem_object_wait_fence(old);
3424 i915_gem_object_fence_lost(old);
3429 i915_gem_object_update_fence(obj, reg, enable);
3434 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3435 unsigned long cache_level)
3437 struct drm_mm_node *gtt_space = &vma->node;
3438 struct drm_mm_node *other;
3441 * On some machines we have to be careful when putting differing types
3442 * of snoopable memory together to avoid the prefetcher crossing memory
3443 * domains and dying. During vm initialisation, we decide whether or not
3444 * these constraints apply and set the drm_mm.color_adjust
3447 if (vma->vm->mm.color_adjust == NULL)
3450 if (!drm_mm_node_allocated(gtt_space))
3453 if (list_empty(>t_space->node_list))
3456 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3457 if (other->allocated && !other->hole_follows && other->color != cache_level)
3460 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3461 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3468 * Finds free space in the GTT aperture and binds the object there.
3470 static struct i915_vma *
3471 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3472 struct i915_address_space *vm,
3476 struct drm_device *dev = obj->base.dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 u32 size, fence_size, fence_alignment, unfenced_alignment;
3479 unsigned long start =
3480 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3482 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3483 struct i915_vma *vma;
3486 fence_size = i915_gem_get_gtt_size(dev,
3489 fence_alignment = i915_gem_get_gtt_alignment(dev,
3491 obj->tiling_mode, true);
3492 unfenced_alignment =
3493 i915_gem_get_gtt_alignment(dev,
3495 obj->tiling_mode, false);
3498 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3500 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3501 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3502 return ERR_PTR(-EINVAL);
3505 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3507 /* If the object is bigger than the entire aperture, reject it early
3508 * before evicting everything in a vain attempt to find space.
3510 if (obj->base.size > end) {
3511 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3513 flags & PIN_MAPPABLE ? "mappable" : "total",
3515 return ERR_PTR(-E2BIG);
3518 ret = i915_gem_object_get_pages(obj);
3520 return ERR_PTR(ret);
3522 i915_gem_object_pin_pages(obj);
3524 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3529 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3533 DRM_MM_SEARCH_DEFAULT,
3534 DRM_MM_CREATE_DEFAULT);
3536 ret = i915_gem_evict_something(dev, vm, size, alignment,
3545 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3547 goto err_remove_node;
3550 ret = i915_gem_gtt_prepare_object(obj);
3552 goto err_remove_node;
3554 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3555 list_add_tail(&vma->mm_list, &vm->inactive_list);
3557 trace_i915_vma_bind(vma, flags);
3558 vma->bind_vma(vma, obj->cache_level,
3559 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3564 drm_mm_remove_node(&vma->node);
3566 i915_gem_vma_destroy(vma);
3569 i915_gem_object_unpin_pages(obj);
3574 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3577 /* If we don't have a page list set up, then we're not pinned
3578 * to GPU, and we can ignore the cache flush because it'll happen
3579 * again at bind time.
3581 if (obj->pages == NULL)
3585 * Stolen memory is always coherent with the GPU as it is explicitly
3586 * marked as wc by the system, or the system is cache-coherent.
3588 if (obj->stolen || obj->phys_handle)
3591 /* If the GPU is snooping the contents of the CPU cache,
3592 * we do not need to manually clear the CPU cache lines. However,
3593 * the caches are only snooped when the render cache is
3594 * flushed/invalidated. As we always have to emit invalidations
3595 * and flushes when moving into and out of the RENDER domain, correct
3596 * snooping behaviour occurs naturally as the result of our domain
3599 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3602 trace_i915_gem_object_clflush(obj);
3603 drm_clflush_sg(obj->pages);
3608 /** Flushes the GTT write domain for the object if it's dirty. */
3610 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3612 uint32_t old_write_domain;
3614 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3617 /* No actual flushing is required for the GTT write domain. Writes
3618 * to it immediately go to main memory as far as we know, so there's
3619 * no chipset flush. It also doesn't land in render cache.
3621 * However, we do have to enforce the order so that all writes through
3622 * the GTT land before any writes to the device, such as updates to
3627 old_write_domain = obj->base.write_domain;
3628 obj->base.write_domain = 0;
3630 intel_fb_obj_flush(obj, false);
3632 trace_i915_gem_object_change_domain(obj,
3633 obj->base.read_domains,
3637 /** Flushes the CPU write domain for the object if it's dirty. */
3639 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3642 uint32_t old_write_domain;
3644 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3647 if (i915_gem_clflush_object(obj, force))
3648 i915_gem_chipset_flush(obj->base.dev);
3650 old_write_domain = obj->base.write_domain;
3651 obj->base.write_domain = 0;
3653 intel_fb_obj_flush(obj, false);
3655 trace_i915_gem_object_change_domain(obj,
3656 obj->base.read_domains,
3661 * Moves a single object to the GTT read, and possibly write domain.
3663 * This function returns when the move is complete, including waiting on
3667 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3669 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3670 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3671 uint32_t old_write_domain, old_read_domains;
3674 /* Not valid to be called on unbound objects. */
3678 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3681 ret = i915_gem_object_wait_rendering(obj, !write);
3685 i915_gem_object_retire(obj);
3686 i915_gem_object_flush_cpu_write_domain(obj, false);
3688 /* Serialise direct access to this object with the barriers for
3689 * coherent writes from the GPU, by effectively invalidating the
3690 * GTT domain upon first access.
3692 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3695 old_write_domain = obj->base.write_domain;
3696 old_read_domains = obj->base.read_domains;
3698 /* It should now be out of any other write domains, and we can update
3699 * the domain values for our changes.
3701 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3702 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3704 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3705 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3710 intel_fb_obj_invalidate(obj, NULL);
3712 trace_i915_gem_object_change_domain(obj,
3716 /* And bump the LRU for this access */
3717 if (i915_gem_object_is_inactive(obj))
3718 list_move_tail(&vma->mm_list,
3719 &dev_priv->gtt.base.inactive_list);
3724 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3725 enum i915_cache_level cache_level)
3727 struct drm_device *dev = obj->base.dev;
3728 struct i915_vma *vma, *next;
3731 if (obj->cache_level == cache_level)
3734 if (i915_gem_obj_is_pinned(obj)) {
3735 DRM_DEBUG("can not change the cache level of pinned objects\n");
3739 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3740 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3741 ret = i915_vma_unbind(vma);
3747 if (i915_gem_obj_bound_any(obj)) {
3748 ret = i915_gem_object_finish_gpu(obj);
3752 i915_gem_object_finish_gtt(obj);
3754 /* Before SandyBridge, you could not use tiling or fence
3755 * registers with snooped memory, so relinquish any fences
3756 * currently pointing to our region in the aperture.
3758 if (INTEL_INFO(dev)->gen < 6) {
3759 ret = i915_gem_object_put_fence(obj);
3764 list_for_each_entry(vma, &obj->vma_list, vma_link)
3765 if (drm_mm_node_allocated(&vma->node))
3766 vma->bind_vma(vma, cache_level,
3767 vma->bound & GLOBAL_BIND);
3770 list_for_each_entry(vma, &obj->vma_list, vma_link)
3771 vma->node.color = cache_level;
3772 obj->cache_level = cache_level;
3774 if (cpu_write_needs_clflush(obj)) {
3775 u32 old_read_domains, old_write_domain;
3777 /* If we're coming from LLC cached, then we haven't
3778 * actually been tracking whether the data is in the
3779 * CPU cache or not, since we only allow one bit set
3780 * in obj->write_domain and have been skipping the clflushes.
3781 * Just set it to the CPU cache for now.
3783 i915_gem_object_retire(obj);
3784 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3786 old_read_domains = obj->base.read_domains;
3787 old_write_domain = obj->base.write_domain;
3789 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3790 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3792 trace_i915_gem_object_change_domain(obj,
3800 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3801 struct drm_file *file)
3803 struct drm_i915_gem_caching *args = data;
3804 struct drm_i915_gem_object *obj;
3807 ret = i915_mutex_lock_interruptible(dev);
3811 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3812 if (&obj->base == NULL) {
3817 switch (obj->cache_level) {
3818 case I915_CACHE_LLC:
3819 case I915_CACHE_L3_LLC:
3820 args->caching = I915_CACHING_CACHED;
3824 args->caching = I915_CACHING_DISPLAY;
3828 args->caching = I915_CACHING_NONE;
3832 drm_gem_object_unreference(&obj->base);
3834 mutex_unlock(&dev->struct_mutex);
3838 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3839 struct drm_file *file)
3841 struct drm_i915_gem_caching *args = data;
3842 struct drm_i915_gem_object *obj;
3843 enum i915_cache_level level;
3846 switch (args->caching) {
3847 case I915_CACHING_NONE:
3848 level = I915_CACHE_NONE;
3850 case I915_CACHING_CACHED:
3851 level = I915_CACHE_LLC;
3853 case I915_CACHING_DISPLAY:
3854 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3860 ret = i915_mutex_lock_interruptible(dev);
3864 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3865 if (&obj->base == NULL) {
3870 ret = i915_gem_object_set_cache_level(obj, level);
3872 drm_gem_object_unreference(&obj->base);
3874 mutex_unlock(&dev->struct_mutex);
3878 static bool is_pin_display(struct drm_i915_gem_object *obj)
3880 struct i915_vma *vma;
3882 vma = i915_gem_obj_to_ggtt(obj);
3886 /* There are 3 sources that pin objects:
3887 * 1. The display engine (scanouts, sprites, cursors);
3888 * 2. Reservations for execbuffer;
3891 * We can ignore reservations as we hold the struct_mutex and
3892 * are only called outside of the reservation path. The user
3893 * can only increment pin_count once, and so if after
3894 * subtracting the potential reference by the user, any pin_count
3895 * remains, it must be due to another use by the display engine.
3897 return vma->pin_count - !!obj->user_pin_count;
3901 * Prepare buffer for display plane (scanout, cursors, etc).
3902 * Can be called from an uninterruptible phase (modesetting) and allows
3903 * any flushes to be pipelined (for pageflips).
3906 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3908 struct intel_engine_cs *pipelined)
3910 u32 old_read_domains, old_write_domain;
3911 bool was_pin_display;
3914 if (pipelined != obj->ring) {
3915 ret = i915_gem_object_sync(obj, pipelined);
3920 /* Mark the pin_display early so that we account for the
3921 * display coherency whilst setting up the cache domains.
3923 was_pin_display = obj->pin_display;
3924 obj->pin_display = true;
3926 /* The display engine is not coherent with the LLC cache on gen6. As
3927 * a result, we make sure that the pinning that is about to occur is
3928 * done with uncached PTEs. This is lowest common denominator for all
3931 * However for gen6+, we could do better by using the GFDT bit instead
3932 * of uncaching, which would allow us to flush all the LLC-cached data
3933 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3935 ret = i915_gem_object_set_cache_level(obj,
3936 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3938 goto err_unpin_display;
3940 /* As the user may map the buffer once pinned in the display plane
3941 * (e.g. libkms for the bootup splash), we have to ensure that we
3942 * always use map_and_fenceable for all scanout buffers.
3944 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3946 goto err_unpin_display;
3948 i915_gem_object_flush_cpu_write_domain(obj, true);
3950 old_write_domain = obj->base.write_domain;
3951 old_read_domains = obj->base.read_domains;
3953 /* It should now be out of any other write domains, and we can update
3954 * the domain values for our changes.
3956 obj->base.write_domain = 0;
3957 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3959 trace_i915_gem_object_change_domain(obj,
3966 WARN_ON(was_pin_display != is_pin_display(obj));
3967 obj->pin_display = was_pin_display;
3972 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3974 i915_gem_object_ggtt_unpin(obj);
3975 obj->pin_display = is_pin_display(obj);
3979 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3983 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3986 ret = i915_gem_object_wait_rendering(obj, false);
3990 /* Ensure that we invalidate the GPU's caches and TLBs. */
3991 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3996 * Moves a single object to the CPU read, and possibly write domain.
3998 * This function returns when the move is complete, including waiting on
4002 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4004 uint32_t old_write_domain, old_read_domains;
4007 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4010 ret = i915_gem_object_wait_rendering(obj, !write);
4014 i915_gem_object_retire(obj);
4015 i915_gem_object_flush_gtt_write_domain(obj);
4017 old_write_domain = obj->base.write_domain;
4018 old_read_domains = obj->base.read_domains;
4020 /* Flush the CPU cache if it's still invalid. */
4021 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4022 i915_gem_clflush_object(obj, false);
4024 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4027 /* It should now be out of any other write domains, and we can update
4028 * the domain values for our changes.
4030 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4032 /* If we're writing through the CPU, then the GPU read domains will
4033 * need to be invalidated at next use.
4036 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4037 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4041 intel_fb_obj_invalidate(obj, NULL);
4043 trace_i915_gem_object_change_domain(obj,
4050 /* Throttle our rendering by waiting until the ring has completed our requests
4051 * emitted over 20 msec ago.
4053 * Note that if we were to use the current jiffies each time around the loop,
4054 * we wouldn't escape the function with any frames outstanding if the time to
4055 * render a frame was over 20ms.
4057 * This should get us reasonable parallelism between CPU and GPU but also
4058 * relatively low latency when blocking on a particular request to finish.
4061 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4064 struct drm_i915_file_private *file_priv = file->driver_priv;
4065 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4066 struct drm_i915_gem_request *request;
4067 struct intel_engine_cs *ring = NULL;
4068 unsigned reset_counter;
4072 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4076 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4080 spin_lock(&file_priv->mm.lock);
4081 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4082 if (time_after_eq(request->emitted_jiffies, recent_enough))
4085 ring = request->ring;
4086 seqno = request->seqno;
4088 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4089 spin_unlock(&file_priv->mm.lock);
4094 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4096 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4102 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4104 struct drm_i915_gem_object *obj = vma->obj;
4107 vma->node.start & (alignment - 1))
4110 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4113 if (flags & PIN_OFFSET_BIAS &&
4114 vma->node.start < (flags & PIN_OFFSET_MASK))
4121 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4122 struct i915_address_space *vm,
4126 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4127 struct i915_vma *vma;
4131 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4134 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4137 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4140 vma = i915_gem_obj_to_vma(obj, vm);
4142 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4145 if (i915_vma_misplaced(vma, alignment, flags)) {
4146 WARN(vma->pin_count,
4147 "bo is already pinned with incorrect alignment:"
4148 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4149 " obj->map_and_fenceable=%d\n",
4150 i915_gem_obj_offset(obj, vm), alignment,
4151 !!(flags & PIN_MAPPABLE),
4152 obj->map_and_fenceable);
4153 ret = i915_vma_unbind(vma);
4161 bound = vma ? vma->bound : 0;
4162 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4163 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4165 return PTR_ERR(vma);
4168 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4169 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4171 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4172 bool mappable, fenceable;
4173 u32 fence_size, fence_alignment;
4175 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4178 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4183 fenceable = (vma->node.size == fence_size &&
4184 (vma->node.start & (fence_alignment - 1)) == 0);
4186 mappable = (vma->node.start + obj->base.size <=
4187 dev_priv->gtt.mappable_end);
4189 obj->map_and_fenceable = mappable && fenceable;
4192 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4195 if (flags & PIN_MAPPABLE)
4196 obj->pin_mappable |= true;
4202 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4204 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4207 BUG_ON(vma->pin_count == 0);
4208 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4210 if (--vma->pin_count == 0)
4211 obj->pin_mappable = false;
4215 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4217 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4218 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4219 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4221 WARN_ON(!ggtt_vma ||
4222 dev_priv->fence_regs[obj->fence_reg].pin_count >
4223 ggtt_vma->pin_count);
4224 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4231 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4233 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4234 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4235 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4236 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4241 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4242 struct drm_file *file)
4244 struct drm_i915_gem_pin *args = data;
4245 struct drm_i915_gem_object *obj;
4248 if (INTEL_INFO(dev)->gen >= 6)
4251 ret = i915_mutex_lock_interruptible(dev);
4255 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4256 if (&obj->base == NULL) {
4261 if (obj->madv != I915_MADV_WILLNEED) {
4262 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4267 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4268 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4274 if (obj->user_pin_count == ULONG_MAX) {
4279 if (obj->user_pin_count == 0) {
4280 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4285 obj->user_pin_count++;
4286 obj->pin_filp = file;
4288 args->offset = i915_gem_obj_ggtt_offset(obj);
4290 drm_gem_object_unreference(&obj->base);
4292 mutex_unlock(&dev->struct_mutex);
4297 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4298 struct drm_file *file)
4300 struct drm_i915_gem_pin *args = data;
4301 struct drm_i915_gem_object *obj;
4304 ret = i915_mutex_lock_interruptible(dev);
4308 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4309 if (&obj->base == NULL) {
4314 if (obj->pin_filp != file) {
4315 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4320 obj->user_pin_count--;
4321 if (obj->user_pin_count == 0) {
4322 obj->pin_filp = NULL;
4323 i915_gem_object_ggtt_unpin(obj);
4327 drm_gem_object_unreference(&obj->base);
4329 mutex_unlock(&dev->struct_mutex);
4334 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4335 struct drm_file *file)
4337 struct drm_i915_gem_busy *args = data;
4338 struct drm_i915_gem_object *obj;
4341 ret = i915_mutex_lock_interruptible(dev);
4345 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4346 if (&obj->base == NULL) {
4351 /* Count all active objects as busy, even if they are currently not used
4352 * by the gpu. Users of this interface expect objects to eventually
4353 * become non-busy without any further actions, therefore emit any
4354 * necessary flushes here.
4356 ret = i915_gem_object_flush_active(obj);
4358 args->busy = obj->active;
4360 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4361 args->busy |= intel_ring_flag(obj->ring) << 16;
4364 drm_gem_object_unreference(&obj->base);
4366 mutex_unlock(&dev->struct_mutex);
4371 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4372 struct drm_file *file_priv)
4374 return i915_gem_ring_throttle(dev, file_priv);
4378 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4379 struct drm_file *file_priv)
4381 struct drm_i915_private *dev_priv = dev->dev_private;
4382 struct drm_i915_gem_madvise *args = data;
4383 struct drm_i915_gem_object *obj;
4386 switch (args->madv) {
4387 case I915_MADV_DONTNEED:
4388 case I915_MADV_WILLNEED:
4394 ret = i915_mutex_lock_interruptible(dev);
4398 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4399 if (&obj->base == NULL) {
4404 if (i915_gem_obj_is_pinned(obj)) {
4410 obj->tiling_mode != I915_TILING_NONE &&
4411 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4412 if (obj->madv == I915_MADV_WILLNEED)
4413 i915_gem_object_unpin_pages(obj);
4414 if (args->madv == I915_MADV_WILLNEED)
4415 i915_gem_object_pin_pages(obj);
4418 if (obj->madv != __I915_MADV_PURGED)
4419 obj->madv = args->madv;
4421 /* if the object is no longer attached, discard its backing storage */
4422 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4423 i915_gem_object_truncate(obj);
4425 args->retained = obj->madv != __I915_MADV_PURGED;
4428 drm_gem_object_unreference(&obj->base);
4430 mutex_unlock(&dev->struct_mutex);
4434 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4435 const struct drm_i915_gem_object_ops *ops)
4437 INIT_LIST_HEAD(&obj->global_list);
4438 INIT_LIST_HEAD(&obj->ring_list);
4439 INIT_LIST_HEAD(&obj->obj_exec_link);
4440 INIT_LIST_HEAD(&obj->vma_list);
4444 obj->fence_reg = I915_FENCE_REG_NONE;
4445 obj->madv = I915_MADV_WILLNEED;
4447 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4450 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4451 .get_pages = i915_gem_object_get_pages_gtt,
4452 .put_pages = i915_gem_object_put_pages_gtt,
4455 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4458 struct drm_i915_gem_object *obj;
4459 struct address_space *mapping;
4462 obj = i915_gem_object_alloc(dev);
4466 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4467 i915_gem_object_free(obj);
4471 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4472 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4473 /* 965gm cannot relocate objects above 4GiB. */
4474 mask &= ~__GFP_HIGHMEM;
4475 mask |= __GFP_DMA32;
4478 mapping = file_inode(obj->base.filp)->i_mapping;
4479 mapping_set_gfp_mask(mapping, mask);
4481 i915_gem_object_init(obj, &i915_gem_object_ops);
4483 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4484 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4487 /* On some devices, we can have the GPU use the LLC (the CPU
4488 * cache) for about a 10% performance improvement
4489 * compared to uncached. Graphics requests other than
4490 * display scanout are coherent with the CPU in
4491 * accessing this cache. This means in this mode we
4492 * don't need to clflush on the CPU side, and on the
4493 * GPU side we only need to flush internal caches to
4494 * get data visible to the CPU.
4496 * However, we maintain the display planes as UC, and so
4497 * need to rebind when first used as such.
4499 obj->cache_level = I915_CACHE_LLC;
4501 obj->cache_level = I915_CACHE_NONE;
4503 trace_i915_gem_object_create(obj);
4508 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4510 /* If we are the last user of the backing storage (be it shmemfs
4511 * pages or stolen etc), we know that the pages are going to be
4512 * immediately released. In this case, we can then skip copying
4513 * back the contents from the GPU.
4516 if (obj->madv != I915_MADV_WILLNEED)
4519 if (obj->base.filp == NULL)
4522 /* At first glance, this looks racy, but then again so would be
4523 * userspace racing mmap against close. However, the first external
4524 * reference to the filp can only be obtained through the
4525 * i915_gem_mmap_ioctl() which safeguards us against the user
4526 * acquiring such a reference whilst we are in the middle of
4527 * freeing the object.
4529 return atomic_long_read(&obj->base.filp->f_count) == 1;
4532 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4534 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4535 struct drm_device *dev = obj->base.dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct i915_vma *vma, *next;
4539 intel_runtime_pm_get(dev_priv);
4541 trace_i915_gem_object_destroy(obj);
4543 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4547 ret = i915_vma_unbind(vma);
4548 if (WARN_ON(ret == -ERESTARTSYS)) {
4549 bool was_interruptible;
4551 was_interruptible = dev_priv->mm.interruptible;
4552 dev_priv->mm.interruptible = false;
4554 WARN_ON(i915_vma_unbind(vma));
4556 dev_priv->mm.interruptible = was_interruptible;
4560 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4561 * before progressing. */
4563 i915_gem_object_unpin_pages(obj);
4565 WARN_ON(obj->frontbuffer_bits);
4567 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4568 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4569 obj->tiling_mode != I915_TILING_NONE)
4570 i915_gem_object_unpin_pages(obj);
4572 if (WARN_ON(obj->pages_pin_count))
4573 obj->pages_pin_count = 0;
4574 if (discard_backing_storage(obj))
4575 obj->madv = I915_MADV_DONTNEED;
4576 i915_gem_object_put_pages(obj);
4577 i915_gem_object_free_mmap_offset(obj);
4581 if (obj->base.import_attach)
4582 drm_prime_gem_destroy(&obj->base, NULL);
4584 if (obj->ops->release)
4585 obj->ops->release(obj);
4587 drm_gem_object_release(&obj->base);
4588 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4591 i915_gem_object_free(obj);
4593 intel_runtime_pm_put(dev_priv);
4596 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4597 struct i915_address_space *vm)
4599 struct i915_vma *vma;
4600 list_for_each_entry(vma, &obj->vma_list, vma_link)
4607 void i915_gem_vma_destroy(struct i915_vma *vma)
4609 struct i915_address_space *vm = NULL;
4610 WARN_ON(vma->node.allocated);
4612 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4613 if (!list_empty(&vma->exec_list))
4618 if (!i915_is_ggtt(vm))
4619 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4621 list_del(&vma->vma_link);
4627 i915_gem_stop_ringbuffers(struct drm_device *dev)
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_engine_cs *ring;
4633 for_each_ring(ring, dev_priv, i)
4634 dev_priv->gt.stop_ring(ring);
4638 i915_gem_suspend(struct drm_device *dev)
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4643 mutex_lock(&dev->struct_mutex);
4644 ret = i915_gpu_idle(dev);
4648 i915_gem_retire_requests(dev);
4650 /* Under UMS, be paranoid and evict. */
4651 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4652 i915_gem_evict_everything(dev);
4654 i915_gem_stop_ringbuffers(dev);
4655 mutex_unlock(&dev->struct_mutex);
4657 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4658 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4659 flush_delayed_work(&dev_priv->mm.idle_work);
4664 mutex_unlock(&dev->struct_mutex);
4668 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4670 struct drm_device *dev = ring->dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4673 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4676 if (!HAS_L3_DPF(dev) || !remap_info)
4679 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4684 * Note: We do not worry about the concurrent register cacheline hang
4685 * here because no other code should access these registers other than
4686 * at initialization time.
4688 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4689 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4690 intel_ring_emit(ring, reg_base + i);
4691 intel_ring_emit(ring, remap_info[i/4]);
4694 intel_ring_advance(ring);
4699 void i915_gem_init_swizzling(struct drm_device *dev)
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4703 if (INTEL_INFO(dev)->gen < 5 ||
4704 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4707 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4708 DISP_TILE_SURFACE_SWIZZLING);
4713 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4715 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4716 else if (IS_GEN7(dev))
4717 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4718 else if (IS_GEN8(dev))
4719 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4725 intel_enable_blt(struct drm_device *dev)
4730 /* The blitter was dysfunctional on early prototypes */
4731 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4732 DRM_INFO("BLT not supported on this pre-production hardware;"
4733 " graphics performance will be degraded.\n");
4740 static void init_unused_ring(struct drm_device *dev, u32 base)
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4744 I915_WRITE(RING_CTL(base), 0);
4745 I915_WRITE(RING_HEAD(base), 0);
4746 I915_WRITE(RING_TAIL(base), 0);
4747 I915_WRITE(RING_START(base), 0);
4750 static void init_unused_rings(struct drm_device *dev)
4753 init_unused_ring(dev, PRB1_BASE);
4754 init_unused_ring(dev, SRB0_BASE);
4755 init_unused_ring(dev, SRB1_BASE);
4756 init_unused_ring(dev, SRB2_BASE);
4757 init_unused_ring(dev, SRB3_BASE);
4758 } else if (IS_GEN2(dev)) {
4759 init_unused_ring(dev, SRB0_BASE);
4760 init_unused_ring(dev, SRB1_BASE);
4761 } else if (IS_GEN3(dev)) {
4762 init_unused_ring(dev, PRB1_BASE);
4763 init_unused_ring(dev, PRB2_BASE);
4767 int i915_gem_init_rings(struct drm_device *dev)
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4773 * At least 830 can leave some of the unused rings
4774 * "active" (ie. head != tail) after resume which
4775 * will prevent c3 entry. Makes sure all unused rings
4778 init_unused_rings(dev);
4780 ret = intel_init_render_ring_buffer(dev);
4785 ret = intel_init_bsd_ring_buffer(dev);
4787 goto cleanup_render_ring;
4790 if (intel_enable_blt(dev)) {
4791 ret = intel_init_blt_ring_buffer(dev);
4793 goto cleanup_bsd_ring;
4796 if (HAS_VEBOX(dev)) {
4797 ret = intel_init_vebox_ring_buffer(dev);
4799 goto cleanup_blt_ring;
4802 if (HAS_BSD2(dev)) {
4803 ret = intel_init_bsd2_ring_buffer(dev);
4805 goto cleanup_vebox_ring;
4808 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4810 goto cleanup_bsd2_ring;
4815 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4817 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4819 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4821 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4822 cleanup_render_ring:
4823 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4829 i915_gem_init_hw(struct drm_device *dev)
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4834 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4837 if (dev_priv->ellc_size)
4838 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4840 if (IS_HASWELL(dev))
4841 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4842 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4844 if (HAS_PCH_NOP(dev)) {
4845 if (IS_IVYBRIDGE(dev)) {
4846 u32 temp = I915_READ(GEN7_MSG_CTL);
4847 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4848 I915_WRITE(GEN7_MSG_CTL, temp);
4849 } else if (INTEL_INFO(dev)->gen >= 7) {
4850 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4851 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4852 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4856 i915_gem_init_swizzling(dev);
4858 ret = dev_priv->gt.init_rings(dev);
4862 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4863 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4866 * XXX: Contexts should only be initialized once. Doing a switch to the
4867 * default context switch however is something we'd like to do after
4868 * reset or thaw (the latter may not actually be necessary for HW, but
4869 * goes with our code better). Context switching requires rings (for
4870 * the do_switch), but before enabling PPGTT. So don't move this.
4872 ret = i915_gem_context_enable(dev_priv);
4873 if (ret && ret != -EIO) {
4874 DRM_ERROR("Context enable failed %d\n", ret);
4875 i915_gem_cleanup_ringbuffer(dev);
4880 ret = i915_ppgtt_init_hw(dev);
4881 if (ret && ret != -EIO) {
4882 DRM_ERROR("PPGTT enable failed %d\n", ret);
4883 i915_gem_cleanup_ringbuffer(dev);
4889 int i915_gem_init(struct drm_device *dev)
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4894 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4895 i915.enable_execlists);
4897 mutex_lock(&dev->struct_mutex);
4899 if (IS_VALLEYVIEW(dev)) {
4900 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4901 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4902 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4903 VLV_GTLC_ALLOWWAKEACK), 10))
4904 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4907 if (!i915.enable_execlists) {
4908 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4909 dev_priv->gt.init_rings = i915_gem_init_rings;
4910 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4911 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4913 dev_priv->gt.do_execbuf = intel_execlists_submission;
4914 dev_priv->gt.init_rings = intel_logical_rings_init;
4915 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4916 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4919 ret = i915_gem_init_userptr(dev);
4921 mutex_unlock(&dev->struct_mutex);
4925 i915_gem_init_global_gtt(dev);
4927 ret = i915_gem_context_init(dev);
4929 mutex_unlock(&dev->struct_mutex);
4933 ret = i915_gem_init_hw(dev);
4935 /* Allow ring initialisation to fail by marking the GPU as
4936 * wedged. But we only want to do this where the GPU is angry,
4937 * for all other failure, such as an allocation failure, bail.
4939 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4940 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4943 mutex_unlock(&dev->struct_mutex);
4949 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952 struct intel_engine_cs *ring;
4955 for_each_ring(ring, dev_priv, i)
4956 dev_priv->gt.cleanup_ring(ring);
4960 init_ring_lists(struct intel_engine_cs *ring)
4962 INIT_LIST_HEAD(&ring->active_list);
4963 INIT_LIST_HEAD(&ring->request_list);
4966 void i915_init_vm(struct drm_i915_private *dev_priv,
4967 struct i915_address_space *vm)
4969 if (!i915_is_ggtt(vm))
4970 drm_mm_init(&vm->mm, vm->start, vm->total);
4971 vm->dev = dev_priv->dev;
4972 INIT_LIST_HEAD(&vm->active_list);
4973 INIT_LIST_HEAD(&vm->inactive_list);
4974 INIT_LIST_HEAD(&vm->global_link);
4975 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4979 i915_gem_load(struct drm_device *dev)
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4985 kmem_cache_create("i915_gem_object",
4986 sizeof(struct drm_i915_gem_object), 0,
4990 INIT_LIST_HEAD(&dev_priv->vm_list);
4991 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4993 INIT_LIST_HEAD(&dev_priv->context_list);
4994 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4995 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4996 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4997 for (i = 0; i < I915_NUM_RINGS; i++)
4998 init_ring_lists(&dev_priv->ring[i]);
4999 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5000 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5001 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5002 i915_gem_retire_work_handler);
5003 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5004 i915_gem_idle_work_handler);
5005 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5007 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5008 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5009 I915_WRITE(MI_ARB_STATE,
5010 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5013 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5015 /* Old X drivers will take 0-2 for front, back, depth buffers */
5016 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5017 dev_priv->fence_reg_start = 3;
5019 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5020 dev_priv->num_fence_regs = 32;
5021 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5022 dev_priv->num_fence_regs = 16;
5024 dev_priv->num_fence_regs = 8;
5026 /* Initialize fence registers to zero */
5027 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5028 i915_gem_restore_fences(dev);
5030 i915_gem_detect_bit_6_swizzle(dev);
5031 init_waitqueue_head(&dev_priv->pending_flip_queue);
5033 dev_priv->mm.interruptible = true;
5035 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5036 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5037 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5038 register_shrinker(&dev_priv->mm.shrinker);
5040 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5041 register_oom_notifier(&dev_priv->mm.oom_notifier);
5043 mutex_init(&dev_priv->fb_tracking.lock);
5046 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5048 struct drm_i915_file_private *file_priv = file->driver_priv;
5050 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5052 /* Clean up our request list when the client is going away, so that
5053 * later retire_requests won't dereference our soon-to-be-gone
5056 spin_lock(&file_priv->mm.lock);
5057 while (!list_empty(&file_priv->mm.request_list)) {
5058 struct drm_i915_gem_request *request;
5060 request = list_first_entry(&file_priv->mm.request_list,
5061 struct drm_i915_gem_request,
5063 list_del(&request->client_list);
5064 request->file_priv = NULL;
5066 spin_unlock(&file_priv->mm.lock);
5070 i915_gem_file_idle_work_handler(struct work_struct *work)
5072 struct drm_i915_file_private *file_priv =
5073 container_of(work, typeof(*file_priv), mm.idle_work.work);
5075 atomic_set(&file_priv->rps_wait_boost, false);
5078 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5080 struct drm_i915_file_private *file_priv;
5083 DRM_DEBUG_DRIVER("\n");
5085 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5089 file->driver_priv = file_priv;
5090 file_priv->dev_priv = dev->dev_private;
5091 file_priv->file = file;
5093 spin_lock_init(&file_priv->mm.lock);
5094 INIT_LIST_HEAD(&file_priv->mm.request_list);
5095 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5096 i915_gem_file_idle_work_handler);
5098 ret = i915_gem_context_open(dev, file);
5106 * i915_gem_track_fb - update frontbuffer tracking
5107 * old: current GEM buffer for the frontbuffer slots
5108 * new: new GEM buffer for the frontbuffer slots
5109 * frontbuffer_bits: bitmask of frontbuffer slots
5111 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5112 * from @old and setting them in @new. Both @old and @new can be NULL.
5114 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5115 struct drm_i915_gem_object *new,
5116 unsigned frontbuffer_bits)
5119 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5120 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5121 old->frontbuffer_bits &= ~frontbuffer_bits;
5125 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5126 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5127 new->frontbuffer_bits |= frontbuffer_bits;
5131 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5133 if (!mutex_is_locked(mutex))
5136 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5137 return mutex->owner == task;
5139 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5144 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5146 if (!mutex_trylock(&dev->struct_mutex)) {
5147 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5150 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5160 static int num_vma_bound(struct drm_i915_gem_object *obj)
5162 struct i915_vma *vma;
5165 list_for_each_entry(vma, &obj->vma_list, vma_link)
5166 if (drm_mm_node_allocated(&vma->node))
5172 static unsigned long
5173 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5175 struct drm_i915_private *dev_priv =
5176 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5177 struct drm_device *dev = dev_priv->dev;
5178 struct drm_i915_gem_object *obj;
5179 unsigned long count;
5182 if (!i915_gem_shrinker_lock(dev, &unlock))
5186 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5187 if (obj->pages_pin_count == 0)
5188 count += obj->base.size >> PAGE_SHIFT;
5190 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5191 if (!i915_gem_obj_is_pinned(obj) &&
5192 obj->pages_pin_count == num_vma_bound(obj))
5193 count += obj->base.size >> PAGE_SHIFT;
5197 mutex_unlock(&dev->struct_mutex);
5202 /* All the new VM stuff */
5203 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5204 struct i915_address_space *vm)
5206 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5207 struct i915_vma *vma;
5209 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5211 list_for_each_entry(vma, &o->vma_list, vma_link) {
5213 return vma->node.start;
5216 WARN(1, "%s vma for this object not found.\n",
5217 i915_is_ggtt(vm) ? "global" : "ppgtt");
5221 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5222 struct i915_address_space *vm)
5224 struct i915_vma *vma;
5226 list_for_each_entry(vma, &o->vma_list, vma_link)
5227 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5233 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5235 struct i915_vma *vma;
5237 list_for_each_entry(vma, &o->vma_list, vma_link)
5238 if (drm_mm_node_allocated(&vma->node))
5244 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5245 struct i915_address_space *vm)
5247 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5248 struct i915_vma *vma;
5250 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5252 BUG_ON(list_empty(&o->vma_list));
5254 list_for_each_entry(vma, &o->vma_list, vma_link)
5256 return vma->node.size;
5261 static unsigned long
5262 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5264 struct drm_i915_private *dev_priv =
5265 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5266 struct drm_device *dev = dev_priv->dev;
5267 unsigned long freed;
5270 if (!i915_gem_shrinker_lock(dev, &unlock))
5273 freed = i915_gem_shrink(dev_priv,
5276 I915_SHRINK_UNBOUND |
5277 I915_SHRINK_PURGEABLE);
5278 if (freed < sc->nr_to_scan)
5279 freed += i915_gem_shrink(dev_priv,
5280 sc->nr_to_scan - freed,
5282 I915_SHRINK_UNBOUND);
5284 mutex_unlock(&dev->struct_mutex);
5290 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5292 struct drm_i915_private *dev_priv =
5293 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5294 struct drm_device *dev = dev_priv->dev;
5295 struct drm_i915_gem_object *obj;
5296 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5297 unsigned long pinned, bound, unbound, freed_pages;
5298 bool was_interruptible;
5301 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5302 schedule_timeout_killable(1);
5303 if (fatal_signal_pending(current))
5307 pr_err("Unable to purge GPU memory due lock contention.\n");
5311 was_interruptible = dev_priv->mm.interruptible;
5312 dev_priv->mm.interruptible = false;
5314 freed_pages = i915_gem_shrink_all(dev_priv);
5316 dev_priv->mm.interruptible = was_interruptible;
5318 /* Because we may be allocating inside our own driver, we cannot
5319 * assert that there are no objects with pinned pages that are not
5320 * being pointed to by hardware.
5322 unbound = bound = pinned = 0;
5323 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5324 if (!obj->base.filp) /* not backed by a freeable object */
5327 if (obj->pages_pin_count)
5328 pinned += obj->base.size;
5330 unbound += obj->base.size;
5332 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5333 if (!obj->base.filp)
5336 if (obj->pages_pin_count)
5337 pinned += obj->base.size;
5339 bound += obj->base.size;
5343 mutex_unlock(&dev->struct_mutex);
5345 if (freed_pages || unbound || bound)
5346 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5347 freed_pages << PAGE_SHIFT, pinned);
5348 if (unbound || bound)
5349 pr_err("%lu and %lu bytes still available in the "
5350 "bound and unbound GPU page lists.\n",
5353 *(unsigned long *)ptr += freed_pages;
5357 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5359 struct i915_vma *vma;
5361 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5362 if (vma->vm != i915_obj_to_ggtt(obj))