drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                              bool write);
  43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                      uint64_t offset,
  45                                                      uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                        unsigned alignment,
  49                                        bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     int nr_to_scan,
  60                                     gfp_t gfp_mask);
  61
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 int
  79 i915_gem_check_is_wedged(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         /* Success, we reset the GPU! */
  94         if (!atomic_read(&dev_priv->mm.wedged))
  95                 return 0;
  96
  97         /* GPU is hung, bump the completion count to account for
  98          * the token we just consumed so that we never hit zero and
  99          * end up waiting upon a subsequent completion event that
 100          * will never happen.
 101          */
 102         spin_lock_irqsave(&x->wait.lock, flags);
 103         x->done++;
 104         spin_unlock_irqrestore(&x->wait.lock, flags);
 105         return -EIO;
 106 }
 107
 108 int i915_mutex_lock_interruptible(struct drm_device *dev)
 109 {
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         int ret;
 112
 113         ret = i915_gem_check_is_wedged(dev);
 114         if (ret)
 115                 return ret;
 116
 117         ret = mutex_lock_interruptible(&dev->struct_mutex);
 118         if (ret)
 119                 return ret;
 120
 121         if (atomic_read(&dev_priv->mm.wedged)) {
 122                 mutex_unlock(&dev->struct_mutex);
 123                 return -EAGAIN;
 124         }
 125
 126         WARN_ON(i915_verify_lists(dev));
 127         return 0;
 128 }
 129
 130 static inline bool
 131 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 132 {
 133         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 134 }
 135
 136 void i915_gem_do_init(struct drm_device *dev,
 137                       unsigned long start,
 138                       unsigned long mappable_end,
 139                       unsigned long end)
 140 {
 141         drm_i915_private_t *dev_priv = dev->dev_private;
 142
 143         drm_mm_init(&dev_priv->mm.gtt_space, start,
 144                     end - start);
 145
 146         dev_priv->mm.gtt_total = end - start;
 147         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 148         dev_priv->mm.gtt_mappable_end = mappable_end;
 149 }
 150
 151 int
 152 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 153                     struct drm_file *file)
 154 {
 155         struct drm_i915_gem_init *args = data;
 156
 157         if (args->gtt_start >= args->gtt_end ||
 158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 159                 return -EINVAL;
 160
 161         mutex_lock(&dev->struct_mutex);
 162         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         if (!(dev->driver->driver_features & DRIVER_GEM))
 178                 return -ENODEV;
 179
 180         pinned = 0;
 181         mutex_lock(&dev->struct_mutex);
 182         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 183                 pinned += obj->gtt_space->size;
 184         mutex_unlock(&dev->struct_mutex);
 185
 186         args->aper_size = dev_priv->mm.gtt_total;
 187         args->aper_available_size = args->aper_size -pinned;
 188
 189         return 0;
 190 }
 191
 192 /**
 193  * Creates a new mm object and returns a handle to it.
 194  */
 195 int
 196 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 197                       struct drm_file *file)
 198 {
 199         struct drm_i915_gem_create *args = data;
 200         struct drm_i915_gem_object *obj;
 201         int ret;
 202         u32 handle;
 203
 204         args->size = roundup(args->size, PAGE_SIZE);
 205
 206         /* Allocate the new object */
 207         obj = i915_gem_alloc_object(dev, args->size);
 208         if (obj == NULL)
 209                 return -ENOMEM;
 210
 211         ret = drm_gem_handle_create(file, &obj->base, &handle);
 212         if (ret) {
 213                 drm_gem_object_release(&obj->base);
 214                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 215                 kfree(obj);
 216                 return ret;
 217         }
 218
 219         /* drop reference from allocate - handle holds it now */
 220         drm_gem_object_unreference(&obj->base);
 221         trace_i915_gem_object_create(obj);
 222
 223         args->handle = handle;
 224         return 0;
 225 }
 226
 227 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 228 {
 229         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 230
 231         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 232                 obj->tiling_mode != I915_TILING_NONE;
 233 }
 234
 235 static inline void
 236 slow_shmem_copy(struct page *dst_page,
 237                 int dst_offset,
 238                 struct page *src_page,
 239                 int src_offset,
 240                 int length)
 241 {
 242         char *dst_vaddr, *src_vaddr;
 243
 244         dst_vaddr = kmap(dst_page);
 245         src_vaddr = kmap(src_page);
 246
 247         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 248
 249         kunmap(src_page);
 250         kunmap(dst_page);
 251 }
 252
 253 static inline void
 254 slow_shmem_bit17_copy(struct page *gpu_page,
 255                       int gpu_offset,
 256                       struct page *cpu_page,
 257                       int cpu_offset,
 258                       int length,
 259                       int is_read)
 260 {
 261         char *gpu_vaddr, *cpu_vaddr;
 262
 263         /* Use the unswizzled path if this page isn't affected. */
 264         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 265                 if (is_read)
 266                         return slow_shmem_copy(cpu_page, cpu_offset,
 267                                                gpu_page, gpu_offset, length);
 268                 else
 269                         return slow_shmem_copy(gpu_page, gpu_offset,
 270                                                cpu_page, cpu_offset, length);
 271         }
 272
 273         gpu_vaddr = kmap(gpu_page);
 274         cpu_vaddr = kmap(cpu_page);
 275
 276         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 277          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 278          */
 279         while (length > 0) {
 280                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 281                 int this_length = min(cacheline_end - gpu_offset, length);
 282                 int swizzled_gpu_offset = gpu_offset ^ 64;
 283
 284                 if (is_read) {
 285                         memcpy(cpu_vaddr + cpu_offset,
 286                                gpu_vaddr + swizzled_gpu_offset,
 287                                this_length);
 288                 } else {
 289                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 290                                cpu_vaddr + cpu_offset,
 291                                this_length);
 292                 }
 293                 cpu_offset += this_length;
 294                 gpu_offset += this_length;
 295                 length -= this_length;
 296         }
 297
 298         kunmap(cpu_page);
 299         kunmap(gpu_page);
 300 }
 301
 302 /**
 303  * This is the fast shmem pread path, which attempts to copy_from_user directly
 304  * from the backing pages of the object to the user's address space.  On a
 305  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 306  */
 307 static int
 308 i915_gem_shmem_pread_fast(struct drm_device *dev,
 309                           struct drm_i915_gem_object *obj,
 310                           struct drm_i915_gem_pread *args,
 311                           struct drm_file *file)
 312 {
 313         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 314         ssize_t remain;
 315         loff_t offset;
 316         char __user *user_data;
 317         int page_offset, page_length;
 318
 319         user_data = (char __user *) (uintptr_t) args->data_ptr;
 320         remain = args->size;
 321
 322         offset = args->offset;
 323
 324         while (remain > 0) {
 325                 struct page *page;
 326                 char *vaddr;
 327                 int ret;
 328
 329                 /* Operation in this page
 330                  *
 331                  * page_offset = offset within page
 332                  * page_length = bytes to copy for this page
 333                  */
 334                 page_offset = offset & (PAGE_SIZE-1);
 335                 page_length = remain;
 336                 if ((page_offset + remain) > PAGE_SIZE)
 337                         page_length = PAGE_SIZE - page_offset;
 338
 339                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 340                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 341                 if (IS_ERR(page))
 342                         return PTR_ERR(page);
 343
 344                 vaddr = kmap_atomic(page);
 345                 ret = __copy_to_user_inatomic(user_data,
 346                                               vaddr + page_offset,
 347                                               page_length);
 348                 kunmap_atomic(vaddr);
 349
 350                 mark_page_accessed(page);
 351                 page_cache_release(page);
 352                 if (ret)
 353                         return -EFAULT;
 354
 355                 remain -= page_length;
 356                 user_data += page_length;
 357                 offset += page_length;
 358         }
 359
 360         return 0;
 361 }
 362
 363 /**
 364  * This is the fallback shmem pread path, which allocates temporary storage
 365  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 366  * can copy out of the object's backing pages while holding the struct mutex
 367  * and not take page faults.
 368  */
 369 static int
 370 i915_gem_shmem_pread_slow(struct drm_device *dev,
 371                           struct drm_i915_gem_object *obj,
 372                           struct drm_i915_gem_pread *args,
 373                           struct drm_file *file)
 374 {
 375         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 376         struct mm_struct *mm = current->mm;
 377         struct page **user_pages;
 378         ssize_t remain;
 379         loff_t offset, pinned_pages, i;
 380         loff_t first_data_page, last_data_page, num_pages;
 381         int shmem_page_offset;
 382         int data_page_index, data_page_offset;
 383         int page_length;
 384         int ret;
 385         uint64_t data_ptr = args->data_ptr;
 386         int do_bit17_swizzling;
 387
 388         remain = args->size;
 389
 390         /* Pin the user pages containing the data.  We can't fault while
 391          * holding the struct mutex, yet we want to hold it while
 392          * dereferencing the user data.
 393          */
 394         first_data_page = data_ptr / PAGE_SIZE;
 395         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 396         num_pages = last_data_page - first_data_page + 1;
 397
 398         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 399         if (user_pages == NULL)
 400                 return -ENOMEM;
 401
 402         mutex_unlock(&dev->struct_mutex);
 403         down_read(&mm->mmap_sem);
 404         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 405                                       num_pages, 1, 0, user_pages, NULL);
 406         up_read(&mm->mmap_sem);
 407         mutex_lock(&dev->struct_mutex);
 408         if (pinned_pages < num_pages) {
 409                 ret = -EFAULT;
 410                 goto out;
 411         }
 412
 413         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 414                                                         args->offset,
 415                                                         args->size);
 416         if (ret)
 417                 goto out;
 418
 419         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 420
 421         offset = args->offset;
 422
 423         while (remain > 0) {
 424                 struct page *page;
 425
 426                 /* Operation in this page
 427                  *
 428                  * shmem_page_offset = offset within page in shmem file
 429                  * data_page_index = page number in get_user_pages return
 430                  * data_page_offset = offset with data_page_index page.
 431                  * page_length = bytes to copy for this page
 432                  */
 433                 shmem_page_offset = offset & ~PAGE_MASK;
 434                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 435                 data_page_offset = data_ptr & ~PAGE_MASK;
 436
 437                 page_length = remain;
 438                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 439                         page_length = PAGE_SIZE - shmem_page_offset;
 440                 if ((data_page_offset + page_length) > PAGE_SIZE)
 441                         page_length = PAGE_SIZE - data_page_offset;
 442
 443                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 444                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 445                 if (IS_ERR(page))
 446                         return PTR_ERR(page);
 447
 448                 if (do_bit17_swizzling) {
 449                         slow_shmem_bit17_copy(page,
 450                                               shmem_page_offset,
 451                                               user_pages[data_page_index],
 452                                               data_page_offset,
 453                                               page_length,
 454                                               1);
 455                 } else {
 456                         slow_shmem_copy(user_pages[data_page_index],
 457                                         data_page_offset,
 458                                         page,
 459                                         shmem_page_offset,
 460                                         page_length);
 461                 }
 462
 463                 mark_page_accessed(page);
 464                 page_cache_release(page);
 465
 466                 remain -= page_length;
 467                 data_ptr += page_length;
 468                 offset += page_length;
 469         }
 470
 471 out:
 472         for (i = 0; i < pinned_pages; i++) {
 473                 SetPageDirty(user_pages[i]);
 474                 mark_page_accessed(user_pages[i]);
 475                 page_cache_release(user_pages[i]);
 476         }
 477         drm_free_large(user_pages);
 478
 479         return ret;
 480 }
 481
 482 /**
 483  * Reads data from the object referenced by handle.
 484  *
 485  * On error, the contents of *data are undefined.
 486  */
 487 int
 488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 489                      struct drm_file *file)
 490 {
 491         struct drm_i915_gem_pread *args = data;
 492         struct drm_i915_gem_object *obj;
 493         int ret = 0;
 494
 495         if (args->size == 0)
 496                 return 0;
 497
 498         if (!access_ok(VERIFY_WRITE,
 499                        (char __user *)(uintptr_t)args->data_ptr,
 500                        args->size))
 501                 return -EFAULT;
 502
 503         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 504                                        args->size);
 505         if (ret)
 506                 return -EFAULT;
 507
 508         ret = i915_mutex_lock_interruptible(dev);
 509         if (ret)
 510                 return ret;
 511
 512         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 513         if (obj == NULL) {
 514                 ret = -ENOENT;
 515                 goto unlock;
 516         }
 517
 518         /* Bounds check source.  */
 519         if (args->offset > obj->base.size ||
 520             args->size > obj->base.size - args->offset) {
 521                 ret = -EINVAL;
 522                 goto out;
 523         }
 524
 525         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 526                                                         args->offset,
 527                                                         args->size);
 528         if (ret)
 529                 goto out;
 530
 531         ret = -EFAULT;
 532         if (!i915_gem_object_needs_bit17_swizzle(obj))
 533                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 534         if (ret == -EFAULT)
 535                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 536
 537 out:
 538         drm_gem_object_unreference(&obj->base);
 539 unlock:
 540         mutex_unlock(&dev->struct_mutex);
 541         return ret;
 542 }
 543
 544 /* This is the fast write path which cannot handle
 545  * page faults in the source data
 546  */
 547
 548 static inline int
 549 fast_user_write(struct io_mapping *mapping,
 550                 loff_t page_base, int page_offset,
 551                 char __user *user_data,
 552                 int length)
 553 {
 554         char *vaddr_atomic;
 555         unsigned long unwritten;
 556
 557         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 558         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 559                                                       user_data, length);
 560         io_mapping_unmap_atomic(vaddr_atomic);
 561         return unwritten;
 562 }
 563
 564 /* Here's the write path which can sleep for
 565  * page faults
 566  */
 567
 568 static inline void
 569 slow_kernel_write(struct io_mapping *mapping,
 570                   loff_t gtt_base, int gtt_offset,
 571                   struct page *user_page, int user_offset,
 572                   int length)
 573 {
 574         char __iomem *dst_vaddr;
 575         char *src_vaddr;
 576
 577         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 578         src_vaddr = kmap(user_page);
 579
 580         memcpy_toio(dst_vaddr + gtt_offset,
 581                     src_vaddr + user_offset,
 582                     length);
 583
 584         kunmap(user_page);
 585         io_mapping_unmap(dst_vaddr);
 586 }
 587
 588 /**
 589  * This is the fast pwrite path, where we copy the data directly from the
 590  * user into the GTT, uncached.
 591  */
 592 static int
 593 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 594                          struct drm_i915_gem_object *obj,
 595                          struct drm_i915_gem_pwrite *args,
 596                          struct drm_file *file)
 597 {
 598         drm_i915_private_t *dev_priv = dev->dev_private;
 599         ssize_t remain;
 600         loff_t offset, page_base;
 601         char __user *user_data;
 602         int page_offset, page_length;
 603
 604         user_data = (char __user *) (uintptr_t) args->data_ptr;
 605         remain = args->size;
 606
 607         offset = obj->gtt_offset + args->offset;
 608
 609         while (remain > 0) {
 610                 /* Operation in this page
 611                  *
 612                  * page_base = page offset within aperture
 613                  * page_offset = offset within page
 614                  * page_length = bytes to copy for this page
 615                  */
 616                 page_base = (offset & ~(PAGE_SIZE-1));
 617                 page_offset = offset & (PAGE_SIZE-1);
 618                 page_length = remain;
 619                 if ((page_offset + remain) > PAGE_SIZE)
 620                         page_length = PAGE_SIZE - page_offset;
 621
 622                 /* If we get a fault while copying data, then (presumably) our
 623                  * source page isn't available.  Return the error and we'll
 624                  * retry in the slow path.
 625                  */
 626                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 627                                     page_offset, user_data, page_length))
 628
 629                         return -EFAULT;
 630
 631                 remain -= page_length;
 632                 user_data += page_length;
 633                 offset += page_length;
 634         }
 635
 636         return 0;
 637 }
 638
 639 /**
 640  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 641  * the memory and maps it using kmap_atomic for copying.
 642  *
 643  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 644  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 645  */
 646 static int
 647 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 648                          struct drm_i915_gem_object *obj,
 649                          struct drm_i915_gem_pwrite *args,
 650                          struct drm_file *file)
 651 {
 652         drm_i915_private_t *dev_priv = dev->dev_private;
 653         ssize_t remain;
 654         loff_t gtt_page_base, offset;
 655         loff_t first_data_page, last_data_page, num_pages;
 656         loff_t pinned_pages, i;
 657         struct page **user_pages;
 658         struct mm_struct *mm = current->mm;
 659         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 660         int ret;
 661         uint64_t data_ptr = args->data_ptr;
 662
 663         remain = args->size;
 664
 665         /* Pin the user pages containing the data.  We can't fault while
 666          * holding the struct mutex, and all of the pwrite implementations
 667          * want to hold it while dereferencing the user data.
 668          */
 669         first_data_page = data_ptr / PAGE_SIZE;
 670         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 671         num_pages = last_data_page - first_data_page + 1;
 672
 673         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 674         if (user_pages == NULL)
 675                 return -ENOMEM;
 676
 677         mutex_unlock(&dev->struct_mutex);
 678         down_read(&mm->mmap_sem);
 679         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 680                                       num_pages, 0, 0, user_pages, NULL);
 681         up_read(&mm->mmap_sem);
 682         mutex_lock(&dev->struct_mutex);
 683         if (pinned_pages < num_pages) {
 684                 ret = -EFAULT;
 685                 goto out_unpin_pages;
 686         }
 687
 688         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 689         if (ret)
 690                 goto out_unpin_pages;
 691
 692         ret = i915_gem_object_put_fence(obj);
 693         if (ret)
 694                 goto out_unpin_pages;
 695
 696         offset = obj->gtt_offset + args->offset;
 697
 698         while (remain > 0) {
 699                 /* Operation in this page
 700                  *
 701                  * gtt_page_base = page offset within aperture
 702                  * gtt_page_offset = offset within page in aperture
 703                  * data_page_index = page number in get_user_pages return
 704                  * data_page_offset = offset with data_page_index page.
 705                  * page_length = bytes to copy for this page
 706                  */
 707                 gtt_page_base = offset & PAGE_MASK;
 708                 gtt_page_offset = offset & ~PAGE_MASK;
 709                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 710                 data_page_offset = data_ptr & ~PAGE_MASK;
 711
 712                 page_length = remain;
 713                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 714                         page_length = PAGE_SIZE - gtt_page_offset;
 715                 if ((data_page_offset + page_length) > PAGE_SIZE)
 716                         page_length = PAGE_SIZE - data_page_offset;
 717
 718                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 719                                   gtt_page_base, gtt_page_offset,
 720                                   user_pages[data_page_index],
 721                                   data_page_offset,
 722                                   page_length);
 723
 724                 remain -= page_length;
 725                 offset += page_length;
 726                 data_ptr += page_length;
 727         }
 728
 729 out_unpin_pages:
 730         for (i = 0; i < pinned_pages; i++)
 731                 page_cache_release(user_pages[i]);
 732         drm_free_large(user_pages);
 733
 734         return ret;
 735 }
 736
 737 /**
 738  * This is the fast shmem pwrite path, which attempts to directly
 739  * copy_from_user into the kmapped pages backing the object.
 740  */
 741 static int
 742 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 743                            struct drm_i915_gem_object *obj,
 744                            struct drm_i915_gem_pwrite *args,
 745                            struct drm_file *file)
 746 {
 747         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 748         ssize_t remain;
 749         loff_t offset;
 750         char __user *user_data;
 751         int page_offset, page_length;
 752
 753         user_data = (char __user *) (uintptr_t) args->data_ptr;
 754         remain = args->size;
 755
 756         offset = args->offset;
 757         obj->dirty = 1;
 758
 759         while (remain > 0) {
 760                 struct page *page;
 761                 char *vaddr;
 762                 int ret;
 763
 764                 /* Operation in this page
 765                  *
 766                  * page_offset = offset within page
 767                  * page_length = bytes to copy for this page
 768                  */
 769                 page_offset = offset & (PAGE_SIZE-1);
 770                 page_length = remain;
 771                 if ((page_offset + remain) > PAGE_SIZE)
 772                         page_length = PAGE_SIZE - page_offset;
 773
 774                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 775                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 776                 if (IS_ERR(page))
 777                         return PTR_ERR(page);
 778
 779                 vaddr = kmap_atomic(page, KM_USER0);
 780                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 781                                                 user_data,
 782                                                 page_length);
 783                 kunmap_atomic(vaddr, KM_USER0);
 784
 785                 set_page_dirty(page);
 786                 mark_page_accessed(page);
 787                 page_cache_release(page);
 788
 789                 /* If we get a fault while copying data, then (presumably) our
 790                  * source page isn't available.  Return the error and we'll
 791                  * retry in the slow path.
 792                  */
 793                 if (ret)
 794                         return -EFAULT;
 795
 796                 remain -= page_length;
 797                 user_data += page_length;
 798                 offset += page_length;
 799         }
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 806  * the memory and maps it using kmap_atomic for copying.
 807  *
 808  * This avoids taking mmap_sem for faulting on the user's address while the
 809  * struct_mutex is held.
 810  */
 811 static int
 812 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 813                            struct drm_i915_gem_object *obj,
 814                            struct drm_i915_gem_pwrite *args,
 815                            struct drm_file *file)
 816 {
 817         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 818         struct mm_struct *mm = current->mm;
 819         struct page **user_pages;
 820         ssize_t remain;
 821         loff_t offset, pinned_pages, i;
 822         loff_t first_data_page, last_data_page, num_pages;
 823         int shmem_page_offset;
 824         int data_page_index,  data_page_offset;
 825         int page_length;
 826         int ret;
 827         uint64_t data_ptr = args->data_ptr;
 828         int do_bit17_swizzling;
 829
 830         remain = args->size;
 831
 832         /* Pin the user pages containing the data.  We can't fault while
 833          * holding the struct mutex, and all of the pwrite implementations
 834          * want to hold it while dereferencing the user data.
 835          */
 836         first_data_page = data_ptr / PAGE_SIZE;
 837         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 838         num_pages = last_data_page - first_data_page + 1;
 839
 840         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 841         if (user_pages == NULL)
 842                 return -ENOMEM;
 843
 844         mutex_unlock(&dev->struct_mutex);
 845         down_read(&mm->mmap_sem);
 846         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 847                                       num_pages, 0, 0, user_pages, NULL);
 848         up_read(&mm->mmap_sem);
 849         mutex_lock(&dev->struct_mutex);
 850         if (pinned_pages < num_pages) {
 851                 ret = -EFAULT;
 852                 goto out;
 853         }
 854
 855         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 856         if (ret)
 857                 goto out;
 858
 859         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 860
 861         offset = args->offset;
 862         obj->dirty = 1;
 863
 864         while (remain > 0) {
 865                 struct page *page;
 866
 867                 /* Operation in this page
 868                  *
 869                  * shmem_page_offset = offset within page in shmem file
 870                  * data_page_index = page number in get_user_pages return
 871                  * data_page_offset = offset with data_page_index page.
 872                  * page_length = bytes to copy for this page
 873                  */
 874                 shmem_page_offset = offset & ~PAGE_MASK;
 875                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 876                 data_page_offset = data_ptr & ~PAGE_MASK;
 877
 878                 page_length = remain;
 879                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 880                         page_length = PAGE_SIZE - shmem_page_offset;
 881                 if ((data_page_offset + page_length) > PAGE_SIZE)
 882                         page_length = PAGE_SIZE - data_page_offset;
 883
 884                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 885                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 886                 if (IS_ERR(page)) {
 887                         ret = PTR_ERR(page);
 888                         goto out;
 889                 }
 890
 891                 if (do_bit17_swizzling) {
 892                         slow_shmem_bit17_copy(page,
 893                                               shmem_page_offset,
 894                                               user_pages[data_page_index],
 895                                               data_page_offset,
 896                                               page_length,
 897                                               0);
 898                 } else {
 899                         slow_shmem_copy(page,
 900                                         shmem_page_offset,
 901                                         user_pages[data_page_index],
 902                                         data_page_offset,
 903                                         page_length);
 904                 }
 905
 906                 set_page_dirty(page);
 907                 mark_page_accessed(page);
 908                 page_cache_release(page);
 909
 910                 remain -= page_length;
 911                 data_ptr += page_length;
 912                 offset += page_length;
 913         }
 914
 915 out:
 916         for (i = 0; i < pinned_pages; i++)
 917                 page_cache_release(user_pages[i]);
 918         drm_free_large(user_pages);
 919
 920         return ret;
 921 }
 922
 923 /**
 924  * Writes data to the object referenced by handle.
 925  *
 926  * On error, the contents of the buffer that were to be modified are undefined.
 927  */
 928 int
 929 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 930                       struct drm_file *file)
 931 {
 932         struct drm_i915_gem_pwrite *args = data;
 933         struct drm_i915_gem_object *obj;
 934         int ret;
 935
 936         if (args->size == 0)
 937                 return 0;
 938
 939         if (!access_ok(VERIFY_READ,
 940                        (char __user *)(uintptr_t)args->data_ptr,
 941                        args->size))
 942                 return -EFAULT;
 943
 944         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 945                                       args->size);
 946         if (ret)
 947                 return -EFAULT;
 948
 949         ret = i915_mutex_lock_interruptible(dev);
 950         if (ret)
 951                 return ret;
 952
 953         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 954         if (obj == NULL) {
 955                 ret = -ENOENT;
 956                 goto unlock;
 957         }
 958
 959         /* Bounds check destination. */
 960         if (args->offset > obj->base.size ||
 961             args->size > obj->base.size - args->offset) {
 962                 ret = -EINVAL;
 963                 goto out;
 964         }
 965
 966         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 967          * it would end up going through the fenced access, and we'll get
 968          * different detiling behavior between reading and writing.
 969          * pread/pwrite currently are reading and writing from the CPU
 970          * perspective, requiring manual detiling by the client.
 971          */
 972         if (obj->phys_obj)
 973                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 974         else if (obj->gtt_space &&
 975                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 976                 ret = i915_gem_object_pin(obj, 0, true);
 977                 if (ret)
 978                         goto out;
 979
 980                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
 981                 if (ret)
 982                         goto out_unpin;
 983
 984                 ret = i915_gem_object_put_fence(obj);
 985                 if (ret)
 986                         goto out_unpin;
 987
 988                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 989                 if (ret == -EFAULT)
 990                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
 991
 992 out_unpin:
 993                 i915_gem_object_unpin(obj);
 994         } else {
 995                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 996                 if (ret)
 997                         goto out;
 998
 999                 ret = -EFAULT;
1000                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1001                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1002                 if (ret == -EFAULT)
1003                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1004         }
1005
1006 out:
1007         drm_gem_object_unreference(&obj->base);
1008 unlock:
1009         mutex_unlock(&dev->struct_mutex);
1010         return ret;
1011 }
1012
1013 /**
1014  * Called when user space prepares to use an object with the CPU, either
1015  * through the mmap ioctl's mapping or a GTT mapping.
1016  */
1017 int
1018 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1019                           struct drm_file *file)
1020 {
1021         struct drm_i915_gem_set_domain *args = data;
1022         struct drm_i915_gem_object *obj;
1023         uint32_t read_domains = args->read_domains;
1024         uint32_t write_domain = args->write_domain;
1025         int ret;
1026
1027         if (!(dev->driver->driver_features & DRIVER_GEM))
1028                 return -ENODEV;
1029
1030         /* Only handle setting domains to types used by the CPU. */
1031         if (write_domain & I915_GEM_GPU_DOMAINS)
1032                 return -EINVAL;
1033
1034         if (read_domains & I915_GEM_GPU_DOMAINS)
1035                 return -EINVAL;
1036
1037         /* Having something in the write domain implies it's in the read
1038          * domain, and only that read domain.  Enforce that in the request.
1039          */
1040         if (write_domain != 0 && read_domains != write_domain)
1041                 return -EINVAL;
1042
1043         ret = i915_mutex_lock_interruptible(dev);
1044         if (ret)
1045                 return ret;
1046
1047         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1048         if (obj == NULL) {
1049                 ret = -ENOENT;
1050                 goto unlock;
1051         }
1052
1053         if (read_domains & I915_GEM_DOMAIN_GTT) {
1054                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1055
1056                 /* Silently promote "you're not bound, there was nothing to do"
1057                  * to success, since the client was just asking us to
1058                  * make sure everything was done.
1059                  */
1060                 if (ret == -EINVAL)
1061                         ret = 0;
1062         } else {
1063                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1064         }
1065
1066         drm_gem_object_unreference(&obj->base);
1067 unlock:
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space has done writes to this buffer
1074  */
1075 int
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077                          struct drm_file *file)
1078 {
1079         struct drm_i915_gem_sw_finish *args = data;
1080         struct drm_i915_gem_object *obj;
1081         int ret = 0;
1082
1083         if (!(dev->driver->driver_features & DRIVER_GEM))
1084                 return -ENODEV;
1085
1086         ret = i915_mutex_lock_interruptible(dev);
1087         if (ret)
1088                 return ret;
1089
1090         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1091         if (obj == NULL) {
1092                 ret = -ENOENT;
1093                 goto unlock;
1094         }
1095
1096         /* Pinned buffers may be scanout, so flush the cache */
1097         if (obj->pin_count)
1098                 i915_gem_object_flush_cpu_write_domain(obj);
1099
1100         drm_gem_object_unreference(&obj->base);
1101 unlock:
1102         mutex_unlock(&dev->struct_mutex);
1103         return ret;
1104 }
1105
1106 /**
1107  * Maps the contents of an object, returning the address it is mapped
1108  * into.
1109  *
1110  * While the mapping holds a reference on the contents of the object, it doesn't
1111  * imply a ref on the object itself.
1112  */
1113 int
1114 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1115                     struct drm_file *file)
1116 {
1117         struct drm_i915_private *dev_priv = dev->dev_private;
1118         struct drm_i915_gem_mmap *args = data;
1119         struct drm_gem_object *obj;
1120         loff_t offset;
1121         unsigned long addr;
1122
1123         if (!(dev->driver->driver_features & DRIVER_GEM))
1124                 return -ENODEV;
1125
1126         obj = drm_gem_object_lookup(dev, file, args->handle);
1127         if (obj == NULL)
1128                 return -ENOENT;
1129
1130         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1131                 drm_gem_object_unreference_unlocked(obj);
1132                 return -E2BIG;
1133         }
1134
1135         offset = args->offset;
1136
1137         down_write(&current->mm->mmap_sem);
1138         addr = do_mmap(obj->filp, 0, args->size,
1139                        PROT_READ | PROT_WRITE, MAP_SHARED,
1140                        args->offset);
1141         up_write(&current->mm->mmap_sem);
1142         drm_gem_object_unreference_unlocked(obj);
1143         if (IS_ERR((void *)addr))
1144                 return addr;
1145
1146         args->addr_ptr = (uint64_t) addr;
1147
1148         return 0;
1149 }
1150
1151 /**
1152  * i915_gem_fault - fault a page into the GTT
1153  * vma: VMA in question
1154  * vmf: fault info
1155  *
1156  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1157  * from userspace.  The fault handler takes care of binding the object to
1158  * the GTT (if needed), allocating and programming a fence register (again,
1159  * only if needed based on whether the old reg is still valid or the object
1160  * is tiled) and inserting a new PTE into the faulting process.
1161  *
1162  * Note that the faulting process may involve evicting existing objects
1163  * from the GTT and/or fence registers to make room.  So performance may
1164  * suffer if the GTT working set is large or there are few fence registers
1165  * left.
1166  */
1167 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1168 {
1169         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1170         struct drm_device *dev = obj->base.dev;
1171         drm_i915_private_t *dev_priv = dev->dev_private;
1172         pgoff_t page_offset;
1173         unsigned long pfn;
1174         int ret = 0;
1175         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1176
1177         /* We don't use vmf->pgoff since that has the fake offset */
1178         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1179                 PAGE_SHIFT;
1180
1181         /* Now bind it into the GTT if needed */
1182         mutex_lock(&dev->struct_mutex);
1183
1184         if (!obj->map_and_fenceable) {
1185                 ret = i915_gem_object_unbind(obj);
1186                 if (ret)
1187                         goto unlock;
1188         }
1189         if (!obj->gtt_space) {
1190                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1191                 if (ret)
1192                         goto unlock;
1193         }
1194
1195         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1196         if (ret)
1197                 goto unlock;
1198
1199         if (obj->tiling_mode == I915_TILING_NONE)
1200                 ret = i915_gem_object_put_fence(obj);
1201         else
1202                 ret = i915_gem_object_get_fence(obj, NULL, true);
1203         if (ret)
1204                 goto unlock;
1205
1206         if (i915_gem_object_is_inactive(obj))
1207                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1208
1209         obj->fault_mappable = true;
1210
1211         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1212                 page_offset;
1213
1214         /* Finally, remap it using the new GTT offset */
1215         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1216 unlock:
1217         mutex_unlock(&dev->struct_mutex);
1218
1219         switch (ret) {
1220         case -EAGAIN:
1221                 set_need_resched();
1222         case 0:
1223         case -ERESTARTSYS:
1224                 return VM_FAULT_NOPAGE;
1225         case -ENOMEM:
1226                 return VM_FAULT_OOM;
1227         default:
1228                 return VM_FAULT_SIGBUS;
1229         }
1230 }
1231
1232 /**
1233  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1234  * @obj: obj in question
1235  *
1236  * GEM memory mapping works by handing back to userspace a fake mmap offset
1237  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1238  * up the object based on the offset and sets up the various memory mapping
1239  * structures.
1240  *
1241  * This routine allocates and attaches a fake offset for @obj.
1242  */
1243 static int
1244 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1245 {
1246         struct drm_device *dev = obj->base.dev;
1247         struct drm_gem_mm *mm = dev->mm_private;
1248         struct drm_map_list *list;
1249         struct drm_local_map *map;
1250         int ret = 0;
1251
1252         /* Set the object up for mmap'ing */
1253         list = &obj->base.map_list;
1254         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1255         if (!list->map)
1256                 return -ENOMEM;
1257
1258         map = list->map;
1259         map->type = _DRM_GEM;
1260         map->size = obj->base.size;
1261         map->handle = obj;
1262
1263         /* Get a DRM GEM mmap offset allocated... */
1264         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1265                                                     obj->base.size / PAGE_SIZE,
1266                                                     0, 0);
1267         if (!list->file_offset_node) {
1268                 DRM_ERROR("failed to allocate offset for bo %d\n",
1269                           obj->base.name);
1270                 ret = -ENOSPC;
1271                 goto out_free_list;
1272         }
1273
1274         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1275                                                   obj->base.size / PAGE_SIZE,
1276                                                   0);
1277         if (!list->file_offset_node) {
1278                 ret = -ENOMEM;
1279                 goto out_free_list;
1280         }
1281
1282         list->hash.key = list->file_offset_node->start;
1283         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1284         if (ret) {
1285                 DRM_ERROR("failed to add to map hash\n");
1286                 goto out_free_mm;
1287         }
1288
1289         return 0;
1290
1291 out_free_mm:
1292         drm_mm_put_block(list->file_offset_node);
1293 out_free_list:
1294         kfree(list->map);
1295         list->map = NULL;
1296
1297         return ret;
1298 }
1299
1300 /**
1301  * i915_gem_release_mmap - remove physical page mappings
1302  * @obj: obj in question
1303  *
1304  * Preserve the reservation of the mmapping with the DRM core code, but
1305  * relinquish ownership of the pages back to the system.
1306  *
1307  * It is vital that we remove the page mapping if we have mapped a tiled
1308  * object through the GTT and then lose the fence register due to
1309  * resource pressure. Similarly if the object has been moved out of the
1310  * aperture, than pages mapped into userspace must be revoked. Removing the
1311  * mapping will then trigger a page fault on the next user access, allowing
1312  * fixup by i915_gem_fault().
1313  */
1314 void
1315 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1316 {
1317         if (!obj->fault_mappable)
1318                 return;
1319
1320         unmap_mapping_range(obj->base.dev->dev_mapping,
1321                             (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1322                             obj->base.size, 1);
1323
1324         obj->fault_mappable = false;
1325 }
1326
1327 static void
1328 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1329 {
1330         struct drm_device *dev = obj->base.dev;
1331         struct drm_gem_mm *mm = dev->mm_private;
1332         struct drm_map_list *list = &obj->base.map_list;
1333
1334         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1335         drm_mm_put_block(list->file_offset_node);
1336         kfree(list->map);
1337         list->map = NULL;
1338 }
1339
1340 static uint32_t
1341 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1342 {
1343         struct drm_device *dev = obj->base.dev;
1344         uint32_t size;
1345
1346         if (INTEL_INFO(dev)->gen >= 4 ||
1347             obj->tiling_mode == I915_TILING_NONE)
1348                 return obj->base.size;
1349
1350         /* Previous chips need a power-of-two fence region when tiling */
1351         if (INTEL_INFO(dev)->gen == 3)
1352                 size = 1024*1024;
1353         else
1354                 size = 512*1024;
1355
1356         while (size < obj->base.size)
1357                 size <<= 1;
1358
1359         return size;
1360 }
1361
1362 /**
1363  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364  * @obj: object to check
1365  *
1366  * Return the required GTT alignment for an object, taking into account
1367  * potential fence register mapping.
1368  */
1369 static uint32_t
1370 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1371 {
1372         struct drm_device *dev = obj->base.dev;
1373
1374         /*
1375          * Minimum alignment is 4k (GTT page size), but might be greater
1376          * if a fence register is needed for the object.
1377          */
1378         if (INTEL_INFO(dev)->gen >= 4 ||
1379             obj->tiling_mode == I915_TILING_NONE)
1380                 return 4096;
1381
1382         /*
1383          * Previous chips need to be aligned to the size of the smallest
1384          * fence register that can contain the object.
1385          */
1386         return i915_gem_get_gtt_size(obj);
1387 }
1388
1389 /**
1390  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1391  *                                       unfenced object
1392  * @obj: object to check
1393  *
1394  * Return the required GTT alignment for an object, only taking into account
1395  * unfenced tiled surface requirements.
1396  */
1397 static uint32_t
1398 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1399 {
1400         struct drm_device *dev = obj->base.dev;
1401         int tile_height;
1402
1403         /*
1404          * Minimum alignment is 4k (GTT page size) for sane hw.
1405          */
1406         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1407             obj->tiling_mode == I915_TILING_NONE)
1408                 return 4096;
1409
1410         /*
1411          * Older chips need unfenced tiled buffers to be aligned to the left
1412          * edge of an even tile row (where tile rows are counted as if the bo is
1413          * placed in a fenced gtt region).
1414          */
1415         if (IS_GEN2(dev) ||
1416             (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1417                 tile_height = 32;
1418         else
1419                 tile_height = 8;
1420
1421         return tile_height * obj->stride * 2;
1422 }
1423
1424 /**
1425  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1426  * @dev: DRM device
1427  * @data: GTT mapping ioctl data
1428  * @file: GEM object info
1429  *
1430  * Simply returns the fake offset to userspace so it can mmap it.
1431  * The mmap call will end up in drm_gem_mmap(), which will set things
1432  * up so we can get faults in the handler above.
1433  *
1434  * The fault handler will take care of binding the object into the GTT
1435  * (since it may have been evicted to make room for something), allocating
1436  * a fence register, and mapping the appropriate aperture address into
1437  * userspace.
1438  */
1439 int
1440 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1441                         struct drm_file *file)
1442 {
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         struct drm_i915_gem_mmap_gtt *args = data;
1445         struct drm_i915_gem_object *obj;
1446         int ret;
1447
1448         if (!(dev->driver->driver_features & DRIVER_GEM))
1449                 return -ENODEV;
1450
1451         ret = i915_mutex_lock_interruptible(dev);
1452         if (ret)
1453                 return ret;
1454
1455         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1456         if (obj == NULL) {
1457                 ret = -ENOENT;
1458                 goto unlock;
1459         }
1460
1461         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1462                 ret = -E2BIG;
1463                 goto unlock;
1464         }
1465
1466         if (obj->madv != I915_MADV_WILLNEED) {
1467                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1468                 ret = -EINVAL;
1469                 goto out;
1470         }
1471
1472         if (!obj->base.map_list.map) {
1473                 ret = i915_gem_create_mmap_offset(obj);
1474                 if (ret)
1475                         goto out;
1476         }
1477
1478         args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1479
1480 out:
1481         drm_gem_object_unreference(&obj->base);
1482 unlock:
1483         mutex_unlock(&dev->struct_mutex);
1484         return ret;
1485 }
1486
1487 static int
1488 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1489                               gfp_t gfpmask)
1490 {
1491         int page_count, i;
1492         struct address_space *mapping;
1493         struct inode *inode;
1494         struct page *page;
1495
1496         /* Get the list of pages out of our struct file.  They'll be pinned
1497          * at this point until we release them.
1498          */
1499         page_count = obj->base.size / PAGE_SIZE;
1500         BUG_ON(obj->pages != NULL);
1501         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1502         if (obj->pages == NULL)
1503                 return -ENOMEM;
1504
1505         inode = obj->base.filp->f_path.dentry->d_inode;
1506         mapping = inode->i_mapping;
1507         for (i = 0; i < page_count; i++) {
1508                 page = read_cache_page_gfp(mapping, i,
1509                                            GFP_HIGHUSER |
1510                                            __GFP_COLD |
1511                                            __GFP_RECLAIMABLE |
1512                                            gfpmask);
1513                 if (IS_ERR(page))
1514                         goto err_pages;
1515
1516                 obj->pages[i] = page;
1517         }
1518
1519         if (obj->tiling_mode != I915_TILING_NONE)
1520                 i915_gem_object_do_bit_17_swizzle(obj);
1521
1522         return 0;
1523
1524 err_pages:
1525         while (i--)
1526                 page_cache_release(obj->pages[i]);
1527
1528         drm_free_large(obj->pages);
1529         obj->pages = NULL;
1530         return PTR_ERR(page);
1531 }
1532
1533 static void
1534 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1535 {
1536         int page_count = obj->base.size / PAGE_SIZE;
1537         int i;
1538
1539         BUG_ON(obj->madv == __I915_MADV_PURGED);
1540
1541         if (obj->tiling_mode != I915_TILING_NONE)
1542                 i915_gem_object_save_bit_17_swizzle(obj);
1543
1544         if (obj->madv == I915_MADV_DONTNEED)
1545                 obj->dirty = 0;
1546
1547         for (i = 0; i < page_count; i++) {
1548                 if (obj->dirty)
1549                         set_page_dirty(obj->pages[i]);
1550
1551                 if (obj->madv == I915_MADV_WILLNEED)
1552                         mark_page_accessed(obj->pages[i]);
1553
1554                 page_cache_release(obj->pages[i]);
1555         }
1556         obj->dirty = 0;
1557
1558         drm_free_large(obj->pages);
1559         obj->pages = NULL;
1560 }
1561
1562 void
1563 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1564                                struct intel_ring_buffer *ring,
1565                                u32 seqno)
1566 {
1567         struct drm_device *dev = obj->base.dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569
1570         BUG_ON(ring == NULL);
1571         obj->ring = ring;
1572
1573         /* Add a reference if we're newly entering the active list. */
1574         if (!obj->active) {
1575                 drm_gem_object_reference(&obj->base);
1576                 obj->active = 1;
1577         }
1578
1579         /* Move from whatever list we were on to the tail of execution. */
1580         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1581         list_move_tail(&obj->ring_list, &ring->active_list);
1582
1583         obj->last_rendering_seqno = seqno;
1584         if (obj->fenced_gpu_access) {
1585                 struct drm_i915_fence_reg *reg;
1586
1587                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1588
1589                 obj->last_fenced_seqno = seqno;
1590                 obj->last_fenced_ring = ring;
1591
1592                 reg = &dev_priv->fence_regs[obj->fence_reg];
1593                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1594         }
1595 }
1596
1597 static void
1598 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1599 {
1600         list_del_init(&obj->ring_list);
1601         obj->last_rendering_seqno = 0;
1602 }
1603
1604 static void
1605 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1606 {
1607         struct drm_device *dev = obj->base.dev;
1608         drm_i915_private_t *dev_priv = dev->dev_private;
1609
1610         BUG_ON(!obj->active);
1611         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1612
1613         i915_gem_object_move_off_active(obj);
1614 }
1615
1616 static void
1617 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1618 {
1619         struct drm_device *dev = obj->base.dev;
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621
1622         if (obj->pin_count != 0)
1623                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1624         else
1625                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1626
1627         BUG_ON(!list_empty(&obj->gpu_write_list));
1628         BUG_ON(!obj->active);
1629         obj->ring = NULL;
1630
1631         i915_gem_object_move_off_active(obj);
1632         obj->fenced_gpu_access = false;
1633
1634         obj->active = 0;
1635         obj->pending_gpu_write = false;
1636         drm_gem_object_unreference(&obj->base);
1637
1638         WARN_ON(i915_verify_lists(dev));
1639 }
1640
1641 /* Immediately discard the backing storage */
1642 static void
1643 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1644 {
1645         struct inode *inode;
1646
1647         /* Our goal here is to return as much of the memory as
1648          * is possible back to the system as we are called from OOM.
1649          * To do this we must instruct the shmfs to drop all of its
1650          * backing pages, *now*. Here we mirror the actions taken
1651          * when by shmem_delete_inode() to release the backing store.
1652          */
1653         inode = obj->base.filp->f_path.dentry->d_inode;
1654         truncate_inode_pages(inode->i_mapping, 0);
1655         if (inode->i_op->truncate_range)
1656                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1657
1658         obj->madv = __I915_MADV_PURGED;
1659 }
1660
1661 static inline int
1662 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1663 {
1664         return obj->madv == I915_MADV_DONTNEED;
1665 }
1666
1667 static void
1668 i915_gem_process_flushing_list(struct drm_device *dev,
1669                                uint32_t flush_domains,
1670                                struct intel_ring_buffer *ring)
1671 {
1672         struct drm_i915_gem_object *obj, *next;
1673
1674         list_for_each_entry_safe(obj, next,
1675                                  &ring->gpu_write_list,
1676                                  gpu_write_list) {
1677                 if (obj->base.write_domain & flush_domains) {
1678                         uint32_t old_write_domain = obj->base.write_domain;
1679
1680                         obj->base.write_domain = 0;
1681                         list_del_init(&obj->gpu_write_list);
1682                         i915_gem_object_move_to_active(obj, ring,
1683                                                        i915_gem_next_request_seqno(dev, ring));
1684
1685                         trace_i915_gem_object_change_domain(obj,
1686                                                             obj->base.read_domains,
1687                                                             old_write_domain);
1688                 }
1689         }
1690 }
1691
1692 int
1693 i915_add_request(struct drm_device *dev,
1694                  struct drm_file *file,
1695                  struct drm_i915_gem_request *request,
1696                  struct intel_ring_buffer *ring)
1697 {
1698         drm_i915_private_t *dev_priv = dev->dev_private;
1699         struct drm_i915_file_private *file_priv = NULL;
1700         uint32_t seqno;
1701         int was_empty;
1702         int ret;
1703
1704         BUG_ON(request == NULL);
1705
1706         if (file != NULL)
1707                 file_priv = file->driver_priv;
1708
1709         ret = ring->add_request(ring, &seqno);
1710         if (ret)
1711             return ret;
1712
1713         ring->outstanding_lazy_request = false;
1714
1715         request->seqno = seqno;
1716         request->ring = ring;
1717         request->emitted_jiffies = jiffies;
1718         was_empty = list_empty(&ring->request_list);
1719         list_add_tail(&request->list, &ring->request_list);
1720
1721         if (file_priv) {
1722                 spin_lock(&file_priv->mm.lock);
1723                 request->file_priv = file_priv;
1724                 list_add_tail(&request->client_list,
1725                               &file_priv->mm.request_list);
1726                 spin_unlock(&file_priv->mm.lock);
1727         }
1728
1729         if (!dev_priv->mm.suspended) {
1730                 mod_timer(&dev_priv->hangcheck_timer,
1731                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1732                 if (was_empty)
1733                         queue_delayed_work(dev_priv->wq,
1734                                            &dev_priv->mm.retire_work, HZ);
1735         }
1736         return 0;
1737 }
1738
1739 static inline void
1740 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1741 {
1742         struct drm_i915_file_private *file_priv = request->file_priv;
1743
1744         if (!file_priv)
1745                 return;
1746
1747         spin_lock(&file_priv->mm.lock);
1748         list_del(&request->client_list);
1749         request->file_priv = NULL;
1750         spin_unlock(&file_priv->mm.lock);
1751 }
1752
1753 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1754                                       struct intel_ring_buffer *ring)
1755 {
1756         while (!list_empty(&ring->request_list)) {
1757                 struct drm_i915_gem_request *request;
1758
1759                 request = list_first_entry(&ring->request_list,
1760                                            struct drm_i915_gem_request,
1761                                            list);
1762
1763                 list_del(&request->list);
1764                 i915_gem_request_remove_from_client(request);
1765                 kfree(request);
1766         }
1767
1768         while (!list_empty(&ring->active_list)) {
1769                 struct drm_i915_gem_object *obj;
1770
1771                 obj = list_first_entry(&ring->active_list,
1772                                        struct drm_i915_gem_object,
1773                                        ring_list);
1774
1775                 obj->base.write_domain = 0;
1776                 list_del_init(&obj->gpu_write_list);
1777                 i915_gem_object_move_to_inactive(obj);
1778         }
1779 }
1780
1781 static void i915_gem_reset_fences(struct drm_device *dev)
1782 {
1783         struct drm_i915_private *dev_priv = dev->dev_private;
1784         int i;
1785
1786         for (i = 0; i < 16; i++) {
1787                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1788                 struct drm_i915_gem_object *obj = reg->obj;
1789
1790                 if (!obj)
1791                         continue;
1792
1793                 if (obj->tiling_mode)
1794                         i915_gem_release_mmap(obj);
1795
1796                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1797                 reg->obj->fenced_gpu_access = false;
1798                 reg->obj->last_fenced_seqno = 0;
1799                 reg->obj->last_fenced_ring = NULL;
1800                 i915_gem_clear_fence_reg(dev, reg);
1801         }
1802 }
1803
1804 void i915_gem_reset(struct drm_device *dev)
1805 {
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct drm_i915_gem_object *obj;
1808         int i;
1809
1810         for (i = 0; i < I915_NUM_RINGS; i++)
1811                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1812
1813         /* Remove anything from the flushing lists. The GPU cache is likely
1814          * to be lost on reset along with the data, so simply move the
1815          * lost bo to the inactive list.
1816          */
1817         while (!list_empty(&dev_priv->mm.flushing_list)) {
1818                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1819                                       struct drm_i915_gem_object,
1820                                       mm_list);
1821
1822                 obj->base.write_domain = 0;
1823                 list_del_init(&obj->gpu_write_list);
1824                 i915_gem_object_move_to_inactive(obj);
1825         }
1826
1827         /* Move everything out of the GPU domains to ensure we do any
1828          * necessary invalidation upon reuse.
1829          */
1830         list_for_each_entry(obj,
1831                             &dev_priv->mm.inactive_list,
1832                             mm_list)
1833         {
1834                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1835         }
1836
1837         /* The fence registers are invalidated so clear them out */
1838         i915_gem_reset_fences(dev);
1839 }
1840
1841 /**
1842  * This function clears the request list as sequence numbers are passed.
1843  */
1844 static void
1845 i915_gem_retire_requests_ring(struct drm_device *dev,
1846                               struct intel_ring_buffer *ring)
1847 {
1848         drm_i915_private_t *dev_priv = dev->dev_private;
1849         uint32_t seqno;
1850         int i;
1851
1852         if (!ring->status_page.page_addr ||
1853             list_empty(&ring->request_list))
1854                 return;
1855
1856         WARN_ON(i915_verify_lists(dev));
1857
1858         seqno = ring->get_seqno(ring);
1859
1860         for (i = 0; i < I915_NUM_RINGS; i++)
1861                 if (seqno >= ring->sync_seqno[i])
1862                         ring->sync_seqno[i] = 0;
1863
1864         while (!list_empty(&ring->request_list)) {
1865                 struct drm_i915_gem_request *request;
1866
1867                 request = list_first_entry(&ring->request_list,
1868                                            struct drm_i915_gem_request,
1869                                            list);
1870
1871                 if (!i915_seqno_passed(seqno, request->seqno))
1872                         break;
1873
1874                 trace_i915_gem_request_retire(dev, request->seqno);
1875
1876                 list_del(&request->list);
1877                 i915_gem_request_remove_from_client(request);
1878                 kfree(request);
1879         }
1880
1881         /* Move any buffers on the active list that are no longer referenced
1882          * by the ringbuffer to the flushing/inactive lists as appropriate.
1883          */
1884         while (!list_empty(&ring->active_list)) {
1885                 struct drm_i915_gem_object *obj;
1886
1887                 obj= list_first_entry(&ring->active_list,
1888                                       struct drm_i915_gem_object,
1889                                       ring_list);
1890
1891                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1892                         break;
1893
1894                 if (obj->base.write_domain != 0)
1895                         i915_gem_object_move_to_flushing(obj);
1896                 else
1897                         i915_gem_object_move_to_inactive(obj);
1898         }
1899
1900         if (unlikely (dev_priv->trace_irq_seqno &&
1901                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1902                 ring->irq_put(ring);
1903                 dev_priv->trace_irq_seqno = 0;
1904         }
1905
1906         WARN_ON(i915_verify_lists(dev));
1907 }
1908
1909 void
1910 i915_gem_retire_requests(struct drm_device *dev)
1911 {
1912         drm_i915_private_t *dev_priv = dev->dev_private;
1913         int i;
1914
1915         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1916             struct drm_i915_gem_object *obj, *next;
1917
1918             /* We must be careful that during unbind() we do not
1919              * accidentally infinitely recurse into retire requests.
1920              * Currently:
1921              *   retire -> free -> unbind -> wait -> retire_ring
1922              */
1923             list_for_each_entry_safe(obj, next,
1924                                      &dev_priv->mm.deferred_free_list,
1925                                      mm_list)
1926                     i915_gem_free_object_tail(obj);
1927         }
1928
1929         for (i = 0; i < I915_NUM_RINGS; i++)
1930                 i915_gem_retire_requests_ring(dev, &dev_priv->ring[i]);
1931 }
1932
1933 static void
1934 i915_gem_retire_work_handler(struct work_struct *work)
1935 {
1936         drm_i915_private_t *dev_priv;
1937         struct drm_device *dev;
1938
1939         dev_priv = container_of(work, drm_i915_private_t,
1940                                 mm.retire_work.work);
1941         dev = dev_priv->dev;
1942
1943         /* Come back later if the device is busy... */
1944         if (!mutex_trylock(&dev->struct_mutex)) {
1945                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1946                 return;
1947         }
1948
1949         i915_gem_retire_requests(dev);
1950
1951         if (!dev_priv->mm.suspended &&
1952                 (!list_empty(&dev_priv->ring[RCS].request_list) ||
1953                  !list_empty(&dev_priv->ring[VCS].request_list) ||
1954                  !list_empty(&dev_priv->ring[BCS].request_list)))
1955                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1956         mutex_unlock(&dev->struct_mutex);
1957 }
1958
1959 int
1960 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1961                      bool interruptible, struct intel_ring_buffer *ring)
1962 {
1963         drm_i915_private_t *dev_priv = dev->dev_private;
1964         u32 ier;
1965         int ret = 0;
1966
1967         BUG_ON(seqno == 0);
1968
1969         if (atomic_read(&dev_priv->mm.wedged))
1970                 return -EAGAIN;
1971
1972         if (seqno == ring->outstanding_lazy_request) {
1973                 struct drm_i915_gem_request *request;
1974
1975                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1976                 if (request == NULL)
1977                         return -ENOMEM;
1978
1979                 ret = i915_add_request(dev, NULL, request, ring);
1980                 if (ret) {
1981                         kfree(request);
1982                         return ret;
1983                 }
1984
1985                 seqno = request->seqno;
1986         }
1987
1988         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
1989                 if (HAS_PCH_SPLIT(dev))
1990                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1991                 else
1992                         ier = I915_READ(IER);
1993                 if (!ier) {
1994                         DRM_ERROR("something (likely vbetool) disabled "
1995                                   "interrupts, re-enabling\n");
1996                         i915_driver_irq_preinstall(dev);
1997                         i915_driver_irq_postinstall(dev);
1998                 }
1999
2000                 trace_i915_gem_request_wait_begin(dev, seqno);
2001
2002                 ring->waiting_seqno = seqno;
2003                 ret = -ENODEV;
2004                 if (ring->irq_get(ring)) {
2005                         if (interruptible)
2006                                 ret = wait_event_interruptible(ring->irq_queue,
2007                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2008                                                                || atomic_read(&dev_priv->mm.wedged));
2009                         else
2010                                 wait_event(ring->irq_queue,
2011                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2012                                            || atomic_read(&dev_priv->mm.wedged));
2013
2014                         ring->irq_put(ring);
2015                 }
2016                 ring->waiting_seqno = 0;
2017
2018                 trace_i915_gem_request_wait_end(dev, seqno);
2019         }
2020         if (atomic_read(&dev_priv->mm.wedged))
2021                 ret = -EAGAIN;
2022
2023         if (ret && ret != -ERESTARTSYS)
2024                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2025                           __func__, ret, seqno, ring->get_seqno(ring),
2026                           dev_priv->next_seqno);
2027
2028         /* Directly dispatch request retiring.  While we have the work queue
2029          * to handle this, the waiter on a request often wants an associated
2030          * buffer to have made it to the inactive list, and we would need
2031          * a separate wait queue to handle that.
2032          */
2033         if (ret == 0)
2034                 i915_gem_retire_requests_ring(dev, ring);
2035
2036         return ret;
2037 }
2038
2039 /**
2040  * Waits for a sequence number to be signaled, and cleans up the
2041  * request and object lists appropriately for that event.
2042  */
2043 static int
2044 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2045                   struct intel_ring_buffer *ring)
2046 {
2047         return i915_do_wait_request(dev, seqno, 1, ring);
2048 }
2049
2050 /**
2051  * Ensures that all rendering to the object has completed and the object is
2052  * safe to unbind from the GTT or access from the CPU.
2053  */
2054 int
2055 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2056                                bool interruptible)
2057 {
2058         struct drm_device *dev = obj->base.dev;
2059         int ret;
2060
2061         /* This function only exists to support waiting for existing rendering,
2062          * not for emitting required flushes.
2063          */
2064         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2065
2066         /* If there is rendering queued on the buffer being evicted, wait for
2067          * it.
2068          */
2069         if (obj->active) {
2070                 ret = i915_do_wait_request(dev,
2071                                            obj->last_rendering_seqno,
2072                                            interruptible,
2073                                            obj->ring);
2074                 if (ret)
2075                         return ret;
2076         }
2077
2078         return 0;
2079 }
2080
2081 /**
2082  * Unbinds an object from the GTT aperture.
2083  */
2084 int
2085 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2086 {
2087         int ret = 0;
2088
2089         if (obj->gtt_space == NULL)
2090                 return 0;
2091
2092         if (obj->pin_count != 0) {
2093                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2094                 return -EINVAL;
2095         }
2096
2097         /* blow away mappings if mapped through GTT */
2098         i915_gem_release_mmap(obj);
2099
2100         /* Move the object to the CPU domain to ensure that
2101          * any possible CPU writes while it's not in the GTT
2102          * are flushed when we go to remap it. This will
2103          * also ensure that all pending GPU writes are finished
2104          * before we unbind.
2105          */
2106         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2107         if (ret == -ERESTARTSYS)
2108                 return ret;
2109         /* Continue on if we fail due to EIO, the GPU is hung so we
2110          * should be safe and we need to cleanup or else we might
2111          * cause memory corruption through use-after-free.
2112          */
2113         if (ret) {
2114                 i915_gem_clflush_object(obj);
2115                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2116         }
2117
2118         /* release the fence reg _after_ flushing */
2119         ret = i915_gem_object_put_fence(obj);
2120         if (ret == -ERESTARTSYS)
2121                 return ret;
2122
2123         i915_gem_gtt_unbind_object(obj);
2124         i915_gem_object_put_pages_gtt(obj);
2125
2126         list_del_init(&obj->gtt_list);
2127         list_del_init(&obj->mm_list);
2128         /* Avoid an unnecessary call to unbind on rebind. */
2129         obj->map_and_fenceable = true;
2130
2131         drm_mm_put_block(obj->gtt_space);
2132         obj->gtt_space = NULL;
2133         obj->gtt_offset = 0;
2134
2135         if (i915_gem_object_is_purgeable(obj))
2136                 i915_gem_object_truncate(obj);
2137
2138         trace_i915_gem_object_unbind(obj);
2139
2140         return ret;
2141 }
2142
2143 void
2144 i915_gem_flush_ring(struct drm_device *dev,
2145                     struct intel_ring_buffer *ring,
2146                     uint32_t invalidate_domains,
2147                     uint32_t flush_domains)
2148 {
2149         ring->flush(ring, invalidate_domains, flush_domains);
2150         i915_gem_process_flushing_list(dev, flush_domains, ring);
2151 }
2152
2153 static int i915_ring_idle(struct drm_device *dev,
2154                           struct intel_ring_buffer *ring)
2155 {
2156         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2157                 return 0;
2158
2159         if (!list_empty(&ring->gpu_write_list))
2160                 i915_gem_flush_ring(dev, ring,
2161                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2162         return i915_wait_request(dev,
2163                                  i915_gem_next_request_seqno(dev, ring),
2164                                  ring);
2165 }
2166
2167 int
2168 i915_gpu_idle(struct drm_device *dev)
2169 {
2170         drm_i915_private_t *dev_priv = dev->dev_private;
2171         bool lists_empty;
2172         int ret, i;
2173
2174         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2175                        list_empty(&dev_priv->mm.active_list));
2176         if (lists_empty)
2177                 return 0;
2178
2179         /* Flush everything onto the inactive list. */
2180         for (i = 0; i < I915_NUM_RINGS; i++) {
2181                 ret = i915_ring_idle(dev, &dev_priv->ring[i]);
2182                 if (ret)
2183                         return ret;
2184         }
2185
2186         return 0;
2187 }
2188
2189 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2190                                        struct intel_ring_buffer *pipelined)
2191 {
2192         struct drm_device *dev = obj->base.dev;
2193         drm_i915_private_t *dev_priv = dev->dev_private;
2194         u32 size = obj->gtt_space->size;
2195         int regnum = obj->fence_reg;
2196         uint64_t val;
2197
2198         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2199                          0xfffff000) << 32;
2200         val |= obj->gtt_offset & 0xfffff000;
2201         val |= (uint64_t)((obj->stride / 128) - 1) <<
2202                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2203
2204         if (obj->tiling_mode == I915_TILING_Y)
2205                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2206         val |= I965_FENCE_REG_VALID;
2207
2208         if (pipelined) {
2209                 int ret = intel_ring_begin(pipelined, 6);
2210                 if (ret)
2211                         return ret;
2212
2213                 intel_ring_emit(pipelined, MI_NOOP);
2214                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2215                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2216                 intel_ring_emit(pipelined, (u32)val);
2217                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2218                 intel_ring_emit(pipelined, (u32)(val >> 32));
2219                 intel_ring_advance(pipelined);
2220         } else
2221                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2222
2223         return 0;
2224 }
2225
2226 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2227                                 struct intel_ring_buffer *pipelined)
2228 {
2229         struct drm_device *dev = obj->base.dev;
2230         drm_i915_private_t *dev_priv = dev->dev_private;
2231         u32 size = obj->gtt_space->size;
2232         int regnum = obj->fence_reg;
2233         uint64_t val;
2234
2235         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2236                     0xfffff000) << 32;
2237         val |= obj->gtt_offset & 0xfffff000;
2238         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2239         if (obj->tiling_mode == I915_TILING_Y)
2240                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2241         val |= I965_FENCE_REG_VALID;
2242
2243         if (pipelined) {
2244                 int ret = intel_ring_begin(pipelined, 6);
2245                 if (ret)
2246                         return ret;
2247
2248                 intel_ring_emit(pipelined, MI_NOOP);
2249                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2250                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2251                 intel_ring_emit(pipelined, (u32)val);
2252                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2253                 intel_ring_emit(pipelined, (u32)(val >> 32));
2254                 intel_ring_advance(pipelined);
2255         } else
2256                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2257
2258         return 0;
2259 }
2260
2261 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2262                                 struct intel_ring_buffer *pipelined)
2263 {
2264         struct drm_device *dev = obj->base.dev;
2265         drm_i915_private_t *dev_priv = dev->dev_private;
2266         u32 size = obj->gtt_space->size;
2267         u32 fence_reg, val, pitch_val;
2268         int tile_width;
2269
2270         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2271                  (size & -size) != size ||
2272                  (obj->gtt_offset & (size - 1)),
2273                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2274                  obj->gtt_offset, obj->map_and_fenceable, size))
2275                 return -EINVAL;
2276
2277         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2278                 tile_width = 128;
2279         else
2280                 tile_width = 512;
2281
2282         /* Note: pitch better be a power of two tile widths */
2283         pitch_val = obj->stride / tile_width;
2284         pitch_val = ffs(pitch_val) - 1;
2285
2286         val = obj->gtt_offset;
2287         if (obj->tiling_mode == I915_TILING_Y)
2288                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2289         val |= I915_FENCE_SIZE_BITS(size);
2290         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2291         val |= I830_FENCE_REG_VALID;
2292
2293         fence_reg = obj->fence_reg;
2294         if (fence_reg < 8)
2295                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2296         else
2297                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2298
2299         if (pipelined) {
2300                 int ret = intel_ring_begin(pipelined, 4);
2301                 if (ret)
2302                         return ret;
2303
2304                 intel_ring_emit(pipelined, MI_NOOP);
2305                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2306                 intel_ring_emit(pipelined, fence_reg);
2307                 intel_ring_emit(pipelined, val);
2308                 intel_ring_advance(pipelined);
2309         } else
2310                 I915_WRITE(fence_reg, val);
2311
2312         return 0;
2313 }
2314
2315 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2316                                 struct intel_ring_buffer *pipelined)
2317 {
2318         struct drm_device *dev = obj->base.dev;
2319         drm_i915_private_t *dev_priv = dev->dev_private;
2320         u32 size = obj->gtt_space->size;
2321         int regnum = obj->fence_reg;
2322         uint32_t val;
2323         uint32_t pitch_val;
2324
2325         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2326                  (size & -size) != size ||
2327                  (obj->gtt_offset & (size - 1)),
2328                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2329                  obj->gtt_offset, size))
2330                 return -EINVAL;
2331
2332         pitch_val = obj->stride / 128;
2333         pitch_val = ffs(pitch_val) - 1;
2334
2335         val = obj->gtt_offset;
2336         if (obj->tiling_mode == I915_TILING_Y)
2337                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2338         val |= I830_FENCE_SIZE_BITS(size);
2339         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2340         val |= I830_FENCE_REG_VALID;
2341
2342         if (pipelined) {
2343                 int ret = intel_ring_begin(pipelined, 4);
2344                 if (ret)
2345                         return ret;
2346
2347                 intel_ring_emit(pipelined, MI_NOOP);
2348                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2349                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2350                 intel_ring_emit(pipelined, val);
2351                 intel_ring_advance(pipelined);
2352         } else
2353                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2354
2355         return 0;
2356 }
2357
2358 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2359 {
2360         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2361 }
2362
2363 static int
2364 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2365                             struct intel_ring_buffer *pipelined,
2366                             bool interruptible)
2367 {
2368         int ret;
2369
2370         if (obj->fenced_gpu_access) {
2371                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2372                         i915_gem_flush_ring(obj->base.dev,
2373                                             obj->last_fenced_ring,
2374                                             0, obj->base.write_domain);
2375
2376                 obj->fenced_gpu_access = false;
2377         }
2378
2379         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2380                 if (!ring_passed_seqno(obj->last_fenced_ring,
2381                                        obj->last_fenced_seqno)) {
2382                         ret = i915_do_wait_request(obj->base.dev,
2383                                                    obj->last_fenced_seqno,
2384                                                    interruptible,
2385                                                    obj->last_fenced_ring);
2386                         if (ret)
2387                                 return ret;
2388                 }
2389
2390                 obj->last_fenced_seqno = 0;
2391                 obj->last_fenced_ring = NULL;
2392         }
2393
2394         return 0;
2395 }
2396
2397 int
2398 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2399 {
2400         int ret;
2401
2402         if (obj->tiling_mode)
2403                 i915_gem_release_mmap(obj);
2404
2405         ret = i915_gem_object_flush_fence(obj, NULL, true);
2406         if (ret)
2407                 return ret;
2408
2409         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2410                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2411                 i915_gem_clear_fence_reg(obj->base.dev,
2412                                          &dev_priv->fence_regs[obj->fence_reg]);
2413
2414                 obj->fence_reg = I915_FENCE_REG_NONE;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static struct drm_i915_fence_reg *
2421 i915_find_fence_reg(struct drm_device *dev,
2422                     struct intel_ring_buffer *pipelined)
2423 {
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct drm_i915_fence_reg *reg, *first, *avail;
2426         int i;
2427
2428         /* First try to find a free reg */
2429         avail = NULL;
2430         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2431                 reg = &dev_priv->fence_regs[i];
2432                 if (!reg->obj)
2433                         return reg;
2434
2435                 if (!reg->obj->pin_count)
2436                         avail = reg;
2437         }
2438
2439         if (avail == NULL)
2440                 return NULL;
2441
2442         /* None available, try to steal one or wait for a user to finish */
2443         avail = first = NULL;
2444         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2445                 if (reg->obj->pin_count)
2446                         continue;
2447
2448                 if (first == NULL)
2449                         first = reg;
2450
2451                 if (!pipelined ||
2452                     !reg->obj->last_fenced_ring ||
2453                     reg->obj->last_fenced_ring == pipelined) {
2454                         avail = reg;
2455                         break;
2456                 }
2457         }
2458
2459         if (avail == NULL)
2460                 avail = first;
2461
2462         return avail;
2463 }
2464
2465 /**
2466  * i915_gem_object_get_fence - set up a fence reg for an object
2467  * @obj: object to map through a fence reg
2468  * @pipelined: ring on which to queue the change, or NULL for CPU access
2469  * @interruptible: must we wait uninterruptibly for the register to retire?
2470  *
2471  * When mapping objects through the GTT, userspace wants to be able to write
2472  * to them without having to worry about swizzling if the object is tiled.
2473  *
2474  * This function walks the fence regs looking for a free one for @obj,
2475  * stealing one if it can't find any.
2476  *
2477  * It then sets up the reg based on the object's properties: address, pitch
2478  * and tiling format.
2479  */
2480 int
2481 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2482                           struct intel_ring_buffer *pipelined,
2483                           bool interruptible)
2484 {
2485         struct drm_device *dev = obj->base.dev;
2486         struct drm_i915_private *dev_priv = dev->dev_private;
2487         struct drm_i915_fence_reg *reg;
2488         int ret;
2489
2490         /* XXX disable pipelining. There are bugs. Shocking. */
2491         pipelined = NULL;
2492
2493         /* Just update our place in the LRU if our fence is getting reused. */
2494         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2495                 reg = &dev_priv->fence_regs[obj->fence_reg];
2496                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2497
2498                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2499                         pipelined = NULL;
2500
2501                 if (!pipelined) {
2502                         if (reg->setup_seqno) {
2503                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2504                                                        reg->setup_seqno)) {
2505                                         ret = i915_do_wait_request(obj->base.dev,
2506                                                                    reg->setup_seqno,
2507                                                                    interruptible,
2508                                                                    obj->last_fenced_ring);
2509                                         if (ret)
2510                                                 return ret;
2511                                 }
2512
2513                                 reg->setup_seqno = 0;
2514                         }
2515                 } else if (obj->last_fenced_ring &&
2516                            obj->last_fenced_ring != pipelined) {
2517                         ret = i915_gem_object_flush_fence(obj,
2518                                                           pipelined,
2519                                                           interruptible);
2520                         if (ret)
2521                                 return ret;
2522                 } else if (obj->tiling_changed) {
2523                         if (obj->fenced_gpu_access) {
2524                                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2525                                         i915_gem_flush_ring(obj->base.dev, obj->ring,
2526                                                             0, obj->base.write_domain);
2527
2528                                 obj->fenced_gpu_access = false;
2529                         }
2530                 }
2531
2532                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2533                         pipelined = NULL;
2534                 BUG_ON(!pipelined && reg->setup_seqno);
2535
2536                 if (obj->tiling_changed) {
2537                         if (pipelined) {
2538                                 reg->setup_seqno =
2539                                         i915_gem_next_request_seqno(dev, pipelined);
2540                                 obj->last_fenced_seqno = reg->setup_seqno;
2541                                 obj->last_fenced_ring = pipelined;
2542                         }
2543                         goto update;
2544                 }
2545
2546                 return 0;
2547         }
2548
2549         reg = i915_find_fence_reg(dev, pipelined);
2550         if (reg == NULL)
2551                 return -ENOSPC;
2552
2553         ret = i915_gem_object_flush_fence(obj, pipelined, interruptible);
2554         if (ret)
2555                 return ret;
2556
2557         if (reg->obj) {
2558                 struct drm_i915_gem_object *old = reg->obj;
2559
2560                 drm_gem_object_reference(&old->base);
2561
2562                 if (old->tiling_mode)
2563                         i915_gem_release_mmap(old);
2564
2565                 ret = i915_gem_object_flush_fence(old,
2566                                                   pipelined,
2567                                                   interruptible);
2568                 if (ret) {
2569                         drm_gem_object_unreference(&old->base);
2570                         return ret;
2571                 }
2572
2573                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2574                         pipelined = NULL;
2575
2576                 old->fence_reg = I915_FENCE_REG_NONE;
2577                 old->last_fenced_ring = pipelined;
2578                 old->last_fenced_seqno =
2579                         pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2580
2581                 drm_gem_object_unreference(&old->base);
2582         } else if (obj->last_fenced_seqno == 0)
2583                 pipelined = NULL;
2584
2585         reg->obj = obj;
2586         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2587         obj->fence_reg = reg - dev_priv->fence_regs;
2588         obj->last_fenced_ring = pipelined;
2589
2590         reg->setup_seqno =
2591                 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2592         obj->last_fenced_seqno = reg->setup_seqno;
2593
2594 update:
2595         obj->tiling_changed = false;
2596         switch (INTEL_INFO(dev)->gen) {
2597         case 6:
2598                 ret = sandybridge_write_fence_reg(obj, pipelined);
2599                 break;
2600         case 5:
2601         case 4:
2602                 ret = i965_write_fence_reg(obj, pipelined);
2603                 break;
2604         case 3:
2605                 ret = i915_write_fence_reg(obj, pipelined);
2606                 break;
2607         case 2:
2608                 ret = i830_write_fence_reg(obj, pipelined);
2609                 break;
2610         }
2611
2612         return ret;
2613 }
2614
2615 /**
2616  * i915_gem_clear_fence_reg - clear out fence register info
2617  * @obj: object to clear
2618  *
2619  * Zeroes out the fence register itself and clears out the associated
2620  * data structures in dev_priv and obj.
2621  */
2622 static void
2623 i915_gem_clear_fence_reg(struct drm_device *dev,
2624                          struct drm_i915_fence_reg *reg)
2625 {
2626         drm_i915_private_t *dev_priv = dev->dev_private;
2627         uint32_t fence_reg = reg - dev_priv->fence_regs;
2628
2629         switch (INTEL_INFO(dev)->gen) {
2630         case 6:
2631                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2632                 break;
2633         case 5:
2634         case 4:
2635                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2636                 break;
2637         case 3:
2638                 if (fence_reg >= 8)
2639                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2640                 else
2641         case 2:
2642                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2643
2644                 I915_WRITE(fence_reg, 0);
2645                 break;
2646         }
2647
2648         list_del_init(&reg->lru_list);
2649         reg->obj = NULL;
2650         reg->setup_seqno = 0;
2651 }
2652
2653 /**
2654  * Finds free space in the GTT aperture and binds the object there.
2655  */
2656 static int
2657 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2658                             unsigned alignment,
2659                             bool map_and_fenceable)
2660 {
2661         struct drm_device *dev = obj->base.dev;
2662         drm_i915_private_t *dev_priv = dev->dev_private;
2663         struct drm_mm_node *free_space;
2664         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2665         u32 size, fence_size, fence_alignment, unfenced_alignment;
2666         bool mappable, fenceable;
2667         int ret;
2668
2669         if (obj->madv != I915_MADV_WILLNEED) {
2670                 DRM_ERROR("Attempting to bind a purgeable object\n");
2671                 return -EINVAL;
2672         }
2673
2674         fence_size = i915_gem_get_gtt_size(obj);
2675         fence_alignment = i915_gem_get_gtt_alignment(obj);
2676         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2677
2678         if (alignment == 0)
2679                 alignment = map_and_fenceable ? fence_alignment :
2680                                                 unfenced_alignment;
2681         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2682                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2683                 return -EINVAL;
2684         }
2685
2686         size = map_and_fenceable ? fence_size : obj->base.size;
2687
2688         /* If the object is bigger than the entire aperture, reject it early
2689          * before evicting everything in a vain attempt to find space.
2690          */
2691         if (obj->base.size >
2692             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2693                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2694                 return -E2BIG;
2695         }
2696
2697  search_free:
2698         if (map_and_fenceable)
2699                 free_space =
2700                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2701                                                     size, alignment, 0,
2702                                                     dev_priv->mm.gtt_mappable_end,
2703                                                     0);
2704         else
2705                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2706                                                 size, alignment, 0);
2707
2708         if (free_space != NULL) {
2709                 if (map_and_fenceable)
2710                         obj->gtt_space =
2711                                 drm_mm_get_block_range_generic(free_space,
2712                                                                size, alignment, 0,
2713                                                                dev_priv->mm.gtt_mappable_end,
2714                                                                0);
2715                 else
2716                         obj->gtt_space =
2717                                 drm_mm_get_block(free_space, size, alignment);
2718         }
2719         if (obj->gtt_space == NULL) {
2720                 /* If the gtt is empty and we're still having trouble
2721                  * fitting our object in, we're out of memory.
2722                  */
2723                 ret = i915_gem_evict_something(dev, size, alignment,
2724                                                map_and_fenceable);
2725                 if (ret)
2726                         return ret;
2727
2728                 goto search_free;
2729         }
2730
2731         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2732         if (ret) {
2733                 drm_mm_put_block(obj->gtt_space);
2734                 obj->gtt_space = NULL;
2735
2736                 if (ret == -ENOMEM) {
2737                         /* first try to clear up some space from the GTT */
2738                         ret = i915_gem_evict_something(dev, size,
2739                                                        alignment,
2740                                                        map_and_fenceable);
2741                         if (ret) {
2742                                 /* now try to shrink everyone else */
2743                                 if (gfpmask) {
2744                                         gfpmask = 0;
2745                                         goto search_free;
2746                                 }
2747
2748                                 return ret;
2749                         }
2750
2751                         goto search_free;
2752                 }
2753
2754                 return ret;
2755         }
2756
2757         ret = i915_gem_gtt_bind_object(obj);
2758         if (ret) {
2759                 i915_gem_object_put_pages_gtt(obj);
2760                 drm_mm_put_block(obj->gtt_space);
2761                 obj->gtt_space = NULL;
2762
2763                 ret = i915_gem_evict_something(dev, size,
2764                                                alignment, map_and_fenceable);
2765                 if (ret)
2766                         return ret;
2767
2768                 goto search_free;
2769         }
2770
2771         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2772         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2773
2774         /* Assert that the object is not currently in any GPU domain. As it
2775          * wasn't in the GTT, there shouldn't be any way it could have been in
2776          * a GPU cache
2777          */
2778         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2779         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2780
2781         obj->gtt_offset = obj->gtt_space->start;
2782
2783         fenceable =
2784                 obj->gtt_space->size == fence_size &&
2785                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2786
2787         mappable =
2788                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2789
2790         obj->map_and_fenceable = mappable && fenceable;
2791
2792         trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable);
2793         return 0;
2794 }
2795
2796 void
2797 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2798 {
2799         /* If we don't have a page list set up, then we're not pinned
2800          * to GPU, and we can ignore the cache flush because it'll happen
2801          * again at bind time.
2802          */
2803         if (obj->pages == NULL)
2804                 return;
2805
2806         trace_i915_gem_object_clflush(obj);
2807
2808         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2809 }
2810
2811 /** Flushes any GPU write domain for the object if it's dirty. */
2812 static void
2813 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2814 {
2815         struct drm_device *dev = obj->base.dev;
2816
2817         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2818                 return;
2819
2820         /* Queue the GPU write cache flushing we need. */
2821         i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
2822         BUG_ON(obj->base.write_domain);
2823 }
2824
2825 /** Flushes the GTT write domain for the object if it's dirty. */
2826 static void
2827 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2828 {
2829         uint32_t old_write_domain;
2830
2831         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2832                 return;
2833
2834         /* No actual flushing is required for the GTT write domain.   Writes
2835          * to it immediately go to main memory as far as we know, so there's
2836          * no chipset flush.  It also doesn't land in render cache.
2837          */
2838         i915_gem_release_mmap(obj);
2839
2840         old_write_domain = obj->base.write_domain;
2841         obj->base.write_domain = 0;
2842
2843         trace_i915_gem_object_change_domain(obj,
2844                                             obj->base.read_domains,
2845                                             old_write_domain);
2846 }
2847
2848 /** Flushes the CPU write domain for the object if it's dirty. */
2849 static void
2850 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2851 {
2852         uint32_t old_write_domain;
2853
2854         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2855                 return;
2856
2857         i915_gem_clflush_object(obj);
2858         intel_gtt_chipset_flush();
2859         old_write_domain = obj->base.write_domain;
2860         obj->base.write_domain = 0;
2861
2862         trace_i915_gem_object_change_domain(obj,
2863                                             obj->base.read_domains,
2864                                             old_write_domain);
2865 }
2866
2867 /**
2868  * Moves a single object to the GTT read, and possibly write domain.
2869  *
2870  * This function returns when the move is complete, including waiting on
2871  * flushes to occur.
2872  */
2873 int
2874 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2875 {
2876         uint32_t old_write_domain, old_read_domains;
2877         int ret;
2878
2879         /* Not valid to be called on unbound objects. */
2880         if (obj->gtt_space == NULL)
2881                 return -EINVAL;
2882
2883         i915_gem_object_flush_gpu_write_domain(obj);
2884         if (obj->pending_gpu_write || write) {
2885                 ret = i915_gem_object_wait_rendering(obj, true);
2886                 if (ret)
2887                         return ret;
2888         }
2889
2890         i915_gem_object_flush_cpu_write_domain(obj);
2891
2892         old_write_domain = obj->base.write_domain;
2893         old_read_domains = obj->base.read_domains;
2894
2895         /* It should now be out of any other write domains, and we can update
2896          * the domain values for our changes.
2897          */
2898         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2899         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2900         if (write) {
2901                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2902                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2903                 obj->dirty = 1;
2904         }
2905
2906         trace_i915_gem_object_change_domain(obj,
2907                                             old_read_domains,
2908                                             old_write_domain);
2909
2910         return 0;
2911 }
2912
2913 /*
2914  * Prepare buffer for display plane. Use uninterruptible for possible flush
2915  * wait, as in modesetting process we're not supposed to be interrupted.
2916  */
2917 int
2918 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
2919                                      struct intel_ring_buffer *pipelined)
2920 {
2921         uint32_t old_read_domains;
2922         int ret;
2923
2924         /* Not valid to be called on unbound objects. */
2925         if (obj->gtt_space == NULL)
2926                 return -EINVAL;
2927
2928         i915_gem_object_flush_gpu_write_domain(obj);
2929
2930         /* Currently, we are always called from an non-interruptible context. */
2931         if (pipelined != obj->ring) {
2932                 ret = i915_gem_object_wait_rendering(obj, false);
2933                 if (ret)
2934                         return ret;
2935         }
2936
2937         i915_gem_object_flush_cpu_write_domain(obj);
2938
2939         old_read_domains = obj->base.read_domains;
2940         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2941
2942         trace_i915_gem_object_change_domain(obj,
2943                                             old_read_domains,
2944                                             obj->base.write_domain);
2945
2946         return 0;
2947 }
2948
2949 int
2950 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
2951                           bool interruptible)
2952 {
2953         if (!obj->active)
2954                 return 0;
2955
2956         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2957                 i915_gem_flush_ring(obj->base.dev, obj->ring,
2958                                     0, obj->base.write_domain);
2959
2960         return i915_gem_object_wait_rendering(obj, interruptible);
2961 }
2962
2963 /**
2964  * Moves a single object to the CPU read, and possibly write domain.
2965  *
2966  * This function returns when the move is complete, including waiting on
2967  * flushes to occur.
2968  */
2969 static int
2970 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2971 {
2972         uint32_t old_write_domain, old_read_domains;
2973         int ret;
2974
2975         i915_gem_object_flush_gpu_write_domain(obj);
2976         ret = i915_gem_object_wait_rendering(obj, true);
2977         if (ret)
2978                 return ret;
2979
2980         i915_gem_object_flush_gtt_write_domain(obj);
2981
2982         /* If we have a partially-valid cache of the object in the CPU,
2983          * finish invalidating it and free the per-page flags.
2984          */
2985         i915_gem_object_set_to_full_cpu_read_domain(obj);
2986
2987         old_write_domain = obj->base.write_domain;
2988         old_read_domains = obj->base.read_domains;
2989
2990         /* Flush the CPU cache if it's still invalid. */
2991         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2992                 i915_gem_clflush_object(obj);
2993
2994                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2995         }
2996
2997         /* It should now be out of any other write domains, and we can update
2998          * the domain values for our changes.
2999          */
3000         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3001
3002         /* If we're writing through the CPU, then the GPU read domains will
3003          * need to be invalidated at next use.
3004          */
3005         if (write) {
3006                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3007                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3008         }
3009
3010         trace_i915_gem_object_change_domain(obj,
3011                                             old_read_domains,
3012                                             old_write_domain);
3013
3014         return 0;
3015 }
3016
3017 /**
3018  * Moves the object from a partially CPU read to a full one.
3019  *
3020  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3021  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3022  */
3023 static void
3024 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3025 {
3026         if (!obj->page_cpu_valid)
3027                 return;
3028
3029         /* If we're partially in the CPU read domain, finish moving it in.
3030          */
3031         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3032                 int i;
3033
3034                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3035                         if (obj->page_cpu_valid[i])
3036                                 continue;
3037                         drm_clflush_pages(obj->pages + i, 1);
3038                 }
3039         }
3040
3041         /* Free the page_cpu_valid mappings which are now stale, whether
3042          * or not we've got I915_GEM_DOMAIN_CPU.
3043          */
3044         kfree(obj->page_cpu_valid);
3045         obj->page_cpu_valid = NULL;
3046 }
3047
3048 /**
3049  * Set the CPU read domain on a range of the object.
3050  *
3051  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3052  * not entirely valid.  The page_cpu_valid member of the object flags which
3053  * pages have been flushed, and will be respected by
3054  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3055  * of the whole object.
3056  *
3057  * This function returns when the move is complete, including waiting on
3058  * flushes to occur.
3059  */
3060 static int
3061 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3062                                           uint64_t offset, uint64_t size)
3063 {
3064         uint32_t old_read_domains;
3065         int i, ret;
3066
3067         if (offset == 0 && size == obj->base.size)
3068                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3069
3070         i915_gem_object_flush_gpu_write_domain(obj);
3071         ret = i915_gem_object_wait_rendering(obj, true);
3072         if (ret)
3073                 return ret;
3074
3075         i915_gem_object_flush_gtt_write_domain(obj);
3076
3077         /* If we're already fully in the CPU read domain, we're done. */
3078         if (obj->page_cpu_valid == NULL &&
3079             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3080                 return 0;
3081
3082         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3083          * newly adding I915_GEM_DOMAIN_CPU
3084          */
3085         if (obj->page_cpu_valid == NULL) {
3086                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3087                                               GFP_KERNEL);
3088                 if (obj->page_cpu_valid == NULL)
3089                         return -ENOMEM;
3090         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3091                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3092
3093         /* Flush the cache on any pages that are still invalid from the CPU's
3094          * perspective.
3095          */
3096         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3097              i++) {
3098                 if (obj->page_cpu_valid[i])
3099                         continue;
3100
3101                 drm_clflush_pages(obj->pages + i, 1);
3102
3103                 obj->page_cpu_valid[i] = 1;
3104         }
3105
3106         /* It should now be out of any other write domains, and we can update
3107          * the domain values for our changes.
3108          */
3109         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3110
3111         old_read_domains = obj->base.read_domains;
3112         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3113
3114         trace_i915_gem_object_change_domain(obj,
3115                                             old_read_domains,
3116                                             obj->base.write_domain);
3117
3118         return 0;
3119 }
3120
3121 /* Throttle our rendering by waiting until the ring has completed our requests
3122  * emitted over 20 msec ago.
3123  *
3124  * Note that if we were to use the current jiffies each time around the loop,
3125  * we wouldn't escape the function with any frames outstanding if the time to
3126  * render a frame was over 20ms.
3127  *
3128  * This should get us reasonable parallelism between CPU and GPU but also
3129  * relatively low latency when blocking on a particular request to finish.
3130  */
3131 static int
3132 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3133 {
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135         struct drm_i915_file_private *file_priv = file->driver_priv;
3136         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3137         struct drm_i915_gem_request *request;
3138         struct intel_ring_buffer *ring = NULL;
3139         u32 seqno = 0;
3140         int ret;
3141
3142         spin_lock(&file_priv->mm.lock);
3143         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3144                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3145                         break;
3146
3147                 ring = request->ring;
3148                 seqno = request->seqno;
3149         }
3150         spin_unlock(&file_priv->mm.lock);
3151
3152         if (seqno == 0)
3153                 return 0;
3154
3155         ret = 0;
3156         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3157                 /* And wait for the seqno passing without holding any locks and
3158                  * causing extra latency for others. This is safe as the irq
3159                  * generation is designed to be run atomically and so is
3160                  * lockless.
3161                  */
3162                 if (ring->irq_get(ring)) {
3163                         ret = wait_event_interruptible(ring->irq_queue,
3164                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3165                                                        || atomic_read(&dev_priv->mm.wedged));
3166                         ring->irq_put(ring);
3167
3168                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3169                                 ret = -EIO;
3170                 }
3171         }
3172
3173         if (ret == 0)
3174                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3175
3176         return ret;
3177 }
3178
3179 int
3180 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3181                     uint32_t alignment,
3182                     bool map_and_fenceable)
3183 {
3184         struct drm_device *dev = obj->base.dev;
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186         int ret;
3187
3188         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3189         WARN_ON(i915_verify_lists(dev));
3190
3191         if (obj->gtt_space != NULL) {
3192                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3193                     (map_and_fenceable && !obj->map_and_fenceable)) {
3194                         WARN(obj->pin_count,
3195                              "bo is already pinned with incorrect alignment:"
3196                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3197                              " obj->map_and_fenceable=%d\n",
3198                              obj->gtt_offset, alignment,
3199                              map_and_fenceable,
3200                              obj->map_and_fenceable);
3201                         ret = i915_gem_object_unbind(obj);
3202                         if (ret)
3203                                 return ret;
3204                 }
3205         }
3206
3207         if (obj->gtt_space == NULL) {
3208                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3209                                                   map_and_fenceable);
3210                 if (ret)
3211                         return ret;
3212         }
3213
3214         if (obj->pin_count++ == 0) {
3215                 if (!obj->active)
3216                         list_move_tail(&obj->mm_list,
3217                                        &dev_priv->mm.pinned_list);
3218         }
3219         obj->pin_mappable |= map_and_fenceable;
3220
3221         WARN_ON(i915_verify_lists(dev));
3222         return 0;
3223 }
3224
3225 void
3226 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3227 {
3228         struct drm_device *dev = obj->base.dev;
3229         drm_i915_private_t *dev_priv = dev->dev_private;
3230
3231         WARN_ON(i915_verify_lists(dev));
3232         BUG_ON(obj->pin_count == 0);
3233         BUG_ON(obj->gtt_space == NULL);
3234
3235         if (--obj->pin_count == 0) {
3236                 if (!obj->active)
3237                         list_move_tail(&obj->mm_list,
3238                                        &dev_priv->mm.inactive_list);
3239                 obj->pin_mappable = false;
3240         }
3241         WARN_ON(i915_verify_lists(dev));
3242 }
3243
3244 int
3245 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3246                    struct drm_file *file)
3247 {
3248         struct drm_i915_gem_pin *args = data;
3249         struct drm_i915_gem_object *obj;
3250         int ret;
3251
3252         ret = i915_mutex_lock_interruptible(dev);
3253         if (ret)
3254                 return ret;
3255
3256         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3257         if (obj == NULL) {
3258                 ret = -ENOENT;
3259                 goto unlock;
3260         }
3261
3262         if (obj->madv != I915_MADV_WILLNEED) {
3263                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3264                 ret = -EINVAL;
3265                 goto out;
3266         }
3267
3268         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3269                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3270                           args->handle);
3271                 ret = -EINVAL;
3272                 goto out;
3273         }
3274
3275         obj->user_pin_count++;
3276         obj->pin_filp = file;
3277         if (obj->user_pin_count == 1) {
3278                 ret = i915_gem_object_pin(obj, args->alignment, true);
3279                 if (ret)
3280                         goto out;
3281         }
3282
3283         /* XXX - flush the CPU caches for pinned objects
3284          * as the X server doesn't manage domains yet
3285          */
3286         i915_gem_object_flush_cpu_write_domain(obj);
3287         args->offset = obj->gtt_offset;
3288 out:
3289         drm_gem_object_unreference(&obj->base);
3290 unlock:
3291         mutex_unlock(&dev->struct_mutex);
3292         return ret;
3293 }
3294
3295 int
3296 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3297                      struct drm_file *file)
3298 {
3299         struct drm_i915_gem_pin *args = data;
3300         struct drm_i915_gem_object *obj;
3301         int ret;
3302
3303         ret = i915_mutex_lock_interruptible(dev);
3304         if (ret)
3305                 return ret;
3306
3307         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3308         if (obj == NULL) {
3309                 ret = -ENOENT;
3310                 goto unlock;
3311         }
3312
3313         if (obj->pin_filp != file) {
3314                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3315                           args->handle);
3316                 ret = -EINVAL;
3317                 goto out;
3318         }
3319         obj->user_pin_count--;
3320         if (obj->user_pin_count == 0) {
3321                 obj->pin_filp = NULL;
3322                 i915_gem_object_unpin(obj);
3323         }
3324
3325 out:
3326         drm_gem_object_unreference(&obj->base);
3327 unlock:
3328         mutex_unlock(&dev->struct_mutex);
3329         return ret;
3330 }
3331
3332 int
3333 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3334                     struct drm_file *file)
3335 {
3336         struct drm_i915_gem_busy *args = data;
3337         struct drm_i915_gem_object *obj;
3338         int ret;
3339
3340         ret = i915_mutex_lock_interruptible(dev);
3341         if (ret)
3342                 return ret;
3343
3344         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3345         if (obj == NULL) {
3346                 ret = -ENOENT;
3347                 goto unlock;
3348         }
3349
3350         /* Count all active objects as busy, even if they are currently not used
3351          * by the gpu. Users of this interface expect objects to eventually
3352          * become non-busy without any further actions, therefore emit any
3353          * necessary flushes here.
3354          */
3355         args->busy = obj->active;
3356         if (args->busy) {
3357                 /* Unconditionally flush objects, even when the gpu still uses this
3358                  * object. Userspace calling this function indicates that it wants to
3359                  * use this buffer rather sooner than later, so issuing the required
3360                  * flush earlier is beneficial.
3361                  */
3362                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3363                         i915_gem_flush_ring(dev, obj->ring,
3364                                             0, obj->base.write_domain);
3365                 } else if (obj->ring->outstanding_lazy_request ==
3366                            obj->last_rendering_seqno) {
3367                         struct drm_i915_gem_request *request;
3368
3369                         /* This ring is not being cleared by active usage,
3370                          * so emit a request to do so.
3371                          */
3372                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3373                         if (request)
3374                                 ret = i915_add_request(dev,
3375                                                        NULL, request,
3376                                                        obj->ring);
3377                         else
3378                                 ret = -ENOMEM;
3379                 }
3380
3381                 /* Update the active list for the hardware's current position.
3382                  * Otherwise this only updates on a delayed timer or when irqs
3383                  * are actually unmasked, and our working set ends up being
3384                  * larger than required.
3385                  */
3386                 i915_gem_retire_requests_ring(dev, obj->ring);
3387
3388                 args->busy = obj->active;
3389         }
3390
3391         drm_gem_object_unreference(&obj->base);
3392 unlock:
3393         mutex_unlock(&dev->struct_mutex);
3394         return ret;
3395 }
3396
3397 int
3398 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3399                         struct drm_file *file_priv)
3400 {
3401     return i915_gem_ring_throttle(dev, file_priv);
3402 }
3403
3404 int
3405 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3406                        struct drm_file *file_priv)
3407 {
3408         struct drm_i915_gem_madvise *args = data;
3409         struct drm_i915_gem_object *obj;
3410         int ret;
3411
3412         switch (args->madv) {
3413         case I915_MADV_DONTNEED:
3414         case I915_MADV_WILLNEED:
3415             break;
3416         default:
3417             return -EINVAL;
3418         }
3419
3420         ret = i915_mutex_lock_interruptible(dev);
3421         if (ret)
3422                 return ret;
3423
3424         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3425         if (obj == NULL) {
3426                 ret = -ENOENT;
3427                 goto unlock;
3428         }
3429
3430         if (obj->pin_count) {
3431                 ret = -EINVAL;
3432                 goto out;
3433         }
3434
3435         if (obj->madv != __I915_MADV_PURGED)
3436                 obj->madv = args->madv;
3437
3438         /* if the object is no longer bound, discard its backing storage */
3439         if (i915_gem_object_is_purgeable(obj) &&
3440             obj->gtt_space == NULL)
3441                 i915_gem_object_truncate(obj);
3442
3443         args->retained = obj->madv != __I915_MADV_PURGED;
3444
3445 out:
3446         drm_gem_object_unreference(&obj->base);
3447 unlock:
3448         mutex_unlock(&dev->struct_mutex);
3449         return ret;
3450 }
3451
3452 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3453                                                   size_t size)
3454 {
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456         struct drm_i915_gem_object *obj;
3457
3458         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3459         if (obj == NULL)
3460                 return NULL;
3461
3462         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3463                 kfree(obj);
3464                 return NULL;
3465         }
3466
3467         i915_gem_info_add_obj(dev_priv, size);
3468
3469         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3470         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3471
3472         obj->agp_type = AGP_USER_MEMORY;
3473         obj->base.driver_private = NULL;
3474         obj->fence_reg = I915_FENCE_REG_NONE;
3475         INIT_LIST_HEAD(&obj->mm_list);
3476         INIT_LIST_HEAD(&obj->gtt_list);
3477         INIT_LIST_HEAD(&obj->ring_list);
3478         INIT_LIST_HEAD(&obj->exec_list);
3479         INIT_LIST_HEAD(&obj->gpu_write_list);
3480         obj->madv = I915_MADV_WILLNEED;
3481         /* Avoid an unnecessary call to unbind on the first bind. */
3482         obj->map_and_fenceable = true;
3483
3484         return obj;
3485 }
3486
3487 int i915_gem_init_object(struct drm_gem_object *obj)
3488 {
3489         BUG();
3490
3491         return 0;
3492 }
3493
3494 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3495 {
3496         struct drm_device *dev = obj->base.dev;
3497         drm_i915_private_t *dev_priv = dev->dev_private;
3498         int ret;
3499
3500         ret = i915_gem_object_unbind(obj);
3501         if (ret == -ERESTARTSYS) {
3502                 list_move(&obj->mm_list,
3503                           &dev_priv->mm.deferred_free_list);
3504                 return;
3505         }
3506
3507         if (obj->base.map_list.map)
3508                 i915_gem_free_mmap_offset(obj);
3509
3510         drm_gem_object_release(&obj->base);
3511         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3512
3513         kfree(obj->page_cpu_valid);
3514         kfree(obj->bit_17);
3515         kfree(obj);
3516 }
3517
3518 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3519 {
3520         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3521         struct drm_device *dev = obj->base.dev;
3522
3523         trace_i915_gem_object_destroy(obj);
3524
3525         while (obj->pin_count > 0)
3526                 i915_gem_object_unpin(obj);
3527
3528         if (obj->phys_obj)
3529                 i915_gem_detach_phys_object(dev, obj);
3530
3531         i915_gem_free_object_tail(obj);
3532 }
3533
3534 int
3535 i915_gem_idle(struct drm_device *dev)
3536 {
3537         drm_i915_private_t *dev_priv = dev->dev_private;
3538         int ret;
3539
3540         mutex_lock(&dev->struct_mutex);
3541
3542         if (dev_priv->mm.suspended) {
3543                 mutex_unlock(&dev->struct_mutex);
3544                 return 0;
3545         }
3546
3547         ret = i915_gpu_idle(dev);
3548         if (ret) {
3549                 mutex_unlock(&dev->struct_mutex);
3550                 return ret;
3551         }
3552
3553         /* Under UMS, be paranoid and evict. */
3554         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3555                 ret = i915_gem_evict_inactive(dev, false);
3556                 if (ret) {
3557                         mutex_unlock(&dev->struct_mutex);
3558                         return ret;
3559                 }
3560         }
3561
3562         i915_gem_reset_fences(dev);
3563
3564         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3565          * We need to replace this with a semaphore, or something.
3566          * And not confound mm.suspended!
3567          */
3568         dev_priv->mm.suspended = 1;
3569         del_timer_sync(&dev_priv->hangcheck_timer);
3570
3571         i915_kernel_lost_context(dev);
3572         i915_gem_cleanup_ringbuffer(dev);
3573
3574         mutex_unlock(&dev->struct_mutex);
3575
3576         /* Cancel the retire work handler, which should be idle now. */
3577         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3578
3579         return 0;
3580 }
3581
3582 int
3583 i915_gem_init_ringbuffer(struct drm_device *dev)
3584 {
3585         drm_i915_private_t *dev_priv = dev->dev_private;
3586         int ret;
3587
3588         ret = intel_init_render_ring_buffer(dev);
3589         if (ret)
3590                 return ret;
3591
3592         if (HAS_BSD(dev)) {
3593                 ret = intel_init_bsd_ring_buffer(dev);
3594                 if (ret)
3595                         goto cleanup_render_ring;
3596         }
3597
3598         if (HAS_BLT(dev)) {
3599                 ret = intel_init_blt_ring_buffer(dev);
3600                 if (ret)
3601                         goto cleanup_bsd_ring;
3602         }
3603
3604         dev_priv->next_seqno = 1;
3605
3606         return 0;
3607
3608 cleanup_bsd_ring:
3609         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3610 cleanup_render_ring:
3611         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3612         return ret;
3613 }
3614
3615 void
3616 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3617 {
3618         drm_i915_private_t *dev_priv = dev->dev_private;
3619         int i;
3620
3621         for (i = 0; i < I915_NUM_RINGS; i++)
3622                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3623 }
3624
3625 int
3626 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3627                        struct drm_file *file_priv)
3628 {
3629         drm_i915_private_t *dev_priv = dev->dev_private;
3630         int ret, i;
3631
3632         if (drm_core_check_feature(dev, DRIVER_MODESET))
3633                 return 0;
3634
3635         if (atomic_read(&dev_priv->mm.wedged)) {
3636                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3637                 atomic_set(&dev_priv->mm.wedged, 0);
3638         }
3639
3640         mutex_lock(&dev->struct_mutex);
3641         dev_priv->mm.suspended = 0;
3642
3643         ret = i915_gem_init_ringbuffer(dev);
3644         if (ret != 0) {
3645                 mutex_unlock(&dev->struct_mutex);
3646                 return ret;
3647         }
3648
3649         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3650         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3651         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3652         for (i = 0; i < I915_NUM_RINGS; i++) {
3653                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3654                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3655         }
3656         mutex_unlock(&dev->struct_mutex);
3657
3658         ret = drm_irq_install(dev);
3659         if (ret)
3660                 goto cleanup_ringbuffer;
3661
3662         return 0;
3663
3664 cleanup_ringbuffer:
3665         mutex_lock(&dev->struct_mutex);
3666         i915_gem_cleanup_ringbuffer(dev);
3667         dev_priv->mm.suspended = 1;
3668         mutex_unlock(&dev->struct_mutex);
3669
3670         return ret;
3671 }
3672
3673 int
3674 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3675                        struct drm_file *file_priv)
3676 {
3677         if (drm_core_check_feature(dev, DRIVER_MODESET))
3678                 return 0;
3679
3680         drm_irq_uninstall(dev);
3681         return i915_gem_idle(dev);
3682 }
3683
3684 void
3685 i915_gem_lastclose(struct drm_device *dev)
3686 {
3687         int ret;
3688
3689         if (drm_core_check_feature(dev, DRIVER_MODESET))
3690                 return;
3691
3692         ret = i915_gem_idle(dev);
3693         if (ret)
3694                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3695 }
3696
3697 static void
3698 init_ring_lists(struct intel_ring_buffer *ring)
3699 {
3700         INIT_LIST_HEAD(&ring->active_list);
3701         INIT_LIST_HEAD(&ring->request_list);
3702         INIT_LIST_HEAD(&ring->gpu_write_list);
3703 }
3704
3705 void
3706 i915_gem_load(struct drm_device *dev)
3707 {
3708         int i;
3709         drm_i915_private_t *dev_priv = dev->dev_private;
3710
3711         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3712         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3713         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3714         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3715         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3716         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3717         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3718         for (i = 0; i < I915_NUM_RINGS; i++)
3719                 init_ring_lists(&dev_priv->ring[i]);
3720         for (i = 0; i < 16; i++)
3721                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3722         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3723                           i915_gem_retire_work_handler);
3724         init_completion(&dev_priv->error_completion);
3725
3726         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3727         if (IS_GEN3(dev)) {
3728                 u32 tmp = I915_READ(MI_ARB_STATE);
3729                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3730                         /* arb state is a masked write, so set bit + bit in mask */
3731                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3732                         I915_WRITE(MI_ARB_STATE, tmp);
3733                 }
3734         }
3735
3736         /* Old X drivers will take 0-2 for front, back, depth buffers */
3737         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3738                 dev_priv->fence_reg_start = 3;
3739
3740         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3741                 dev_priv->num_fence_regs = 16;
3742         else
3743                 dev_priv->num_fence_regs = 8;
3744
3745         /* Initialize fence registers to zero */
3746         switch (INTEL_INFO(dev)->gen) {
3747         case 6:
3748                 for (i = 0; i < 16; i++)
3749                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3750                 break;
3751         case 5:
3752         case 4:
3753                 for (i = 0; i < 16; i++)
3754                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3755                 break;
3756         case 3:
3757                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3758                         for (i = 0; i < 8; i++)
3759                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3760         case 2:
3761                 for (i = 0; i < 8; i++)
3762                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3763                 break;
3764         }
3765         i915_gem_detect_bit_6_swizzle(dev);
3766         init_waitqueue_head(&dev_priv->pending_flip_queue);
3767
3768         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3769         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3770         register_shrinker(&dev_priv->mm.inactive_shrinker);
3771 }
3772
3773 /*
3774  * Create a physically contiguous memory object for this object
3775  * e.g. for cursor + overlay regs
3776  */
3777 static int i915_gem_init_phys_object(struct drm_device *dev,
3778                                      int id, int size, int align)
3779 {
3780         drm_i915_private_t *dev_priv = dev->dev_private;
3781         struct drm_i915_gem_phys_object *phys_obj;
3782         int ret;
3783
3784         if (dev_priv->mm.phys_objs[id - 1] || !size)
3785                 return 0;
3786
3787         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3788         if (!phys_obj)
3789                 return -ENOMEM;
3790
3791         phys_obj->id = id;
3792
3793         phys_obj->handle = drm_pci_alloc(dev, size, align);
3794         if (!phys_obj->handle) {
3795                 ret = -ENOMEM;
3796                 goto kfree_obj;
3797         }
3798 #ifdef CONFIG_X86
3799         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3800 #endif
3801
3802         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3803
3804         return 0;
3805 kfree_obj:
3806         kfree(phys_obj);
3807         return ret;
3808 }
3809
3810 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3811 {
3812         drm_i915_private_t *dev_priv = dev->dev_private;
3813         struct drm_i915_gem_phys_object *phys_obj;
3814
3815         if (!dev_priv->mm.phys_objs[id - 1])
3816                 return;
3817
3818         phys_obj = dev_priv->mm.phys_objs[id - 1];
3819         if (phys_obj->cur_obj) {
3820                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3821         }
3822
3823 #ifdef CONFIG_X86
3824         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3825 #endif
3826         drm_pci_free(dev, phys_obj->handle);
3827         kfree(phys_obj);
3828         dev_priv->mm.phys_objs[id - 1] = NULL;
3829 }
3830
3831 void i915_gem_free_all_phys_object(struct drm_device *dev)
3832 {
3833         int i;
3834
3835         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3836                 i915_gem_free_phys_object(dev, i);
3837 }
3838
3839 void i915_gem_detach_phys_object(struct drm_device *dev,
3840                                  struct drm_i915_gem_object *obj)
3841 {
3842         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3843         char *vaddr;
3844         int i;
3845         int page_count;
3846
3847         if (!obj->phys_obj)
3848                 return;
3849         vaddr = obj->phys_obj->handle->vaddr;
3850
3851         page_count = obj->base.size / PAGE_SIZE;
3852         for (i = 0; i < page_count; i++) {
3853                 struct page *page = read_cache_page_gfp(mapping, i,
3854                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3855                 if (!IS_ERR(page)) {
3856                         char *dst = kmap_atomic(page);
3857                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3858                         kunmap_atomic(dst);
3859
3860                         drm_clflush_pages(&page, 1);
3861
3862                         set_page_dirty(page);
3863                         mark_page_accessed(page);
3864                         page_cache_release(page);
3865                 }
3866         }
3867         intel_gtt_chipset_flush();
3868
3869         obj->phys_obj->cur_obj = NULL;
3870         obj->phys_obj = NULL;
3871 }
3872
3873 int
3874 i915_gem_attach_phys_object(struct drm_device *dev,
3875                             struct drm_i915_gem_object *obj,
3876                             int id,
3877                             int align)
3878 {
3879         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3880         drm_i915_private_t *dev_priv = dev->dev_private;
3881         int ret = 0;
3882         int page_count;
3883         int i;
3884
3885         if (id > I915_MAX_PHYS_OBJECT)
3886                 return -EINVAL;
3887
3888         if (obj->phys_obj) {
3889                 if (obj->phys_obj->id == id)
3890                         return 0;
3891                 i915_gem_detach_phys_object(dev, obj);
3892         }
3893
3894         /* create a new object */
3895         if (!dev_priv->mm.phys_objs[id - 1]) {
3896                 ret = i915_gem_init_phys_object(dev, id,
3897                                                 obj->base.size, align);
3898                 if (ret) {
3899                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3900                                   id, obj->base.size);
3901                         return ret;
3902                 }
3903         }
3904
3905         /* bind to the object */
3906         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3907         obj->phys_obj->cur_obj = obj;
3908
3909         page_count = obj->base.size / PAGE_SIZE;
3910
3911         for (i = 0; i < page_count; i++) {
3912                 struct page *page;
3913                 char *dst, *src;
3914
3915                 page = read_cache_page_gfp(mapping, i,
3916                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
3917                 if (IS_ERR(page))
3918                         return PTR_ERR(page);
3919
3920                 src = kmap_atomic(page);
3921                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3922                 memcpy(dst, src, PAGE_SIZE);
3923                 kunmap_atomic(src);
3924
3925                 mark_page_accessed(page);
3926                 page_cache_release(page);
3927         }
3928
3929         return 0;
3930 }
3931
3932 static int
3933 i915_gem_phys_pwrite(struct drm_device *dev,
3934                      struct drm_i915_gem_object *obj,
3935                      struct drm_i915_gem_pwrite *args,
3936                      struct drm_file *file_priv)
3937 {
3938         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3939         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3940
3941         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3942                 unsigned long unwritten;
3943
3944                 /* The physical object once assigned is fixed for the lifetime
3945                  * of the obj, so we can safely drop the lock and continue
3946                  * to access vaddr.
3947                  */
3948                 mutex_unlock(&dev->struct_mutex);
3949                 unwritten = copy_from_user(vaddr, user_data, args->size);
3950                 mutex_lock(&dev->struct_mutex);
3951                 if (unwritten)
3952                         return -EFAULT;
3953         }
3954
3955         intel_gtt_chipset_flush();
3956         return 0;
3957 }
3958
3959 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3960 {
3961         struct drm_i915_file_private *file_priv = file->driver_priv;
3962
3963         /* Clean up our request list when the client is going away, so that
3964          * later retire_requests won't dereference our soon-to-be-gone
3965          * file_priv.
3966          */
3967         spin_lock(&file_priv->mm.lock);
3968         while (!list_empty(&file_priv->mm.request_list)) {
3969                 struct drm_i915_gem_request *request;
3970
3971                 request = list_first_entry(&file_priv->mm.request_list,
3972                                            struct drm_i915_gem_request,
3973                                            client_list);
3974                 list_del(&request->client_list);
3975                 request->file_priv = NULL;
3976         }
3977         spin_unlock(&file_priv->mm.lock);
3978 }
3979
3980 static int
3981 i915_gpu_is_active(struct drm_device *dev)
3982 {
3983         drm_i915_private_t *dev_priv = dev->dev_private;
3984         int lists_empty;
3985
3986         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3987                       list_empty(&dev_priv->mm.active_list);
3988
3989         return !lists_empty;
3990 }
3991
3992 static int
3993 i915_gem_inactive_shrink(struct shrinker *shrinker,
3994                          int nr_to_scan,
3995                          gfp_t gfp_mask)
3996 {
3997         struct drm_i915_private *dev_priv =
3998                 container_of(shrinker,
3999                              struct drm_i915_private,
4000                              mm.inactive_shrinker);
4001         struct drm_device *dev = dev_priv->dev;
4002         struct drm_i915_gem_object *obj, *next;
4003         int cnt;
4004
4005         if (!mutex_trylock(&dev->struct_mutex))
4006                 return 0;
4007
4008         /* "fast-path" to count number of available objects */
4009         if (nr_to_scan == 0) {
4010                 cnt = 0;
4011                 list_for_each_entry(obj,
4012                                     &dev_priv->mm.inactive_list,
4013                                     mm_list)
4014                         cnt++;
4015                 mutex_unlock(&dev->struct_mutex);
4016                 return cnt / 100 * sysctl_vfs_cache_pressure;
4017         }
4018
4019 rescan:
4020         /* first scan for clean buffers */
4021         i915_gem_retire_requests(dev);
4022
4023         list_for_each_entry_safe(obj, next,
4024                                  &dev_priv->mm.inactive_list,
4025                                  mm_list) {
4026                 if (i915_gem_object_is_purgeable(obj)) {
4027                         if (i915_gem_object_unbind(obj) == 0 &&
4028                             --nr_to_scan == 0)
4029                                 break;
4030                 }
4031         }
4032
4033         /* second pass, evict/count anything still on the inactive list */
4034         cnt = 0;
4035         list_for_each_entry_safe(obj, next,
4036                                  &dev_priv->mm.inactive_list,
4037                                  mm_list) {
4038                 if (nr_to_scan &&
4039                     i915_gem_object_unbind(obj) == 0)
4040                         nr_to_scan--;
4041                 else
4042                         cnt++;
4043         }
4044
4045         if (nr_to_scan && i915_gpu_is_active(dev)) {
4046                 /*
4047                  * We are desperate for pages, so as a last resort, wait
4048                  * for the GPU to finish and discard whatever we can.
4049                  * This has a dramatic impact to reduce the number of
4050                  * OOM-killer events whilst running the GPU aggressively.
4051                  */
4052                 if (i915_gpu_idle(dev) == 0)
4053                         goto rescan;
4054         }
4055         mutex_unlock(&dev->struct_mutex);
4056         return cnt / 100 * sysctl_vfs_cache_pressure;
4057 }