2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static bool cpu_cache_is_coherent(struct drm_device *dev,
56 enum i915_cache_level level)
58 return HAS_LLC(dev) || level != I915_CACHE_NONE;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
63 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
66 return obj->pin_display;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
72 i915_gem_release_mmap(obj);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj->fence_dirty = false;
78 obj->fence_reg = I915_FENCE_REG_NONE;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
85 spin_lock(&dev_priv->mm.object_stat_lock);
86 dev_priv->mm.object_count++;
87 dev_priv->mm.object_memory += size;
88 spin_unlock(&dev_priv->mm.object_stat_lock);
91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count--;
96 dev_priv->mm.object_memory -= size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
101 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret = wait_event_interruptible_timeout(error->reset_queue,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret < 0) {
129 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
138 ret = mutex_lock_interruptible(&dev->struct_mutex);
142 WARN_ON(i915_verify_lists(dev));
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_i915_gem_get_aperture *args = data;
152 struct drm_i915_gem_object *obj;
156 mutex_lock(&dev->struct_mutex);
157 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
158 if (i915_gem_obj_is_pinned(obj))
159 pinned += i915_gem_obj_ggtt_size(obj);
160 mutex_unlock(&dev->struct_mutex);
162 args->aper_size = dev_priv->gtt.base.total;
163 args->aper_available_size = args->aper_size - pinned;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
171 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
172 char *vaddr = obj->phys_handle->vaddr;
174 struct scatterlist *sg;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
184 page = shmem_read_mapping_page(mapping, i);
186 return PTR_ERR(page);
188 src = kmap_atomic(page);
189 memcpy(vaddr, src, PAGE_SIZE);
190 drm_clflush_virt_range(vaddr, PAGE_SIZE);
193 page_cache_release(page);
197 i915_gem_chipset_flush(obj->base.dev);
199 st = kmalloc(sizeof(*st), GFP_KERNEL);
203 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 sg->length = obj->base.size;
212 sg_dma_address(sg) = obj->phys_handle->busaddr;
213 sg_dma_len(sg) = obj->base.size;
216 obj->has_dma_mapping = true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
225 BUG_ON(obj->madv == __I915_MADV_PURGED);
227 ret = i915_gem_object_set_to_cpu_domain(obj, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret != -EIO);
233 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
236 if (obj->madv == I915_MADV_DONTNEED)
240 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
241 char *vaddr = obj->phys_handle->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
248 page = shmem_read_mapping_page(mapping, i);
252 dst = kmap_atomic(page);
253 drm_clflush_virt_range(vaddr, PAGE_SIZE);
254 memcpy(dst, vaddr, PAGE_SIZE);
257 set_page_dirty(page);
258 if (obj->madv == I915_MADV_WILLNEED)
259 mark_page_accessed(page);
260 page_cache_release(page);
266 sg_free_table(obj->pages);
269 obj->has_dma_mapping = false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
275 drm_pci_free(obj->base.dev, obj->phys_handle);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
279 .get_pages = i915_gem_object_get_pages_phys,
280 .put_pages = i915_gem_object_put_pages_phys,
281 .release = i915_gem_object_release_phys,
285 drop_pages(struct drm_i915_gem_object *obj)
287 struct i915_vma *vma, *next;
290 drm_gem_object_reference(&obj->base);
291 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
292 if (i915_vma_unbind(vma))
295 ret = i915_gem_object_put_pages(obj);
296 drm_gem_object_unreference(&obj->base);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
305 drm_dma_handle_t *phys;
308 if (obj->phys_handle) {
309 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
315 if (obj->madv != I915_MADV_WILLNEED)
318 if (obj->base.filp == NULL)
321 ret = drop_pages(obj);
325 /* create a new object */
326 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
330 obj->phys_handle = phys;
331 obj->ops = &i915_gem_phys_ops;
333 return i915_gem_object_get_pages(obj);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
338 struct drm_i915_gem_pwrite *args,
339 struct drm_file *file_priv)
341 struct drm_device *dev = obj->base.dev;
342 void *vaddr = obj->phys_handle->vaddr + args->offset;
343 char __user *user_data = to_user_ptr(args->data_ptr);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret = i915_gem_object_wait_rendering(obj, false);
353 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
354 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
355 unsigned long unwritten;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev->struct_mutex);
362 unwritten = copy_from_user(vaddr, user_data, args->size);
363 mutex_lock(&dev->struct_mutex);
370 drm_clflush_virt_range(vaddr, args->size);
371 i915_gem_chipset_flush(dev);
374 intel_fb_obj_flush(obj, false);
378 void *i915_gem_object_alloc(struct drm_device *dev)
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
387 kmem_cache_free(dev_priv->objects, obj);
391 i915_gem_create(struct drm_file *file,
392 struct drm_device *dev,
396 struct drm_i915_gem_object *obj;
400 size = roundup(size, PAGE_SIZE);
404 /* Allocate the new object */
405 obj = i915_gem_alloc_object(dev, size);
409 ret = drm_gem_handle_create(file, &obj->base, &handle);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj->base);
420 i915_gem_dumb_create(struct drm_file *file,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args)
424 /* have to work out size/pitch and return them */
425 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
426 args->size = args->pitch * args->height;
427 return i915_gem_create(file, dev,
428 args->size, &args->handle);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
436 struct drm_file *file)
438 struct drm_i915_gem_create *args = data;
440 return i915_gem_create(file, dev,
441 args->size, &args->handle);
445 __copy_to_user_swizzled(char __user *cpu_vaddr,
446 const char *gpu_vaddr, int gpu_offset,
449 int ret, cpu_offset = 0;
452 int cacheline_end = ALIGN(gpu_offset + 1, 64);
453 int this_length = min(cacheline_end - gpu_offset, length);
454 int swizzled_gpu_offset = gpu_offset ^ 64;
456 ret = __copy_to_user(cpu_vaddr + cpu_offset,
457 gpu_vaddr + swizzled_gpu_offset,
462 cpu_offset += this_length;
463 gpu_offset += this_length;
464 length -= this_length;
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
472 const char __user *cpu_vaddr,
475 int ret, cpu_offset = 0;
478 int cacheline_end = ALIGN(gpu_offset + 1, 64);
479 int this_length = min(cacheline_end - gpu_offset, length);
480 int swizzled_gpu_offset = gpu_offset ^ 64;
482 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
483 cpu_vaddr + cpu_offset,
488 cpu_offset += this_length;
489 gpu_offset += this_length;
490 length -= this_length;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
511 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
518 ret = i915_gem_object_wait_rendering(obj, true);
523 ret = i915_gem_object_get_pages(obj);
527 i915_gem_object_pin_pages(obj);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
537 char __user *user_data,
538 bool page_do_bit17_swizzling, bool needs_clflush)
543 if (unlikely(page_do_bit17_swizzling))
546 vaddr = kmap_atomic(page);
548 drm_clflush_virt_range(vaddr + shmem_page_offset,
550 ret = __copy_to_user_inatomic(user_data,
551 vaddr + shmem_page_offset,
553 kunmap_atomic(vaddr);
555 return ret ? -EFAULT : 0;
559 shmem_clflush_swizzled_range(char *addr, unsigned long length,
562 if (unlikely(swizzled)) {
563 unsigned long start = (unsigned long) addr;
564 unsigned long end = (unsigned long) addr + length;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start = round_down(start, 128);
571 end = round_up(end, 128);
573 drm_clflush_virt_range((void *)start, end - start);
575 drm_clflush_virt_range(addr, length);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
584 char __user *user_data,
585 bool page_do_bit17_swizzling, bool needs_clflush)
592 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
594 page_do_bit17_swizzling);
596 if (page_do_bit17_swizzling)
597 ret = __copy_to_user_swizzled(user_data,
598 vaddr, shmem_page_offset,
601 ret = __copy_to_user(user_data,
602 vaddr + shmem_page_offset,
606 return ret ? - EFAULT : 0;
610 i915_gem_shmem_pread(struct drm_device *dev,
611 struct drm_i915_gem_object *obj,
612 struct drm_i915_gem_pread *args,
613 struct drm_file *file)
615 char __user *user_data;
618 int shmem_page_offset, page_length, ret = 0;
619 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
621 int needs_clflush = 0;
622 struct sg_page_iter sg_iter;
624 user_data = to_user_ptr(args->data_ptr);
627 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
629 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
633 offset = args->offset;
635 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
636 offset >> PAGE_SHIFT) {
637 struct page *page = sg_page_iter_page(&sg_iter);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset = offset_in_page(offset);
648 page_length = remain;
649 if ((shmem_page_offset + page_length) > PAGE_SIZE)
650 page_length = PAGE_SIZE - shmem_page_offset;
652 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
653 (page_to_phys(page) & (1 << 17)) != 0;
655 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
656 user_data, page_do_bit17_swizzling,
661 mutex_unlock(&dev->struct_mutex);
663 if (likely(!i915.prefault_disable) && !prefaulted) {
664 ret = fault_in_multipages_writeable(user_data, remain);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
674 user_data, page_do_bit17_swizzling,
677 mutex_lock(&dev->struct_mutex);
683 remain -= page_length;
684 user_data += page_length;
685 offset += page_length;
689 i915_gem_object_unpin_pages(obj);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file)
703 struct drm_i915_gem_pread *args = data;
704 struct drm_i915_gem_object *obj;
710 if (!access_ok(VERIFY_WRITE,
711 to_user_ptr(args->data_ptr),
715 ret = i915_mutex_lock_interruptible(dev);
719 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
720 if (&obj->base == NULL) {
725 /* Bounds check source. */
726 if (args->offset > obj->base.size ||
727 args->size > obj->base.size - args->offset) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj->base.filp) {
740 trace_i915_gem_object_pread(obj, args->offset, args->size);
742 ret = i915_gem_shmem_pread(dev, obj, args, file);
745 drm_gem_object_unreference(&obj->base);
747 mutex_unlock(&dev->struct_mutex);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping *mapping,
757 loff_t page_base, int page_offset,
758 char __user *user_data,
761 void __iomem *vaddr_atomic;
763 unsigned long unwritten;
765 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr = (void __force*)vaddr_atomic + page_offset;
768 unwritten = __copy_from_user_inatomic_nocache(vaddr,
770 io_mapping_unmap_atomic(vaddr_atomic);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
780 struct drm_i915_gem_object *obj,
781 struct drm_i915_gem_pwrite *args,
782 struct drm_file *file)
784 struct drm_i915_private *dev_priv = dev->dev_private;
786 loff_t offset, page_base;
787 char __user *user_data;
788 int page_offset, page_length, ret;
790 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
794 ret = i915_gem_object_set_to_gtt_domain(obj, true);
798 ret = i915_gem_object_put_fence(obj);
802 user_data = to_user_ptr(args->data_ptr);
805 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
807 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base = offset & PAGE_MASK;
817 page_offset = offset_in_page(offset);
818 page_length = remain;
819 if ((page_offset + remain) > PAGE_SIZE)
820 page_length = PAGE_SIZE - page_offset;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv->gtt.mappable, page_base,
827 page_offset, user_data, page_length)) {
832 remain -= page_length;
833 user_data += page_length;
834 offset += page_length;
838 intel_fb_obj_flush(obj, false);
840 i915_gem_object_ggtt_unpin(obj);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
851 char __user *user_data,
852 bool page_do_bit17_swizzling,
853 bool needs_clflush_before,
854 bool needs_clflush_after)
859 if (unlikely(page_do_bit17_swizzling))
862 vaddr = kmap_atomic(page);
863 if (needs_clflush_before)
864 drm_clflush_virt_range(vaddr + shmem_page_offset,
866 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
867 user_data, page_length);
868 if (needs_clflush_after)
869 drm_clflush_virt_range(vaddr + shmem_page_offset,
871 kunmap_atomic(vaddr);
873 return ret ? -EFAULT : 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
880 char __user *user_data,
881 bool page_do_bit17_swizzling,
882 bool needs_clflush_before,
883 bool needs_clflush_after)
889 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
890 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
892 page_do_bit17_swizzling);
893 if (page_do_bit17_swizzling)
894 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
898 ret = __copy_from_user(vaddr + shmem_page_offset,
901 if (needs_clflush_after)
902 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
904 page_do_bit17_swizzling);
907 return ret ? -EFAULT : 0;
911 i915_gem_shmem_pwrite(struct drm_device *dev,
912 struct drm_i915_gem_object *obj,
913 struct drm_i915_gem_pwrite *args,
914 struct drm_file *file)
918 char __user *user_data;
919 int shmem_page_offset, page_length, ret = 0;
920 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
921 int hit_slowpath = 0;
922 int needs_clflush_after = 0;
923 int needs_clflush_before = 0;
924 struct sg_page_iter sg_iter;
926 user_data = to_user_ptr(args->data_ptr);
929 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
931 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after = cpu_write_needs_clflush(obj);
937 ret = i915_gem_object_wait_rendering(obj, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
944 needs_clflush_before =
945 !cpu_cache_is_coherent(dev, obj->cache_level);
947 ret = i915_gem_object_get_pages(obj);
951 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
953 i915_gem_object_pin_pages(obj);
955 offset = args->offset;
958 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
959 offset >> PAGE_SHIFT) {
960 struct page *page = sg_page_iter_page(&sg_iter);
961 int partial_cacheline_write;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset = offset_in_page(offset);
973 page_length = remain;
974 if ((shmem_page_offset + page_length) > PAGE_SIZE)
975 page_length = PAGE_SIZE - shmem_page_offset;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write = needs_clflush_before &&
981 ((shmem_page_offset | page_length)
982 & (boot_cpu_data.x86_clflush_size - 1));
984 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
985 (page_to_phys(page) & (1 << 17)) != 0;
987 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
988 user_data, page_do_bit17_swizzling,
989 partial_cacheline_write,
990 needs_clflush_after);
995 mutex_unlock(&dev->struct_mutex);
996 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
997 user_data, page_do_bit17_swizzling,
998 partial_cacheline_write,
999 needs_clflush_after);
1001 mutex_lock(&dev->struct_mutex);
1007 remain -= page_length;
1008 user_data += page_length;
1009 offset += page_length;
1013 i915_gem_object_unpin_pages(obj);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after &&
1022 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1023 if (i915_gem_clflush_object(obj, obj->pin_display))
1024 i915_gem_chipset_flush(dev);
1028 if (needs_clflush_after)
1029 i915_gem_chipset_flush(dev);
1031 intel_fb_obj_flush(obj, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1042 struct drm_file *file)
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct drm_i915_gem_pwrite *args = data;
1046 struct drm_i915_gem_object *obj;
1049 if (args->size == 0)
1052 if (!access_ok(VERIFY_READ,
1053 to_user_ptr(args->data_ptr),
1057 if (likely(!i915.prefault_disable)) {
1058 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1064 intel_runtime_pm_get(dev_priv);
1066 ret = i915_mutex_lock_interruptible(dev);
1070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071 if (&obj->base == NULL) {
1076 /* Bounds check destination. */
1077 if (args->offset > obj->base.size ||
1078 args->size > obj->base.size - args->offset) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj->base.filp) {
1091 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj->tiling_mode == I915_TILING_NONE &&
1101 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102 cpu_write_needs_clflush(obj)) {
1103 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret == -EFAULT || ret == -ENOSPC) {
1110 if (obj->phys_handle)
1111 ret = i915_gem_phys_pwrite(obj, args, file);
1113 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1117 drm_gem_object_unreference(&obj->base);
1119 mutex_unlock(&dev->struct_mutex);
1121 intel_runtime_pm_put(dev_priv);
1127 i915_gem_check_wedge(struct i915_gpu_error *error,
1130 if (i915_reset_in_progress(error)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error->reload_in_reset)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request *req)
1158 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1160 if (req == req->ring->outstanding_lazy_request)
1161 i915_add_request(req->ring);
1166 static void fake_irq(unsigned long data)
1168 wake_up_process((struct task_struct *)data);
1171 static bool missed_irq(struct drm_i915_private *dev_priv,
1172 struct intel_engine_cs *ring)
1174 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1177 static int __i915_spin_request(struct drm_i915_gem_request *req)
1179 unsigned long timeout;
1181 if (i915_gem_request_get_ring(req)->irq_refcount)
1184 timeout = jiffies + 1;
1185 while (!need_resched()) {
1186 if (i915_gem_request_completed(req, true))
1189 if (time_after_eq(jiffies, timeout))
1192 cpu_relax_lowlatency();
1194 if (i915_gem_request_completed(req, false))
1201 * __i915_wait_request - wait until execution of request has finished
1203 * @reset_counter: reset sequence associated with the given request
1204 * @interruptible: do an interruptible wait (normally yes)
1205 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1207 * Note: It is of utmost importance that the passed in seqno and reset_counter
1208 * values have been read by the caller in an smp safe manner. Where read-side
1209 * locks are involved, it is sufficient to read the reset_counter before
1210 * unlocking the lock that protects the seqno. For lockless tricks, the
1211 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1214 * Returns 0 if the request was found within the alloted time. Else returns the
1215 * errno with remaining time filled in timeout argument.
1217 int __i915_wait_request(struct drm_i915_gem_request *req,
1218 unsigned reset_counter,
1221 struct intel_rps_client *rps)
1223 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1224 struct drm_device *dev = ring->dev;
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 const bool irq_test_in_progress =
1227 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1229 unsigned long timeout_expire;
1233 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1235 if (list_empty(&req->list))
1238 if (i915_gem_request_completed(req, true))
1241 timeout_expire = timeout ?
1242 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1244 if (INTEL_INFO(dev_priv)->gen >= 6)
1245 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1247 /* Record current time in case interrupted by signal, or wedged */
1248 trace_i915_gem_request_wait_begin(req);
1249 before = ktime_get_raw_ns();
1251 /* Optimistic spin for the next jiffie before touching IRQs */
1252 ret = __i915_spin_request(req);
1256 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1262 struct timer_list timer;
1264 prepare_to_wait(&ring->irq_queue, &wait,
1265 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1267 /* We need to check whether any gpu reset happened in between
1268 * the caller grabbing the seqno and now ... */
1269 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1270 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1271 * is truely gone. */
1272 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1278 if (i915_gem_request_completed(req, false)) {
1283 if (interruptible && signal_pending(current)) {
1288 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1293 timer.function = NULL;
1294 if (timeout || missed_irq(dev_priv, ring)) {
1295 unsigned long expire;
1297 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1298 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1299 mod_timer(&timer, expire);
1304 if (timer.function) {
1305 del_singleshot_timer_sync(&timer);
1306 destroy_timer_on_stack(&timer);
1309 if (!irq_test_in_progress)
1310 ring->irq_put(ring);
1312 finish_wait(&ring->irq_queue, &wait);
1315 now = ktime_get_raw_ns();
1316 trace_i915_gem_request_wait_end(req);
1319 s64 tres = *timeout - (now - before);
1321 *timeout = tres < 0 ? 0 : tres;
1324 * Apparently ktime isn't accurate enough and occasionally has a
1325 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1326 * things up to make the test happy. We allow up to 1 jiffy.
1328 * This is a regrssion from the timespec->ktime conversion.
1330 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1338 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1340 struct drm_i915_file_private *file_priv = request->file_priv;
1345 spin_lock(&file_priv->mm.lock);
1346 list_del(&request->client_list);
1347 request->file_priv = NULL;
1348 spin_unlock(&file_priv->mm.lock);
1351 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1353 trace_i915_gem_request_retire(request);
1355 /* We know the GPU must have read the request to have
1356 * sent us the seqno + interrupt, so use the position
1357 * of tail of the request to update the last known position
1360 * Note this requires that we are always called in request
1363 request->ringbuf->last_retired_head = request->postfix;
1365 list_del_init(&request->list);
1366 i915_gem_request_remove_from_client(request);
1368 put_pid(request->pid);
1370 i915_gem_request_unreference(request);
1374 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1376 struct intel_engine_cs *engine = req->ring;
1377 struct drm_i915_gem_request *tmp;
1379 lockdep_assert_held(&engine->dev->struct_mutex);
1381 if (list_empty(&req->list))
1385 tmp = list_first_entry(&engine->request_list,
1386 typeof(*tmp), list);
1388 i915_gem_request_retire(tmp);
1389 } while (tmp != req);
1391 WARN_ON(i915_verify_lists(engine->dev));
1395 * Waits for a request to be signaled, and cleans up the
1396 * request and object lists appropriately for that event.
1399 i915_wait_request(struct drm_i915_gem_request *req)
1401 struct drm_device *dev;
1402 struct drm_i915_private *dev_priv;
1406 BUG_ON(req == NULL);
1408 dev = req->ring->dev;
1409 dev_priv = dev->dev_private;
1410 interruptible = dev_priv->mm.interruptible;
1412 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1414 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1418 ret = i915_gem_check_olr(req);
1422 ret = __i915_wait_request(req,
1423 atomic_read(&dev_priv->gpu_error.reset_counter),
1424 interruptible, NULL, NULL);
1428 __i915_gem_request_retire__upto(req);
1433 * Ensures that all rendering to the object has completed and the object is
1434 * safe to unbind from the GTT or access from the CPU.
1437 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1446 if (obj->last_write_req != NULL) {
1447 ret = i915_wait_request(obj->last_write_req);
1451 i = obj->last_write_req->ring->id;
1452 if (obj->last_read_req[i] == obj->last_write_req)
1453 i915_gem_object_retire__read(obj, i);
1455 i915_gem_object_retire__write(obj);
1458 for (i = 0; i < I915_NUM_RINGS; i++) {
1459 if (obj->last_read_req[i] == NULL)
1462 ret = i915_wait_request(obj->last_read_req[i]);
1466 i915_gem_object_retire__read(obj, i);
1468 RQ_BUG_ON(obj->active);
1475 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1476 struct drm_i915_gem_request *req)
1478 int ring = req->ring->id;
1480 if (obj->last_read_req[ring] == req)
1481 i915_gem_object_retire__read(obj, ring);
1482 else if (obj->last_write_req == req)
1483 i915_gem_object_retire__write(obj);
1485 __i915_gem_request_retire__upto(req);
1488 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1489 * as the object state may change during this call.
1491 static __must_check int
1492 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1493 struct intel_rps_client *rps,
1496 struct drm_device *dev = obj->base.dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1499 unsigned reset_counter;
1502 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1503 BUG_ON(!dev_priv->mm.interruptible);
1508 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1512 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1515 struct drm_i915_gem_request *req;
1517 req = obj->last_write_req;
1521 ret = i915_gem_check_olr(req);
1525 requests[n++] = i915_gem_request_reference(req);
1527 for (i = 0; i < I915_NUM_RINGS; i++) {
1528 struct drm_i915_gem_request *req;
1530 req = obj->last_read_req[i];
1534 ret = i915_gem_check_olr(req);
1538 requests[n++] = i915_gem_request_reference(req);
1542 mutex_unlock(&dev->struct_mutex);
1543 for (i = 0; ret == 0 && i < n; i++)
1544 ret = __i915_wait_request(requests[i], reset_counter, true,
1546 mutex_lock(&dev->struct_mutex);
1549 for (i = 0; i < n; i++) {
1551 i915_gem_object_retire_request(obj, requests[i]);
1552 i915_gem_request_unreference(requests[i]);
1558 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1560 struct drm_i915_file_private *fpriv = file->driver_priv;
1565 * Called when user space prepares to use an object with the CPU, either
1566 * through the mmap ioctl's mapping or a GTT mapping.
1569 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1570 struct drm_file *file)
1572 struct drm_i915_gem_set_domain *args = data;
1573 struct drm_i915_gem_object *obj;
1574 uint32_t read_domains = args->read_domains;
1575 uint32_t write_domain = args->write_domain;
1578 /* Only handle setting domains to types used by the CPU. */
1579 if (write_domain & I915_GEM_GPU_DOMAINS)
1582 if (read_domains & I915_GEM_GPU_DOMAINS)
1585 /* Having something in the write domain implies it's in the read
1586 * domain, and only that read domain. Enforce that in the request.
1588 if (write_domain != 0 && read_domains != write_domain)
1591 ret = i915_mutex_lock_interruptible(dev);
1595 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1596 if (&obj->base == NULL) {
1601 /* Try to flush the object off the GPU without holding the lock.
1602 * We will repeat the flush holding the lock in the normal manner
1603 * to catch cases where we are gazumped.
1605 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1606 to_rps_client(file),
1611 if (read_domains & I915_GEM_DOMAIN_GTT)
1612 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1614 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1617 drm_gem_object_unreference(&obj->base);
1619 mutex_unlock(&dev->struct_mutex);
1624 * Called when user space has done writes to this buffer
1627 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1628 struct drm_file *file)
1630 struct drm_i915_gem_sw_finish *args = data;
1631 struct drm_i915_gem_object *obj;
1634 ret = i915_mutex_lock_interruptible(dev);
1638 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1639 if (&obj->base == NULL) {
1644 /* Pinned buffers may be scanout, so flush the cache */
1645 if (obj->pin_display)
1646 i915_gem_object_flush_cpu_write_domain(obj);
1648 drm_gem_object_unreference(&obj->base);
1650 mutex_unlock(&dev->struct_mutex);
1655 * Maps the contents of an object, returning the address it is mapped
1658 * While the mapping holds a reference on the contents of the object, it doesn't
1659 * imply a ref on the object itself.
1663 * DRM driver writers who look a this function as an example for how to do GEM
1664 * mmap support, please don't implement mmap support like here. The modern way
1665 * to implement DRM mmap support is with an mmap offset ioctl (like
1666 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1667 * That way debug tooling like valgrind will understand what's going on, hiding
1668 * the mmap call in a driver private ioctl will break that. The i915 driver only
1669 * does cpu mmaps this way because we didn't know better.
1672 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1673 struct drm_file *file)
1675 struct drm_i915_gem_mmap *args = data;
1676 struct drm_gem_object *obj;
1679 if (args->flags & ~(I915_MMAP_WC))
1682 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1685 obj = drm_gem_object_lookup(dev, file, args->handle);
1689 /* prime objects have no backing filp to GEM mmap
1693 drm_gem_object_unreference_unlocked(obj);
1697 addr = vm_mmap(obj->filp, 0, args->size,
1698 PROT_READ | PROT_WRITE, MAP_SHARED,
1700 if (args->flags & I915_MMAP_WC) {
1701 struct mm_struct *mm = current->mm;
1702 struct vm_area_struct *vma;
1704 down_write(&mm->mmap_sem);
1705 vma = find_vma(mm, addr);
1708 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1711 up_write(&mm->mmap_sem);
1713 drm_gem_object_unreference_unlocked(obj);
1714 if (IS_ERR((void *)addr))
1717 args->addr_ptr = (uint64_t) addr;
1723 * i915_gem_fault - fault a page into the GTT
1724 * vma: VMA in question
1727 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1728 * from userspace. The fault handler takes care of binding the object to
1729 * the GTT (if needed), allocating and programming a fence register (again,
1730 * only if needed based on whether the old reg is still valid or the object
1731 * is tiled) and inserting a new PTE into the faulting process.
1733 * Note that the faulting process may involve evicting existing objects
1734 * from the GTT and/or fence registers to make room. So performance may
1735 * suffer if the GTT working set is large or there are few fence registers
1738 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1740 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1741 struct drm_device *dev = obj->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 struct i915_ggtt_view view = i915_ggtt_view_normal;
1744 pgoff_t page_offset;
1747 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1749 intel_runtime_pm_get(dev_priv);
1751 /* We don't use vmf->pgoff since that has the fake offset */
1752 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1755 ret = i915_mutex_lock_interruptible(dev);
1759 trace_i915_gem_object_fault(obj, page_offset, true, write);
1761 /* Try to flush the object off the GPU first without holding the lock.
1762 * Upon reacquiring the lock, we will perform our sanity checks and then
1763 * repeat the flush holding the lock in the normal manner to catch cases
1764 * where we are gazumped.
1766 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1770 /* Access to snoopable pages through the GTT is incoherent. */
1771 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1776 /* Use a partial view if the object is bigger than the aperture. */
1777 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1778 obj->tiling_mode == I915_TILING_NONE) {
1779 static const unsigned int chunk_size = 256; // 1 MiB
1781 memset(&view, 0, sizeof(view));
1782 view.type = I915_GGTT_VIEW_PARTIAL;
1783 view.params.partial.offset = rounddown(page_offset, chunk_size);
1784 view.params.partial.size =
1787 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1788 view.params.partial.offset);
1791 /* Now pin it into the GTT if needed */
1792 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1796 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1800 ret = i915_gem_object_get_fence(obj);
1804 /* Finally, remap it using the new GTT offset */
1805 pfn = dev_priv->gtt.mappable_base +
1806 i915_gem_obj_ggtt_offset_view(obj, &view);
1809 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1810 /* Overriding existing pages in partial view does not cause
1811 * us any trouble as TLBs are still valid because the fault
1812 * is due to userspace losing part of the mapping or never
1813 * having accessed it before (at this partials' range).
1815 unsigned long base = vma->vm_start +
1816 (view.params.partial.offset << PAGE_SHIFT);
1819 for (i = 0; i < view.params.partial.size; i++) {
1820 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1825 obj->fault_mappable = true;
1827 if (!obj->fault_mappable) {
1828 unsigned long size = min_t(unsigned long,
1829 vma->vm_end - vma->vm_start,
1833 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1834 ret = vm_insert_pfn(vma,
1835 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1841 obj->fault_mappable = true;
1843 ret = vm_insert_pfn(vma,
1844 (unsigned long)vmf->virtual_address,
1848 i915_gem_object_ggtt_unpin_view(obj, &view);
1850 mutex_unlock(&dev->struct_mutex);
1855 * We eat errors when the gpu is terminally wedged to avoid
1856 * userspace unduly crashing (gl has no provisions for mmaps to
1857 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1858 * and so needs to be reported.
1860 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1861 ret = VM_FAULT_SIGBUS;
1866 * EAGAIN means the gpu is hung and we'll wait for the error
1867 * handler to reset everything when re-faulting in
1868 * i915_mutex_lock_interruptible.
1875 * EBUSY is ok: this just means that another thread
1876 * already did the job.
1878 ret = VM_FAULT_NOPAGE;
1885 ret = VM_FAULT_SIGBUS;
1888 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1889 ret = VM_FAULT_SIGBUS;
1893 intel_runtime_pm_put(dev_priv);
1898 * i915_gem_release_mmap - remove physical page mappings
1899 * @obj: obj in question
1901 * Preserve the reservation of the mmapping with the DRM core code, but
1902 * relinquish ownership of the pages back to the system.
1904 * It is vital that we remove the page mapping if we have mapped a tiled
1905 * object through the GTT and then lose the fence register due to
1906 * resource pressure. Similarly if the object has been moved out of the
1907 * aperture, than pages mapped into userspace must be revoked. Removing the
1908 * mapping will then trigger a page fault on the next user access, allowing
1909 * fixup by i915_gem_fault().
1912 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1914 if (!obj->fault_mappable)
1917 drm_vma_node_unmap(&obj->base.vma_node,
1918 obj->base.dev->anon_inode->i_mapping);
1919 obj->fault_mappable = false;
1923 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1925 struct drm_i915_gem_object *obj;
1927 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1928 i915_gem_release_mmap(obj);
1932 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1936 if (INTEL_INFO(dev)->gen >= 4 ||
1937 tiling_mode == I915_TILING_NONE)
1940 /* Previous chips need a power-of-two fence region when tiling */
1941 if (INTEL_INFO(dev)->gen == 3)
1942 gtt_size = 1024*1024;
1944 gtt_size = 512*1024;
1946 while (gtt_size < size)
1953 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1954 * @obj: object to check
1956 * Return the required GTT alignment for an object, taking into account
1957 * potential fence register mapping.
1960 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1961 int tiling_mode, bool fenced)
1964 * Minimum alignment is 4k (GTT page size), but might be greater
1965 * if a fence register is needed for the object.
1967 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1968 tiling_mode == I915_TILING_NONE)
1972 * Previous chips need to be aligned to the size of the smallest
1973 * fence register that can contain the object.
1975 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1978 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1980 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1983 if (drm_vma_node_has_offset(&obj->base.vma_node))
1986 dev_priv->mm.shrinker_no_lock_stealing = true;
1988 ret = drm_gem_create_mmap_offset(&obj->base);
1992 /* Badly fragmented mmap space? The only way we can recover
1993 * space is by destroying unwanted objects. We can't randomly release
1994 * mmap_offsets as userspace expects them to be persistent for the
1995 * lifetime of the objects. The closest we can is to release the
1996 * offsets on purgeable objects by truncating it and marking it purged,
1997 * which prevents userspace from ever using that object again.
1999 i915_gem_shrink(dev_priv,
2000 obj->base.size >> PAGE_SHIFT,
2002 I915_SHRINK_UNBOUND |
2003 I915_SHRINK_PURGEABLE);
2004 ret = drm_gem_create_mmap_offset(&obj->base);
2008 i915_gem_shrink_all(dev_priv);
2009 ret = drm_gem_create_mmap_offset(&obj->base);
2011 dev_priv->mm.shrinker_no_lock_stealing = false;
2016 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2018 drm_gem_free_mmap_offset(&obj->base);
2022 i915_gem_mmap_gtt(struct drm_file *file,
2023 struct drm_device *dev,
2027 struct drm_i915_gem_object *obj;
2030 ret = i915_mutex_lock_interruptible(dev);
2034 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2035 if (&obj->base == NULL) {
2040 if (obj->madv != I915_MADV_WILLNEED) {
2041 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2046 ret = i915_gem_object_create_mmap_offset(obj);
2050 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2053 drm_gem_object_unreference(&obj->base);
2055 mutex_unlock(&dev->struct_mutex);
2060 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2062 * @data: GTT mapping ioctl data
2063 * @file: GEM object info
2065 * Simply returns the fake offset to userspace so it can mmap it.
2066 * The mmap call will end up in drm_gem_mmap(), which will set things
2067 * up so we can get faults in the handler above.
2069 * The fault handler will take care of binding the object into the GTT
2070 * (since it may have been evicted to make room for something), allocating
2071 * a fence register, and mapping the appropriate aperture address into
2075 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2076 struct drm_file *file)
2078 struct drm_i915_gem_mmap_gtt *args = data;
2080 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2083 /* Immediately discard the backing storage */
2085 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2087 i915_gem_object_free_mmap_offset(obj);
2089 if (obj->base.filp == NULL)
2092 /* Our goal here is to return as much of the memory as
2093 * is possible back to the system as we are called from OOM.
2094 * To do this we must instruct the shmfs to drop all of its
2095 * backing pages, *now*.
2097 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2098 obj->madv = __I915_MADV_PURGED;
2101 /* Try to discard unwanted pages */
2103 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2105 struct address_space *mapping;
2107 switch (obj->madv) {
2108 case I915_MADV_DONTNEED:
2109 i915_gem_object_truncate(obj);
2110 case __I915_MADV_PURGED:
2114 if (obj->base.filp == NULL)
2117 mapping = file_inode(obj->base.filp)->i_mapping,
2118 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2122 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2124 struct sg_page_iter sg_iter;
2127 BUG_ON(obj->madv == __I915_MADV_PURGED);
2129 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2131 /* In the event of a disaster, abandon all caches and
2132 * hope for the best.
2134 WARN_ON(ret != -EIO);
2135 i915_gem_clflush_object(obj, true);
2136 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2139 if (i915_gem_object_needs_bit17_swizzle(obj))
2140 i915_gem_object_save_bit_17_swizzle(obj);
2142 if (obj->madv == I915_MADV_DONTNEED)
2145 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2146 struct page *page = sg_page_iter_page(&sg_iter);
2149 set_page_dirty(page);
2151 if (obj->madv == I915_MADV_WILLNEED)
2152 mark_page_accessed(page);
2154 page_cache_release(page);
2158 sg_free_table(obj->pages);
2163 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2165 const struct drm_i915_gem_object_ops *ops = obj->ops;
2167 if (obj->pages == NULL)
2170 if (obj->pages_pin_count)
2173 BUG_ON(i915_gem_obj_bound_any(obj));
2175 /* ->put_pages might need to allocate memory for the bit17 swizzle
2176 * array, hence protect them from being reaped by removing them from gtt
2178 list_del(&obj->global_list);
2180 ops->put_pages(obj);
2183 i915_gem_object_invalidate(obj);
2189 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2191 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2193 struct address_space *mapping;
2194 struct sg_table *st;
2195 struct scatterlist *sg;
2196 struct sg_page_iter sg_iter;
2198 unsigned long last_pfn = 0; /* suppress gcc warning */
2201 /* Assert that the object is not currently in any GPU domain. As it
2202 * wasn't in the GTT, there shouldn't be any way it could have been in
2205 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2206 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2208 st = kmalloc(sizeof(*st), GFP_KERNEL);
2212 page_count = obj->base.size / PAGE_SIZE;
2213 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2218 /* Get the list of pages out of our struct file. They'll be pinned
2219 * at this point until we release them.
2221 * Fail silently without starting the shrinker
2223 mapping = file_inode(obj->base.filp)->i_mapping;
2224 gfp = mapping_gfp_mask(mapping);
2225 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2226 gfp &= ~(__GFP_IO | __GFP_WAIT);
2229 for (i = 0; i < page_count; i++) {
2230 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2232 i915_gem_shrink(dev_priv,
2235 I915_SHRINK_UNBOUND |
2236 I915_SHRINK_PURGEABLE);
2237 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2240 /* We've tried hard to allocate the memory by reaping
2241 * our own buffer, now let the real VM do its job and
2242 * go down in flames if truly OOM.
2244 i915_gem_shrink_all(dev_priv);
2245 page = shmem_read_mapping_page(mapping, i);
2249 #ifdef CONFIG_SWIOTLB
2250 if (swiotlb_nr_tbl()) {
2252 sg_set_page(sg, page, PAGE_SIZE, 0);
2257 if (!i || page_to_pfn(page) != last_pfn + 1) {
2261 sg_set_page(sg, page, PAGE_SIZE, 0);
2263 sg->length += PAGE_SIZE;
2265 last_pfn = page_to_pfn(page);
2267 /* Check that the i965g/gm workaround works. */
2268 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2270 #ifdef CONFIG_SWIOTLB
2271 if (!swiotlb_nr_tbl())
2276 if (i915_gem_object_needs_bit17_swizzle(obj))
2277 i915_gem_object_do_bit_17_swizzle(obj);
2279 if (obj->tiling_mode != I915_TILING_NONE &&
2280 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2281 i915_gem_object_pin_pages(obj);
2287 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2288 page_cache_release(sg_page_iter_page(&sg_iter));
2292 /* shmemfs first checks if there is enough memory to allocate the page
2293 * and reports ENOSPC should there be insufficient, along with the usual
2294 * ENOMEM for a genuine allocation failure.
2296 * We use ENOSPC in our driver to mean that we have run out of aperture
2297 * space and so want to translate the error from shmemfs back to our
2298 * usual understanding of ENOMEM.
2300 if (PTR_ERR(page) == -ENOSPC)
2303 return PTR_ERR(page);
2306 /* Ensure that the associated pages are gathered from the backing storage
2307 * and pinned into our object. i915_gem_object_get_pages() may be called
2308 * multiple times before they are released by a single call to
2309 * i915_gem_object_put_pages() - once the pages are no longer referenced
2310 * either as a result of memory pressure (reaping pages under the shrinker)
2311 * or as the object is itself released.
2314 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2316 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2317 const struct drm_i915_gem_object_ops *ops = obj->ops;
2323 if (obj->madv != I915_MADV_WILLNEED) {
2324 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2328 BUG_ON(obj->pages_pin_count);
2330 ret = ops->get_pages(obj);
2334 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2336 obj->get_page.sg = obj->pages->sgl;
2337 obj->get_page.last = 0;
2342 void i915_vma_move_to_active(struct i915_vma *vma,
2343 struct intel_engine_cs *ring)
2345 struct drm_i915_gem_object *obj = vma->obj;
2347 /* Add a reference if we're newly entering the active list. */
2348 if (obj->active == 0)
2349 drm_gem_object_reference(&obj->base);
2350 obj->active |= intel_ring_flag(ring);
2352 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2353 i915_gem_request_assign(&obj->last_read_req[ring->id],
2354 intel_ring_get_request(ring));
2356 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2360 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2362 RQ_BUG_ON(obj->last_write_req == NULL);
2363 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2365 i915_gem_request_assign(&obj->last_write_req, NULL);
2366 intel_fb_obj_flush(obj, true);
2370 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2372 struct i915_vma *vma;
2374 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2375 RQ_BUG_ON(!(obj->active & (1 << ring)));
2377 list_del_init(&obj->ring_list[ring]);
2378 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2380 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2381 i915_gem_object_retire__write(obj);
2383 obj->active &= ~(1 << ring);
2387 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2388 if (!list_empty(&vma->mm_list))
2389 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2392 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2393 drm_gem_object_unreference(&obj->base);
2397 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_engine_cs *ring;
2403 /* Carefully retire all requests without writing to the rings */
2404 for_each_ring(ring, dev_priv, i) {
2405 ret = intel_ring_idle(ring);
2409 i915_gem_retire_requests(dev);
2411 /* Finally reset hw state */
2412 for_each_ring(ring, dev_priv, i) {
2413 intel_ring_init_seqno(ring, seqno);
2415 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2416 ring->semaphore.sync_seqno[j] = 0;
2422 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2430 /* HWS page needs to be set less than what we
2431 * will inject to ring
2433 ret = i915_gem_init_seqno(dev, seqno - 1);
2437 /* Carefully set the last_seqno value so that wrap
2438 * detection still works
2440 dev_priv->next_seqno = seqno;
2441 dev_priv->last_seqno = seqno - 1;
2442 if (dev_priv->last_seqno == 0)
2443 dev_priv->last_seqno--;
2449 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2453 /* reserve 0 for non-seqno */
2454 if (dev_priv->next_seqno == 0) {
2455 int ret = i915_gem_init_seqno(dev, 0);
2459 dev_priv->next_seqno = 1;
2462 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2467 * NB: This function is not allowed to fail. Doing so would mean the the
2468 * request is not being tracked for completion but the work itself is
2469 * going to happen on the hardware. This would be a Bad Thing(tm).
2471 void __i915_add_request(struct intel_engine_cs *ring,
2472 struct drm_file *file,
2473 struct drm_i915_gem_object *obj,
2476 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2477 struct drm_i915_gem_request *request;
2478 struct intel_ringbuffer *ringbuf;
2482 request = ring->outstanding_lazy_request;
2483 if (WARN_ON(request == NULL))
2486 if (i915.enable_execlists) {
2487 ringbuf = request->ctx->engine[ring->id].ringbuf;
2489 ringbuf = ring->buffer;
2492 * To ensure that this call will not fail, space for its emissions
2493 * should already have been reserved in the ring buffer. Let the ring
2494 * know that it is time to use that space up.
2496 intel_ring_reserved_space_use(ringbuf);
2498 request_start = intel_ring_get_tail(ringbuf);
2500 * Emit any outstanding flushes - execbuf can fail to emit the flush
2501 * after having emitted the batchbuffer command. Hence we need to fix
2502 * things up similar to emitting the lazy request. The difference here
2503 * is that the flush _must_ happen before the next request, no matter
2507 if (i915.enable_execlists)
2508 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2510 ret = intel_ring_flush_all_caches(ring);
2511 /* Not allowed to fail! */
2512 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2515 /* Record the position of the start of the request so that
2516 * should we detect the updated seqno part-way through the
2517 * GPU processing the request, we never over-estimate the
2518 * position of the head.
2520 request->postfix = intel_ring_get_tail(ringbuf);
2522 if (i915.enable_execlists)
2523 ret = ring->emit_request(ringbuf, request);
2525 ret = ring->add_request(ring);
2527 request->tail = intel_ring_get_tail(ringbuf);
2529 /* Not allowed to fail! */
2530 WARN(ret, "emit|add_request failed: %d!\n", ret);
2532 request->head = request_start;
2534 /* Whilst this request exists, batch_obj will be on the
2535 * active_list, and so will hold the active reference. Only when this
2536 * request is retired will the the batch_obj be moved onto the
2537 * inactive_list and lose its active reference. Hence we do not need
2538 * to explicitly hold another reference here.
2540 request->batch_obj = obj;
2542 WARN_ON(!i915.enable_execlists && (request->ctx != ring->last_context));
2544 request->emitted_jiffies = jiffies;
2545 list_add_tail(&request->list, &ring->request_list);
2546 request->file_priv = NULL;
2549 struct drm_i915_file_private *file_priv = file->driver_priv;
2551 spin_lock(&file_priv->mm.lock);
2552 request->file_priv = file_priv;
2553 list_add_tail(&request->client_list,
2554 &file_priv->mm.request_list);
2555 spin_unlock(&file_priv->mm.lock);
2557 request->pid = get_pid(task_pid(current));
2560 trace_i915_gem_request_add(request);
2561 ring->outstanding_lazy_request = NULL;
2563 i915_queue_hangcheck(ring->dev);
2565 queue_delayed_work(dev_priv->wq,
2566 &dev_priv->mm.retire_work,
2567 round_jiffies_up_relative(HZ));
2568 intel_mark_busy(dev_priv->dev);
2570 /* Sanity check that the reserved size was large enough. */
2571 intel_ring_reserved_space_end(ringbuf);
2574 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2575 const struct intel_context *ctx)
2577 unsigned long elapsed;
2579 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2581 if (ctx->hang_stats.banned)
2584 if (ctx->hang_stats.ban_period_seconds &&
2585 elapsed <= ctx->hang_stats.ban_period_seconds) {
2586 if (!i915_gem_context_is_default(ctx)) {
2587 DRM_DEBUG("context hanging too fast, banning!\n");
2589 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2590 if (i915_stop_ring_allow_warn(dev_priv))
2591 DRM_ERROR("gpu hanging too fast, banning!\n");
2599 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2600 struct intel_context *ctx,
2603 struct i915_ctx_hang_stats *hs;
2608 hs = &ctx->hang_stats;
2611 hs->banned = i915_context_is_banned(dev_priv, ctx);
2613 hs->guilty_ts = get_seconds();
2615 hs->batch_pending++;
2619 void i915_gem_request_free(struct kref *req_ref)
2621 struct drm_i915_gem_request *req = container_of(req_ref,
2623 struct intel_context *ctx = req->ctx;
2626 if (i915.enable_execlists) {
2627 struct intel_engine_cs *ring = req->ring;
2629 if (ctx != ring->default_context)
2630 intel_lr_context_unpin(ring, ctx);
2633 i915_gem_context_unreference(ctx);
2636 kmem_cache_free(req->i915->requests, req);
2639 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2640 struct intel_context *ctx,
2641 struct drm_i915_gem_request **req_out)
2643 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2644 struct drm_i915_gem_request *req;
2650 if ((*req_out = ring->outstanding_lazy_request) != NULL)
2653 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2657 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2661 kref_init(&req->ref);
2662 req->i915 = dev_priv;
2665 i915_gem_context_reference(req->ctx);
2667 if (i915.enable_execlists)
2668 ret = intel_logical_ring_alloc_request_extras(req);
2670 ret = intel_ring_alloc_request_extras(req);
2672 i915_gem_context_unreference(req->ctx);
2677 * Reserve space in the ring buffer for all the commands required to
2678 * eventually emit this request. This is to guarantee that the
2679 * i915_add_request() call can't fail. Note that the reserve may need
2680 * to be redone if the request is not actually submitted straight
2681 * away, e.g. because a GPU scheduler has deferred it.
2683 * Note further that this call merely notes the reserve request. A
2684 * subsequent call to *_ring_begin() is required to actually ensure
2685 * that the reservation is available. Without the begin, if the
2686 * request creator immediately submitted the request without adding
2687 * any commands to it then there might not actually be sufficient
2688 * room for the submission commands. Unfortunately, the current
2689 * *_ring_begin() implementations potentially call back here to
2690 * i915_gem_request_alloc(). Thus calling _begin() here would lead to
2691 * infinite recursion! Until that back call path is removed, it is
2692 * necessary to do a manual _begin() outside.
2694 intel_ring_reserved_space_reserve(req->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2696 *req_out = ring->outstanding_lazy_request = req;
2700 kmem_cache_free(dev_priv->requests, req);
2704 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2706 intel_ring_reserved_space_cancel(req->ringbuf);
2708 i915_gem_request_unreference(req);
2711 struct drm_i915_gem_request *
2712 i915_gem_find_active_request(struct intel_engine_cs *ring)
2714 struct drm_i915_gem_request *request;
2716 list_for_each_entry(request, &ring->request_list, list) {
2717 if (i915_gem_request_completed(request, false))
2726 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2727 struct intel_engine_cs *ring)
2729 struct drm_i915_gem_request *request;
2732 request = i915_gem_find_active_request(ring);
2734 if (request == NULL)
2737 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2739 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2741 list_for_each_entry_continue(request, &ring->request_list, list)
2742 i915_set_reset_status(dev_priv, request->ctx, false);
2745 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2746 struct intel_engine_cs *ring)
2748 while (!list_empty(&ring->active_list)) {
2749 struct drm_i915_gem_object *obj;
2751 obj = list_first_entry(&ring->active_list,
2752 struct drm_i915_gem_object,
2753 ring_list[ring->id]);
2755 i915_gem_object_retire__read(obj, ring->id);
2759 * Clear the execlists queue up before freeing the requests, as those
2760 * are the ones that keep the context and ringbuffer backing objects
2763 while (!list_empty(&ring->execlist_queue)) {
2764 struct drm_i915_gem_request *submit_req;
2766 submit_req = list_first_entry(&ring->execlist_queue,
2767 struct drm_i915_gem_request,
2769 list_del(&submit_req->execlist_link);
2771 if (submit_req->ctx != ring->default_context)
2772 intel_lr_context_unpin(ring, submit_req->ctx);
2774 i915_gem_request_unreference(submit_req);
2778 * We must free the requests after all the corresponding objects have
2779 * been moved off active lists. Which is the same order as the normal
2780 * retire_requests function does. This is important if object hold
2781 * implicit references on things like e.g. ppgtt address spaces through
2784 while (!list_empty(&ring->request_list)) {
2785 struct drm_i915_gem_request *request;
2787 request = list_first_entry(&ring->request_list,
2788 struct drm_i915_gem_request,
2791 i915_gem_request_retire(request);
2794 /* This may not have been flushed before the reset, so clean it now */
2795 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2798 void i915_gem_restore_fences(struct drm_device *dev)
2800 struct drm_i915_private *dev_priv = dev->dev_private;
2803 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2804 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2807 * Commit delayed tiling changes if we have an object still
2808 * attached to the fence, otherwise just clear the fence.
2811 i915_gem_object_update_fence(reg->obj, reg,
2812 reg->obj->tiling_mode);
2814 i915_gem_write_fence(dev, i, NULL);
2819 void i915_gem_reset(struct drm_device *dev)
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_engine_cs *ring;
2826 * Before we free the objects from the requests, we need to inspect
2827 * them for finding the guilty party. As the requests only borrow
2828 * their reference to the objects, the inspection must be done first.
2830 for_each_ring(ring, dev_priv, i)
2831 i915_gem_reset_ring_status(dev_priv, ring);
2833 for_each_ring(ring, dev_priv, i)
2834 i915_gem_reset_ring_cleanup(dev_priv, ring);
2836 i915_gem_context_reset(dev);
2838 i915_gem_restore_fences(dev);
2840 WARN_ON(i915_verify_lists(dev));
2844 * This function clears the request list as sequence numbers are passed.
2847 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2849 WARN_ON(i915_verify_lists(ring->dev));
2851 /* Retire requests first as we use it above for the early return.
2852 * If we retire requests last, we may use a later seqno and so clear
2853 * the requests lists without clearing the active list, leading to
2856 while (!list_empty(&ring->request_list)) {
2857 struct drm_i915_gem_request *request;
2859 request = list_first_entry(&ring->request_list,
2860 struct drm_i915_gem_request,
2863 if (!i915_gem_request_completed(request, true))
2866 i915_gem_request_retire(request);
2869 /* Move any buffers on the active list that are no longer referenced
2870 * by the ringbuffer to the flushing/inactive lists as appropriate,
2871 * before we free the context associated with the requests.
2873 while (!list_empty(&ring->active_list)) {
2874 struct drm_i915_gem_object *obj;
2876 obj = list_first_entry(&ring->active_list,
2877 struct drm_i915_gem_object,
2878 ring_list[ring->id]);
2880 if (!list_empty(&obj->last_read_req[ring->id]->list))
2883 i915_gem_object_retire__read(obj, ring->id);
2886 if (unlikely(ring->trace_irq_req &&
2887 i915_gem_request_completed(ring->trace_irq_req, true))) {
2888 ring->irq_put(ring);
2889 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2892 WARN_ON(i915_verify_lists(ring->dev));
2896 i915_gem_retire_requests(struct drm_device *dev)
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_engine_cs *ring;
2903 for_each_ring(ring, dev_priv, i) {
2904 i915_gem_retire_requests_ring(ring);
2905 idle &= list_empty(&ring->request_list);
2906 if (i915.enable_execlists) {
2907 unsigned long flags;
2909 spin_lock_irqsave(&ring->execlist_lock, flags);
2910 idle &= list_empty(&ring->execlist_queue);
2911 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2913 intel_execlists_retire_requests(ring);
2918 mod_delayed_work(dev_priv->wq,
2919 &dev_priv->mm.idle_work,
2920 msecs_to_jiffies(100));
2926 i915_gem_retire_work_handler(struct work_struct *work)
2928 struct drm_i915_private *dev_priv =
2929 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2930 struct drm_device *dev = dev_priv->dev;
2933 /* Come back later if the device is busy... */
2935 if (mutex_trylock(&dev->struct_mutex)) {
2936 idle = i915_gem_retire_requests(dev);
2937 mutex_unlock(&dev->struct_mutex);
2940 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2941 round_jiffies_up_relative(HZ));
2945 i915_gem_idle_work_handler(struct work_struct *work)
2947 struct drm_i915_private *dev_priv =
2948 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2949 struct drm_device *dev = dev_priv->dev;
2950 struct intel_engine_cs *ring;
2953 for_each_ring(ring, dev_priv, i)
2954 if (!list_empty(&ring->request_list))
2957 intel_mark_idle(dev);
2959 if (mutex_trylock(&dev->struct_mutex)) {
2960 struct intel_engine_cs *ring;
2963 for_each_ring(ring, dev_priv, i)
2964 i915_gem_batch_pool_fini(&ring->batch_pool);
2966 mutex_unlock(&dev->struct_mutex);
2971 * Ensures that an object will eventually get non-busy by flushing any required
2972 * write domains, emitting any outstanding lazy request and retiring and
2973 * completed requests.
2976 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2983 for (i = 0; i < I915_NUM_RINGS; i++) {
2984 struct drm_i915_gem_request *req;
2986 req = obj->last_read_req[i];
2990 if (list_empty(&req->list))
2993 ret = i915_gem_check_olr(req);
2997 if (i915_gem_request_completed(req, true)) {
2998 __i915_gem_request_retire__upto(req);
3000 i915_gem_object_retire__read(obj, i);
3008 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3009 * @DRM_IOCTL_ARGS: standard ioctl arguments
3011 * Returns 0 if successful, else an error is returned with the remaining time in
3012 * the timeout parameter.
3013 * -ETIME: object is still busy after timeout
3014 * -ERESTARTSYS: signal interrupted the wait
3015 * -ENONENT: object doesn't exist
3016 * Also possible, but rare:
3017 * -EAGAIN: GPU wedged
3019 * -ENODEV: Internal IRQ fail
3020 * -E?: The add request failed
3022 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3023 * non-zero timeout parameter the wait ioctl will wait for the given number of
3024 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3025 * without holding struct_mutex the object may become re-busied before this
3026 * function completes. A similar but shorter * race condition exists in the busy
3030 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 struct drm_i915_gem_wait *args = data;
3034 struct drm_i915_gem_object *obj;
3035 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3036 unsigned reset_counter;
3040 if (args->flags != 0)
3043 ret = i915_mutex_lock_interruptible(dev);
3047 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3048 if (&obj->base == NULL) {
3049 mutex_unlock(&dev->struct_mutex);
3053 /* Need to make sure the object gets inactive eventually. */
3054 ret = i915_gem_object_flush_active(obj);
3061 /* Do this after OLR check to make sure we make forward progress polling
3062 * on this IOCTL with a timeout == 0 (like busy ioctl)
3064 if (args->timeout_ns == 0) {
3069 drm_gem_object_unreference(&obj->base);
3070 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3072 for (i = 0; i < I915_NUM_RINGS; i++) {
3073 if (obj->last_read_req[i] == NULL)
3076 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3079 mutex_unlock(&dev->struct_mutex);
3081 for (i = 0; i < n; i++) {
3083 ret = __i915_wait_request(req[i], reset_counter, true,
3084 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3086 i915_gem_request_unreference__unlocked(req[i]);
3091 drm_gem_object_unreference(&obj->base);
3092 mutex_unlock(&dev->struct_mutex);
3097 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3098 struct intel_engine_cs *to,
3099 struct drm_i915_gem_request *req)
3101 struct intel_engine_cs *from;
3104 from = i915_gem_request_get_ring(req);
3108 if (i915_gem_request_completed(req, true))
3111 ret = i915_gem_check_olr(req);
3115 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3116 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3117 ret = __i915_wait_request(req,
3118 atomic_read(&i915->gpu_error.reset_counter),
3119 i915->mm.interruptible,
3121 &i915->rps.semaphores);
3125 i915_gem_object_retire_request(obj, req);
3127 int idx = intel_ring_sync_index(from, to);
3128 u32 seqno = i915_gem_request_get_seqno(req);
3130 if (seqno <= from->semaphore.sync_seqno[idx])
3133 trace_i915_gem_ring_sync_to(from, to, req);
3134 ret = to->semaphore.sync_to(to, from, seqno);
3138 /* We use last_read_req because sync_to()
3139 * might have just caused seqno wrap under
3142 from->semaphore.sync_seqno[idx] =
3143 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3150 * i915_gem_object_sync - sync an object to a ring.
3152 * @obj: object which may be in use on another ring.
3153 * @to: ring we wish to use the object on. May be NULL.
3155 * This code is meant to abstract object synchronization with the GPU.
3156 * Calling with NULL implies synchronizing the object with the CPU
3157 * rather than a particular GPU ring. Conceptually we serialise writes
3158 * between engines inside the GPU. We only allow on engine to write
3159 * into a buffer at any time, but multiple readers. To ensure each has
3160 * a coherent view of memory, we must:
3162 * - If there is an outstanding write request to the object, the new
3163 * request must wait for it to complete (either CPU or in hw, requests
3164 * on the same ring will be naturally ordered).
3166 * - If we are a write request (pending_write_domain is set), the new
3167 * request must wait for outstanding read requests to complete.
3169 * Returns 0 if successful, else propagates up the lower layer error.
3172 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3173 struct intel_engine_cs *to)
3175 const bool readonly = obj->base.pending_write_domain == 0;
3176 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3183 return i915_gem_object_wait_rendering(obj, readonly);
3187 if (obj->last_write_req)
3188 req[n++] = obj->last_write_req;
3190 for (i = 0; i < I915_NUM_RINGS; i++)
3191 if (obj->last_read_req[i])
3192 req[n++] = obj->last_read_req[i];
3194 for (i = 0; i < n; i++) {
3195 ret = __i915_gem_object_sync(obj, to, req[i]);
3203 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3205 u32 old_write_domain, old_read_domains;
3207 /* Force a pagefault for domain tracking on next user access */
3208 i915_gem_release_mmap(obj);
3210 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3213 /* Wait for any direct GTT access to complete */
3216 old_read_domains = obj->base.read_domains;
3217 old_write_domain = obj->base.write_domain;
3219 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3220 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3222 trace_i915_gem_object_change_domain(obj,
3227 int i915_vma_unbind(struct i915_vma *vma)
3229 struct drm_i915_gem_object *obj = vma->obj;
3230 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3233 if (list_empty(&vma->vma_link))
3236 if (!drm_mm_node_allocated(&vma->node)) {
3237 i915_gem_vma_destroy(vma);
3244 BUG_ON(obj->pages == NULL);
3246 ret = i915_gem_object_wait_rendering(obj, false);
3249 /* Continue on if we fail due to EIO, the GPU is hung so we
3250 * should be safe and we need to cleanup or else we might
3251 * cause memory corruption through use-after-free.
3254 if (i915_is_ggtt(vma->vm) &&
3255 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3256 i915_gem_object_finish_gtt(obj);
3258 /* release the fence reg _after_ flushing */
3259 ret = i915_gem_object_put_fence(obj);
3264 trace_i915_vma_unbind(vma);
3266 vma->vm->unbind_vma(vma);
3269 list_del_init(&vma->mm_list);
3270 if (i915_is_ggtt(vma->vm)) {
3271 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3272 obj->map_and_fenceable = false;
3273 } else if (vma->ggtt_view.pages) {
3274 sg_free_table(vma->ggtt_view.pages);
3275 kfree(vma->ggtt_view.pages);
3276 vma->ggtt_view.pages = NULL;
3280 drm_mm_remove_node(&vma->node);
3281 i915_gem_vma_destroy(vma);
3283 /* Since the unbound list is global, only move to that list if
3284 * no more VMAs exist. */
3285 if (list_empty(&obj->vma_list)) {
3286 i915_gem_gtt_finish_object(obj);
3287 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3290 /* And finally now the object is completely decoupled from this vma,
3291 * we can drop its hold on the backing storage and allow it to be
3292 * reaped by the shrinker.
3294 i915_gem_object_unpin_pages(obj);
3299 int i915_gpu_idle(struct drm_device *dev)
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct intel_engine_cs *ring;
3305 /* Flush everything onto the inactive list. */
3306 for_each_ring(ring, dev_priv, i) {
3307 if (!i915.enable_execlists) {
3308 struct drm_i915_gem_request *req;
3310 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3314 ret = i915_switch_context(req->ring, ring->default_context);
3316 i915_gem_request_cancel(req);
3320 i915_add_request_no_flush(req->ring);
3323 WARN_ON(ring->outstanding_lazy_request);
3325 ret = intel_ring_idle(ring);
3330 WARN_ON(i915_verify_lists(dev));
3334 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3335 struct drm_i915_gem_object *obj)
3337 struct drm_i915_private *dev_priv = dev->dev_private;
3339 int fence_pitch_shift;
3341 if (INTEL_INFO(dev)->gen >= 6) {
3342 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3343 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3345 fence_reg = FENCE_REG_965_0;
3346 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3349 fence_reg += reg * 8;
3351 /* To w/a incoherency with non-atomic 64-bit register updates,
3352 * we split the 64-bit update into two 32-bit writes. In order
3353 * for a partial fence not to be evaluated between writes, we
3354 * precede the update with write to turn off the fence register,
3355 * and only enable the fence as the last step.
3357 * For extra levels of paranoia, we make sure each step lands
3358 * before applying the next step.
3360 I915_WRITE(fence_reg, 0);
3361 POSTING_READ(fence_reg);
3364 u32 size = i915_gem_obj_ggtt_size(obj);
3367 /* Adjust fence size to match tiled area */
3368 if (obj->tiling_mode != I915_TILING_NONE) {
3369 uint32_t row_size = obj->stride *
3370 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3371 size = (size / row_size) * row_size;
3374 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3376 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3377 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3378 if (obj->tiling_mode == I915_TILING_Y)
3379 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3380 val |= I965_FENCE_REG_VALID;
3382 I915_WRITE(fence_reg + 4, val >> 32);
3383 POSTING_READ(fence_reg + 4);
3385 I915_WRITE(fence_reg + 0, val);
3386 POSTING_READ(fence_reg);
3388 I915_WRITE(fence_reg + 4, 0);
3389 POSTING_READ(fence_reg + 4);
3393 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3394 struct drm_i915_gem_object *obj)
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3400 u32 size = i915_gem_obj_ggtt_size(obj);
3404 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3405 (size & -size) != size ||
3406 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3407 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3408 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3410 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3415 /* Note: pitch better be a power of two tile widths */
3416 pitch_val = obj->stride / tile_width;
3417 pitch_val = ffs(pitch_val) - 1;
3419 val = i915_gem_obj_ggtt_offset(obj);
3420 if (obj->tiling_mode == I915_TILING_Y)
3421 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3422 val |= I915_FENCE_SIZE_BITS(size);
3423 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3424 val |= I830_FENCE_REG_VALID;
3429 reg = FENCE_REG_830_0 + reg * 4;
3431 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3433 I915_WRITE(reg, val);
3437 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3438 struct drm_i915_gem_object *obj)
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3444 u32 size = i915_gem_obj_ggtt_size(obj);
3447 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3448 (size & -size) != size ||
3449 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3450 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3451 i915_gem_obj_ggtt_offset(obj), size);
3453 pitch_val = obj->stride / 128;
3454 pitch_val = ffs(pitch_val) - 1;
3456 val = i915_gem_obj_ggtt_offset(obj);
3457 if (obj->tiling_mode == I915_TILING_Y)
3458 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3459 val |= I830_FENCE_SIZE_BITS(size);
3460 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3461 val |= I830_FENCE_REG_VALID;
3465 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3466 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3469 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3471 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3474 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3475 struct drm_i915_gem_object *obj)
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3479 /* Ensure that all CPU reads are completed before installing a fence
3480 * and all writes before removing the fence.
3482 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3485 WARN(obj && (!obj->stride || !obj->tiling_mode),
3486 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3487 obj->stride, obj->tiling_mode);
3490 i830_write_fence_reg(dev, reg, obj);
3491 else if (IS_GEN3(dev))
3492 i915_write_fence_reg(dev, reg, obj);
3493 else if (INTEL_INFO(dev)->gen >= 4)
3494 i965_write_fence_reg(dev, reg, obj);
3496 /* And similarly be paranoid that no direct access to this region
3497 * is reordered to before the fence is installed.
3499 if (i915_gem_object_needs_mb(obj))
3503 static inline int fence_number(struct drm_i915_private *dev_priv,
3504 struct drm_i915_fence_reg *fence)
3506 return fence - dev_priv->fence_regs;
3509 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3510 struct drm_i915_fence_reg *fence,
3513 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3514 int reg = fence_number(dev_priv, fence);
3516 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3519 obj->fence_reg = reg;
3521 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3523 obj->fence_reg = I915_FENCE_REG_NONE;
3525 list_del_init(&fence->lru_list);
3527 obj->fence_dirty = false;
3531 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3533 if (obj->last_fenced_req) {
3534 int ret = i915_wait_request(obj->last_fenced_req);
3538 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3545 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3547 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3548 struct drm_i915_fence_reg *fence;
3551 ret = i915_gem_object_wait_fence(obj);
3555 if (obj->fence_reg == I915_FENCE_REG_NONE)
3558 fence = &dev_priv->fence_regs[obj->fence_reg];
3560 if (WARN_ON(fence->pin_count))
3563 i915_gem_object_fence_lost(obj);
3564 i915_gem_object_update_fence(obj, fence, false);
3569 static struct drm_i915_fence_reg *
3570 i915_find_fence_reg(struct drm_device *dev)
3572 struct drm_i915_private *dev_priv = dev->dev_private;
3573 struct drm_i915_fence_reg *reg, *avail;
3576 /* First try to find a free reg */
3578 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3579 reg = &dev_priv->fence_regs[i];
3583 if (!reg->pin_count)
3590 /* None available, try to steal one or wait for a user to finish */
3591 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3599 /* Wait for completion of pending flips which consume fences */
3600 if (intel_has_pending_fb_unpin(dev))
3601 return ERR_PTR(-EAGAIN);
3603 return ERR_PTR(-EDEADLK);
3607 * i915_gem_object_get_fence - set up fencing for an object
3608 * @obj: object to map through a fence reg
3610 * When mapping objects through the GTT, userspace wants to be able to write
3611 * to them without having to worry about swizzling if the object is tiled.
3612 * This function walks the fence regs looking for a free one for @obj,
3613 * stealing one if it can't find any.
3615 * It then sets up the reg based on the object's properties: address, pitch
3616 * and tiling format.
3618 * For an untiled surface, this removes any existing fence.
3621 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3623 struct drm_device *dev = obj->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 bool enable = obj->tiling_mode != I915_TILING_NONE;
3626 struct drm_i915_fence_reg *reg;
3629 /* Have we updated the tiling parameters upon the object and so
3630 * will need to serialise the write to the associated fence register?
3632 if (obj->fence_dirty) {
3633 ret = i915_gem_object_wait_fence(obj);
3638 /* Just update our place in the LRU if our fence is getting reused. */
3639 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3640 reg = &dev_priv->fence_regs[obj->fence_reg];
3641 if (!obj->fence_dirty) {
3642 list_move_tail(®->lru_list,
3643 &dev_priv->mm.fence_list);
3646 } else if (enable) {
3647 if (WARN_ON(!obj->map_and_fenceable))
3650 reg = i915_find_fence_reg(dev);
3652 return PTR_ERR(reg);
3655 struct drm_i915_gem_object *old = reg->obj;
3657 ret = i915_gem_object_wait_fence(old);
3661 i915_gem_object_fence_lost(old);
3666 i915_gem_object_update_fence(obj, reg, enable);
3671 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3672 unsigned long cache_level)
3674 struct drm_mm_node *gtt_space = &vma->node;
3675 struct drm_mm_node *other;
3678 * On some machines we have to be careful when putting differing types
3679 * of snoopable memory together to avoid the prefetcher crossing memory
3680 * domains and dying. During vm initialisation, we decide whether or not
3681 * these constraints apply and set the drm_mm.color_adjust
3684 if (vma->vm->mm.color_adjust == NULL)
3687 if (!drm_mm_node_allocated(gtt_space))
3690 if (list_empty(>t_space->node_list))
3693 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3694 if (other->allocated && !other->hole_follows && other->color != cache_level)
3697 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3698 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3705 * Finds free space in the GTT aperture and binds the object or a view of it
3708 static struct i915_vma *
3709 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3710 struct i915_address_space *vm,
3711 const struct i915_ggtt_view *ggtt_view,
3715 struct drm_device *dev = obj->base.dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 u32 size, fence_size, fence_alignment, unfenced_alignment;
3718 unsigned long start =
3719 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3721 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3722 struct i915_vma *vma;
3725 if (i915_is_ggtt(vm)) {
3728 if (WARN_ON(!ggtt_view))
3729 return ERR_PTR(-EINVAL);
3731 view_size = i915_ggtt_view_size(obj, ggtt_view);
3733 fence_size = i915_gem_get_gtt_size(dev,
3736 fence_alignment = i915_gem_get_gtt_alignment(dev,
3740 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3744 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3746 fence_size = i915_gem_get_gtt_size(dev,
3749 fence_alignment = i915_gem_get_gtt_alignment(dev,
3753 unfenced_alignment =
3754 i915_gem_get_gtt_alignment(dev,
3758 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3762 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3764 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3765 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3766 ggtt_view ? ggtt_view->type : 0,
3768 return ERR_PTR(-EINVAL);
3771 /* If binding the object/GGTT view requires more space than the entire
3772 * aperture has, reject it early before evicting everything in a vain
3773 * attempt to find space.
3776 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3777 ggtt_view ? ggtt_view->type : 0,
3779 flags & PIN_MAPPABLE ? "mappable" : "total",
3781 return ERR_PTR(-E2BIG);
3784 ret = i915_gem_object_get_pages(obj);
3786 return ERR_PTR(ret);
3788 i915_gem_object_pin_pages(obj);
3790 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3791 i915_gem_obj_lookup_or_create_vma(obj, vm);
3797 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3801 DRM_MM_SEARCH_DEFAULT,
3802 DRM_MM_CREATE_DEFAULT);
3804 ret = i915_gem_evict_something(dev, vm, size, alignment,
3813 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3815 goto err_remove_node;
3818 ret = i915_gem_gtt_prepare_object(obj);
3820 goto err_remove_node;
3822 trace_i915_vma_bind(vma, flags);
3823 ret = i915_vma_bind(vma, obj->cache_level, flags);
3825 goto err_finish_gtt;
3827 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3828 list_add_tail(&vma->mm_list, &vm->inactive_list);
3833 i915_gem_gtt_finish_object(obj);
3835 drm_mm_remove_node(&vma->node);
3837 i915_gem_vma_destroy(vma);
3840 i915_gem_object_unpin_pages(obj);
3845 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3848 /* If we don't have a page list set up, then we're not pinned
3849 * to GPU, and we can ignore the cache flush because it'll happen
3850 * again at bind time.
3852 if (obj->pages == NULL)
3856 * Stolen memory is always coherent with the GPU as it is explicitly
3857 * marked as wc by the system, or the system is cache-coherent.
3859 if (obj->stolen || obj->phys_handle)
3862 /* If the GPU is snooping the contents of the CPU cache,
3863 * we do not need to manually clear the CPU cache lines. However,
3864 * the caches are only snooped when the render cache is
3865 * flushed/invalidated. As we always have to emit invalidations
3866 * and flushes when moving into and out of the RENDER domain, correct
3867 * snooping behaviour occurs naturally as the result of our domain
3870 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3871 obj->cache_dirty = true;
3875 trace_i915_gem_object_clflush(obj);
3876 drm_clflush_sg(obj->pages);
3877 obj->cache_dirty = false;
3882 /** Flushes the GTT write domain for the object if it's dirty. */
3884 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3886 uint32_t old_write_domain;
3888 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3891 /* No actual flushing is required for the GTT write domain. Writes
3892 * to it immediately go to main memory as far as we know, so there's
3893 * no chipset flush. It also doesn't land in render cache.
3895 * However, we do have to enforce the order so that all writes through
3896 * the GTT land before any writes to the device, such as updates to
3901 old_write_domain = obj->base.write_domain;
3902 obj->base.write_domain = 0;
3904 intel_fb_obj_flush(obj, false);
3906 trace_i915_gem_object_change_domain(obj,
3907 obj->base.read_domains,
3911 /** Flushes the CPU write domain for the object if it's dirty. */
3913 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3915 uint32_t old_write_domain;
3917 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3920 if (i915_gem_clflush_object(obj, obj->pin_display))
3921 i915_gem_chipset_flush(obj->base.dev);
3923 old_write_domain = obj->base.write_domain;
3924 obj->base.write_domain = 0;
3926 intel_fb_obj_flush(obj, false);
3928 trace_i915_gem_object_change_domain(obj,
3929 obj->base.read_domains,
3934 * Moves a single object to the GTT read, and possibly write domain.
3936 * This function returns when the move is complete, including waiting on
3940 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3942 uint32_t old_write_domain, old_read_domains;
3943 struct i915_vma *vma;
3946 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3949 ret = i915_gem_object_wait_rendering(obj, !write);
3953 /* Flush and acquire obj->pages so that we are coherent through
3954 * direct access in memory with previous cached writes through
3955 * shmemfs and that our cache domain tracking remains valid.
3956 * For example, if the obj->filp was moved to swap without us
3957 * being notified and releasing the pages, we would mistakenly
3958 * continue to assume that the obj remained out of the CPU cached
3961 ret = i915_gem_object_get_pages(obj);
3965 i915_gem_object_flush_cpu_write_domain(obj);
3967 /* Serialise direct access to this object with the barriers for
3968 * coherent writes from the GPU, by effectively invalidating the
3969 * GTT domain upon first access.
3971 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3974 old_write_domain = obj->base.write_domain;
3975 old_read_domains = obj->base.read_domains;
3977 /* It should now be out of any other write domains, and we can update
3978 * the domain values for our changes.
3980 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3981 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3983 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3984 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3989 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
3991 trace_i915_gem_object_change_domain(obj,
3995 /* And bump the LRU for this access */
3996 vma = i915_gem_obj_to_ggtt(obj);
3997 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3998 list_move_tail(&vma->mm_list,
3999 &to_i915(obj->base.dev)->gtt.base.inactive_list);
4004 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
4005 enum i915_cache_level cache_level)
4007 struct drm_device *dev = obj->base.dev;
4008 struct i915_vma *vma, *next;
4011 if (obj->cache_level == cache_level)
4014 if (i915_gem_obj_is_pinned(obj)) {
4015 DRM_DEBUG("can not change the cache level of pinned objects\n");
4019 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4020 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
4021 ret = i915_vma_unbind(vma);
4027 if (i915_gem_obj_bound_any(obj)) {
4028 ret = i915_gem_object_wait_rendering(obj, false);
4032 i915_gem_object_finish_gtt(obj);
4034 /* Before SandyBridge, you could not use tiling or fence
4035 * registers with snooped memory, so relinquish any fences
4036 * currently pointing to our region in the aperture.
4038 if (INTEL_INFO(dev)->gen < 6) {
4039 ret = i915_gem_object_put_fence(obj);
4044 list_for_each_entry(vma, &obj->vma_list, vma_link)
4045 if (drm_mm_node_allocated(&vma->node)) {
4046 ret = i915_vma_bind(vma, cache_level,
4053 list_for_each_entry(vma, &obj->vma_list, vma_link)
4054 vma->node.color = cache_level;
4055 obj->cache_level = cache_level;
4057 if (obj->cache_dirty &&
4058 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
4059 cpu_write_needs_clflush(obj)) {
4060 if (i915_gem_clflush_object(obj, true))
4061 i915_gem_chipset_flush(obj->base.dev);
4067 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4068 struct drm_file *file)
4070 struct drm_i915_gem_caching *args = data;
4071 struct drm_i915_gem_object *obj;
4073 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4074 if (&obj->base == NULL)
4077 switch (obj->cache_level) {
4078 case I915_CACHE_LLC:
4079 case I915_CACHE_L3_LLC:
4080 args->caching = I915_CACHING_CACHED;
4084 args->caching = I915_CACHING_DISPLAY;
4088 args->caching = I915_CACHING_NONE;
4092 drm_gem_object_unreference_unlocked(&obj->base);
4096 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4097 struct drm_file *file)
4099 struct drm_i915_gem_caching *args = data;
4100 struct drm_i915_gem_object *obj;
4101 enum i915_cache_level level;
4104 switch (args->caching) {
4105 case I915_CACHING_NONE:
4106 level = I915_CACHE_NONE;
4108 case I915_CACHING_CACHED:
4109 level = I915_CACHE_LLC;
4111 case I915_CACHING_DISPLAY:
4112 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4118 ret = i915_mutex_lock_interruptible(dev);
4122 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4123 if (&obj->base == NULL) {
4128 ret = i915_gem_object_set_cache_level(obj, level);
4130 drm_gem_object_unreference(&obj->base);
4132 mutex_unlock(&dev->struct_mutex);
4137 * Prepare buffer for display plane (scanout, cursors, etc).
4138 * Can be called from an uninterruptible phase (modesetting) and allows
4139 * any flushes to be pipelined (for pageflips).
4142 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4144 struct intel_engine_cs *pipelined,
4145 const struct i915_ggtt_view *view)
4147 u32 old_read_domains, old_write_domain;
4150 ret = i915_gem_object_sync(obj, pipelined);
4154 /* Mark the pin_display early so that we account for the
4155 * display coherency whilst setting up the cache domains.
4159 /* The display engine is not coherent with the LLC cache on gen6. As
4160 * a result, we make sure that the pinning that is about to occur is
4161 * done with uncached PTEs. This is lowest common denominator for all
4164 * However for gen6+, we could do better by using the GFDT bit instead
4165 * of uncaching, which would allow us to flush all the LLC-cached data
4166 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4168 ret = i915_gem_object_set_cache_level(obj,
4169 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4171 goto err_unpin_display;
4173 /* As the user may map the buffer once pinned in the display plane
4174 * (e.g. libkms for the bootup splash), we have to ensure that we
4175 * always use map_and_fenceable for all scanout buffers.
4177 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4178 view->type == I915_GGTT_VIEW_NORMAL ?
4181 goto err_unpin_display;
4183 i915_gem_object_flush_cpu_write_domain(obj);
4185 old_write_domain = obj->base.write_domain;
4186 old_read_domains = obj->base.read_domains;
4188 /* It should now be out of any other write domains, and we can update
4189 * the domain values for our changes.
4191 obj->base.write_domain = 0;
4192 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4194 trace_i915_gem_object_change_domain(obj,
4206 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4207 const struct i915_ggtt_view *view)
4209 if (WARN_ON(obj->pin_display == 0))
4212 i915_gem_object_ggtt_unpin_view(obj, view);
4218 * Moves a single object to the CPU read, and possibly write domain.
4220 * This function returns when the move is complete, including waiting on
4224 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4226 uint32_t old_write_domain, old_read_domains;
4229 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4232 ret = i915_gem_object_wait_rendering(obj, !write);
4236 i915_gem_object_flush_gtt_write_domain(obj);
4238 old_write_domain = obj->base.write_domain;
4239 old_read_domains = obj->base.read_domains;
4241 /* Flush the CPU cache if it's still invalid. */
4242 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4243 i915_gem_clflush_object(obj, false);
4245 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4248 /* It should now be out of any other write domains, and we can update
4249 * the domain values for our changes.
4251 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4253 /* If we're writing through the CPU, then the GPU read domains will
4254 * need to be invalidated at next use.
4257 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4258 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4262 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
4264 trace_i915_gem_object_change_domain(obj,
4271 /* Throttle our rendering by waiting until the ring has completed our requests
4272 * emitted over 20 msec ago.
4274 * Note that if we were to use the current jiffies each time around the loop,
4275 * we wouldn't escape the function with any frames outstanding if the time to
4276 * render a frame was over 20ms.
4278 * This should get us reasonable parallelism between CPU and GPU but also
4279 * relatively low latency when blocking on a particular request to finish.
4282 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 struct drm_i915_file_private *file_priv = file->driver_priv;
4286 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4287 struct drm_i915_gem_request *request, *target = NULL;
4288 unsigned reset_counter;
4291 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4295 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4299 spin_lock(&file_priv->mm.lock);
4300 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4301 if (time_after_eq(request->emitted_jiffies, recent_enough))
4306 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4308 i915_gem_request_reference(target);
4309 spin_unlock(&file_priv->mm.lock);
4314 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4316 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4318 i915_gem_request_unreference__unlocked(target);
4324 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4326 struct drm_i915_gem_object *obj = vma->obj;
4329 vma->node.start & (alignment - 1))
4332 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4335 if (flags & PIN_OFFSET_BIAS &&
4336 vma->node.start < (flags & PIN_OFFSET_MASK))
4343 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4344 struct i915_address_space *vm,
4345 const struct i915_ggtt_view *ggtt_view,
4349 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4350 struct i915_vma *vma;
4354 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4357 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4360 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4363 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4366 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4367 i915_gem_obj_to_vma(obj, vm);
4370 return PTR_ERR(vma);
4373 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4376 if (i915_vma_misplaced(vma, alignment, flags)) {
4377 unsigned long offset;
4378 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4379 i915_gem_obj_offset(obj, vm);
4380 WARN(vma->pin_count,
4381 "bo is already pinned in %s with incorrect alignment:"
4382 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4383 " obj->map_and_fenceable=%d\n",
4384 ggtt_view ? "ggtt" : "ppgtt",
4387 !!(flags & PIN_MAPPABLE),
4388 obj->map_and_fenceable);
4389 ret = i915_vma_unbind(vma);
4397 bound = vma ? vma->bound : 0;
4398 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4399 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4402 return PTR_ERR(vma);
4404 ret = i915_vma_bind(vma, obj->cache_level, flags);
4409 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4410 (bound ^ vma->bound) & GLOBAL_BIND) {
4411 bool mappable, fenceable;
4412 u32 fence_size, fence_alignment;
4414 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4417 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4422 fenceable = (vma->node.size == fence_size &&
4423 (vma->node.start & (fence_alignment - 1)) == 0);
4425 mappable = (vma->node.start + fence_size <=
4426 dev_priv->gtt.mappable_end);
4428 obj->map_and_fenceable = mappable && fenceable;
4430 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4438 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4439 struct i915_address_space *vm,
4443 return i915_gem_object_do_pin(obj, vm,
4444 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4449 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4450 const struct i915_ggtt_view *view,
4454 if (WARN_ONCE(!view, "no view specified"))
4457 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4458 alignment, flags | PIN_GLOBAL);
4462 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4463 const struct i915_ggtt_view *view)
4465 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4468 WARN_ON(vma->pin_count == 0);
4469 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4475 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4477 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4478 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4479 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4481 WARN_ON(!ggtt_vma ||
4482 dev_priv->fence_regs[obj->fence_reg].pin_count >
4483 ggtt_vma->pin_count);
4484 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4491 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4493 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4494 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4495 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4496 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4501 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4502 struct drm_file *file)
4504 struct drm_i915_gem_busy *args = data;
4505 struct drm_i915_gem_object *obj;
4508 ret = i915_mutex_lock_interruptible(dev);
4512 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4513 if (&obj->base == NULL) {
4518 /* Count all active objects as busy, even if they are currently not used
4519 * by the gpu. Users of this interface expect objects to eventually
4520 * become non-busy without any further actions, therefore emit any
4521 * necessary flushes here.
4523 ret = i915_gem_object_flush_active(obj);
4527 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4528 args->busy = obj->active << 16;
4529 if (obj->last_write_req)
4530 args->busy |= obj->last_write_req->ring->id;
4533 drm_gem_object_unreference(&obj->base);
4535 mutex_unlock(&dev->struct_mutex);
4540 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4541 struct drm_file *file_priv)
4543 return i915_gem_ring_throttle(dev, file_priv);
4547 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4548 struct drm_file *file_priv)
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 struct drm_i915_gem_madvise *args = data;
4552 struct drm_i915_gem_object *obj;
4555 switch (args->madv) {
4556 case I915_MADV_DONTNEED:
4557 case I915_MADV_WILLNEED:
4563 ret = i915_mutex_lock_interruptible(dev);
4567 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4568 if (&obj->base == NULL) {
4573 if (i915_gem_obj_is_pinned(obj)) {
4579 obj->tiling_mode != I915_TILING_NONE &&
4580 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4581 if (obj->madv == I915_MADV_WILLNEED)
4582 i915_gem_object_unpin_pages(obj);
4583 if (args->madv == I915_MADV_WILLNEED)
4584 i915_gem_object_pin_pages(obj);
4587 if (obj->madv != __I915_MADV_PURGED)
4588 obj->madv = args->madv;
4590 /* if the object is no longer attached, discard its backing storage */
4591 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4592 i915_gem_object_truncate(obj);
4594 args->retained = obj->madv != __I915_MADV_PURGED;
4597 drm_gem_object_unreference(&obj->base);
4599 mutex_unlock(&dev->struct_mutex);
4603 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4604 const struct drm_i915_gem_object_ops *ops)
4608 INIT_LIST_HEAD(&obj->global_list);
4609 for (i = 0; i < I915_NUM_RINGS; i++)
4610 INIT_LIST_HEAD(&obj->ring_list[i]);
4611 INIT_LIST_HEAD(&obj->obj_exec_link);
4612 INIT_LIST_HEAD(&obj->vma_list);
4613 INIT_LIST_HEAD(&obj->batch_pool_link);
4617 obj->fence_reg = I915_FENCE_REG_NONE;
4618 obj->madv = I915_MADV_WILLNEED;
4620 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4623 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4624 .get_pages = i915_gem_object_get_pages_gtt,
4625 .put_pages = i915_gem_object_put_pages_gtt,
4628 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4631 struct drm_i915_gem_object *obj;
4632 struct address_space *mapping;
4635 obj = i915_gem_object_alloc(dev);
4639 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4640 i915_gem_object_free(obj);
4644 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4645 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4646 /* 965gm cannot relocate objects above 4GiB. */
4647 mask &= ~__GFP_HIGHMEM;
4648 mask |= __GFP_DMA32;
4651 mapping = file_inode(obj->base.filp)->i_mapping;
4652 mapping_set_gfp_mask(mapping, mask);
4654 i915_gem_object_init(obj, &i915_gem_object_ops);
4656 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4657 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4660 /* On some devices, we can have the GPU use the LLC (the CPU
4661 * cache) for about a 10% performance improvement
4662 * compared to uncached. Graphics requests other than
4663 * display scanout are coherent with the CPU in
4664 * accessing this cache. This means in this mode we
4665 * don't need to clflush on the CPU side, and on the
4666 * GPU side we only need to flush internal caches to
4667 * get data visible to the CPU.
4669 * However, we maintain the display planes as UC, and so
4670 * need to rebind when first used as such.
4672 obj->cache_level = I915_CACHE_LLC;
4674 obj->cache_level = I915_CACHE_NONE;
4676 trace_i915_gem_object_create(obj);
4681 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4683 /* If we are the last user of the backing storage (be it shmemfs
4684 * pages or stolen etc), we know that the pages are going to be
4685 * immediately released. In this case, we can then skip copying
4686 * back the contents from the GPU.
4689 if (obj->madv != I915_MADV_WILLNEED)
4692 if (obj->base.filp == NULL)
4695 /* At first glance, this looks racy, but then again so would be
4696 * userspace racing mmap against close. However, the first external
4697 * reference to the filp can only be obtained through the
4698 * i915_gem_mmap_ioctl() which safeguards us against the user
4699 * acquiring such a reference whilst we are in the middle of
4700 * freeing the object.
4702 return atomic_long_read(&obj->base.filp->f_count) == 1;
4705 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4707 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4708 struct drm_device *dev = obj->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 struct i915_vma *vma, *next;
4712 intel_runtime_pm_get(dev_priv);
4714 trace_i915_gem_object_destroy(obj);
4716 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4720 ret = i915_vma_unbind(vma);
4721 if (WARN_ON(ret == -ERESTARTSYS)) {
4722 bool was_interruptible;
4724 was_interruptible = dev_priv->mm.interruptible;
4725 dev_priv->mm.interruptible = false;
4727 WARN_ON(i915_vma_unbind(vma));
4729 dev_priv->mm.interruptible = was_interruptible;
4733 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4734 * before progressing. */
4736 i915_gem_object_unpin_pages(obj);
4738 WARN_ON(obj->frontbuffer_bits);
4740 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4741 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4742 obj->tiling_mode != I915_TILING_NONE)
4743 i915_gem_object_unpin_pages(obj);
4745 if (WARN_ON(obj->pages_pin_count))
4746 obj->pages_pin_count = 0;
4747 if (discard_backing_storage(obj))
4748 obj->madv = I915_MADV_DONTNEED;
4749 i915_gem_object_put_pages(obj);
4750 i915_gem_object_free_mmap_offset(obj);
4754 if (obj->base.import_attach)
4755 drm_prime_gem_destroy(&obj->base, NULL);
4757 if (obj->ops->release)
4758 obj->ops->release(obj);
4760 drm_gem_object_release(&obj->base);
4761 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4764 i915_gem_object_free(obj);
4766 intel_runtime_pm_put(dev_priv);
4769 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4770 struct i915_address_space *vm)
4772 struct i915_vma *vma;
4773 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4774 if (i915_is_ggtt(vma->vm) &&
4775 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4783 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4784 const struct i915_ggtt_view *view)
4786 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4787 struct i915_vma *vma;
4789 if (WARN_ONCE(!view, "no view specified"))
4790 return ERR_PTR(-EINVAL);
4792 list_for_each_entry(vma, &obj->vma_list, vma_link)
4793 if (vma->vm == ggtt &&
4794 i915_ggtt_view_equal(&vma->ggtt_view, view))
4799 void i915_gem_vma_destroy(struct i915_vma *vma)
4801 struct i915_address_space *vm = NULL;
4802 WARN_ON(vma->node.allocated);
4804 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4805 if (!list_empty(&vma->exec_list))
4810 if (!i915_is_ggtt(vm))
4811 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4813 list_del(&vma->vma_link);
4815 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4819 i915_gem_stop_ringbuffers(struct drm_device *dev)
4821 struct drm_i915_private *dev_priv = dev->dev_private;
4822 struct intel_engine_cs *ring;
4825 for_each_ring(ring, dev_priv, i)
4826 dev_priv->gt.stop_ring(ring);
4830 i915_gem_suspend(struct drm_device *dev)
4832 struct drm_i915_private *dev_priv = dev->dev_private;
4835 mutex_lock(&dev->struct_mutex);
4836 ret = i915_gpu_idle(dev);
4840 i915_gem_retire_requests(dev);
4842 i915_gem_stop_ringbuffers(dev);
4843 mutex_unlock(&dev->struct_mutex);
4845 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4846 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4847 flush_delayed_work(&dev_priv->mm.idle_work);
4849 /* Assert that we sucessfully flushed all the work and
4850 * reset the GPU back to its idle, low power state.
4852 WARN_ON(dev_priv->mm.busy);
4857 mutex_unlock(&dev->struct_mutex);
4861 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4863 struct drm_device *dev = ring->dev;
4864 struct drm_i915_private *dev_priv = dev->dev_private;
4865 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4866 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4869 if (!HAS_L3_DPF(dev) || !remap_info)
4872 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4877 * Note: We do not worry about the concurrent register cacheline hang
4878 * here because no other code should access these registers other than
4879 * at initialization time.
4881 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4882 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4883 intel_ring_emit(ring, reg_base + i);
4884 intel_ring_emit(ring, remap_info[i/4]);
4887 intel_ring_advance(ring);
4892 void i915_gem_init_swizzling(struct drm_device *dev)
4894 struct drm_i915_private *dev_priv = dev->dev_private;
4896 if (INTEL_INFO(dev)->gen < 5 ||
4897 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4900 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4901 DISP_TILE_SURFACE_SWIZZLING);
4906 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4908 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4909 else if (IS_GEN7(dev))
4910 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4911 else if (IS_GEN8(dev))
4912 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4918 intel_enable_blt(struct drm_device *dev)
4923 /* The blitter was dysfunctional on early prototypes */
4924 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4925 DRM_INFO("BLT not supported on this pre-production hardware;"
4926 " graphics performance will be degraded.\n");
4933 static void init_unused_ring(struct drm_device *dev, u32 base)
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4937 I915_WRITE(RING_CTL(base), 0);
4938 I915_WRITE(RING_HEAD(base), 0);
4939 I915_WRITE(RING_TAIL(base), 0);
4940 I915_WRITE(RING_START(base), 0);
4943 static void init_unused_rings(struct drm_device *dev)
4946 init_unused_ring(dev, PRB1_BASE);
4947 init_unused_ring(dev, SRB0_BASE);
4948 init_unused_ring(dev, SRB1_BASE);
4949 init_unused_ring(dev, SRB2_BASE);
4950 init_unused_ring(dev, SRB3_BASE);
4951 } else if (IS_GEN2(dev)) {
4952 init_unused_ring(dev, SRB0_BASE);
4953 init_unused_ring(dev, SRB1_BASE);
4954 } else if (IS_GEN3(dev)) {
4955 init_unused_ring(dev, PRB1_BASE);
4956 init_unused_ring(dev, PRB2_BASE);
4960 int i915_gem_init_rings(struct drm_device *dev)
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4965 ret = intel_init_render_ring_buffer(dev);
4970 ret = intel_init_bsd_ring_buffer(dev);
4972 goto cleanup_render_ring;
4975 if (intel_enable_blt(dev)) {
4976 ret = intel_init_blt_ring_buffer(dev);
4978 goto cleanup_bsd_ring;
4981 if (HAS_VEBOX(dev)) {
4982 ret = intel_init_vebox_ring_buffer(dev);
4984 goto cleanup_blt_ring;
4987 if (HAS_BSD2(dev)) {
4988 ret = intel_init_bsd2_ring_buffer(dev);
4990 goto cleanup_vebox_ring;
4993 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4995 goto cleanup_bsd2_ring;
5000 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
5002 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
5004 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
5006 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
5007 cleanup_render_ring:
5008 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
5014 i915_gem_init_hw(struct drm_device *dev)
5016 struct drm_i915_private *dev_priv = dev->dev_private;
5017 struct intel_engine_cs *ring;
5020 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
5023 /* Double layer security blanket, see i915_gem_init() */
5024 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5026 if (dev_priv->ellc_size)
5027 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
5029 if (IS_HASWELL(dev))
5030 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
5031 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
5033 if (HAS_PCH_NOP(dev)) {
5034 if (IS_IVYBRIDGE(dev)) {
5035 u32 temp = I915_READ(GEN7_MSG_CTL);
5036 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
5037 I915_WRITE(GEN7_MSG_CTL, temp);
5038 } else if (INTEL_INFO(dev)->gen >= 7) {
5039 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
5040 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
5041 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
5045 i915_gem_init_swizzling(dev);
5048 * At least 830 can leave some of the unused rings
5049 * "active" (ie. head != tail) after resume which
5050 * will prevent c3 entry. Makes sure all unused rings
5053 init_unused_rings(dev);
5055 BUG_ON(!dev_priv->ring[RCS].default_context);
5057 ret = i915_ppgtt_init_hw(dev);
5059 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
5063 /* Need to do basic initialisation of all rings first: */
5064 for_each_ring(ring, dev_priv, i) {
5065 ret = ring->init_hw(ring);
5070 /* Now it is safe to go back round and do everything else: */
5071 for_each_ring(ring, dev_priv, i) {
5072 WARN_ON(!ring->default_context);
5074 if (ring->id == RCS) {
5075 for (j = 0; j < NUM_L3_SLICES(dev); j++)
5076 i915_gem_l3_remap(ring, j);
5079 ret = i915_ppgtt_init_ring(ring);
5080 if (ret && ret != -EIO) {
5081 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
5082 i915_gem_cleanup_ringbuffer(dev);
5086 ret = i915_gem_context_enable(ring);
5087 if (ret && ret != -EIO) {
5088 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
5089 i915_gem_cleanup_ringbuffer(dev);
5095 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5099 int i915_gem_init(struct drm_device *dev)
5101 struct drm_i915_private *dev_priv = dev->dev_private;
5104 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
5105 i915.enable_execlists);
5107 mutex_lock(&dev->struct_mutex);
5109 if (IS_VALLEYVIEW(dev)) {
5110 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5111 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
5112 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
5113 VLV_GTLC_ALLOWWAKEACK), 10))
5114 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5117 if (!i915.enable_execlists) {
5118 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5119 dev_priv->gt.init_rings = i915_gem_init_rings;
5120 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
5121 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
5123 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5124 dev_priv->gt.init_rings = intel_logical_rings_init;
5125 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
5126 dev_priv->gt.stop_ring = intel_logical_ring_stop;
5129 /* This is just a security blanket to placate dragons.
5130 * On some systems, we very sporadically observe that the first TLBs
5131 * used by the CS may be stale, despite us poking the TLB reset. If
5132 * we hold the forcewake during initialisation these problems
5133 * just magically go away.
5135 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5137 ret = i915_gem_init_userptr(dev);
5141 i915_gem_init_global_gtt(dev);
5143 ret = i915_gem_context_init(dev);
5147 ret = dev_priv->gt.init_rings(dev);
5151 ret = i915_gem_init_hw(dev);
5153 /* Allow ring initialisation to fail by marking the GPU as
5154 * wedged. But we only want to do this where the GPU is angry,
5155 * for all other failure, such as an allocation failure, bail.
5157 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5158 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5163 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5164 mutex_unlock(&dev->struct_mutex);
5170 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 struct intel_engine_cs *ring;
5176 for_each_ring(ring, dev_priv, i)
5177 dev_priv->gt.cleanup_ring(ring);
5181 init_ring_lists(struct intel_engine_cs *ring)
5183 INIT_LIST_HEAD(&ring->active_list);
5184 INIT_LIST_HEAD(&ring->request_list);
5187 void i915_init_vm(struct drm_i915_private *dev_priv,
5188 struct i915_address_space *vm)
5190 if (!i915_is_ggtt(vm))
5191 drm_mm_init(&vm->mm, vm->start, vm->total);
5192 vm->dev = dev_priv->dev;
5193 INIT_LIST_HEAD(&vm->active_list);
5194 INIT_LIST_HEAD(&vm->inactive_list);
5195 INIT_LIST_HEAD(&vm->global_link);
5196 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5200 i915_gem_load(struct drm_device *dev)
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5206 kmem_cache_create("i915_gem_object",
5207 sizeof(struct drm_i915_gem_object), 0,
5211 kmem_cache_create("i915_gem_vma",
5212 sizeof(struct i915_vma), 0,
5215 dev_priv->requests =
5216 kmem_cache_create("i915_gem_request",
5217 sizeof(struct drm_i915_gem_request), 0,
5221 INIT_LIST_HEAD(&dev_priv->vm_list);
5222 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5224 INIT_LIST_HEAD(&dev_priv->context_list);
5225 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5226 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5227 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5228 for (i = 0; i < I915_NUM_RINGS; i++)
5229 init_ring_lists(&dev_priv->ring[i]);
5230 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5231 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5232 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5233 i915_gem_retire_work_handler);
5234 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5235 i915_gem_idle_work_handler);
5236 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5238 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5240 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5241 dev_priv->num_fence_regs = 32;
5242 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5243 dev_priv->num_fence_regs = 16;
5245 dev_priv->num_fence_regs = 8;
5247 if (intel_vgpu_active(dev))
5248 dev_priv->num_fence_regs =
5249 I915_READ(vgtif_reg(avail_rs.fence_num));
5251 /* Initialize fence registers to zero */
5252 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5253 i915_gem_restore_fences(dev);
5255 i915_gem_detect_bit_6_swizzle(dev);
5256 init_waitqueue_head(&dev_priv->pending_flip_queue);
5258 dev_priv->mm.interruptible = true;
5260 i915_gem_shrinker_init(dev_priv);
5262 mutex_init(&dev_priv->fb_tracking.lock);
5265 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5267 struct drm_i915_file_private *file_priv = file->driver_priv;
5269 /* Clean up our request list when the client is going away, so that
5270 * later retire_requests won't dereference our soon-to-be-gone
5273 spin_lock(&file_priv->mm.lock);
5274 while (!list_empty(&file_priv->mm.request_list)) {
5275 struct drm_i915_gem_request *request;
5277 request = list_first_entry(&file_priv->mm.request_list,
5278 struct drm_i915_gem_request,
5280 list_del(&request->client_list);
5281 request->file_priv = NULL;
5283 spin_unlock(&file_priv->mm.lock);
5285 if (!list_empty(&file_priv->rps.link)) {
5286 spin_lock(&to_i915(dev)->rps.client_lock);
5287 list_del(&file_priv->rps.link);
5288 spin_unlock(&to_i915(dev)->rps.client_lock);
5292 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5294 struct drm_i915_file_private *file_priv;
5297 DRM_DEBUG_DRIVER("\n");
5299 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5303 file->driver_priv = file_priv;
5304 file_priv->dev_priv = dev->dev_private;
5305 file_priv->file = file;
5306 INIT_LIST_HEAD(&file_priv->rps.link);
5308 spin_lock_init(&file_priv->mm.lock);
5309 INIT_LIST_HEAD(&file_priv->mm.request_list);
5311 ret = i915_gem_context_open(dev, file);
5319 * i915_gem_track_fb - update frontbuffer tracking
5320 * old: current GEM buffer for the frontbuffer slots
5321 * new: new GEM buffer for the frontbuffer slots
5322 * frontbuffer_bits: bitmask of frontbuffer slots
5324 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5325 * from @old and setting them in @new. Both @old and @new can be NULL.
5327 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5328 struct drm_i915_gem_object *new,
5329 unsigned frontbuffer_bits)
5332 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5333 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5334 old->frontbuffer_bits &= ~frontbuffer_bits;
5338 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5339 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5340 new->frontbuffer_bits |= frontbuffer_bits;
5344 /* All the new VM stuff */
5346 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5347 struct i915_address_space *vm)
5349 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5350 struct i915_vma *vma;
5352 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5354 list_for_each_entry(vma, &o->vma_list, vma_link) {
5355 if (i915_is_ggtt(vma->vm) &&
5356 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5359 return vma->node.start;
5362 WARN(1, "%s vma for this object not found.\n",
5363 i915_is_ggtt(vm) ? "global" : "ppgtt");
5368 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5369 const struct i915_ggtt_view *view)
5371 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5372 struct i915_vma *vma;
5374 list_for_each_entry(vma, &o->vma_list, vma_link)
5375 if (vma->vm == ggtt &&
5376 i915_ggtt_view_equal(&vma->ggtt_view, view))
5377 return vma->node.start;
5379 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5383 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5384 struct i915_address_space *vm)
5386 struct i915_vma *vma;
5388 list_for_each_entry(vma, &o->vma_list, vma_link) {
5389 if (i915_is_ggtt(vma->vm) &&
5390 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5392 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5399 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5400 const struct i915_ggtt_view *view)
5402 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5403 struct i915_vma *vma;
5405 list_for_each_entry(vma, &o->vma_list, vma_link)
5406 if (vma->vm == ggtt &&
5407 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5408 drm_mm_node_allocated(&vma->node))
5414 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5416 struct i915_vma *vma;
5418 list_for_each_entry(vma, &o->vma_list, vma_link)
5419 if (drm_mm_node_allocated(&vma->node))
5425 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5426 struct i915_address_space *vm)
5428 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5429 struct i915_vma *vma;
5431 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5433 BUG_ON(list_empty(&o->vma_list));
5435 list_for_each_entry(vma, &o->vma_list, vma_link) {
5436 if (i915_is_ggtt(vma->vm) &&
5437 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5440 return vma->node.size;
5445 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5447 struct i915_vma *vma;
5448 list_for_each_entry(vma, &obj->vma_list, vma_link)
5449 if (vma->pin_count > 0)