2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_init_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_init *args = data;
169 if (drm_core_check_feature(dev, DRIVER_MODESET))
172 if (args->gtt_start >= args->gtt_end ||
173 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
176 /* GEM with user mode setting was never supported on ilk and later. */
177 if (INTEL_INFO(dev)->gen >= 5)
180 mutex_lock(&dev->struct_mutex);
181 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
183 dev_priv->gtt.mappable_end = args->gtt_end;
184 mutex_unlock(&dev->struct_mutex);
190 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
191 struct drm_file *file)
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct drm_i915_gem_get_aperture *args = data;
195 struct drm_i915_gem_object *obj;
199 mutex_lock(&dev->struct_mutex);
200 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
201 if (i915_gem_obj_is_pinned(obj))
202 pinned += i915_gem_obj_ggtt_size(obj);
203 mutex_unlock(&dev->struct_mutex);
205 args->aper_size = dev_priv->gtt.base.total;
206 args->aper_available_size = args->aper_size - pinned;
212 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
214 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
215 char *vaddr = obj->phys_handle->vaddr;
217 struct scatterlist *sg;
220 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
223 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
227 page = shmem_read_mapping_page(mapping, i);
229 return PTR_ERR(page);
231 src = kmap_atomic(page);
232 memcpy(vaddr, src, PAGE_SIZE);
233 drm_clflush_virt_range(vaddr, PAGE_SIZE);
236 page_cache_release(page);
240 i915_gem_chipset_flush(obj->base.dev);
242 st = kmalloc(sizeof(*st), GFP_KERNEL);
246 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
253 sg->length = obj->base.size;
255 sg_dma_address(sg) = obj->phys_handle->busaddr;
256 sg_dma_len(sg) = obj->base.size;
259 obj->has_dma_mapping = true;
264 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
268 BUG_ON(obj->madv == __I915_MADV_PURGED);
270 ret = i915_gem_object_set_to_cpu_domain(obj, true);
272 /* In the event of a disaster, abandon all caches and
275 WARN_ON(ret != -EIO);
276 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
279 if (obj->madv == I915_MADV_DONTNEED)
283 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
284 char *vaddr = obj->phys_handle->vaddr;
287 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
291 page = shmem_read_mapping_page(mapping, i);
295 dst = kmap_atomic(page);
296 drm_clflush_virt_range(vaddr, PAGE_SIZE);
297 memcpy(dst, vaddr, PAGE_SIZE);
300 set_page_dirty(page);
301 if (obj->madv == I915_MADV_WILLNEED)
302 mark_page_accessed(page);
303 page_cache_release(page);
309 sg_free_table(obj->pages);
312 obj->has_dma_mapping = false;
316 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
318 drm_pci_free(obj->base.dev, obj->phys_handle);
321 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
322 .get_pages = i915_gem_object_get_pages_phys,
323 .put_pages = i915_gem_object_put_pages_phys,
324 .release = i915_gem_object_release_phys,
328 drop_pages(struct drm_i915_gem_object *obj)
330 struct i915_vma *vma, *next;
333 drm_gem_object_reference(&obj->base);
334 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
335 if (i915_vma_unbind(vma))
338 ret = i915_gem_object_put_pages(obj);
339 drm_gem_object_unreference(&obj->base);
345 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
348 drm_dma_handle_t *phys;
351 if (obj->phys_handle) {
352 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
358 if (obj->madv != I915_MADV_WILLNEED)
361 if (obj->base.filp == NULL)
364 ret = drop_pages(obj);
368 /* create a new object */
369 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
373 obj->phys_handle = phys;
374 obj->ops = &i915_gem_phys_ops;
376 return i915_gem_object_get_pages(obj);
380 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
381 struct drm_i915_gem_pwrite *args,
382 struct drm_file *file_priv)
384 struct drm_device *dev = obj->base.dev;
385 void *vaddr = obj->phys_handle->vaddr + args->offset;
386 char __user *user_data = to_user_ptr(args->data_ptr);
389 /* We manually control the domain here and pretend that it
390 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
392 ret = i915_gem_object_wait_rendering(obj, false);
396 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
397 unsigned long unwritten;
399 /* The physical object once assigned is fixed for the lifetime
400 * of the obj, so we can safely drop the lock and continue
403 mutex_unlock(&dev->struct_mutex);
404 unwritten = copy_from_user(vaddr, user_data, args->size);
405 mutex_lock(&dev->struct_mutex);
410 drm_clflush_virt_range(vaddr, args->size);
411 i915_gem_chipset_flush(dev);
415 void *i915_gem_object_alloc(struct drm_device *dev)
417 struct drm_i915_private *dev_priv = dev->dev_private;
418 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
421 void i915_gem_object_free(struct drm_i915_gem_object *obj)
423 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
424 kmem_cache_free(dev_priv->slab, obj);
428 i915_gem_create(struct drm_file *file,
429 struct drm_device *dev,
433 struct drm_i915_gem_object *obj;
437 size = roundup(size, PAGE_SIZE);
441 /* Allocate the new object */
442 obj = i915_gem_alloc_object(dev, size);
446 ret = drm_gem_handle_create(file, &obj->base, &handle);
447 /* drop reference from allocate - handle holds it now */
448 drm_gem_object_unreference_unlocked(&obj->base);
457 i915_gem_dumb_create(struct drm_file *file,
458 struct drm_device *dev,
459 struct drm_mode_create_dumb *args)
461 /* have to work out size/pitch and return them */
462 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
463 args->size = args->pitch * args->height;
464 return i915_gem_create(file, dev,
465 args->size, &args->handle);
469 * Creates a new mm object and returns a handle to it.
472 i915_gem_create_ioctl(struct drm_device *dev, void *data,
473 struct drm_file *file)
475 struct drm_i915_gem_create *args = data;
477 return i915_gem_create(file, dev,
478 args->size, &args->handle);
482 __copy_to_user_swizzled(char __user *cpu_vaddr,
483 const char *gpu_vaddr, int gpu_offset,
486 int ret, cpu_offset = 0;
489 int cacheline_end = ALIGN(gpu_offset + 1, 64);
490 int this_length = min(cacheline_end - gpu_offset, length);
491 int swizzled_gpu_offset = gpu_offset ^ 64;
493 ret = __copy_to_user(cpu_vaddr + cpu_offset,
494 gpu_vaddr + swizzled_gpu_offset,
499 cpu_offset += this_length;
500 gpu_offset += this_length;
501 length -= this_length;
508 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
509 const char __user *cpu_vaddr,
512 int ret, cpu_offset = 0;
515 int cacheline_end = ALIGN(gpu_offset + 1, 64);
516 int this_length = min(cacheline_end - gpu_offset, length);
517 int swizzled_gpu_offset = gpu_offset ^ 64;
519 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
520 cpu_vaddr + cpu_offset,
525 cpu_offset += this_length;
526 gpu_offset += this_length;
527 length -= this_length;
534 * Pins the specified object's pages and synchronizes the object with
535 * GPU accesses. Sets needs_clflush to non-zero if the caller should
536 * flush the object from the CPU cache.
538 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
548 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
549 /* If we're not in the cpu read domain, set ourself into the gtt
550 * read domain and manually flush cachelines (if required). This
551 * optimizes for the case when the gpu will dirty the data
552 * anyway again before the next pread happens. */
553 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
555 ret = i915_gem_object_wait_rendering(obj, true);
559 i915_gem_object_retire(obj);
562 ret = i915_gem_object_get_pages(obj);
566 i915_gem_object_pin_pages(obj);
571 /* Per-page copy function for the shmem pread fastpath.
572 * Flushes invalid cachelines before reading the target if
573 * needs_clflush is set. */
575 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
576 char __user *user_data,
577 bool page_do_bit17_swizzling, bool needs_clflush)
582 if (unlikely(page_do_bit17_swizzling))
585 vaddr = kmap_atomic(page);
587 drm_clflush_virt_range(vaddr + shmem_page_offset,
589 ret = __copy_to_user_inatomic(user_data,
590 vaddr + shmem_page_offset,
592 kunmap_atomic(vaddr);
594 return ret ? -EFAULT : 0;
598 shmem_clflush_swizzled_range(char *addr, unsigned long length,
601 if (unlikely(swizzled)) {
602 unsigned long start = (unsigned long) addr;
603 unsigned long end = (unsigned long) addr + length;
605 /* For swizzling simply ensure that we always flush both
606 * channels. Lame, but simple and it works. Swizzled
607 * pwrite/pread is far from a hotpath - current userspace
608 * doesn't use it at all. */
609 start = round_down(start, 128);
610 end = round_up(end, 128);
612 drm_clflush_virt_range((void *)start, end - start);
614 drm_clflush_virt_range(addr, length);
619 /* Only difference to the fast-path function is that this can handle bit17
620 * and uses non-atomic copy and kmap functions. */
622 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
623 char __user *user_data,
624 bool page_do_bit17_swizzling, bool needs_clflush)
631 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
633 page_do_bit17_swizzling);
635 if (page_do_bit17_swizzling)
636 ret = __copy_to_user_swizzled(user_data,
637 vaddr, shmem_page_offset,
640 ret = __copy_to_user(user_data,
641 vaddr + shmem_page_offset,
645 return ret ? - EFAULT : 0;
649 i915_gem_shmem_pread(struct drm_device *dev,
650 struct drm_i915_gem_object *obj,
651 struct drm_i915_gem_pread *args,
652 struct drm_file *file)
654 char __user *user_data;
657 int shmem_page_offset, page_length, ret = 0;
658 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
660 int needs_clflush = 0;
661 struct sg_page_iter sg_iter;
663 user_data = to_user_ptr(args->data_ptr);
666 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
668 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
672 offset = args->offset;
674 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
675 offset >> PAGE_SHIFT) {
676 struct page *page = sg_page_iter_page(&sg_iter);
681 /* Operation in this page
683 * shmem_page_offset = offset within page in shmem file
684 * page_length = bytes to copy for this page
686 shmem_page_offset = offset_in_page(offset);
687 page_length = remain;
688 if ((shmem_page_offset + page_length) > PAGE_SIZE)
689 page_length = PAGE_SIZE - shmem_page_offset;
691 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
692 (page_to_phys(page) & (1 << 17)) != 0;
694 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
695 user_data, page_do_bit17_swizzling,
700 mutex_unlock(&dev->struct_mutex);
702 if (likely(!i915.prefault_disable) && !prefaulted) {
703 ret = fault_in_multipages_writeable(user_data, remain);
704 /* Userspace is tricking us, but we've already clobbered
705 * its pages with the prefault and promised to write the
706 * data up to the first fault. Hence ignore any errors
707 * and just continue. */
712 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
713 user_data, page_do_bit17_swizzling,
716 mutex_lock(&dev->struct_mutex);
722 remain -= page_length;
723 user_data += page_length;
724 offset += page_length;
728 i915_gem_object_unpin_pages(obj);
734 * Reads data from the object referenced by handle.
736 * On error, the contents of *data are undefined.
739 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *file)
742 struct drm_i915_gem_pread *args = data;
743 struct drm_i915_gem_object *obj;
749 if (!access_ok(VERIFY_WRITE,
750 to_user_ptr(args->data_ptr),
754 ret = i915_mutex_lock_interruptible(dev);
758 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
759 if (&obj->base == NULL) {
764 /* Bounds check source. */
765 if (args->offset > obj->base.size ||
766 args->size > obj->base.size - args->offset) {
771 /* prime objects have no backing filp to GEM pread/pwrite
774 if (!obj->base.filp) {
779 trace_i915_gem_object_pread(obj, args->offset, args->size);
781 ret = i915_gem_shmem_pread(dev, obj, args, file);
784 drm_gem_object_unreference(&obj->base);
786 mutex_unlock(&dev->struct_mutex);
790 /* This is the fast write path which cannot handle
791 * page faults in the source data
795 fast_user_write(struct io_mapping *mapping,
796 loff_t page_base, int page_offset,
797 char __user *user_data,
800 void __iomem *vaddr_atomic;
802 unsigned long unwritten;
804 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
805 /* We can use the cpu mem copy function because this is X86. */
806 vaddr = (void __force*)vaddr_atomic + page_offset;
807 unwritten = __copy_from_user_inatomic_nocache(vaddr,
809 io_mapping_unmap_atomic(vaddr_atomic);
814 * This is the fast pwrite path, where we copy the data directly from the
815 * user into the GTT, uncached.
818 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
819 struct drm_i915_gem_object *obj,
820 struct drm_i915_gem_pwrite *args,
821 struct drm_file *file)
823 struct drm_i915_private *dev_priv = dev->dev_private;
825 loff_t offset, page_base;
826 char __user *user_data;
827 int page_offset, page_length, ret;
829 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
833 ret = i915_gem_object_set_to_gtt_domain(obj, true);
837 ret = i915_gem_object_put_fence(obj);
841 user_data = to_user_ptr(args->data_ptr);
844 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
847 /* Operation in this page
849 * page_base = page offset within aperture
850 * page_offset = offset within page
851 * page_length = bytes to copy for this page
853 page_base = offset & PAGE_MASK;
854 page_offset = offset_in_page(offset);
855 page_length = remain;
856 if ((page_offset + remain) > PAGE_SIZE)
857 page_length = PAGE_SIZE - page_offset;
859 /* If we get a fault while copying data, then (presumably) our
860 * source page isn't available. Return the error and we'll
861 * retry in the slow path.
863 if (fast_user_write(dev_priv->gtt.mappable, page_base,
864 page_offset, user_data, page_length)) {
869 remain -= page_length;
870 user_data += page_length;
871 offset += page_length;
875 i915_gem_object_ggtt_unpin(obj);
880 /* Per-page copy function for the shmem pwrite fastpath.
881 * Flushes invalid cachelines before writing to the target if
882 * needs_clflush_before is set and flushes out any written cachelines after
883 * writing if needs_clflush is set. */
885 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
886 char __user *user_data,
887 bool page_do_bit17_swizzling,
888 bool needs_clflush_before,
889 bool needs_clflush_after)
894 if (unlikely(page_do_bit17_swizzling))
897 vaddr = kmap_atomic(page);
898 if (needs_clflush_before)
899 drm_clflush_virt_range(vaddr + shmem_page_offset,
901 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
902 user_data, page_length);
903 if (needs_clflush_after)
904 drm_clflush_virt_range(vaddr + shmem_page_offset,
906 kunmap_atomic(vaddr);
908 return ret ? -EFAULT : 0;
911 /* Only difference to the fast-path function is that this can handle bit17
912 * and uses non-atomic copy and kmap functions. */
914 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
915 char __user *user_data,
916 bool page_do_bit17_swizzling,
917 bool needs_clflush_before,
918 bool needs_clflush_after)
924 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
925 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
927 page_do_bit17_swizzling);
928 if (page_do_bit17_swizzling)
929 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
933 ret = __copy_from_user(vaddr + shmem_page_offset,
936 if (needs_clflush_after)
937 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
939 page_do_bit17_swizzling);
942 return ret ? -EFAULT : 0;
946 i915_gem_shmem_pwrite(struct drm_device *dev,
947 struct drm_i915_gem_object *obj,
948 struct drm_i915_gem_pwrite *args,
949 struct drm_file *file)
953 char __user *user_data;
954 int shmem_page_offset, page_length, ret = 0;
955 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
956 int hit_slowpath = 0;
957 int needs_clflush_after = 0;
958 int needs_clflush_before = 0;
959 struct sg_page_iter sg_iter;
961 user_data = to_user_ptr(args->data_ptr);
964 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
966 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
967 /* If we're not in the cpu write domain, set ourself into the gtt
968 * write domain and manually flush cachelines (if required). This
969 * optimizes for the case when the gpu will use the data
970 * right away and we therefore have to clflush anyway. */
971 needs_clflush_after = cpu_write_needs_clflush(obj);
972 ret = i915_gem_object_wait_rendering(obj, false);
976 i915_gem_object_retire(obj);
978 /* Same trick applies to invalidate partially written cachelines read
980 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
981 needs_clflush_before =
982 !cpu_cache_is_coherent(dev, obj->cache_level);
984 ret = i915_gem_object_get_pages(obj);
988 i915_gem_object_pin_pages(obj);
990 offset = args->offset;
993 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
994 offset >> PAGE_SHIFT) {
995 struct page *page = sg_page_iter_page(&sg_iter);
996 int partial_cacheline_write;
1001 /* Operation in this page
1003 * shmem_page_offset = offset within page in shmem file
1004 * page_length = bytes to copy for this page
1006 shmem_page_offset = offset_in_page(offset);
1008 page_length = remain;
1009 if ((shmem_page_offset + page_length) > PAGE_SIZE)
1010 page_length = PAGE_SIZE - shmem_page_offset;
1012 /* If we don't overwrite a cacheline completely we need to be
1013 * careful to have up-to-date data by first clflushing. Don't
1014 * overcomplicate things and flush the entire patch. */
1015 partial_cacheline_write = needs_clflush_before &&
1016 ((shmem_page_offset | page_length)
1017 & (boot_cpu_data.x86_clflush_size - 1));
1019 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
1020 (page_to_phys(page) & (1 << 17)) != 0;
1022 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
1023 user_data, page_do_bit17_swizzling,
1024 partial_cacheline_write,
1025 needs_clflush_after);
1030 mutex_unlock(&dev->struct_mutex);
1031 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1032 user_data, page_do_bit17_swizzling,
1033 partial_cacheline_write,
1034 needs_clflush_after);
1036 mutex_lock(&dev->struct_mutex);
1042 remain -= page_length;
1043 user_data += page_length;
1044 offset += page_length;
1048 i915_gem_object_unpin_pages(obj);
1052 * Fixup: Flush cpu caches in case we didn't flush the dirty
1053 * cachelines in-line while writing and the object moved
1054 * out of the cpu write domain while we've dropped the lock.
1056 if (!needs_clflush_after &&
1057 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1058 if (i915_gem_clflush_object(obj, obj->pin_display))
1059 i915_gem_chipset_flush(dev);
1063 if (needs_clflush_after)
1064 i915_gem_chipset_flush(dev);
1070 * Writes data to the object referenced by handle.
1072 * On error, the contents of the buffer that were to be modified are undefined.
1075 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1076 struct drm_file *file)
1078 struct drm_i915_gem_pwrite *args = data;
1079 struct drm_i915_gem_object *obj;
1082 if (args->size == 0)
1085 if (!access_ok(VERIFY_READ,
1086 to_user_ptr(args->data_ptr),
1090 if (likely(!i915.prefault_disable)) {
1091 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1097 ret = i915_mutex_lock_interruptible(dev);
1101 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1102 if (&obj->base == NULL) {
1107 /* Bounds check destination. */
1108 if (args->offset > obj->base.size ||
1109 args->size > obj->base.size - args->offset) {
1114 /* prime objects have no backing filp to GEM pread/pwrite
1117 if (!obj->base.filp) {
1122 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1125 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1126 * it would end up going through the fenced access, and we'll get
1127 * different detiling behavior between reading and writing.
1128 * pread/pwrite currently are reading and writing from the CPU
1129 * perspective, requiring manual detiling by the client.
1131 if (obj->tiling_mode == I915_TILING_NONE &&
1132 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1133 cpu_write_needs_clflush(obj)) {
1134 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1135 /* Note that the gtt paths might fail with non-page-backed user
1136 * pointers (e.g. gtt mappings when moving data between
1137 * textures). Fallback to the shmem path in that case. */
1140 if (ret == -EFAULT || ret == -ENOSPC) {
1141 if (obj->phys_handle)
1142 ret = i915_gem_phys_pwrite(obj, args, file);
1144 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1148 drm_gem_object_unreference(&obj->base);
1150 mutex_unlock(&dev->struct_mutex);
1155 i915_gem_check_wedge(struct i915_gpu_error *error,
1158 if (i915_reset_in_progress(error)) {
1159 /* Non-interruptible callers can't handle -EAGAIN, hence return
1160 * -EIO unconditionally for these. */
1164 /* Recovery complete, but the reset failed ... */
1165 if (i915_terminally_wedged(error))
1169 * Check if GPU Reset is in progress - we need intel_ring_begin
1170 * to work properly to reinit the hw state while the gpu is
1171 * still marked as reset-in-progress. Handle this with a flag.
1173 if (!error->reload_in_reset)
1181 * Compare seqno against outstanding lazy request. Emit a request if they are
1185 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1189 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1192 if (seqno == ring->outstanding_lazy_seqno)
1193 ret = i915_add_request(ring, NULL);
1198 static void fake_irq(unsigned long data)
1200 wake_up_process((struct task_struct *)data);
1203 static bool missed_irq(struct drm_i915_private *dev_priv,
1204 struct intel_engine_cs *ring)
1206 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1209 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1211 if (file_priv == NULL)
1214 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1218 * __i915_wait_seqno - wait until execution of seqno has finished
1219 * @ring: the ring expected to report seqno
1221 * @reset_counter: reset sequence associated with the given seqno
1222 * @interruptible: do an interruptible wait (normally yes)
1223 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1225 * Note: It is of utmost importance that the passed in seqno and reset_counter
1226 * values have been read by the caller in an smp safe manner. Where read-side
1227 * locks are involved, it is sufficient to read the reset_counter before
1228 * unlocking the lock that protects the seqno. For lockless tricks, the
1229 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1232 * Returns 0 if the seqno was found within the alloted time. Else returns the
1233 * errno with remaining time filled in timeout argument.
1235 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1236 unsigned reset_counter,
1239 struct drm_i915_file_private *file_priv)
1241 struct drm_device *dev = ring->dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 const bool irq_test_in_progress =
1244 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1246 unsigned long timeout_expire;
1250 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1252 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1255 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1257 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1258 gen6_rps_boost(dev_priv);
1260 mod_delayed_work(dev_priv->wq,
1261 &file_priv->mm.idle_work,
1262 msecs_to_jiffies(100));
1265 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1268 /* Record current time in case interrupted by signal, or wedged */
1269 trace_i915_gem_request_wait_begin(ring, seqno);
1270 before = ktime_get_raw_ns();
1272 struct timer_list timer;
1274 prepare_to_wait(&ring->irq_queue, &wait,
1275 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1277 /* We need to check whether any gpu reset happened in between
1278 * the caller grabbing the seqno and now ... */
1279 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1280 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1281 * is truely gone. */
1282 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1288 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1293 if (interruptible && signal_pending(current)) {
1298 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1303 timer.function = NULL;
1304 if (timeout || missed_irq(dev_priv, ring)) {
1305 unsigned long expire;
1307 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1308 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1309 mod_timer(&timer, expire);
1314 if (timer.function) {
1315 del_singleshot_timer_sync(&timer);
1316 destroy_timer_on_stack(&timer);
1319 now = ktime_get_raw_ns();
1320 trace_i915_gem_request_wait_end(ring, seqno);
1322 if (!irq_test_in_progress)
1323 ring->irq_put(ring);
1325 finish_wait(&ring->irq_queue, &wait);
1328 s64 tres = *timeout - (now - before);
1330 *timeout = tres < 0 ? 0 : tres;
1337 * Waits for a sequence number to be signaled, and cleans up the
1338 * request and object lists appropriately for that event.
1341 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1343 struct drm_device *dev = ring->dev;
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 bool interruptible = dev_priv->mm.interruptible;
1346 unsigned reset_counter;
1349 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1352 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1356 ret = i915_gem_check_olr(ring, seqno);
1360 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1361 return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
1366 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1371 /* Manually manage the write flush as we may have not yet
1372 * retired the buffer.
1374 * Note that the last_write_seqno is always the earlier of
1375 * the two (read/write) seqno, so if we haved successfully waited,
1376 * we know we have passed the last write.
1378 obj->last_write_seqno = 0;
1384 * Ensures that all rendering to the object has completed and the object is
1385 * safe to unbind from the GTT or access from the CPU.
1387 static __must_check int
1388 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1391 struct intel_engine_cs *ring = obj->ring;
1395 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1399 ret = i915_wait_seqno(ring, seqno);
1403 return i915_gem_object_wait_rendering__tail(obj);
1406 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1407 * as the object state may change during this call.
1409 static __must_check int
1410 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1411 struct drm_i915_file_private *file_priv,
1414 struct drm_device *dev = obj->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 struct intel_engine_cs *ring = obj->ring;
1417 unsigned reset_counter;
1421 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1422 BUG_ON(!dev_priv->mm.interruptible);
1424 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1428 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1432 ret = i915_gem_check_olr(ring, seqno);
1436 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1437 mutex_unlock(&dev->struct_mutex);
1438 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
1440 mutex_lock(&dev->struct_mutex);
1444 return i915_gem_object_wait_rendering__tail(obj);
1448 * Called when user space prepares to use an object with the CPU, either
1449 * through the mmap ioctl's mapping or a GTT mapping.
1452 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1453 struct drm_file *file)
1455 struct drm_i915_gem_set_domain *args = data;
1456 struct drm_i915_gem_object *obj;
1457 uint32_t read_domains = args->read_domains;
1458 uint32_t write_domain = args->write_domain;
1461 /* Only handle setting domains to types used by the CPU. */
1462 if (write_domain & I915_GEM_GPU_DOMAINS)
1465 if (read_domains & I915_GEM_GPU_DOMAINS)
1468 /* Having something in the write domain implies it's in the read
1469 * domain, and only that read domain. Enforce that in the request.
1471 if (write_domain != 0 && read_domains != write_domain)
1474 ret = i915_mutex_lock_interruptible(dev);
1478 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1479 if (&obj->base == NULL) {
1484 /* Try to flush the object off the GPU without holding the lock.
1485 * We will repeat the flush holding the lock in the normal manner
1486 * to catch cases where we are gazumped.
1488 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1494 if (read_domains & I915_GEM_DOMAIN_GTT) {
1495 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1497 /* Silently promote "you're not bound, there was nothing to do"
1498 * to success, since the client was just asking us to
1499 * make sure everything was done.
1504 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1508 drm_gem_object_unreference(&obj->base);
1510 mutex_unlock(&dev->struct_mutex);
1515 * Called when user space has done writes to this buffer
1518 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1519 struct drm_file *file)
1521 struct drm_i915_gem_sw_finish *args = data;
1522 struct drm_i915_gem_object *obj;
1525 ret = i915_mutex_lock_interruptible(dev);
1529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1530 if (&obj->base == NULL) {
1535 /* Pinned buffers may be scanout, so flush the cache */
1536 if (obj->pin_display)
1537 i915_gem_object_flush_cpu_write_domain(obj, true);
1539 drm_gem_object_unreference(&obj->base);
1541 mutex_unlock(&dev->struct_mutex);
1546 * Maps the contents of an object, returning the address it is mapped
1549 * While the mapping holds a reference on the contents of the object, it doesn't
1550 * imply a ref on the object itself.
1554 * DRM driver writers who look a this function as an example for how to do GEM
1555 * mmap support, please don't implement mmap support like here. The modern way
1556 * to implement DRM mmap support is with an mmap offset ioctl (like
1557 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1558 * That way debug tooling like valgrind will understand what's going on, hiding
1559 * the mmap call in a driver private ioctl will break that. The i915 driver only
1560 * does cpu mmaps this way because we didn't know better.
1563 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1564 struct drm_file *file)
1566 struct drm_i915_gem_mmap *args = data;
1567 struct drm_gem_object *obj;
1570 obj = drm_gem_object_lookup(dev, file, args->handle);
1574 /* prime objects have no backing filp to GEM mmap
1578 drm_gem_object_unreference_unlocked(obj);
1582 addr = vm_mmap(obj->filp, 0, args->size,
1583 PROT_READ | PROT_WRITE, MAP_SHARED,
1585 drm_gem_object_unreference_unlocked(obj);
1586 if (IS_ERR((void *)addr))
1589 args->addr_ptr = (uint64_t) addr;
1595 * i915_gem_fault - fault a page into the GTT
1596 * vma: VMA in question
1599 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1600 * from userspace. The fault handler takes care of binding the object to
1601 * the GTT (if needed), allocating and programming a fence register (again,
1602 * only if needed based on whether the old reg is still valid or the object
1603 * is tiled) and inserting a new PTE into the faulting process.
1605 * Note that the faulting process may involve evicting existing objects
1606 * from the GTT and/or fence registers to make room. So performance may
1607 * suffer if the GTT working set is large or there are few fence registers
1610 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1612 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1613 struct drm_device *dev = obj->base.dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 pgoff_t page_offset;
1618 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1620 intel_runtime_pm_get(dev_priv);
1622 /* We don't use vmf->pgoff since that has the fake offset */
1623 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1626 ret = i915_mutex_lock_interruptible(dev);
1630 trace_i915_gem_object_fault(obj, page_offset, true, write);
1632 /* Try to flush the object off the GPU first without holding the lock.
1633 * Upon reacquiring the lock, we will perform our sanity checks and then
1634 * repeat the flush holding the lock in the normal manner to catch cases
1635 * where we are gazumped.
1637 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1641 /* Access to snoopable pages through the GTT is incoherent. */
1642 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1647 /* Now bind it into the GTT if needed */
1648 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1652 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1656 ret = i915_gem_object_get_fence(obj);
1660 /* Finally, remap it using the new GTT offset */
1661 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1664 if (!obj->fault_mappable) {
1665 unsigned long size = min_t(unsigned long,
1666 vma->vm_end - vma->vm_start,
1670 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1671 ret = vm_insert_pfn(vma,
1672 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1678 obj->fault_mappable = true;
1680 ret = vm_insert_pfn(vma,
1681 (unsigned long)vmf->virtual_address,
1684 i915_gem_object_ggtt_unpin(obj);
1686 mutex_unlock(&dev->struct_mutex);
1691 * We eat errors when the gpu is terminally wedged to avoid
1692 * userspace unduly crashing (gl has no provisions for mmaps to
1693 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1694 * and so needs to be reported.
1696 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1697 ret = VM_FAULT_SIGBUS;
1702 * EAGAIN means the gpu is hung and we'll wait for the error
1703 * handler to reset everything when re-faulting in
1704 * i915_mutex_lock_interruptible.
1711 * EBUSY is ok: this just means that another thread
1712 * already did the job.
1714 ret = VM_FAULT_NOPAGE;
1721 ret = VM_FAULT_SIGBUS;
1724 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1725 ret = VM_FAULT_SIGBUS;
1729 intel_runtime_pm_put(dev_priv);
1734 * i915_gem_release_mmap - remove physical page mappings
1735 * @obj: obj in question
1737 * Preserve the reservation of the mmapping with the DRM core code, but
1738 * relinquish ownership of the pages back to the system.
1740 * It is vital that we remove the page mapping if we have mapped a tiled
1741 * object through the GTT and then lose the fence register due to
1742 * resource pressure. Similarly if the object has been moved out of the
1743 * aperture, than pages mapped into userspace must be revoked. Removing the
1744 * mapping will then trigger a page fault on the next user access, allowing
1745 * fixup by i915_gem_fault().
1748 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1750 if (!obj->fault_mappable)
1753 drm_vma_node_unmap(&obj->base.vma_node,
1754 obj->base.dev->anon_inode->i_mapping);
1755 obj->fault_mappable = false;
1759 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1761 struct drm_i915_gem_object *obj;
1763 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1764 i915_gem_release_mmap(obj);
1768 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1772 if (INTEL_INFO(dev)->gen >= 4 ||
1773 tiling_mode == I915_TILING_NONE)
1776 /* Previous chips need a power-of-two fence region when tiling */
1777 if (INTEL_INFO(dev)->gen == 3)
1778 gtt_size = 1024*1024;
1780 gtt_size = 512*1024;
1782 while (gtt_size < size)
1789 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1790 * @obj: object to check
1792 * Return the required GTT alignment for an object, taking into account
1793 * potential fence register mapping.
1796 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1797 int tiling_mode, bool fenced)
1800 * Minimum alignment is 4k (GTT page size), but might be greater
1801 * if a fence register is needed for the object.
1803 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1804 tiling_mode == I915_TILING_NONE)
1808 * Previous chips need to be aligned to the size of the smallest
1809 * fence register that can contain the object.
1811 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1814 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1816 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1819 if (drm_vma_node_has_offset(&obj->base.vma_node))
1822 dev_priv->mm.shrinker_no_lock_stealing = true;
1824 ret = drm_gem_create_mmap_offset(&obj->base);
1828 /* Badly fragmented mmap space? The only way we can recover
1829 * space is by destroying unwanted objects. We can't randomly release
1830 * mmap_offsets as userspace expects them to be persistent for the
1831 * lifetime of the objects. The closest we can is to release the
1832 * offsets on purgeable objects by truncating it and marking it purged,
1833 * which prevents userspace from ever using that object again.
1835 i915_gem_shrink(dev_priv,
1836 obj->base.size >> PAGE_SHIFT,
1838 I915_SHRINK_UNBOUND |
1839 I915_SHRINK_PURGEABLE);
1840 ret = drm_gem_create_mmap_offset(&obj->base);
1844 i915_gem_shrink_all(dev_priv);
1845 ret = drm_gem_create_mmap_offset(&obj->base);
1847 dev_priv->mm.shrinker_no_lock_stealing = false;
1852 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1854 drm_gem_free_mmap_offset(&obj->base);
1858 i915_gem_mmap_gtt(struct drm_file *file,
1859 struct drm_device *dev,
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 struct drm_i915_gem_object *obj;
1867 ret = i915_mutex_lock_interruptible(dev);
1871 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1872 if (&obj->base == NULL) {
1877 if (obj->base.size > dev_priv->gtt.mappable_end) {
1882 if (obj->madv != I915_MADV_WILLNEED) {
1883 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1888 ret = i915_gem_object_create_mmap_offset(obj);
1892 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1895 drm_gem_object_unreference(&obj->base);
1897 mutex_unlock(&dev->struct_mutex);
1902 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1904 * @data: GTT mapping ioctl data
1905 * @file: GEM object info
1907 * Simply returns the fake offset to userspace so it can mmap it.
1908 * The mmap call will end up in drm_gem_mmap(), which will set things
1909 * up so we can get faults in the handler above.
1911 * The fault handler will take care of binding the object into the GTT
1912 * (since it may have been evicted to make room for something), allocating
1913 * a fence register, and mapping the appropriate aperture address into
1917 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1918 struct drm_file *file)
1920 struct drm_i915_gem_mmap_gtt *args = data;
1922 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1926 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1928 return obj->madv == I915_MADV_DONTNEED;
1931 /* Immediately discard the backing storage */
1933 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1935 i915_gem_object_free_mmap_offset(obj);
1937 if (obj->base.filp == NULL)
1940 /* Our goal here is to return as much of the memory as
1941 * is possible back to the system as we are called from OOM.
1942 * To do this we must instruct the shmfs to drop all of its
1943 * backing pages, *now*.
1945 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1946 obj->madv = __I915_MADV_PURGED;
1949 /* Try to discard unwanted pages */
1951 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1953 struct address_space *mapping;
1955 switch (obj->madv) {
1956 case I915_MADV_DONTNEED:
1957 i915_gem_object_truncate(obj);
1958 case __I915_MADV_PURGED:
1962 if (obj->base.filp == NULL)
1965 mapping = file_inode(obj->base.filp)->i_mapping,
1966 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1970 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1972 struct sg_page_iter sg_iter;
1975 BUG_ON(obj->madv == __I915_MADV_PURGED);
1977 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1979 /* In the event of a disaster, abandon all caches and
1980 * hope for the best.
1982 WARN_ON(ret != -EIO);
1983 i915_gem_clflush_object(obj, true);
1984 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1987 if (i915_gem_object_needs_bit17_swizzle(obj))
1988 i915_gem_object_save_bit_17_swizzle(obj);
1990 if (obj->madv == I915_MADV_DONTNEED)
1993 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1994 struct page *page = sg_page_iter_page(&sg_iter);
1997 set_page_dirty(page);
1999 if (obj->madv == I915_MADV_WILLNEED)
2000 mark_page_accessed(page);
2002 page_cache_release(page);
2006 sg_free_table(obj->pages);
2011 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2013 const struct drm_i915_gem_object_ops *ops = obj->ops;
2015 if (obj->pages == NULL)
2018 if (obj->pages_pin_count)
2021 BUG_ON(i915_gem_obj_bound_any(obj));
2023 /* ->put_pages might need to allocate memory for the bit17 swizzle
2024 * array, hence protect them from being reaped by removing them from gtt
2026 list_del(&obj->global_list);
2028 ops->put_pages(obj);
2031 i915_gem_object_invalidate(obj);
2037 i915_gem_shrink(struct drm_i915_private *dev_priv,
2038 long target, unsigned flags)
2041 struct list_head *list;
2044 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2045 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2048 unsigned long count = 0;
2051 * As we may completely rewrite the (un)bound list whilst unbinding
2052 * (due to retiring requests) we have to strictly process only
2053 * one element of the list at the time, and recheck the list
2054 * on every iteration.
2056 * In particular, we must hold a reference whilst removing the
2057 * object as we may end up waiting for and/or retiring the objects.
2058 * This might release the final reference (held by the active list)
2059 * and result in the object being freed from under us. This is
2060 * similar to the precautions the eviction code must take whilst
2063 * Also note that although these lists do not hold a reference to
2064 * the object we can safely grab one here: The final object
2065 * unreferencing and the bound_list are both protected by the
2066 * dev->struct_mutex and so we won't ever be able to observe an
2067 * object on the bound_list with a reference count equals 0.
2069 for (phase = phases; phase->list; phase++) {
2070 struct list_head still_in_list;
2072 if ((flags & phase->bit) == 0)
2075 INIT_LIST_HEAD(&still_in_list);
2076 while (count < target && !list_empty(phase->list)) {
2077 struct drm_i915_gem_object *obj;
2078 struct i915_vma *vma, *v;
2080 obj = list_first_entry(phase->list,
2081 typeof(*obj), global_list);
2082 list_move_tail(&obj->global_list, &still_in_list);
2084 if (flags & I915_SHRINK_PURGEABLE &&
2085 !i915_gem_object_is_purgeable(obj))
2088 drm_gem_object_reference(&obj->base);
2090 /* For the unbound phase, this should be a no-op! */
2091 list_for_each_entry_safe(vma, v,
2092 &obj->vma_list, vma_link)
2093 if (i915_vma_unbind(vma))
2096 if (i915_gem_object_put_pages(obj) == 0)
2097 count += obj->base.size >> PAGE_SHIFT;
2099 drm_gem_object_unreference(&obj->base);
2101 list_splice(&still_in_list, phase->list);
2107 static unsigned long
2108 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2110 i915_gem_evict_everything(dev_priv->dev);
2111 return i915_gem_shrink(dev_priv, LONG_MAX,
2112 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2116 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2118 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2120 struct address_space *mapping;
2121 struct sg_table *st;
2122 struct scatterlist *sg;
2123 struct sg_page_iter sg_iter;
2125 unsigned long last_pfn = 0; /* suppress gcc warning */
2128 /* Assert that the object is not currently in any GPU domain. As it
2129 * wasn't in the GTT, there shouldn't be any way it could have been in
2132 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2133 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2135 st = kmalloc(sizeof(*st), GFP_KERNEL);
2139 page_count = obj->base.size / PAGE_SIZE;
2140 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2145 /* Get the list of pages out of our struct file. They'll be pinned
2146 * at this point until we release them.
2148 * Fail silently without starting the shrinker
2150 mapping = file_inode(obj->base.filp)->i_mapping;
2151 gfp = mapping_gfp_mask(mapping);
2152 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2153 gfp &= ~(__GFP_IO | __GFP_WAIT);
2156 for (i = 0; i < page_count; i++) {
2157 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2159 i915_gem_shrink(dev_priv,
2162 I915_SHRINK_UNBOUND |
2163 I915_SHRINK_PURGEABLE);
2164 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2167 /* We've tried hard to allocate the memory by reaping
2168 * our own buffer, now let the real VM do its job and
2169 * go down in flames if truly OOM.
2171 i915_gem_shrink_all(dev_priv);
2172 page = shmem_read_mapping_page(mapping, i);
2176 #ifdef CONFIG_SWIOTLB
2177 if (swiotlb_nr_tbl()) {
2179 sg_set_page(sg, page, PAGE_SIZE, 0);
2184 if (!i || page_to_pfn(page) != last_pfn + 1) {
2188 sg_set_page(sg, page, PAGE_SIZE, 0);
2190 sg->length += PAGE_SIZE;
2192 last_pfn = page_to_pfn(page);
2194 /* Check that the i965g/gm workaround works. */
2195 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2197 #ifdef CONFIG_SWIOTLB
2198 if (!swiotlb_nr_tbl())
2203 if (i915_gem_object_needs_bit17_swizzle(obj))
2204 i915_gem_object_do_bit_17_swizzle(obj);
2210 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2211 page_cache_release(sg_page_iter_page(&sg_iter));
2215 /* shmemfs first checks if there is enough memory to allocate the page
2216 * and reports ENOSPC should there be insufficient, along with the usual
2217 * ENOMEM for a genuine allocation failure.
2219 * We use ENOSPC in our driver to mean that we have run out of aperture
2220 * space and so want to translate the error from shmemfs back to our
2221 * usual understanding of ENOMEM.
2223 if (PTR_ERR(page) == -ENOSPC)
2226 return PTR_ERR(page);
2229 /* Ensure that the associated pages are gathered from the backing storage
2230 * and pinned into our object. i915_gem_object_get_pages() may be called
2231 * multiple times before they are released by a single call to
2232 * i915_gem_object_put_pages() - once the pages are no longer referenced
2233 * either as a result of memory pressure (reaping pages under the shrinker)
2234 * or as the object is itself released.
2237 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2239 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2240 const struct drm_i915_gem_object_ops *ops = obj->ops;
2246 if (obj->madv != I915_MADV_WILLNEED) {
2247 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2251 BUG_ON(obj->pages_pin_count);
2253 ret = ops->get_pages(obj);
2257 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2262 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2263 struct intel_engine_cs *ring)
2265 u32 seqno = intel_ring_get_seqno(ring);
2267 BUG_ON(ring == NULL);
2268 if (obj->ring != ring && obj->last_write_seqno) {
2269 /* Keep the seqno relative to the current ring */
2270 obj->last_write_seqno = seqno;
2274 /* Add a reference if we're newly entering the active list. */
2276 drm_gem_object_reference(&obj->base);
2280 list_move_tail(&obj->ring_list, &ring->active_list);
2282 obj->last_read_seqno = seqno;
2285 void i915_vma_move_to_active(struct i915_vma *vma,
2286 struct intel_engine_cs *ring)
2288 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2289 return i915_gem_object_move_to_active(vma->obj, ring);
2293 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2295 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2296 struct i915_address_space *vm;
2297 struct i915_vma *vma;
2299 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2300 BUG_ON(!obj->active);
2302 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2303 vma = i915_gem_obj_to_vma(obj, vm);
2304 if (vma && !list_empty(&vma->mm_list))
2305 list_move_tail(&vma->mm_list, &vm->inactive_list);
2308 intel_fb_obj_flush(obj, true);
2310 list_del_init(&obj->ring_list);
2313 obj->last_read_seqno = 0;
2314 obj->last_write_seqno = 0;
2315 obj->base.write_domain = 0;
2317 obj->last_fenced_seqno = 0;
2320 drm_gem_object_unreference(&obj->base);
2322 WARN_ON(i915_verify_lists(dev));
2326 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2328 struct intel_engine_cs *ring = obj->ring;
2333 if (i915_seqno_passed(ring->get_seqno(ring, true),
2334 obj->last_read_seqno))
2335 i915_gem_object_move_to_inactive(obj);
2339 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_engine_cs *ring;
2345 /* Carefully retire all requests without writing to the rings */
2346 for_each_ring(ring, dev_priv, i) {
2347 ret = intel_ring_idle(ring);
2351 i915_gem_retire_requests(dev);
2353 /* Finally reset hw state */
2354 for_each_ring(ring, dev_priv, i) {
2355 intel_ring_init_seqno(ring, seqno);
2357 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2358 ring->semaphore.sync_seqno[j] = 0;
2364 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2372 /* HWS page needs to be set less than what we
2373 * will inject to ring
2375 ret = i915_gem_init_seqno(dev, seqno - 1);
2379 /* Carefully set the last_seqno value so that wrap
2380 * detection still works
2382 dev_priv->next_seqno = seqno;
2383 dev_priv->last_seqno = seqno - 1;
2384 if (dev_priv->last_seqno == 0)
2385 dev_priv->last_seqno--;
2391 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2395 /* reserve 0 for non-seqno */
2396 if (dev_priv->next_seqno == 0) {
2397 int ret = i915_gem_init_seqno(dev, 0);
2401 dev_priv->next_seqno = 1;
2404 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2408 int __i915_add_request(struct intel_engine_cs *ring,
2409 struct drm_file *file,
2410 struct drm_i915_gem_object *obj,
2413 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2414 struct drm_i915_gem_request *request;
2415 struct intel_ringbuffer *ringbuf;
2416 u32 request_ring_position, request_start;
2419 request = ring->preallocated_lazy_request;
2420 if (WARN_ON(request == NULL))
2423 if (i915.enable_execlists) {
2424 struct intel_context *ctx = request->ctx;
2425 ringbuf = ctx->engine[ring->id].ringbuf;
2427 ringbuf = ring->buffer;
2429 request_start = intel_ring_get_tail(ringbuf);
2431 * Emit any outstanding flushes - execbuf can fail to emit the flush
2432 * after having emitted the batchbuffer command. Hence we need to fix
2433 * things up similar to emitting the lazy request. The difference here
2434 * is that the flush _must_ happen before the next request, no matter
2437 if (i915.enable_execlists) {
2438 ret = logical_ring_flush_all_caches(ringbuf);
2442 ret = intel_ring_flush_all_caches(ring);
2447 /* Record the position of the start of the request so that
2448 * should we detect the updated seqno part-way through the
2449 * GPU processing the request, we never over-estimate the
2450 * position of the head.
2452 request_ring_position = intel_ring_get_tail(ringbuf);
2454 if (i915.enable_execlists) {
2455 ret = ring->emit_request(ringbuf);
2459 ret = ring->add_request(ring);
2464 request->seqno = intel_ring_get_seqno(ring);
2465 request->ring = ring;
2466 request->head = request_start;
2467 request->tail = request_ring_position;
2469 /* Whilst this request exists, batch_obj will be on the
2470 * active_list, and so will hold the active reference. Only when this
2471 * request is retired will the the batch_obj be moved onto the
2472 * inactive_list and lose its active reference. Hence we do not need
2473 * to explicitly hold another reference here.
2475 request->batch_obj = obj;
2477 if (!i915.enable_execlists) {
2478 /* Hold a reference to the current context so that we can inspect
2479 * it later in case a hangcheck error event fires.
2481 request->ctx = ring->last_context;
2483 i915_gem_context_reference(request->ctx);
2486 request->emitted_jiffies = jiffies;
2487 list_add_tail(&request->list, &ring->request_list);
2488 request->file_priv = NULL;
2491 struct drm_i915_file_private *file_priv = file->driver_priv;
2493 spin_lock(&file_priv->mm.lock);
2494 request->file_priv = file_priv;
2495 list_add_tail(&request->client_list,
2496 &file_priv->mm.request_list);
2497 spin_unlock(&file_priv->mm.lock);
2500 trace_i915_gem_request_add(ring, request->seqno);
2501 ring->outstanding_lazy_seqno = 0;
2502 ring->preallocated_lazy_request = NULL;
2504 i915_queue_hangcheck(ring->dev);
2506 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2507 queue_delayed_work(dev_priv->wq,
2508 &dev_priv->mm.retire_work,
2509 round_jiffies_up_relative(HZ));
2510 intel_mark_busy(dev_priv->dev);
2513 *out_seqno = request->seqno;
2518 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2520 struct drm_i915_file_private *file_priv = request->file_priv;
2525 spin_lock(&file_priv->mm.lock);
2526 list_del(&request->client_list);
2527 request->file_priv = NULL;
2528 spin_unlock(&file_priv->mm.lock);
2531 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2532 const struct intel_context *ctx)
2534 unsigned long elapsed;
2536 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2538 if (ctx->hang_stats.banned)
2541 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2542 if (!i915_gem_context_is_default(ctx)) {
2543 DRM_DEBUG("context hanging too fast, banning!\n");
2545 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2546 if (i915_stop_ring_allow_warn(dev_priv))
2547 DRM_ERROR("gpu hanging too fast, banning!\n");
2555 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2556 struct intel_context *ctx,
2559 struct i915_ctx_hang_stats *hs;
2564 hs = &ctx->hang_stats;
2567 hs->banned = i915_context_is_banned(dev_priv, ctx);
2569 hs->guilty_ts = get_seconds();
2571 hs->batch_pending++;
2575 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2577 struct intel_context *ctx = request->ctx;
2579 list_del(&request->list);
2580 i915_gem_request_remove_from_client(request);
2582 if (i915.enable_execlists && ctx) {
2583 struct intel_engine_cs *ring = request->ring;
2585 if (ctx != ring->default_context)
2586 intel_lr_context_unpin(ring, ctx);
2587 i915_gem_context_unreference(ctx);
2592 struct drm_i915_gem_request *
2593 i915_gem_find_active_request(struct intel_engine_cs *ring)
2595 struct drm_i915_gem_request *request;
2596 u32 completed_seqno;
2598 completed_seqno = ring->get_seqno(ring, false);
2600 list_for_each_entry(request, &ring->request_list, list) {
2601 if (i915_seqno_passed(completed_seqno, request->seqno))
2610 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2611 struct intel_engine_cs *ring)
2613 struct drm_i915_gem_request *request;
2616 request = i915_gem_find_active_request(ring);
2618 if (request == NULL)
2621 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2623 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2625 list_for_each_entry_continue(request, &ring->request_list, list)
2626 i915_set_reset_status(dev_priv, request->ctx, false);
2629 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2630 struct intel_engine_cs *ring)
2632 while (!list_empty(&ring->active_list)) {
2633 struct drm_i915_gem_object *obj;
2635 obj = list_first_entry(&ring->active_list,
2636 struct drm_i915_gem_object,
2639 i915_gem_object_move_to_inactive(obj);
2643 * Clear the execlists queue up before freeing the requests, as those
2644 * are the ones that keep the context and ringbuffer backing objects
2647 while (!list_empty(&ring->execlist_queue)) {
2648 struct intel_ctx_submit_request *submit_req;
2650 submit_req = list_first_entry(&ring->execlist_queue,
2651 struct intel_ctx_submit_request,
2653 list_del(&submit_req->execlist_link);
2654 intel_runtime_pm_put(dev_priv);
2655 i915_gem_context_unreference(submit_req->ctx);
2660 * We must free the requests after all the corresponding objects have
2661 * been moved off active lists. Which is the same order as the normal
2662 * retire_requests function does. This is important if object hold
2663 * implicit references on things like e.g. ppgtt address spaces through
2666 while (!list_empty(&ring->request_list)) {
2667 struct drm_i915_gem_request *request;
2669 request = list_first_entry(&ring->request_list,
2670 struct drm_i915_gem_request,
2673 i915_gem_free_request(request);
2676 /* These may not have been flush before the reset, do so now */
2677 kfree(ring->preallocated_lazy_request);
2678 ring->preallocated_lazy_request = NULL;
2679 ring->outstanding_lazy_seqno = 0;
2682 void i915_gem_restore_fences(struct drm_device *dev)
2684 struct drm_i915_private *dev_priv = dev->dev_private;
2687 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2688 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2691 * Commit delayed tiling changes if we have an object still
2692 * attached to the fence, otherwise just clear the fence.
2695 i915_gem_object_update_fence(reg->obj, reg,
2696 reg->obj->tiling_mode);
2698 i915_gem_write_fence(dev, i, NULL);
2703 void i915_gem_reset(struct drm_device *dev)
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_engine_cs *ring;
2710 * Before we free the objects from the requests, we need to inspect
2711 * them for finding the guilty party. As the requests only borrow
2712 * their reference to the objects, the inspection must be done first.
2714 for_each_ring(ring, dev_priv, i)
2715 i915_gem_reset_ring_status(dev_priv, ring);
2717 for_each_ring(ring, dev_priv, i)
2718 i915_gem_reset_ring_cleanup(dev_priv, ring);
2720 i915_gem_context_reset(dev);
2722 i915_gem_restore_fences(dev);
2726 * This function clears the request list as sequence numbers are passed.
2729 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2733 if (list_empty(&ring->request_list))
2736 WARN_ON(i915_verify_lists(ring->dev));
2738 seqno = ring->get_seqno(ring, true);
2740 /* Move any buffers on the active list that are no longer referenced
2741 * by the ringbuffer to the flushing/inactive lists as appropriate,
2742 * before we free the context associated with the requests.
2744 while (!list_empty(&ring->active_list)) {
2745 struct drm_i915_gem_object *obj;
2747 obj = list_first_entry(&ring->active_list,
2748 struct drm_i915_gem_object,
2751 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2754 i915_gem_object_move_to_inactive(obj);
2758 while (!list_empty(&ring->request_list)) {
2759 struct drm_i915_gem_request *request;
2760 struct intel_ringbuffer *ringbuf;
2762 request = list_first_entry(&ring->request_list,
2763 struct drm_i915_gem_request,
2766 if (!i915_seqno_passed(seqno, request->seqno))
2769 trace_i915_gem_request_retire(ring, request->seqno);
2771 /* This is one of the few common intersection points
2772 * between legacy ringbuffer submission and execlists:
2773 * we need to tell them apart in order to find the correct
2774 * ringbuffer to which the request belongs to.
2776 if (i915.enable_execlists) {
2777 struct intel_context *ctx = request->ctx;
2778 ringbuf = ctx->engine[ring->id].ringbuf;
2780 ringbuf = ring->buffer;
2782 /* We know the GPU must have read the request to have
2783 * sent us the seqno + interrupt, so use the position
2784 * of tail of the request to update the last known position
2787 ringbuf->last_retired_head = request->tail;
2789 i915_gem_free_request(request);
2792 if (unlikely(ring->trace_irq_seqno &&
2793 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2794 ring->irq_put(ring);
2795 ring->trace_irq_seqno = 0;
2798 WARN_ON(i915_verify_lists(ring->dev));
2802 i915_gem_retire_requests(struct drm_device *dev)
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_engine_cs *ring;
2809 for_each_ring(ring, dev_priv, i) {
2810 i915_gem_retire_requests_ring(ring);
2811 idle &= list_empty(&ring->request_list);
2812 if (i915.enable_execlists) {
2813 unsigned long flags;
2815 spin_lock_irqsave(&ring->execlist_lock, flags);
2816 idle &= list_empty(&ring->execlist_queue);
2817 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2819 intel_execlists_retire_requests(ring);
2824 mod_delayed_work(dev_priv->wq,
2825 &dev_priv->mm.idle_work,
2826 msecs_to_jiffies(100));
2832 i915_gem_retire_work_handler(struct work_struct *work)
2834 struct drm_i915_private *dev_priv =
2835 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2836 struct drm_device *dev = dev_priv->dev;
2839 /* Come back later if the device is busy... */
2841 if (mutex_trylock(&dev->struct_mutex)) {
2842 idle = i915_gem_retire_requests(dev);
2843 mutex_unlock(&dev->struct_mutex);
2846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2847 round_jiffies_up_relative(HZ));
2851 i915_gem_idle_work_handler(struct work_struct *work)
2853 struct drm_i915_private *dev_priv =
2854 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2856 intel_mark_idle(dev_priv->dev);
2860 * Ensures that an object will eventually get non-busy by flushing any required
2861 * write domains, emitting any outstanding lazy request and retiring and
2862 * completed requests.
2865 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2870 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2874 i915_gem_retire_requests_ring(obj->ring);
2881 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2882 * @DRM_IOCTL_ARGS: standard ioctl arguments
2884 * Returns 0 if successful, else an error is returned with the remaining time in
2885 * the timeout parameter.
2886 * -ETIME: object is still busy after timeout
2887 * -ERESTARTSYS: signal interrupted the wait
2888 * -ENONENT: object doesn't exist
2889 * Also possible, but rare:
2890 * -EAGAIN: GPU wedged
2892 * -ENODEV: Internal IRQ fail
2893 * -E?: The add request failed
2895 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2896 * non-zero timeout parameter the wait ioctl will wait for the given number of
2897 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2898 * without holding struct_mutex the object may become re-busied before this
2899 * function completes. A similar but shorter * race condition exists in the busy
2903 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906 struct drm_i915_gem_wait *args = data;
2907 struct drm_i915_gem_object *obj;
2908 struct intel_engine_cs *ring = NULL;
2909 unsigned reset_counter;
2913 if (args->flags != 0)
2916 ret = i915_mutex_lock_interruptible(dev);
2920 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2921 if (&obj->base == NULL) {
2922 mutex_unlock(&dev->struct_mutex);
2926 /* Need to make sure the object gets inactive eventually. */
2927 ret = i915_gem_object_flush_active(obj);
2932 seqno = obj->last_read_seqno;
2939 /* Do this after OLR check to make sure we make forward progress polling
2940 * on this IOCTL with a timeout <=0 (like busy ioctl)
2942 if (args->timeout_ns <= 0) {
2947 drm_gem_object_unreference(&obj->base);
2948 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2949 mutex_unlock(&dev->struct_mutex);
2951 return __i915_wait_seqno(ring, seqno, reset_counter, true,
2952 &args->timeout_ns, file->driver_priv);
2955 drm_gem_object_unreference(&obj->base);
2956 mutex_unlock(&dev->struct_mutex);
2961 * i915_gem_object_sync - sync an object to a ring.
2963 * @obj: object which may be in use on another ring.
2964 * @to: ring we wish to use the object on. May be NULL.
2966 * This code is meant to abstract object synchronization with the GPU.
2967 * Calling with NULL implies synchronizing the object with the CPU
2968 * rather than a particular GPU ring.
2970 * Returns 0 if successful, else propagates up the lower layer error.
2973 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2974 struct intel_engine_cs *to)
2976 struct intel_engine_cs *from = obj->ring;
2980 if (from == NULL || to == from)
2983 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2984 return i915_gem_object_wait_rendering(obj, false);
2986 idx = intel_ring_sync_index(from, to);
2988 seqno = obj->last_read_seqno;
2989 /* Optimization: Avoid semaphore sync when we are sure we already
2990 * waited for an object with higher seqno */
2991 if (seqno <= from->semaphore.sync_seqno[idx])
2994 ret = i915_gem_check_olr(obj->ring, seqno);
2998 trace_i915_gem_ring_sync_to(from, to, seqno);
2999 ret = to->semaphore.sync_to(to, from, seqno);
3001 /* We use last_read_seqno because sync_to()
3002 * might have just caused seqno wrap under
3005 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
3010 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3012 u32 old_write_domain, old_read_domains;
3014 /* Force a pagefault for domain tracking on next user access */
3015 i915_gem_release_mmap(obj);
3017 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3020 /* Wait for any direct GTT access to complete */
3023 old_read_domains = obj->base.read_domains;
3024 old_write_domain = obj->base.write_domain;
3026 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3027 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3029 trace_i915_gem_object_change_domain(obj,
3034 int i915_vma_unbind(struct i915_vma *vma)
3036 struct drm_i915_gem_object *obj = vma->obj;
3037 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3040 if (list_empty(&vma->vma_link))
3043 if (!drm_mm_node_allocated(&vma->node)) {
3044 i915_gem_vma_destroy(vma);
3051 BUG_ON(obj->pages == NULL);
3053 ret = i915_gem_object_finish_gpu(obj);
3056 /* Continue on if we fail due to EIO, the GPU is hung so we
3057 * should be safe and we need to cleanup or else we might
3058 * cause memory corruption through use-after-free.
3061 /* Throw away the active reference before moving to the unbound list */
3062 i915_gem_object_retire(obj);
3064 if (i915_is_ggtt(vma->vm)) {
3065 i915_gem_object_finish_gtt(obj);
3067 /* release the fence reg _after_ flushing */
3068 ret = i915_gem_object_put_fence(obj);
3073 trace_i915_vma_unbind(vma);
3075 vma->unbind_vma(vma);
3077 list_del_init(&vma->mm_list);
3078 if (i915_is_ggtt(vma->vm))
3079 obj->map_and_fenceable = false;
3081 drm_mm_remove_node(&vma->node);
3082 i915_gem_vma_destroy(vma);
3084 /* Since the unbound list is global, only move to that list if
3085 * no more VMAs exist. */
3086 if (list_empty(&obj->vma_list)) {
3087 i915_gem_gtt_finish_object(obj);
3088 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3091 /* And finally now the object is completely decoupled from this vma,
3092 * we can drop its hold on the backing storage and allow it to be
3093 * reaped by the shrinker.
3095 i915_gem_object_unpin_pages(obj);
3100 int i915_gpu_idle(struct drm_device *dev)
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_engine_cs *ring;
3106 /* Flush everything onto the inactive list. */
3107 for_each_ring(ring, dev_priv, i) {
3108 if (!i915.enable_execlists) {
3109 ret = i915_switch_context(ring, ring->default_context);
3114 ret = intel_ring_idle(ring);
3122 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3123 struct drm_i915_gem_object *obj)
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3127 int fence_pitch_shift;
3129 if (INTEL_INFO(dev)->gen >= 6) {
3130 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3131 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3133 fence_reg = FENCE_REG_965_0;
3134 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3137 fence_reg += reg * 8;
3139 /* To w/a incoherency with non-atomic 64-bit register updates,
3140 * we split the 64-bit update into two 32-bit writes. In order
3141 * for a partial fence not to be evaluated between writes, we
3142 * precede the update with write to turn off the fence register,
3143 * and only enable the fence as the last step.
3145 * For extra levels of paranoia, we make sure each step lands
3146 * before applying the next step.
3148 I915_WRITE(fence_reg, 0);
3149 POSTING_READ(fence_reg);
3152 u32 size = i915_gem_obj_ggtt_size(obj);
3155 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3157 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3158 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3159 if (obj->tiling_mode == I915_TILING_Y)
3160 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3161 val |= I965_FENCE_REG_VALID;
3163 I915_WRITE(fence_reg + 4, val >> 32);
3164 POSTING_READ(fence_reg + 4);
3166 I915_WRITE(fence_reg + 0, val);
3167 POSTING_READ(fence_reg);
3169 I915_WRITE(fence_reg + 4, 0);
3170 POSTING_READ(fence_reg + 4);
3174 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3175 struct drm_i915_gem_object *obj)
3177 struct drm_i915_private *dev_priv = dev->dev_private;
3181 u32 size = i915_gem_obj_ggtt_size(obj);
3185 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3186 (size & -size) != size ||
3187 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3188 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3189 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3191 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3196 /* Note: pitch better be a power of two tile widths */
3197 pitch_val = obj->stride / tile_width;
3198 pitch_val = ffs(pitch_val) - 1;
3200 val = i915_gem_obj_ggtt_offset(obj);
3201 if (obj->tiling_mode == I915_TILING_Y)
3202 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3203 val |= I915_FENCE_SIZE_BITS(size);
3204 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3205 val |= I830_FENCE_REG_VALID;
3210 reg = FENCE_REG_830_0 + reg * 4;
3212 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3214 I915_WRITE(reg, val);
3218 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3219 struct drm_i915_gem_object *obj)
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3225 u32 size = i915_gem_obj_ggtt_size(obj);
3228 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3229 (size & -size) != size ||
3230 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3231 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3232 i915_gem_obj_ggtt_offset(obj), size);
3234 pitch_val = obj->stride / 128;
3235 pitch_val = ffs(pitch_val) - 1;
3237 val = i915_gem_obj_ggtt_offset(obj);
3238 if (obj->tiling_mode == I915_TILING_Y)
3239 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3240 val |= I830_FENCE_SIZE_BITS(size);
3241 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3242 val |= I830_FENCE_REG_VALID;
3246 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3247 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3250 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3252 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3255 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3256 struct drm_i915_gem_object *obj)
3258 struct drm_i915_private *dev_priv = dev->dev_private;
3260 /* Ensure that all CPU reads are completed before installing a fence
3261 * and all writes before removing the fence.
3263 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3266 WARN(obj && (!obj->stride || !obj->tiling_mode),
3267 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3268 obj->stride, obj->tiling_mode);
3270 switch (INTEL_INFO(dev)->gen) {
3276 case 4: i965_write_fence_reg(dev, reg, obj); break;
3277 case 3: i915_write_fence_reg(dev, reg, obj); break;
3278 case 2: i830_write_fence_reg(dev, reg, obj); break;
3282 /* And similarly be paranoid that no direct access to this region
3283 * is reordered to before the fence is installed.
3285 if (i915_gem_object_needs_mb(obj))
3289 static inline int fence_number(struct drm_i915_private *dev_priv,
3290 struct drm_i915_fence_reg *fence)
3292 return fence - dev_priv->fence_regs;
3295 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3296 struct drm_i915_fence_reg *fence,
3299 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3300 int reg = fence_number(dev_priv, fence);
3302 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3305 obj->fence_reg = reg;
3307 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3309 obj->fence_reg = I915_FENCE_REG_NONE;
3311 list_del_init(&fence->lru_list);
3313 obj->fence_dirty = false;
3317 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3319 if (obj->last_fenced_seqno) {
3320 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3324 obj->last_fenced_seqno = 0;
3331 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3333 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3334 struct drm_i915_fence_reg *fence;
3337 ret = i915_gem_object_wait_fence(obj);
3341 if (obj->fence_reg == I915_FENCE_REG_NONE)
3344 fence = &dev_priv->fence_regs[obj->fence_reg];
3346 if (WARN_ON(fence->pin_count))
3349 i915_gem_object_fence_lost(obj);
3350 i915_gem_object_update_fence(obj, fence, false);
3355 static struct drm_i915_fence_reg *
3356 i915_find_fence_reg(struct drm_device *dev)
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct drm_i915_fence_reg *reg, *avail;
3362 /* First try to find a free reg */
3364 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3365 reg = &dev_priv->fence_regs[i];
3369 if (!reg->pin_count)
3376 /* None available, try to steal one or wait for a user to finish */
3377 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3385 /* Wait for completion of pending flips which consume fences */
3386 if (intel_has_pending_fb_unpin(dev))
3387 return ERR_PTR(-EAGAIN);
3389 return ERR_PTR(-EDEADLK);
3393 * i915_gem_object_get_fence - set up fencing for an object
3394 * @obj: object to map through a fence reg
3396 * When mapping objects through the GTT, userspace wants to be able to write
3397 * to them without having to worry about swizzling if the object is tiled.
3398 * This function walks the fence regs looking for a free one for @obj,
3399 * stealing one if it can't find any.
3401 * It then sets up the reg based on the object's properties: address, pitch
3402 * and tiling format.
3404 * For an untiled surface, this removes any existing fence.
3407 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3409 struct drm_device *dev = obj->base.dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 bool enable = obj->tiling_mode != I915_TILING_NONE;
3412 struct drm_i915_fence_reg *reg;
3415 /* Have we updated the tiling parameters upon the object and so
3416 * will need to serialise the write to the associated fence register?
3418 if (obj->fence_dirty) {
3419 ret = i915_gem_object_wait_fence(obj);
3424 /* Just update our place in the LRU if our fence is getting reused. */
3425 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3426 reg = &dev_priv->fence_regs[obj->fence_reg];
3427 if (!obj->fence_dirty) {
3428 list_move_tail(®->lru_list,
3429 &dev_priv->mm.fence_list);
3432 } else if (enable) {
3433 if (WARN_ON(!obj->map_and_fenceable))
3436 reg = i915_find_fence_reg(dev);
3438 return PTR_ERR(reg);
3441 struct drm_i915_gem_object *old = reg->obj;
3443 ret = i915_gem_object_wait_fence(old);
3447 i915_gem_object_fence_lost(old);
3452 i915_gem_object_update_fence(obj, reg, enable);
3457 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3458 unsigned long cache_level)
3460 struct drm_mm_node *gtt_space = &vma->node;
3461 struct drm_mm_node *other;
3464 * On some machines we have to be careful when putting differing types
3465 * of snoopable memory together to avoid the prefetcher crossing memory
3466 * domains and dying. During vm initialisation, we decide whether or not
3467 * these constraints apply and set the drm_mm.color_adjust
3470 if (vma->vm->mm.color_adjust == NULL)
3473 if (!drm_mm_node_allocated(gtt_space))
3476 if (list_empty(>t_space->node_list))
3479 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3480 if (other->allocated && !other->hole_follows && other->color != cache_level)
3483 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3484 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3491 * Finds free space in the GTT aperture and binds the object there.
3493 static struct i915_vma *
3494 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3495 struct i915_address_space *vm,
3499 struct drm_device *dev = obj->base.dev;
3500 struct drm_i915_private *dev_priv = dev->dev_private;
3501 u32 size, fence_size, fence_alignment, unfenced_alignment;
3502 unsigned long start =
3503 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3505 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3506 struct i915_vma *vma;
3509 fence_size = i915_gem_get_gtt_size(dev,
3512 fence_alignment = i915_gem_get_gtt_alignment(dev,
3514 obj->tiling_mode, true);
3515 unfenced_alignment =
3516 i915_gem_get_gtt_alignment(dev,
3518 obj->tiling_mode, false);
3521 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3523 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3524 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3525 return ERR_PTR(-EINVAL);
3528 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3530 /* If the object is bigger than the entire aperture, reject it early
3531 * before evicting everything in a vain attempt to find space.
3533 if (obj->base.size > end) {
3534 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3536 flags & PIN_MAPPABLE ? "mappable" : "total",
3538 return ERR_PTR(-E2BIG);
3541 ret = i915_gem_object_get_pages(obj);
3543 return ERR_PTR(ret);
3545 i915_gem_object_pin_pages(obj);
3547 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3552 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3556 DRM_MM_SEARCH_DEFAULT,
3557 DRM_MM_CREATE_DEFAULT);
3559 ret = i915_gem_evict_something(dev, vm, size, alignment,
3568 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3570 goto err_remove_node;
3573 ret = i915_gem_gtt_prepare_object(obj);
3575 goto err_remove_node;
3577 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3578 list_add_tail(&vma->mm_list, &vm->inactive_list);
3580 trace_i915_vma_bind(vma, flags);
3581 vma->bind_vma(vma, obj->cache_level,
3582 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3587 drm_mm_remove_node(&vma->node);
3589 i915_gem_vma_destroy(vma);
3592 i915_gem_object_unpin_pages(obj);
3597 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3600 /* If we don't have a page list set up, then we're not pinned
3601 * to GPU, and we can ignore the cache flush because it'll happen
3602 * again at bind time.
3604 if (obj->pages == NULL)
3608 * Stolen memory is always coherent with the GPU as it is explicitly
3609 * marked as wc by the system, or the system is cache-coherent.
3611 if (obj->stolen || obj->phys_handle)
3614 /* If the GPU is snooping the contents of the CPU cache,
3615 * we do not need to manually clear the CPU cache lines. However,
3616 * the caches are only snooped when the render cache is
3617 * flushed/invalidated. As we always have to emit invalidations
3618 * and flushes when moving into and out of the RENDER domain, correct
3619 * snooping behaviour occurs naturally as the result of our domain
3622 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3625 trace_i915_gem_object_clflush(obj);
3626 drm_clflush_sg(obj->pages);
3631 /** Flushes the GTT write domain for the object if it's dirty. */
3633 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3635 uint32_t old_write_domain;
3637 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3640 /* No actual flushing is required for the GTT write domain. Writes
3641 * to it immediately go to main memory as far as we know, so there's
3642 * no chipset flush. It also doesn't land in render cache.
3644 * However, we do have to enforce the order so that all writes through
3645 * the GTT land before any writes to the device, such as updates to
3650 old_write_domain = obj->base.write_domain;
3651 obj->base.write_domain = 0;
3653 intel_fb_obj_flush(obj, false);
3655 trace_i915_gem_object_change_domain(obj,
3656 obj->base.read_domains,
3660 /** Flushes the CPU write domain for the object if it's dirty. */
3662 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3665 uint32_t old_write_domain;
3667 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3670 if (i915_gem_clflush_object(obj, force))
3671 i915_gem_chipset_flush(obj->base.dev);
3673 old_write_domain = obj->base.write_domain;
3674 obj->base.write_domain = 0;
3676 intel_fb_obj_flush(obj, false);
3678 trace_i915_gem_object_change_domain(obj,
3679 obj->base.read_domains,
3684 * Moves a single object to the GTT read, and possibly write domain.
3686 * This function returns when the move is complete, including waiting on
3690 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3692 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3693 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3694 uint32_t old_write_domain, old_read_domains;
3697 /* Not valid to be called on unbound objects. */
3701 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3704 ret = i915_gem_object_wait_rendering(obj, !write);
3708 i915_gem_object_retire(obj);
3709 i915_gem_object_flush_cpu_write_domain(obj, false);
3711 /* Serialise direct access to this object with the barriers for
3712 * coherent writes from the GPU, by effectively invalidating the
3713 * GTT domain upon first access.
3715 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3718 old_write_domain = obj->base.write_domain;
3719 old_read_domains = obj->base.read_domains;
3721 /* It should now be out of any other write domains, and we can update
3722 * the domain values for our changes.
3724 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3725 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3727 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3728 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3733 intel_fb_obj_invalidate(obj, NULL);
3735 trace_i915_gem_object_change_domain(obj,
3739 /* And bump the LRU for this access */
3740 if (i915_gem_object_is_inactive(obj))
3741 list_move_tail(&vma->mm_list,
3742 &dev_priv->gtt.base.inactive_list);
3747 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3748 enum i915_cache_level cache_level)
3750 struct drm_device *dev = obj->base.dev;
3751 struct i915_vma *vma, *next;
3754 if (obj->cache_level == cache_level)
3757 if (i915_gem_obj_is_pinned(obj)) {
3758 DRM_DEBUG("can not change the cache level of pinned objects\n");
3762 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3763 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3764 ret = i915_vma_unbind(vma);
3770 if (i915_gem_obj_bound_any(obj)) {
3771 ret = i915_gem_object_finish_gpu(obj);
3775 i915_gem_object_finish_gtt(obj);
3777 /* Before SandyBridge, you could not use tiling or fence
3778 * registers with snooped memory, so relinquish any fences
3779 * currently pointing to our region in the aperture.
3781 if (INTEL_INFO(dev)->gen < 6) {
3782 ret = i915_gem_object_put_fence(obj);
3787 list_for_each_entry(vma, &obj->vma_list, vma_link)
3788 if (drm_mm_node_allocated(&vma->node))
3789 vma->bind_vma(vma, cache_level,
3790 vma->bound & GLOBAL_BIND);
3793 list_for_each_entry(vma, &obj->vma_list, vma_link)
3794 vma->node.color = cache_level;
3795 obj->cache_level = cache_level;
3797 if (cpu_write_needs_clflush(obj)) {
3798 u32 old_read_domains, old_write_domain;
3800 /* If we're coming from LLC cached, then we haven't
3801 * actually been tracking whether the data is in the
3802 * CPU cache or not, since we only allow one bit set
3803 * in obj->write_domain and have been skipping the clflushes.
3804 * Just set it to the CPU cache for now.
3806 i915_gem_object_retire(obj);
3807 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3809 old_read_domains = obj->base.read_domains;
3810 old_write_domain = obj->base.write_domain;
3812 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3813 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3815 trace_i915_gem_object_change_domain(obj,
3823 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3824 struct drm_file *file)
3826 struct drm_i915_gem_caching *args = data;
3827 struct drm_i915_gem_object *obj;
3830 ret = i915_mutex_lock_interruptible(dev);
3834 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3835 if (&obj->base == NULL) {
3840 switch (obj->cache_level) {
3841 case I915_CACHE_LLC:
3842 case I915_CACHE_L3_LLC:
3843 args->caching = I915_CACHING_CACHED;
3847 args->caching = I915_CACHING_DISPLAY;
3851 args->caching = I915_CACHING_NONE;
3855 drm_gem_object_unreference(&obj->base);
3857 mutex_unlock(&dev->struct_mutex);
3861 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3862 struct drm_file *file)
3864 struct drm_i915_gem_caching *args = data;
3865 struct drm_i915_gem_object *obj;
3866 enum i915_cache_level level;
3869 switch (args->caching) {
3870 case I915_CACHING_NONE:
3871 level = I915_CACHE_NONE;
3873 case I915_CACHING_CACHED:
3874 level = I915_CACHE_LLC;
3876 case I915_CACHING_DISPLAY:
3877 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3883 ret = i915_mutex_lock_interruptible(dev);
3887 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3888 if (&obj->base == NULL) {
3893 ret = i915_gem_object_set_cache_level(obj, level);
3895 drm_gem_object_unreference(&obj->base);
3897 mutex_unlock(&dev->struct_mutex);
3901 static bool is_pin_display(struct drm_i915_gem_object *obj)
3903 struct i915_vma *vma;
3905 vma = i915_gem_obj_to_ggtt(obj);
3909 /* There are 3 sources that pin objects:
3910 * 1. The display engine (scanouts, sprites, cursors);
3911 * 2. Reservations for execbuffer;
3914 * We can ignore reservations as we hold the struct_mutex and
3915 * are only called outside of the reservation path. The user
3916 * can only increment pin_count once, and so if after
3917 * subtracting the potential reference by the user, any pin_count
3918 * remains, it must be due to another use by the display engine.
3920 return vma->pin_count - !!obj->user_pin_count;
3924 * Prepare buffer for display plane (scanout, cursors, etc).
3925 * Can be called from an uninterruptible phase (modesetting) and allows
3926 * any flushes to be pipelined (for pageflips).
3929 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3931 struct intel_engine_cs *pipelined)
3933 u32 old_read_domains, old_write_domain;
3934 bool was_pin_display;
3937 if (pipelined != obj->ring) {
3938 ret = i915_gem_object_sync(obj, pipelined);
3943 /* Mark the pin_display early so that we account for the
3944 * display coherency whilst setting up the cache domains.
3946 was_pin_display = obj->pin_display;
3947 obj->pin_display = true;
3949 /* The display engine is not coherent with the LLC cache on gen6. As
3950 * a result, we make sure that the pinning that is about to occur is
3951 * done with uncached PTEs. This is lowest common denominator for all
3954 * However for gen6+, we could do better by using the GFDT bit instead
3955 * of uncaching, which would allow us to flush all the LLC-cached data
3956 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3958 ret = i915_gem_object_set_cache_level(obj,
3959 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3961 goto err_unpin_display;
3963 /* As the user may map the buffer once pinned in the display plane
3964 * (e.g. libkms for the bootup splash), we have to ensure that we
3965 * always use map_and_fenceable for all scanout buffers.
3967 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3969 goto err_unpin_display;
3971 i915_gem_object_flush_cpu_write_domain(obj, true);
3973 old_write_domain = obj->base.write_domain;
3974 old_read_domains = obj->base.read_domains;
3976 /* It should now be out of any other write domains, and we can update
3977 * the domain values for our changes.
3979 obj->base.write_domain = 0;
3980 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3982 trace_i915_gem_object_change_domain(obj,
3989 WARN_ON(was_pin_display != is_pin_display(obj));
3990 obj->pin_display = was_pin_display;
3995 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3997 i915_gem_object_ggtt_unpin(obj);
3998 obj->pin_display = is_pin_display(obj);
4002 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4006 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4009 ret = i915_gem_object_wait_rendering(obj, false);
4013 /* Ensure that we invalidate the GPU's caches and TLBs. */
4014 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4019 * Moves a single object to the CPU read, and possibly write domain.
4021 * This function returns when the move is complete, including waiting on
4025 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4027 uint32_t old_write_domain, old_read_domains;
4030 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4033 ret = i915_gem_object_wait_rendering(obj, !write);
4037 i915_gem_object_retire(obj);
4038 i915_gem_object_flush_gtt_write_domain(obj);
4040 old_write_domain = obj->base.write_domain;
4041 old_read_domains = obj->base.read_domains;
4043 /* Flush the CPU cache if it's still invalid. */
4044 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4045 i915_gem_clflush_object(obj, false);
4047 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4050 /* It should now be out of any other write domains, and we can update
4051 * the domain values for our changes.
4053 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4055 /* If we're writing through the CPU, then the GPU read domains will
4056 * need to be invalidated at next use.
4059 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4060 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4064 intel_fb_obj_invalidate(obj, NULL);
4066 trace_i915_gem_object_change_domain(obj,
4073 /* Throttle our rendering by waiting until the ring has completed our requests
4074 * emitted over 20 msec ago.
4076 * Note that if we were to use the current jiffies each time around the loop,
4077 * we wouldn't escape the function with any frames outstanding if the time to
4078 * render a frame was over 20ms.
4080 * This should get us reasonable parallelism between CPU and GPU but also
4081 * relatively low latency when blocking on a particular request to finish.
4084 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct drm_i915_file_private *file_priv = file->driver_priv;
4088 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4089 struct drm_i915_gem_request *request;
4090 struct intel_engine_cs *ring = NULL;
4091 unsigned reset_counter;
4095 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4099 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4103 spin_lock(&file_priv->mm.lock);
4104 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4105 if (time_after_eq(request->emitted_jiffies, recent_enough))
4108 ring = request->ring;
4109 seqno = request->seqno;
4111 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4112 spin_unlock(&file_priv->mm.lock);
4117 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4119 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4125 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4127 struct drm_i915_gem_object *obj = vma->obj;
4130 vma->node.start & (alignment - 1))
4133 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4136 if (flags & PIN_OFFSET_BIAS &&
4137 vma->node.start < (flags & PIN_OFFSET_MASK))
4144 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4145 struct i915_address_space *vm,
4149 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4150 struct i915_vma *vma;
4154 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4157 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4160 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4163 vma = i915_gem_obj_to_vma(obj, vm);
4165 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4168 if (i915_vma_misplaced(vma, alignment, flags)) {
4169 WARN(vma->pin_count,
4170 "bo is already pinned with incorrect alignment:"
4171 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4172 " obj->map_and_fenceable=%d\n",
4173 i915_gem_obj_offset(obj, vm), alignment,
4174 !!(flags & PIN_MAPPABLE),
4175 obj->map_and_fenceable);
4176 ret = i915_vma_unbind(vma);
4184 bound = vma ? vma->bound : 0;
4185 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4186 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4188 return PTR_ERR(vma);
4191 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4192 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4194 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4195 bool mappable, fenceable;
4196 u32 fence_size, fence_alignment;
4198 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4201 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4206 fenceable = (vma->node.size == fence_size &&
4207 (vma->node.start & (fence_alignment - 1)) == 0);
4209 mappable = (vma->node.start + obj->base.size <=
4210 dev_priv->gtt.mappable_end);
4212 obj->map_and_fenceable = mappable && fenceable;
4215 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4218 if (flags & PIN_MAPPABLE)
4219 obj->pin_mappable |= true;
4225 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4227 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4230 BUG_ON(vma->pin_count == 0);
4231 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4233 if (--vma->pin_count == 0)
4234 obj->pin_mappable = false;
4238 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4240 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4241 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4242 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4244 WARN_ON(!ggtt_vma ||
4245 dev_priv->fence_regs[obj->fence_reg].pin_count >
4246 ggtt_vma->pin_count);
4247 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4254 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4256 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4257 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4258 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4259 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4264 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4265 struct drm_file *file)
4267 struct drm_i915_gem_pin *args = data;
4268 struct drm_i915_gem_object *obj;
4271 if (INTEL_INFO(dev)->gen >= 6)
4274 ret = i915_mutex_lock_interruptible(dev);
4278 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4279 if (&obj->base == NULL) {
4284 if (obj->madv != I915_MADV_WILLNEED) {
4285 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4290 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4291 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4297 if (obj->user_pin_count == ULONG_MAX) {
4302 if (obj->user_pin_count == 0) {
4303 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4308 obj->user_pin_count++;
4309 obj->pin_filp = file;
4311 args->offset = i915_gem_obj_ggtt_offset(obj);
4313 drm_gem_object_unreference(&obj->base);
4315 mutex_unlock(&dev->struct_mutex);
4320 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4321 struct drm_file *file)
4323 struct drm_i915_gem_pin *args = data;
4324 struct drm_i915_gem_object *obj;
4327 ret = i915_mutex_lock_interruptible(dev);
4331 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4332 if (&obj->base == NULL) {
4337 if (obj->pin_filp != file) {
4338 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4343 obj->user_pin_count--;
4344 if (obj->user_pin_count == 0) {
4345 obj->pin_filp = NULL;
4346 i915_gem_object_ggtt_unpin(obj);
4350 drm_gem_object_unreference(&obj->base);
4352 mutex_unlock(&dev->struct_mutex);
4357 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4358 struct drm_file *file)
4360 struct drm_i915_gem_busy *args = data;
4361 struct drm_i915_gem_object *obj;
4364 ret = i915_mutex_lock_interruptible(dev);
4368 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4369 if (&obj->base == NULL) {
4374 /* Count all active objects as busy, even if they are currently not used
4375 * by the gpu. Users of this interface expect objects to eventually
4376 * become non-busy without any further actions, therefore emit any
4377 * necessary flushes here.
4379 ret = i915_gem_object_flush_active(obj);
4381 args->busy = obj->active;
4383 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4384 args->busy |= intel_ring_flag(obj->ring) << 16;
4387 drm_gem_object_unreference(&obj->base);
4389 mutex_unlock(&dev->struct_mutex);
4394 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4395 struct drm_file *file_priv)
4397 return i915_gem_ring_throttle(dev, file_priv);
4401 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4402 struct drm_file *file_priv)
4404 struct drm_i915_gem_madvise *args = data;
4405 struct drm_i915_gem_object *obj;
4408 switch (args->madv) {
4409 case I915_MADV_DONTNEED:
4410 case I915_MADV_WILLNEED:
4416 ret = i915_mutex_lock_interruptible(dev);
4420 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4421 if (&obj->base == NULL) {
4426 if (i915_gem_obj_is_pinned(obj)) {
4431 if (obj->madv != __I915_MADV_PURGED)
4432 obj->madv = args->madv;
4434 /* if the object is no longer attached, discard its backing storage */
4435 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4436 i915_gem_object_truncate(obj);
4438 args->retained = obj->madv != __I915_MADV_PURGED;
4441 drm_gem_object_unreference(&obj->base);
4443 mutex_unlock(&dev->struct_mutex);
4447 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4448 const struct drm_i915_gem_object_ops *ops)
4450 INIT_LIST_HEAD(&obj->global_list);
4451 INIT_LIST_HEAD(&obj->ring_list);
4452 INIT_LIST_HEAD(&obj->obj_exec_link);
4453 INIT_LIST_HEAD(&obj->vma_list);
4457 obj->fence_reg = I915_FENCE_REG_NONE;
4458 obj->madv = I915_MADV_WILLNEED;
4460 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4463 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4464 .get_pages = i915_gem_object_get_pages_gtt,
4465 .put_pages = i915_gem_object_put_pages_gtt,
4468 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4471 struct drm_i915_gem_object *obj;
4472 struct address_space *mapping;
4475 obj = i915_gem_object_alloc(dev);
4479 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4480 i915_gem_object_free(obj);
4484 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4485 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4486 /* 965gm cannot relocate objects above 4GiB. */
4487 mask &= ~__GFP_HIGHMEM;
4488 mask |= __GFP_DMA32;
4491 mapping = file_inode(obj->base.filp)->i_mapping;
4492 mapping_set_gfp_mask(mapping, mask);
4494 i915_gem_object_init(obj, &i915_gem_object_ops);
4496 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4497 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4500 /* On some devices, we can have the GPU use the LLC (the CPU
4501 * cache) for about a 10% performance improvement
4502 * compared to uncached. Graphics requests other than
4503 * display scanout are coherent with the CPU in
4504 * accessing this cache. This means in this mode we
4505 * don't need to clflush on the CPU side, and on the
4506 * GPU side we only need to flush internal caches to
4507 * get data visible to the CPU.
4509 * However, we maintain the display planes as UC, and so
4510 * need to rebind when first used as such.
4512 obj->cache_level = I915_CACHE_LLC;
4514 obj->cache_level = I915_CACHE_NONE;
4516 trace_i915_gem_object_create(obj);
4521 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4523 /* If we are the last user of the backing storage (be it shmemfs
4524 * pages or stolen etc), we know that the pages are going to be
4525 * immediately released. In this case, we can then skip copying
4526 * back the contents from the GPU.
4529 if (obj->madv != I915_MADV_WILLNEED)
4532 if (obj->base.filp == NULL)
4535 /* At first glance, this looks racy, but then again so would be
4536 * userspace racing mmap against close. However, the first external
4537 * reference to the filp can only be obtained through the
4538 * i915_gem_mmap_ioctl() which safeguards us against the user
4539 * acquiring such a reference whilst we are in the middle of
4540 * freeing the object.
4542 return atomic_long_read(&obj->base.filp->f_count) == 1;
4545 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4547 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4548 struct drm_device *dev = obj->base.dev;
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 struct i915_vma *vma, *next;
4552 intel_runtime_pm_get(dev_priv);
4554 trace_i915_gem_object_destroy(obj);
4556 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4560 ret = i915_vma_unbind(vma);
4561 if (WARN_ON(ret == -ERESTARTSYS)) {
4562 bool was_interruptible;
4564 was_interruptible = dev_priv->mm.interruptible;
4565 dev_priv->mm.interruptible = false;
4567 WARN_ON(i915_vma_unbind(vma));
4569 dev_priv->mm.interruptible = was_interruptible;
4573 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4574 * before progressing. */
4576 i915_gem_object_unpin_pages(obj);
4578 WARN_ON(obj->frontbuffer_bits);
4580 if (WARN_ON(obj->pages_pin_count))
4581 obj->pages_pin_count = 0;
4582 if (discard_backing_storage(obj))
4583 obj->madv = I915_MADV_DONTNEED;
4584 i915_gem_object_put_pages(obj);
4585 i915_gem_object_free_mmap_offset(obj);
4589 if (obj->base.import_attach)
4590 drm_prime_gem_destroy(&obj->base, NULL);
4592 if (obj->ops->release)
4593 obj->ops->release(obj);
4595 drm_gem_object_release(&obj->base);
4596 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4599 i915_gem_object_free(obj);
4601 intel_runtime_pm_put(dev_priv);
4604 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4605 struct i915_address_space *vm)
4607 struct i915_vma *vma;
4608 list_for_each_entry(vma, &obj->vma_list, vma_link)
4615 void i915_gem_vma_destroy(struct i915_vma *vma)
4617 struct i915_address_space *vm = NULL;
4618 WARN_ON(vma->node.allocated);
4620 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4621 if (!list_empty(&vma->exec_list))
4626 if (!i915_is_ggtt(vm))
4627 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4629 list_del(&vma->vma_link);
4635 i915_gem_stop_ringbuffers(struct drm_device *dev)
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 struct intel_engine_cs *ring;
4641 for_each_ring(ring, dev_priv, i)
4642 dev_priv->gt.stop_ring(ring);
4646 i915_gem_suspend(struct drm_device *dev)
4648 struct drm_i915_private *dev_priv = dev->dev_private;
4651 mutex_lock(&dev->struct_mutex);
4652 ret = i915_gpu_idle(dev);
4656 i915_gem_retire_requests(dev);
4658 /* Under UMS, be paranoid and evict. */
4659 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4660 i915_gem_evict_everything(dev);
4662 i915_gem_stop_ringbuffers(dev);
4663 mutex_unlock(&dev->struct_mutex);
4665 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4666 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4667 flush_delayed_work(&dev_priv->mm.idle_work);
4672 mutex_unlock(&dev->struct_mutex);
4676 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4678 struct drm_device *dev = ring->dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4681 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4684 if (!HAS_L3_DPF(dev) || !remap_info)
4687 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4692 * Note: We do not worry about the concurrent register cacheline hang
4693 * here because no other code should access these registers other than
4694 * at initialization time.
4696 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4698 intel_ring_emit(ring, reg_base + i);
4699 intel_ring_emit(ring, remap_info[i/4]);
4702 intel_ring_advance(ring);
4707 void i915_gem_init_swizzling(struct drm_device *dev)
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4711 if (INTEL_INFO(dev)->gen < 5 ||
4712 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4715 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4716 DISP_TILE_SURFACE_SWIZZLING);
4721 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4723 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4724 else if (IS_GEN7(dev))
4725 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4726 else if (IS_GEN8(dev))
4727 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4733 intel_enable_blt(struct drm_device *dev)
4738 /* The blitter was dysfunctional on early prototypes */
4739 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4740 DRM_INFO("BLT not supported on this pre-production hardware;"
4741 " graphics performance will be degraded.\n");
4748 static void init_unused_ring(struct drm_device *dev, u32 base)
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4752 I915_WRITE(RING_CTL(base), 0);
4753 I915_WRITE(RING_HEAD(base), 0);
4754 I915_WRITE(RING_TAIL(base), 0);
4755 I915_WRITE(RING_START(base), 0);
4758 static void init_unused_rings(struct drm_device *dev)
4761 init_unused_ring(dev, PRB1_BASE);
4762 init_unused_ring(dev, SRB0_BASE);
4763 init_unused_ring(dev, SRB1_BASE);
4764 init_unused_ring(dev, SRB2_BASE);
4765 init_unused_ring(dev, SRB3_BASE);
4766 } else if (IS_GEN2(dev)) {
4767 init_unused_ring(dev, SRB0_BASE);
4768 init_unused_ring(dev, SRB1_BASE);
4769 } else if (IS_GEN3(dev)) {
4770 init_unused_ring(dev, PRB1_BASE);
4771 init_unused_ring(dev, PRB2_BASE);
4775 int i915_gem_init_rings(struct drm_device *dev)
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4781 * At least 830 can leave some of the unused rings
4782 * "active" (ie. head != tail) after resume which
4783 * will prevent c3 entry. Makes sure all unused rings
4786 init_unused_rings(dev);
4788 ret = intel_init_render_ring_buffer(dev);
4793 ret = intel_init_bsd_ring_buffer(dev);
4795 goto cleanup_render_ring;
4798 if (intel_enable_blt(dev)) {
4799 ret = intel_init_blt_ring_buffer(dev);
4801 goto cleanup_bsd_ring;
4804 if (HAS_VEBOX(dev)) {
4805 ret = intel_init_vebox_ring_buffer(dev);
4807 goto cleanup_blt_ring;
4810 if (HAS_BSD2(dev)) {
4811 ret = intel_init_bsd2_ring_buffer(dev);
4813 goto cleanup_vebox_ring;
4816 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4818 goto cleanup_bsd2_ring;
4823 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4825 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4827 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4829 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4830 cleanup_render_ring:
4831 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4837 i915_gem_init_hw(struct drm_device *dev)
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4842 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4845 if (dev_priv->ellc_size)
4846 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4848 if (IS_HASWELL(dev))
4849 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4850 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4852 if (HAS_PCH_NOP(dev)) {
4853 if (IS_IVYBRIDGE(dev)) {
4854 u32 temp = I915_READ(GEN7_MSG_CTL);
4855 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4856 I915_WRITE(GEN7_MSG_CTL, temp);
4857 } else if (INTEL_INFO(dev)->gen >= 7) {
4858 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4859 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4860 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4864 i915_gem_init_swizzling(dev);
4866 ret = dev_priv->gt.init_rings(dev);
4870 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4871 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4874 * XXX: Contexts should only be initialized once. Doing a switch to the
4875 * default context switch however is something we'd like to do after
4876 * reset or thaw (the latter may not actually be necessary for HW, but
4877 * goes with our code better). Context switching requires rings (for
4878 * the do_switch), but before enabling PPGTT. So don't move this.
4880 ret = i915_gem_context_enable(dev_priv);
4881 if (ret && ret != -EIO) {
4882 DRM_ERROR("Context enable failed %d\n", ret);
4883 i915_gem_cleanup_ringbuffer(dev);
4888 ret = i915_ppgtt_init_hw(dev);
4889 if (ret && ret != -EIO) {
4890 DRM_ERROR("PPGTT enable failed %d\n", ret);
4891 i915_gem_cleanup_ringbuffer(dev);
4897 int i915_gem_init(struct drm_device *dev)
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4902 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4903 i915.enable_execlists);
4905 mutex_lock(&dev->struct_mutex);
4907 if (IS_VALLEYVIEW(dev)) {
4908 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4909 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4910 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4911 VLV_GTLC_ALLOWWAKEACK), 10))
4912 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4915 if (!i915.enable_execlists) {
4916 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4917 dev_priv->gt.init_rings = i915_gem_init_rings;
4918 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4919 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4921 dev_priv->gt.do_execbuf = intel_execlists_submission;
4922 dev_priv->gt.init_rings = intel_logical_rings_init;
4923 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4924 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4927 ret = i915_gem_init_userptr(dev);
4929 mutex_unlock(&dev->struct_mutex);
4933 i915_gem_init_global_gtt(dev);
4935 ret = i915_gem_context_init(dev);
4937 mutex_unlock(&dev->struct_mutex);
4941 ret = i915_gem_init_hw(dev);
4943 /* Allow ring initialisation to fail by marking the GPU as
4944 * wedged. But we only want to do this where the GPU is angry,
4945 * for all other failure, such as an allocation failure, bail.
4947 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4948 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4951 mutex_unlock(&dev->struct_mutex);
4957 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960 struct intel_engine_cs *ring;
4963 for_each_ring(ring, dev_priv, i)
4964 dev_priv->gt.cleanup_ring(ring);
4968 i915_gem_lastclose(struct drm_device *dev)
4972 if (drm_core_check_feature(dev, DRIVER_MODESET))
4975 ret = i915_gem_suspend(dev);
4977 DRM_ERROR("failed to idle hardware: %d\n", ret);
4981 init_ring_lists(struct intel_engine_cs *ring)
4983 INIT_LIST_HEAD(&ring->active_list);
4984 INIT_LIST_HEAD(&ring->request_list);
4987 void i915_init_vm(struct drm_i915_private *dev_priv,
4988 struct i915_address_space *vm)
4990 if (!i915_is_ggtt(vm))
4991 drm_mm_init(&vm->mm, vm->start, vm->total);
4992 vm->dev = dev_priv->dev;
4993 INIT_LIST_HEAD(&vm->active_list);
4994 INIT_LIST_HEAD(&vm->inactive_list);
4995 INIT_LIST_HEAD(&vm->global_link);
4996 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5000 i915_gem_load(struct drm_device *dev)
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5006 kmem_cache_create("i915_gem_object",
5007 sizeof(struct drm_i915_gem_object), 0,
5011 INIT_LIST_HEAD(&dev_priv->vm_list);
5012 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5014 INIT_LIST_HEAD(&dev_priv->context_list);
5015 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5016 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5017 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5018 for (i = 0; i < I915_NUM_RINGS; i++)
5019 init_ring_lists(&dev_priv->ring[i]);
5020 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5021 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5022 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5023 i915_gem_retire_work_handler);
5024 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5025 i915_gem_idle_work_handler);
5026 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5028 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5029 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5030 I915_WRITE(MI_ARB_STATE,
5031 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5034 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5036 /* Old X drivers will take 0-2 for front, back, depth buffers */
5037 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5038 dev_priv->fence_reg_start = 3;
5040 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5041 dev_priv->num_fence_regs = 32;
5042 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5043 dev_priv->num_fence_regs = 16;
5045 dev_priv->num_fence_regs = 8;
5047 /* Initialize fence registers to zero */
5048 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5049 i915_gem_restore_fences(dev);
5051 i915_gem_detect_bit_6_swizzle(dev);
5052 init_waitqueue_head(&dev_priv->pending_flip_queue);
5054 dev_priv->mm.interruptible = true;
5056 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5057 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5058 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5059 register_shrinker(&dev_priv->mm.shrinker);
5061 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5062 register_oom_notifier(&dev_priv->mm.oom_notifier);
5064 mutex_init(&dev_priv->fb_tracking.lock);
5067 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5069 struct drm_i915_file_private *file_priv = file->driver_priv;
5071 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5073 /* Clean up our request list when the client is going away, so that
5074 * later retire_requests won't dereference our soon-to-be-gone
5077 spin_lock(&file_priv->mm.lock);
5078 while (!list_empty(&file_priv->mm.request_list)) {
5079 struct drm_i915_gem_request *request;
5081 request = list_first_entry(&file_priv->mm.request_list,
5082 struct drm_i915_gem_request,
5084 list_del(&request->client_list);
5085 request->file_priv = NULL;
5087 spin_unlock(&file_priv->mm.lock);
5091 i915_gem_file_idle_work_handler(struct work_struct *work)
5093 struct drm_i915_file_private *file_priv =
5094 container_of(work, typeof(*file_priv), mm.idle_work.work);
5096 atomic_set(&file_priv->rps_wait_boost, false);
5099 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5101 struct drm_i915_file_private *file_priv;
5104 DRM_DEBUG_DRIVER("\n");
5106 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5110 file->driver_priv = file_priv;
5111 file_priv->dev_priv = dev->dev_private;
5112 file_priv->file = file;
5114 spin_lock_init(&file_priv->mm.lock);
5115 INIT_LIST_HEAD(&file_priv->mm.request_list);
5116 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5117 i915_gem_file_idle_work_handler);
5119 ret = i915_gem_context_open(dev, file);
5127 * i915_gem_track_fb - update frontbuffer tracking
5128 * old: current GEM buffer for the frontbuffer slots
5129 * new: new GEM buffer for the frontbuffer slots
5130 * frontbuffer_bits: bitmask of frontbuffer slots
5132 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5133 * from @old and setting them in @new. Both @old and @new can be NULL.
5135 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5136 struct drm_i915_gem_object *new,
5137 unsigned frontbuffer_bits)
5140 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5141 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5142 old->frontbuffer_bits &= ~frontbuffer_bits;
5146 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5147 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5148 new->frontbuffer_bits |= frontbuffer_bits;
5152 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5154 if (!mutex_is_locked(mutex))
5157 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5158 return mutex->owner == task;
5160 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5165 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5167 if (!mutex_trylock(&dev->struct_mutex)) {
5168 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5171 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5181 static int num_vma_bound(struct drm_i915_gem_object *obj)
5183 struct i915_vma *vma;
5186 list_for_each_entry(vma, &obj->vma_list, vma_link)
5187 if (drm_mm_node_allocated(&vma->node))
5193 static unsigned long
5194 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5196 struct drm_i915_private *dev_priv =
5197 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5198 struct drm_device *dev = dev_priv->dev;
5199 struct drm_i915_gem_object *obj;
5200 unsigned long count;
5203 if (!i915_gem_shrinker_lock(dev, &unlock))
5207 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5208 if (obj->pages_pin_count == 0)
5209 count += obj->base.size >> PAGE_SHIFT;
5211 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5212 if (!i915_gem_obj_is_pinned(obj) &&
5213 obj->pages_pin_count == num_vma_bound(obj))
5214 count += obj->base.size >> PAGE_SHIFT;
5218 mutex_unlock(&dev->struct_mutex);
5223 /* All the new VM stuff */
5224 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5225 struct i915_address_space *vm)
5227 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5228 struct i915_vma *vma;
5230 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5232 list_for_each_entry(vma, &o->vma_list, vma_link) {
5234 return vma->node.start;
5237 WARN(1, "%s vma for this object not found.\n",
5238 i915_is_ggtt(vm) ? "global" : "ppgtt");
5242 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5243 struct i915_address_space *vm)
5245 struct i915_vma *vma;
5247 list_for_each_entry(vma, &o->vma_list, vma_link)
5248 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5254 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5256 struct i915_vma *vma;
5258 list_for_each_entry(vma, &o->vma_list, vma_link)
5259 if (drm_mm_node_allocated(&vma->node))
5265 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5266 struct i915_address_space *vm)
5268 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5269 struct i915_vma *vma;
5271 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5273 BUG_ON(list_empty(&o->vma_list));
5275 list_for_each_entry(vma, &o->vma_list, vma_link)
5277 return vma->node.size;
5282 static unsigned long
5283 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5285 struct drm_i915_private *dev_priv =
5286 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5287 struct drm_device *dev = dev_priv->dev;
5288 unsigned long freed;
5291 if (!i915_gem_shrinker_lock(dev, &unlock))
5294 freed = i915_gem_shrink(dev_priv,
5297 I915_SHRINK_UNBOUND |
5298 I915_SHRINK_PURGEABLE);
5299 if (freed < sc->nr_to_scan)
5300 freed += i915_gem_shrink(dev_priv,
5301 sc->nr_to_scan - freed,
5303 I915_SHRINK_UNBOUND);
5305 mutex_unlock(&dev->struct_mutex);
5311 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5313 struct drm_i915_private *dev_priv =
5314 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5315 struct drm_device *dev = dev_priv->dev;
5316 struct drm_i915_gem_object *obj;
5317 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5318 unsigned long pinned, bound, unbound, freed_pages;
5319 bool was_interruptible;
5322 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5323 schedule_timeout_killable(1);
5324 if (fatal_signal_pending(current))
5328 pr_err("Unable to purge GPU memory due lock contention.\n");
5332 was_interruptible = dev_priv->mm.interruptible;
5333 dev_priv->mm.interruptible = false;
5335 freed_pages = i915_gem_shrink_all(dev_priv);
5337 dev_priv->mm.interruptible = was_interruptible;
5339 /* Because we may be allocating inside our own driver, we cannot
5340 * assert that there are no objects with pinned pages that are not
5341 * being pointed to by hardware.
5343 unbound = bound = pinned = 0;
5344 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5345 if (!obj->base.filp) /* not backed by a freeable object */
5348 if (obj->pages_pin_count)
5349 pinned += obj->base.size;
5351 unbound += obj->base.size;
5353 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5354 if (!obj->base.filp)
5357 if (obj->pages_pin_count)
5358 pinned += obj->base.size;
5360 bound += obj->base.size;
5364 mutex_unlock(&dev->struct_mutex);
5366 if (freed_pages || unbound || bound)
5367 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5368 freed_pages << PAGE_SHIFT, pinned);
5369 if (unbound || bound)
5370 pr_err("%lu and %lu bytes still available in the "
5371 "bound and unbound GPU page lists.\n",
5374 *(unsigned long *)ptr += freed_pages;
5378 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5380 struct i915_vma *vma;
5382 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5383 if (vma->vm != i915_obj_to_ggtt(obj))