2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/oom.h>
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
158 struct drm_file *file)
160 struct drm_i915_private *dev_priv = dev->dev_private;
161 struct drm_i915_gem_get_aperture *args = data;
162 struct drm_i915_gem_object *obj;
166 mutex_lock(&dev->struct_mutex);
167 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
168 if (i915_gem_obj_is_pinned(obj))
169 pinned += i915_gem_obj_ggtt_size(obj);
170 mutex_unlock(&dev->struct_mutex);
172 args->aper_size = dev_priv->gtt.base.total;
173 args->aper_available_size = args->aper_size - pinned;
179 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
181 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
182 char *vaddr = obj->phys_handle->vaddr;
184 struct scatterlist *sg;
187 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
190 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
194 page = shmem_read_mapping_page(mapping, i);
196 return PTR_ERR(page);
198 src = kmap_atomic(page);
199 memcpy(vaddr, src, PAGE_SIZE);
200 drm_clflush_virt_range(vaddr, PAGE_SIZE);
203 page_cache_release(page);
207 i915_gem_chipset_flush(obj->base.dev);
209 st = kmalloc(sizeof(*st), GFP_KERNEL);
213 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
220 sg->length = obj->base.size;
222 sg_dma_address(sg) = obj->phys_handle->busaddr;
223 sg_dma_len(sg) = obj->base.size;
226 obj->has_dma_mapping = true;
231 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
235 BUG_ON(obj->madv == __I915_MADV_PURGED);
237 ret = i915_gem_object_set_to_cpu_domain(obj, true);
239 /* In the event of a disaster, abandon all caches and
242 WARN_ON(ret != -EIO);
243 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
246 if (obj->madv == I915_MADV_DONTNEED)
250 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
251 char *vaddr = obj->phys_handle->vaddr;
254 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
258 page = shmem_read_mapping_page(mapping, i);
262 dst = kmap_atomic(page);
263 drm_clflush_virt_range(vaddr, PAGE_SIZE);
264 memcpy(dst, vaddr, PAGE_SIZE);
267 set_page_dirty(page);
268 if (obj->madv == I915_MADV_WILLNEED)
269 mark_page_accessed(page);
270 page_cache_release(page);
276 sg_free_table(obj->pages);
279 obj->has_dma_mapping = false;
283 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
285 drm_pci_free(obj->base.dev, obj->phys_handle);
288 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
289 .get_pages = i915_gem_object_get_pages_phys,
290 .put_pages = i915_gem_object_put_pages_phys,
291 .release = i915_gem_object_release_phys,
295 drop_pages(struct drm_i915_gem_object *obj)
297 struct i915_vma *vma, *next;
300 drm_gem_object_reference(&obj->base);
301 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
302 if (i915_vma_unbind(vma))
305 ret = i915_gem_object_put_pages(obj);
306 drm_gem_object_unreference(&obj->base);
312 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
315 drm_dma_handle_t *phys;
318 if (obj->phys_handle) {
319 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
325 if (obj->madv != I915_MADV_WILLNEED)
328 if (obj->base.filp == NULL)
331 ret = drop_pages(obj);
335 /* create a new object */
336 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
340 obj->phys_handle = phys;
341 obj->ops = &i915_gem_phys_ops;
343 return i915_gem_object_get_pages(obj);
347 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
348 struct drm_i915_gem_pwrite *args,
349 struct drm_file *file_priv)
351 struct drm_device *dev = obj->base.dev;
352 void *vaddr = obj->phys_handle->vaddr + args->offset;
353 char __user *user_data = to_user_ptr(args->data_ptr);
356 /* We manually control the domain here and pretend that it
357 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
359 ret = i915_gem_object_wait_rendering(obj, false);
363 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
364 unsigned long unwritten;
366 /* The physical object once assigned is fixed for the lifetime
367 * of the obj, so we can safely drop the lock and continue
370 mutex_unlock(&dev->struct_mutex);
371 unwritten = copy_from_user(vaddr, user_data, args->size);
372 mutex_lock(&dev->struct_mutex);
377 drm_clflush_virt_range(vaddr, args->size);
378 i915_gem_chipset_flush(dev);
382 void *i915_gem_object_alloc(struct drm_device *dev)
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
388 void i915_gem_object_free(struct drm_i915_gem_object *obj)
390 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
391 kmem_cache_free(dev_priv->slab, obj);
395 i915_gem_create(struct drm_file *file,
396 struct drm_device *dev,
400 struct drm_i915_gem_object *obj;
404 size = roundup(size, PAGE_SIZE);
408 /* Allocate the new object */
409 obj = i915_gem_alloc_object(dev, size);
413 ret = drm_gem_handle_create(file, &obj->base, &handle);
414 /* drop reference from allocate - handle holds it now */
415 drm_gem_object_unreference_unlocked(&obj->base);
424 i915_gem_dumb_create(struct drm_file *file,
425 struct drm_device *dev,
426 struct drm_mode_create_dumb *args)
428 /* have to work out size/pitch and return them */
429 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
430 args->size = args->pitch * args->height;
431 return i915_gem_create(file, dev,
432 args->size, &args->handle);
436 * Creates a new mm object and returns a handle to it.
439 i915_gem_create_ioctl(struct drm_device *dev, void *data,
440 struct drm_file *file)
442 struct drm_i915_gem_create *args = data;
444 return i915_gem_create(file, dev,
445 args->size, &args->handle);
449 __copy_to_user_swizzled(char __user *cpu_vaddr,
450 const char *gpu_vaddr, int gpu_offset,
453 int ret, cpu_offset = 0;
456 int cacheline_end = ALIGN(gpu_offset + 1, 64);
457 int this_length = min(cacheline_end - gpu_offset, length);
458 int swizzled_gpu_offset = gpu_offset ^ 64;
460 ret = __copy_to_user(cpu_vaddr + cpu_offset,
461 gpu_vaddr + swizzled_gpu_offset,
466 cpu_offset += this_length;
467 gpu_offset += this_length;
468 length -= this_length;
475 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
476 const char __user *cpu_vaddr,
479 int ret, cpu_offset = 0;
482 int cacheline_end = ALIGN(gpu_offset + 1, 64);
483 int this_length = min(cacheline_end - gpu_offset, length);
484 int swizzled_gpu_offset = gpu_offset ^ 64;
486 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
487 cpu_vaddr + cpu_offset,
492 cpu_offset += this_length;
493 gpu_offset += this_length;
494 length -= this_length;
501 * Pins the specified object's pages and synchronizes the object with
502 * GPU accesses. Sets needs_clflush to non-zero if the caller should
503 * flush the object from the CPU cache.
505 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
515 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
516 /* If we're not in the cpu read domain, set ourself into the gtt
517 * read domain and manually flush cachelines (if required). This
518 * optimizes for the case when the gpu will dirty the data
519 * anyway again before the next pread happens. */
520 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
522 ret = i915_gem_object_wait_rendering(obj, true);
526 i915_gem_object_retire(obj);
529 ret = i915_gem_object_get_pages(obj);
533 i915_gem_object_pin_pages(obj);
538 /* Per-page copy function for the shmem pread fastpath.
539 * Flushes invalid cachelines before reading the target if
540 * needs_clflush is set. */
542 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
543 char __user *user_data,
544 bool page_do_bit17_swizzling, bool needs_clflush)
549 if (unlikely(page_do_bit17_swizzling))
552 vaddr = kmap_atomic(page);
554 drm_clflush_virt_range(vaddr + shmem_page_offset,
556 ret = __copy_to_user_inatomic(user_data,
557 vaddr + shmem_page_offset,
559 kunmap_atomic(vaddr);
561 return ret ? -EFAULT : 0;
565 shmem_clflush_swizzled_range(char *addr, unsigned long length,
568 if (unlikely(swizzled)) {
569 unsigned long start = (unsigned long) addr;
570 unsigned long end = (unsigned long) addr + length;
572 /* For swizzling simply ensure that we always flush both
573 * channels. Lame, but simple and it works. Swizzled
574 * pwrite/pread is far from a hotpath - current userspace
575 * doesn't use it at all. */
576 start = round_down(start, 128);
577 end = round_up(end, 128);
579 drm_clflush_virt_range((void *)start, end - start);
581 drm_clflush_virt_range(addr, length);
586 /* Only difference to the fast-path function is that this can handle bit17
587 * and uses non-atomic copy and kmap functions. */
589 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
590 char __user *user_data,
591 bool page_do_bit17_swizzling, bool needs_clflush)
598 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
600 page_do_bit17_swizzling);
602 if (page_do_bit17_swizzling)
603 ret = __copy_to_user_swizzled(user_data,
604 vaddr, shmem_page_offset,
607 ret = __copy_to_user(user_data,
608 vaddr + shmem_page_offset,
612 return ret ? - EFAULT : 0;
616 i915_gem_shmem_pread(struct drm_device *dev,
617 struct drm_i915_gem_object *obj,
618 struct drm_i915_gem_pread *args,
619 struct drm_file *file)
621 char __user *user_data;
624 int shmem_page_offset, page_length, ret = 0;
625 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
627 int needs_clflush = 0;
628 struct sg_page_iter sg_iter;
630 user_data = to_user_ptr(args->data_ptr);
633 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
635 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
639 offset = args->offset;
641 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
642 offset >> PAGE_SHIFT) {
643 struct page *page = sg_page_iter_page(&sg_iter);
648 /* Operation in this page
650 * shmem_page_offset = offset within page in shmem file
651 * page_length = bytes to copy for this page
653 shmem_page_offset = offset_in_page(offset);
654 page_length = remain;
655 if ((shmem_page_offset + page_length) > PAGE_SIZE)
656 page_length = PAGE_SIZE - shmem_page_offset;
658 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
659 (page_to_phys(page) & (1 << 17)) != 0;
661 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
662 user_data, page_do_bit17_swizzling,
667 mutex_unlock(&dev->struct_mutex);
669 if (likely(!i915.prefault_disable) && !prefaulted) {
670 ret = fault_in_multipages_writeable(user_data, remain);
671 /* Userspace is tricking us, but we've already clobbered
672 * its pages with the prefault and promised to write the
673 * data up to the first fault. Hence ignore any errors
674 * and just continue. */
679 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
680 user_data, page_do_bit17_swizzling,
683 mutex_lock(&dev->struct_mutex);
689 remain -= page_length;
690 user_data += page_length;
691 offset += page_length;
695 i915_gem_object_unpin_pages(obj);
701 * Reads data from the object referenced by handle.
703 * On error, the contents of *data are undefined.
706 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
707 struct drm_file *file)
709 struct drm_i915_gem_pread *args = data;
710 struct drm_i915_gem_object *obj;
716 if (!access_ok(VERIFY_WRITE,
717 to_user_ptr(args->data_ptr),
721 ret = i915_mutex_lock_interruptible(dev);
725 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
726 if (&obj->base == NULL) {
731 /* Bounds check source. */
732 if (args->offset > obj->base.size ||
733 args->size > obj->base.size - args->offset) {
738 /* prime objects have no backing filp to GEM pread/pwrite
741 if (!obj->base.filp) {
746 trace_i915_gem_object_pread(obj, args->offset, args->size);
748 ret = i915_gem_shmem_pread(dev, obj, args, file);
751 drm_gem_object_unreference(&obj->base);
753 mutex_unlock(&dev->struct_mutex);
757 /* This is the fast write path which cannot handle
758 * page faults in the source data
762 fast_user_write(struct io_mapping *mapping,
763 loff_t page_base, int page_offset,
764 char __user *user_data,
767 void __iomem *vaddr_atomic;
769 unsigned long unwritten;
771 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
772 /* We can use the cpu mem copy function because this is X86. */
773 vaddr = (void __force*)vaddr_atomic + page_offset;
774 unwritten = __copy_from_user_inatomic_nocache(vaddr,
776 io_mapping_unmap_atomic(vaddr_atomic);
781 * This is the fast pwrite path, where we copy the data directly from the
782 * user into the GTT, uncached.
785 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
786 struct drm_i915_gem_object *obj,
787 struct drm_i915_gem_pwrite *args,
788 struct drm_file *file)
790 struct drm_i915_private *dev_priv = dev->dev_private;
792 loff_t offset, page_base;
793 char __user *user_data;
794 int page_offset, page_length, ret;
796 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
800 ret = i915_gem_object_set_to_gtt_domain(obj, true);
804 ret = i915_gem_object_put_fence(obj);
808 user_data = to_user_ptr(args->data_ptr);
811 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
814 /* Operation in this page
816 * page_base = page offset within aperture
817 * page_offset = offset within page
818 * page_length = bytes to copy for this page
820 page_base = offset & PAGE_MASK;
821 page_offset = offset_in_page(offset);
822 page_length = remain;
823 if ((page_offset + remain) > PAGE_SIZE)
824 page_length = PAGE_SIZE - page_offset;
826 /* If we get a fault while copying data, then (presumably) our
827 * source page isn't available. Return the error and we'll
828 * retry in the slow path.
830 if (fast_user_write(dev_priv->gtt.mappable, page_base,
831 page_offset, user_data, page_length)) {
836 remain -= page_length;
837 user_data += page_length;
838 offset += page_length;
842 i915_gem_object_ggtt_unpin(obj);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
853 char __user *user_data,
854 bool page_do_bit17_swizzling,
855 bool needs_clflush_before,
856 bool needs_clflush_after)
861 if (unlikely(page_do_bit17_swizzling))
864 vaddr = kmap_atomic(page);
865 if (needs_clflush_before)
866 drm_clflush_virt_range(vaddr + shmem_page_offset,
868 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
869 user_data, page_length);
870 if (needs_clflush_after)
871 drm_clflush_virt_range(vaddr + shmem_page_offset,
873 kunmap_atomic(vaddr);
875 return ret ? -EFAULT : 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
882 char __user *user_data,
883 bool page_do_bit17_swizzling,
884 bool needs_clflush_before,
885 bool needs_clflush_after)
891 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
892 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
894 page_do_bit17_swizzling);
895 if (page_do_bit17_swizzling)
896 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
900 ret = __copy_from_user(vaddr + shmem_page_offset,
903 if (needs_clflush_after)
904 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
906 page_do_bit17_swizzling);
909 return ret ? -EFAULT : 0;
913 i915_gem_shmem_pwrite(struct drm_device *dev,
914 struct drm_i915_gem_object *obj,
915 struct drm_i915_gem_pwrite *args,
916 struct drm_file *file)
920 char __user *user_data;
921 int shmem_page_offset, page_length, ret = 0;
922 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
923 int hit_slowpath = 0;
924 int needs_clflush_after = 0;
925 int needs_clflush_before = 0;
926 struct sg_page_iter sg_iter;
928 user_data = to_user_ptr(args->data_ptr);
931 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
933 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after = cpu_write_needs_clflush(obj);
939 ret = i915_gem_object_wait_rendering(obj, false);
943 i915_gem_object_retire(obj);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
948 needs_clflush_before =
949 !cpu_cache_is_coherent(dev, obj->cache_level);
951 ret = i915_gem_object_get_pages(obj);
955 i915_gem_object_pin_pages(obj);
957 offset = args->offset;
960 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
961 offset >> PAGE_SHIFT) {
962 struct page *page = sg_page_iter_page(&sg_iter);
963 int partial_cacheline_write;
968 /* Operation in this page
970 * shmem_page_offset = offset within page in shmem file
971 * page_length = bytes to copy for this page
973 shmem_page_offset = offset_in_page(offset);
975 page_length = remain;
976 if ((shmem_page_offset + page_length) > PAGE_SIZE)
977 page_length = PAGE_SIZE - shmem_page_offset;
979 /* If we don't overwrite a cacheline completely we need to be
980 * careful to have up-to-date data by first clflushing. Don't
981 * overcomplicate things and flush the entire patch. */
982 partial_cacheline_write = needs_clflush_before &&
983 ((shmem_page_offset | page_length)
984 & (boot_cpu_data.x86_clflush_size - 1));
986 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
987 (page_to_phys(page) & (1 << 17)) != 0;
989 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
990 user_data, page_do_bit17_swizzling,
991 partial_cacheline_write,
992 needs_clflush_after);
997 mutex_unlock(&dev->struct_mutex);
998 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
999 user_data, page_do_bit17_swizzling,
1000 partial_cacheline_write,
1001 needs_clflush_after);
1003 mutex_lock(&dev->struct_mutex);
1009 remain -= page_length;
1010 user_data += page_length;
1011 offset += page_length;
1015 i915_gem_object_unpin_pages(obj);
1019 * Fixup: Flush cpu caches in case we didn't flush the dirty
1020 * cachelines in-line while writing and the object moved
1021 * out of the cpu write domain while we've dropped the lock.
1023 if (!needs_clflush_after &&
1024 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1025 if (i915_gem_clflush_object(obj, obj->pin_display))
1026 i915_gem_chipset_flush(dev);
1030 if (needs_clflush_after)
1031 i915_gem_chipset_flush(dev);
1037 * Writes data to the object referenced by handle.
1039 * On error, the contents of the buffer that were to be modified are undefined.
1042 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1043 struct drm_file *file)
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 struct drm_i915_gem_pwrite *args = data;
1047 struct drm_i915_gem_object *obj;
1050 if (args->size == 0)
1053 if (!access_ok(VERIFY_READ,
1054 to_user_ptr(args->data_ptr),
1058 if (likely(!i915.prefault_disable)) {
1059 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1065 intel_runtime_pm_get(dev_priv);
1067 ret = i915_mutex_lock_interruptible(dev);
1071 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1072 if (&obj->base == NULL) {
1077 /* Bounds check destination. */
1078 if (args->offset > obj->base.size ||
1079 args->size > obj->base.size - args->offset) {
1084 /* prime objects have no backing filp to GEM pread/pwrite
1087 if (!obj->base.filp) {
1092 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1095 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1096 * it would end up going through the fenced access, and we'll get
1097 * different detiling behavior between reading and writing.
1098 * pread/pwrite currently are reading and writing from the CPU
1099 * perspective, requiring manual detiling by the client.
1101 if (obj->tiling_mode == I915_TILING_NONE &&
1102 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1103 cpu_write_needs_clflush(obj)) {
1104 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1105 /* Note that the gtt paths might fail with non-page-backed user
1106 * pointers (e.g. gtt mappings when moving data between
1107 * textures). Fallback to the shmem path in that case. */
1110 if (ret == -EFAULT || ret == -ENOSPC) {
1111 if (obj->phys_handle)
1112 ret = i915_gem_phys_pwrite(obj, args, file);
1114 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1118 drm_gem_object_unreference(&obj->base);
1120 mutex_unlock(&dev->struct_mutex);
1122 intel_runtime_pm_put(dev_priv);
1128 i915_gem_check_wedge(struct i915_gpu_error *error,
1131 if (i915_reset_in_progress(error)) {
1132 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133 * -EIO unconditionally for these. */
1137 /* Recovery complete, but the reset failed ... */
1138 if (i915_terminally_wedged(error))
1142 * Check if GPU Reset is in progress - we need intel_ring_begin
1143 * to work properly to reinit the hw state while the gpu is
1144 * still marked as reset-in-progress. Handle this with a flag.
1146 if (!error->reload_in_reset)
1154 * Compare arbitrary request against outstanding lazy request. Emit on match.
1157 i915_gem_check_olr(struct drm_i915_gem_request *req)
1161 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1164 if (req == req->ring->outstanding_lazy_request)
1165 ret = i915_add_request(req->ring);
1170 static void fake_irq(unsigned long data)
1172 wake_up_process((struct task_struct *)data);
1175 static bool missed_irq(struct drm_i915_private *dev_priv,
1176 struct intel_engine_cs *ring)
1178 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1181 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1183 if (file_priv == NULL)
1186 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1190 * __i915_wait_request - wait until execution of request has finished
1192 * @reset_counter: reset sequence associated with the given request
1193 * @interruptible: do an interruptible wait (normally yes)
1194 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1196 * Note: It is of utmost importance that the passed in seqno and reset_counter
1197 * values have been read by the caller in an smp safe manner. Where read-side
1198 * locks are involved, it is sufficient to read the reset_counter before
1199 * unlocking the lock that protects the seqno. For lockless tricks, the
1200 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1203 * Returns 0 if the request was found within the alloted time. Else returns the
1204 * errno with remaining time filled in timeout argument.
1206 int __i915_wait_request(struct drm_i915_gem_request *req,
1207 unsigned reset_counter,
1210 struct drm_i915_file_private *file_priv)
1212 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1213 struct drm_device *dev = ring->dev;
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 const bool irq_test_in_progress =
1216 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1218 unsigned long timeout_expire;
1222 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1224 if (i915_gem_request_completed(req, true))
1227 timeout_expire = timeout ?
1228 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1230 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1231 gen6_rps_boost(dev_priv);
1233 mod_delayed_work(dev_priv->wq,
1234 &file_priv->mm.idle_work,
1235 msecs_to_jiffies(100));
1238 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1241 /* Record current time in case interrupted by signal, or wedged */
1242 trace_i915_gem_request_wait_begin(req);
1243 before = ktime_get_raw_ns();
1245 struct timer_list timer;
1247 prepare_to_wait(&ring->irq_queue, &wait,
1248 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1250 /* We need to check whether any gpu reset happened in between
1251 * the caller grabbing the seqno and now ... */
1252 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1253 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1254 * is truely gone. */
1255 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1261 if (i915_gem_request_completed(req, false)) {
1266 if (interruptible && signal_pending(current)) {
1271 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1276 timer.function = NULL;
1277 if (timeout || missed_irq(dev_priv, ring)) {
1278 unsigned long expire;
1280 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1281 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1282 mod_timer(&timer, expire);
1287 if (timer.function) {
1288 del_singleshot_timer_sync(&timer);
1289 destroy_timer_on_stack(&timer);
1292 now = ktime_get_raw_ns();
1293 trace_i915_gem_request_wait_end(req);
1295 if (!irq_test_in_progress)
1296 ring->irq_put(ring);
1298 finish_wait(&ring->irq_queue, &wait);
1301 s64 tres = *timeout - (now - before);
1303 *timeout = tres < 0 ? 0 : tres;
1306 * Apparently ktime isn't accurate enough and occasionally has a
1307 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1308 * things up to make the test happy. We allow up to 1 jiffy.
1310 * This is a regrssion from the timespec->ktime conversion.
1312 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1320 * Waits for a request to be signaled, and cleans up the
1321 * request and object lists appropriately for that event.
1324 i915_wait_request(struct drm_i915_gem_request *req)
1326 struct drm_device *dev;
1327 struct drm_i915_private *dev_priv;
1329 unsigned reset_counter;
1332 BUG_ON(req == NULL);
1334 dev = req->ring->dev;
1335 dev_priv = dev->dev_private;
1336 interruptible = dev_priv->mm.interruptible;
1338 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1340 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1344 ret = i915_gem_check_olr(req);
1348 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1349 i915_gem_request_reference(req);
1350 ret = __i915_wait_request(req, reset_counter,
1351 interruptible, NULL, NULL);
1352 i915_gem_request_unreference(req);
1357 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1362 /* Manually manage the write flush as we may have not yet
1363 * retired the buffer.
1365 * Note that the last_write_req is always the earlier of
1366 * the two (read/write) requests, so if we haved successfully waited,
1367 * we know we have passed the last write.
1369 i915_gem_request_assign(&obj->last_write_req, NULL);
1375 * Ensures that all rendering to the object has completed and the object is
1376 * safe to unbind from the GTT or access from the CPU.
1378 static __must_check int
1379 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1382 struct drm_i915_gem_request *req;
1385 req = readonly ? obj->last_write_req : obj->last_read_req;
1389 ret = i915_wait_request(req);
1393 return i915_gem_object_wait_rendering__tail(obj);
1396 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1397 * as the object state may change during this call.
1399 static __must_check int
1400 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1401 struct drm_i915_file_private *file_priv,
1404 struct drm_i915_gem_request *req;
1405 struct drm_device *dev = obj->base.dev;
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1407 unsigned reset_counter;
1410 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1411 BUG_ON(!dev_priv->mm.interruptible);
1413 req = readonly ? obj->last_write_req : obj->last_read_req;
1417 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1421 ret = i915_gem_check_olr(req);
1425 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1426 i915_gem_request_reference(req);
1427 mutex_unlock(&dev->struct_mutex);
1428 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1429 mutex_lock(&dev->struct_mutex);
1430 i915_gem_request_unreference(req);
1434 return i915_gem_object_wait_rendering__tail(obj);
1438 * Called when user space prepares to use an object with the CPU, either
1439 * through the mmap ioctl's mapping or a GTT mapping.
1442 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1443 struct drm_file *file)
1445 struct drm_i915_gem_set_domain *args = data;
1446 struct drm_i915_gem_object *obj;
1447 uint32_t read_domains = args->read_domains;
1448 uint32_t write_domain = args->write_domain;
1451 /* Only handle setting domains to types used by the CPU. */
1452 if (write_domain & I915_GEM_GPU_DOMAINS)
1455 if (read_domains & I915_GEM_GPU_DOMAINS)
1458 /* Having something in the write domain implies it's in the read
1459 * domain, and only that read domain. Enforce that in the request.
1461 if (write_domain != 0 && read_domains != write_domain)
1464 ret = i915_mutex_lock_interruptible(dev);
1468 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1469 if (&obj->base == NULL) {
1474 /* Try to flush the object off the GPU without holding the lock.
1475 * We will repeat the flush holding the lock in the normal manner
1476 * to catch cases where we are gazumped.
1478 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1484 if (read_domains & I915_GEM_DOMAIN_GTT)
1485 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1487 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1490 drm_gem_object_unreference(&obj->base);
1492 mutex_unlock(&dev->struct_mutex);
1497 * Called when user space has done writes to this buffer
1500 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1501 struct drm_file *file)
1503 struct drm_i915_gem_sw_finish *args = data;
1504 struct drm_i915_gem_object *obj;
1507 ret = i915_mutex_lock_interruptible(dev);
1511 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1512 if (&obj->base == NULL) {
1517 /* Pinned buffers may be scanout, so flush the cache */
1518 if (obj->pin_display)
1519 i915_gem_object_flush_cpu_write_domain(obj);
1521 drm_gem_object_unreference(&obj->base);
1523 mutex_unlock(&dev->struct_mutex);
1528 * Maps the contents of an object, returning the address it is mapped
1531 * While the mapping holds a reference on the contents of the object, it doesn't
1532 * imply a ref on the object itself.
1536 * DRM driver writers who look a this function as an example for how to do GEM
1537 * mmap support, please don't implement mmap support like here. The modern way
1538 * to implement DRM mmap support is with an mmap offset ioctl (like
1539 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1540 * That way debug tooling like valgrind will understand what's going on, hiding
1541 * the mmap call in a driver private ioctl will break that. The i915 driver only
1542 * does cpu mmaps this way because we didn't know better.
1545 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1546 struct drm_file *file)
1548 struct drm_i915_gem_mmap *args = data;
1549 struct drm_gem_object *obj;
1552 if (args->flags & ~(I915_MMAP_WC))
1555 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1558 obj = drm_gem_object_lookup(dev, file, args->handle);
1562 /* prime objects have no backing filp to GEM mmap
1566 drm_gem_object_unreference_unlocked(obj);
1570 addr = vm_mmap(obj->filp, 0, args->size,
1571 PROT_READ | PROT_WRITE, MAP_SHARED,
1573 if (args->flags & I915_MMAP_WC) {
1574 struct mm_struct *mm = current->mm;
1575 struct vm_area_struct *vma;
1577 down_write(&mm->mmap_sem);
1578 vma = find_vma(mm, addr);
1581 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1584 up_write(&mm->mmap_sem);
1586 drm_gem_object_unreference_unlocked(obj);
1587 if (IS_ERR((void *)addr))
1590 args->addr_ptr = (uint64_t) addr;
1596 * i915_gem_fault - fault a page into the GTT
1597 * vma: VMA in question
1600 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1601 * from userspace. The fault handler takes care of binding the object to
1602 * the GTT (if needed), allocating and programming a fence register (again,
1603 * only if needed based on whether the old reg is still valid or the object
1604 * is tiled) and inserting a new PTE into the faulting process.
1606 * Note that the faulting process may involve evicting existing objects
1607 * from the GTT and/or fence registers to make room. So performance may
1608 * suffer if the GTT working set is large or there are few fence registers
1611 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1613 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1614 struct drm_device *dev = obj->base.dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 pgoff_t page_offset;
1619 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1621 intel_runtime_pm_get(dev_priv);
1623 /* We don't use vmf->pgoff since that has the fake offset */
1624 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1627 ret = i915_mutex_lock_interruptible(dev);
1631 trace_i915_gem_object_fault(obj, page_offset, true, write);
1633 /* Try to flush the object off the GPU first without holding the lock.
1634 * Upon reacquiring the lock, we will perform our sanity checks and then
1635 * repeat the flush holding the lock in the normal manner to catch cases
1636 * where we are gazumped.
1638 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1642 /* Access to snoopable pages through the GTT is incoherent. */
1643 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1648 /* Now bind it into the GTT if needed */
1649 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1653 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1657 ret = i915_gem_object_get_fence(obj);
1661 /* Finally, remap it using the new GTT offset */
1662 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1665 if (!obj->fault_mappable) {
1666 unsigned long size = min_t(unsigned long,
1667 vma->vm_end - vma->vm_start,
1671 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1672 ret = vm_insert_pfn(vma,
1673 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1679 obj->fault_mappable = true;
1681 ret = vm_insert_pfn(vma,
1682 (unsigned long)vmf->virtual_address,
1685 i915_gem_object_ggtt_unpin(obj);
1687 mutex_unlock(&dev->struct_mutex);
1692 * We eat errors when the gpu is terminally wedged to avoid
1693 * userspace unduly crashing (gl has no provisions for mmaps to
1694 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1695 * and so needs to be reported.
1697 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1698 ret = VM_FAULT_SIGBUS;
1703 * EAGAIN means the gpu is hung and we'll wait for the error
1704 * handler to reset everything when re-faulting in
1705 * i915_mutex_lock_interruptible.
1712 * EBUSY is ok: this just means that another thread
1713 * already did the job.
1715 ret = VM_FAULT_NOPAGE;
1722 ret = VM_FAULT_SIGBUS;
1725 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1726 ret = VM_FAULT_SIGBUS;
1730 intel_runtime_pm_put(dev_priv);
1735 * i915_gem_release_mmap - remove physical page mappings
1736 * @obj: obj in question
1738 * Preserve the reservation of the mmapping with the DRM core code, but
1739 * relinquish ownership of the pages back to the system.
1741 * It is vital that we remove the page mapping if we have mapped a tiled
1742 * object through the GTT and then lose the fence register due to
1743 * resource pressure. Similarly if the object has been moved out of the
1744 * aperture, than pages mapped into userspace must be revoked. Removing the
1745 * mapping will then trigger a page fault on the next user access, allowing
1746 * fixup by i915_gem_fault().
1749 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1751 if (!obj->fault_mappable)
1754 drm_vma_node_unmap(&obj->base.vma_node,
1755 obj->base.dev->anon_inode->i_mapping);
1756 obj->fault_mappable = false;
1760 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1762 struct drm_i915_gem_object *obj;
1764 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1765 i915_gem_release_mmap(obj);
1769 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1773 if (INTEL_INFO(dev)->gen >= 4 ||
1774 tiling_mode == I915_TILING_NONE)
1777 /* Previous chips need a power-of-two fence region when tiling */
1778 if (INTEL_INFO(dev)->gen == 3)
1779 gtt_size = 1024*1024;
1781 gtt_size = 512*1024;
1783 while (gtt_size < size)
1790 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1791 * @obj: object to check
1793 * Return the required GTT alignment for an object, taking into account
1794 * potential fence register mapping.
1797 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1798 int tiling_mode, bool fenced)
1801 * Minimum alignment is 4k (GTT page size), but might be greater
1802 * if a fence register is needed for the object.
1804 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1805 tiling_mode == I915_TILING_NONE)
1809 * Previous chips need to be aligned to the size of the smallest
1810 * fence register that can contain the object.
1812 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1815 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1820 if (drm_vma_node_has_offset(&obj->base.vma_node))
1823 dev_priv->mm.shrinker_no_lock_stealing = true;
1825 ret = drm_gem_create_mmap_offset(&obj->base);
1829 /* Badly fragmented mmap space? The only way we can recover
1830 * space is by destroying unwanted objects. We can't randomly release
1831 * mmap_offsets as userspace expects them to be persistent for the
1832 * lifetime of the objects. The closest we can is to release the
1833 * offsets on purgeable objects by truncating it and marking it purged,
1834 * which prevents userspace from ever using that object again.
1836 i915_gem_shrink(dev_priv,
1837 obj->base.size >> PAGE_SHIFT,
1839 I915_SHRINK_UNBOUND |
1840 I915_SHRINK_PURGEABLE);
1841 ret = drm_gem_create_mmap_offset(&obj->base);
1845 i915_gem_shrink_all(dev_priv);
1846 ret = drm_gem_create_mmap_offset(&obj->base);
1848 dev_priv->mm.shrinker_no_lock_stealing = false;
1853 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1855 drm_gem_free_mmap_offset(&obj->base);
1859 i915_gem_mmap_gtt(struct drm_file *file,
1860 struct drm_device *dev,
1864 struct drm_i915_private *dev_priv = dev->dev_private;
1865 struct drm_i915_gem_object *obj;
1868 ret = i915_mutex_lock_interruptible(dev);
1872 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1873 if (&obj->base == NULL) {
1878 if (obj->base.size > dev_priv->gtt.mappable_end) {
1883 if (obj->madv != I915_MADV_WILLNEED) {
1884 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1889 ret = i915_gem_object_create_mmap_offset(obj);
1893 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1896 drm_gem_object_unreference(&obj->base);
1898 mutex_unlock(&dev->struct_mutex);
1903 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1905 * @data: GTT mapping ioctl data
1906 * @file: GEM object info
1908 * Simply returns the fake offset to userspace so it can mmap it.
1909 * The mmap call will end up in drm_gem_mmap(), which will set things
1910 * up so we can get faults in the handler above.
1912 * The fault handler will take care of binding the object into the GTT
1913 * (since it may have been evicted to make room for something), allocating
1914 * a fence register, and mapping the appropriate aperture address into
1918 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1919 struct drm_file *file)
1921 struct drm_i915_gem_mmap_gtt *args = data;
1923 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1927 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1929 return obj->madv == I915_MADV_DONTNEED;
1932 /* Immediately discard the backing storage */
1934 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1936 i915_gem_object_free_mmap_offset(obj);
1938 if (obj->base.filp == NULL)
1941 /* Our goal here is to return as much of the memory as
1942 * is possible back to the system as we are called from OOM.
1943 * To do this we must instruct the shmfs to drop all of its
1944 * backing pages, *now*.
1946 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1947 obj->madv = __I915_MADV_PURGED;
1950 /* Try to discard unwanted pages */
1952 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1954 struct address_space *mapping;
1956 switch (obj->madv) {
1957 case I915_MADV_DONTNEED:
1958 i915_gem_object_truncate(obj);
1959 case __I915_MADV_PURGED:
1963 if (obj->base.filp == NULL)
1966 mapping = file_inode(obj->base.filp)->i_mapping,
1967 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1971 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1973 struct sg_page_iter sg_iter;
1976 BUG_ON(obj->madv == __I915_MADV_PURGED);
1978 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1980 /* In the event of a disaster, abandon all caches and
1981 * hope for the best.
1983 WARN_ON(ret != -EIO);
1984 i915_gem_clflush_object(obj, true);
1985 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1988 if (i915_gem_object_needs_bit17_swizzle(obj))
1989 i915_gem_object_save_bit_17_swizzle(obj);
1991 if (obj->madv == I915_MADV_DONTNEED)
1994 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1995 struct page *page = sg_page_iter_page(&sg_iter);
1998 set_page_dirty(page);
2000 if (obj->madv == I915_MADV_WILLNEED)
2001 mark_page_accessed(page);
2003 page_cache_release(page);
2007 sg_free_table(obj->pages);
2012 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2014 const struct drm_i915_gem_object_ops *ops = obj->ops;
2016 if (obj->pages == NULL)
2019 if (obj->pages_pin_count)
2022 BUG_ON(i915_gem_obj_bound_any(obj));
2024 /* ->put_pages might need to allocate memory for the bit17 swizzle
2025 * array, hence protect them from being reaped by removing them from gtt
2027 list_del(&obj->global_list);
2029 ops->put_pages(obj);
2032 i915_gem_object_invalidate(obj);
2038 i915_gem_shrink(struct drm_i915_private *dev_priv,
2039 long target, unsigned flags)
2042 struct list_head *list;
2045 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2046 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2049 unsigned long count = 0;
2052 * As we may completely rewrite the (un)bound list whilst unbinding
2053 * (due to retiring requests) we have to strictly process only
2054 * one element of the list at the time, and recheck the list
2055 * on every iteration.
2057 * In particular, we must hold a reference whilst removing the
2058 * object as we may end up waiting for and/or retiring the objects.
2059 * This might release the final reference (held by the active list)
2060 * and result in the object being freed from under us. This is
2061 * similar to the precautions the eviction code must take whilst
2064 * Also note that although these lists do not hold a reference to
2065 * the object we can safely grab one here: The final object
2066 * unreferencing and the bound_list are both protected by the
2067 * dev->struct_mutex and so we won't ever be able to observe an
2068 * object on the bound_list with a reference count equals 0.
2070 for (phase = phases; phase->list; phase++) {
2071 struct list_head still_in_list;
2073 if ((flags & phase->bit) == 0)
2076 INIT_LIST_HEAD(&still_in_list);
2077 while (count < target && !list_empty(phase->list)) {
2078 struct drm_i915_gem_object *obj;
2079 struct i915_vma *vma, *v;
2081 obj = list_first_entry(phase->list,
2082 typeof(*obj), global_list);
2083 list_move_tail(&obj->global_list, &still_in_list);
2085 if (flags & I915_SHRINK_PURGEABLE &&
2086 !i915_gem_object_is_purgeable(obj))
2089 drm_gem_object_reference(&obj->base);
2091 /* For the unbound phase, this should be a no-op! */
2092 list_for_each_entry_safe(vma, v,
2093 &obj->vma_list, vma_link)
2094 if (i915_vma_unbind(vma))
2097 if (i915_gem_object_put_pages(obj) == 0)
2098 count += obj->base.size >> PAGE_SHIFT;
2100 drm_gem_object_unreference(&obj->base);
2102 list_splice(&still_in_list, phase->list);
2108 static unsigned long
2109 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2111 i915_gem_evict_everything(dev_priv->dev);
2112 return i915_gem_shrink(dev_priv, LONG_MAX,
2113 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2117 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2119 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2121 struct address_space *mapping;
2122 struct sg_table *st;
2123 struct scatterlist *sg;
2124 struct sg_page_iter sg_iter;
2126 unsigned long last_pfn = 0; /* suppress gcc warning */
2129 /* Assert that the object is not currently in any GPU domain. As it
2130 * wasn't in the GTT, there shouldn't be any way it could have been in
2133 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2134 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2136 st = kmalloc(sizeof(*st), GFP_KERNEL);
2140 page_count = obj->base.size / PAGE_SIZE;
2141 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2146 /* Get the list of pages out of our struct file. They'll be pinned
2147 * at this point until we release them.
2149 * Fail silently without starting the shrinker
2151 mapping = file_inode(obj->base.filp)->i_mapping;
2152 gfp = mapping_gfp_mask(mapping);
2153 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2154 gfp &= ~(__GFP_IO | __GFP_WAIT);
2157 for (i = 0; i < page_count; i++) {
2158 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2160 i915_gem_shrink(dev_priv,
2163 I915_SHRINK_UNBOUND |
2164 I915_SHRINK_PURGEABLE);
2165 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2168 /* We've tried hard to allocate the memory by reaping
2169 * our own buffer, now let the real VM do its job and
2170 * go down in flames if truly OOM.
2172 i915_gem_shrink_all(dev_priv);
2173 page = shmem_read_mapping_page(mapping, i);
2177 #ifdef CONFIG_SWIOTLB
2178 if (swiotlb_nr_tbl()) {
2180 sg_set_page(sg, page, PAGE_SIZE, 0);
2185 if (!i || page_to_pfn(page) != last_pfn + 1) {
2189 sg_set_page(sg, page, PAGE_SIZE, 0);
2191 sg->length += PAGE_SIZE;
2193 last_pfn = page_to_pfn(page);
2195 /* Check that the i965g/gm workaround works. */
2196 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2198 #ifdef CONFIG_SWIOTLB
2199 if (!swiotlb_nr_tbl())
2204 if (i915_gem_object_needs_bit17_swizzle(obj))
2205 i915_gem_object_do_bit_17_swizzle(obj);
2207 if (obj->tiling_mode != I915_TILING_NONE &&
2208 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2209 i915_gem_object_pin_pages(obj);
2215 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2216 page_cache_release(sg_page_iter_page(&sg_iter));
2220 /* shmemfs first checks if there is enough memory to allocate the page
2221 * and reports ENOSPC should there be insufficient, along with the usual
2222 * ENOMEM for a genuine allocation failure.
2224 * We use ENOSPC in our driver to mean that we have run out of aperture
2225 * space and so want to translate the error from shmemfs back to our
2226 * usual understanding of ENOMEM.
2228 if (PTR_ERR(page) == -ENOSPC)
2231 return PTR_ERR(page);
2234 /* Ensure that the associated pages are gathered from the backing storage
2235 * and pinned into our object. i915_gem_object_get_pages() may be called
2236 * multiple times before they are released by a single call to
2237 * i915_gem_object_put_pages() - once the pages are no longer referenced
2238 * either as a result of memory pressure (reaping pages under the shrinker)
2239 * or as the object is itself released.
2242 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2244 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2245 const struct drm_i915_gem_object_ops *ops = obj->ops;
2251 if (obj->madv != I915_MADV_WILLNEED) {
2252 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2256 BUG_ON(obj->pages_pin_count);
2258 ret = ops->get_pages(obj);
2262 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2267 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2268 struct intel_engine_cs *ring)
2270 struct drm_i915_gem_request *req;
2271 struct intel_engine_cs *old_ring;
2273 BUG_ON(ring == NULL);
2275 req = intel_ring_get_request(ring);
2276 old_ring = i915_gem_request_get_ring(obj->last_read_req);
2278 if (old_ring != ring && obj->last_write_req) {
2279 /* Keep the request relative to the current ring */
2280 i915_gem_request_assign(&obj->last_write_req, req);
2283 /* Add a reference if we're newly entering the active list. */
2285 drm_gem_object_reference(&obj->base);
2289 list_move_tail(&obj->ring_list, &ring->active_list);
2291 i915_gem_request_assign(&obj->last_read_req, req);
2294 void i915_vma_move_to_active(struct i915_vma *vma,
2295 struct intel_engine_cs *ring)
2297 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2298 return i915_gem_object_move_to_active(vma->obj, ring);
2302 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2304 struct i915_vma *vma;
2306 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2307 BUG_ON(!obj->active);
2309 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2310 if (!list_empty(&vma->mm_list))
2311 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2314 intel_fb_obj_flush(obj, true);
2316 list_del_init(&obj->ring_list);
2318 i915_gem_request_assign(&obj->last_read_req, NULL);
2319 i915_gem_request_assign(&obj->last_write_req, NULL);
2320 obj->base.write_domain = 0;
2322 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2325 drm_gem_object_unreference(&obj->base);
2327 WARN_ON(i915_verify_lists(dev));
2331 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2333 if (obj->last_read_req == NULL)
2336 if (i915_gem_request_completed(obj->last_read_req, true))
2337 i915_gem_object_move_to_inactive(obj);
2341 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_engine_cs *ring;
2347 /* Carefully retire all requests without writing to the rings */
2348 for_each_ring(ring, dev_priv, i) {
2349 ret = intel_ring_idle(ring);
2353 i915_gem_retire_requests(dev);
2355 /* Finally reset hw state */
2356 for_each_ring(ring, dev_priv, i) {
2357 intel_ring_init_seqno(ring, seqno);
2359 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2360 ring->semaphore.sync_seqno[j] = 0;
2366 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2374 /* HWS page needs to be set less than what we
2375 * will inject to ring
2377 ret = i915_gem_init_seqno(dev, seqno - 1);
2381 /* Carefully set the last_seqno value so that wrap
2382 * detection still works
2384 dev_priv->next_seqno = seqno;
2385 dev_priv->last_seqno = seqno - 1;
2386 if (dev_priv->last_seqno == 0)
2387 dev_priv->last_seqno--;
2393 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2397 /* reserve 0 for non-seqno */
2398 if (dev_priv->next_seqno == 0) {
2399 int ret = i915_gem_init_seqno(dev, 0);
2403 dev_priv->next_seqno = 1;
2406 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2410 int __i915_add_request(struct intel_engine_cs *ring,
2411 struct drm_file *file,
2412 struct drm_i915_gem_object *obj)
2414 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2415 struct drm_i915_gem_request *request;
2416 struct intel_ringbuffer *ringbuf;
2420 request = ring->outstanding_lazy_request;
2421 if (WARN_ON(request == NULL))
2424 if (i915.enable_execlists) {
2425 ringbuf = request->ctx->engine[ring->id].ringbuf;
2427 ringbuf = ring->buffer;
2429 request_start = intel_ring_get_tail(ringbuf);
2431 * Emit any outstanding flushes - execbuf can fail to emit the flush
2432 * after having emitted the batchbuffer command. Hence we need to fix
2433 * things up similar to emitting the lazy request. The difference here
2434 * is that the flush _must_ happen before the next request, no matter
2437 if (i915.enable_execlists) {
2438 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2442 ret = intel_ring_flush_all_caches(ring);
2447 /* Record the position of the start of the request so that
2448 * should we detect the updated seqno part-way through the
2449 * GPU processing the request, we never over-estimate the
2450 * position of the head.
2452 request->postfix = intel_ring_get_tail(ringbuf);
2454 if (i915.enable_execlists) {
2455 ret = ring->emit_request(ringbuf, request);
2459 ret = ring->add_request(ring);
2464 request->head = request_start;
2465 request->tail = intel_ring_get_tail(ringbuf);
2467 /* Whilst this request exists, batch_obj will be on the
2468 * active_list, and so will hold the active reference. Only when this
2469 * request is retired will the the batch_obj be moved onto the
2470 * inactive_list and lose its active reference. Hence we do not need
2471 * to explicitly hold another reference here.
2473 request->batch_obj = obj;
2475 if (!i915.enable_execlists) {
2476 /* Hold a reference to the current context so that we can inspect
2477 * it later in case a hangcheck error event fires.
2479 request->ctx = ring->last_context;
2481 i915_gem_context_reference(request->ctx);
2484 request->emitted_jiffies = jiffies;
2485 list_add_tail(&request->list, &ring->request_list);
2486 request->file_priv = NULL;
2489 struct drm_i915_file_private *file_priv = file->driver_priv;
2491 spin_lock(&file_priv->mm.lock);
2492 request->file_priv = file_priv;
2493 list_add_tail(&request->client_list,
2494 &file_priv->mm.request_list);
2495 spin_unlock(&file_priv->mm.lock);
2497 request->pid = get_pid(task_pid(current));
2500 trace_i915_gem_request_add(request);
2501 ring->outstanding_lazy_request = NULL;
2503 i915_queue_hangcheck(ring->dev);
2505 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2506 queue_delayed_work(dev_priv->wq,
2507 &dev_priv->mm.retire_work,
2508 round_jiffies_up_relative(HZ));
2509 intel_mark_busy(dev_priv->dev);
2515 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2517 struct drm_i915_file_private *file_priv = request->file_priv;
2522 spin_lock(&file_priv->mm.lock);
2523 list_del(&request->client_list);
2524 request->file_priv = NULL;
2525 spin_unlock(&file_priv->mm.lock);
2528 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2529 const struct intel_context *ctx)
2531 unsigned long elapsed;
2533 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2535 if (ctx->hang_stats.banned)
2538 if (ctx->hang_stats.ban_period_seconds &&
2539 elapsed <= ctx->hang_stats.ban_period_seconds) {
2540 if (!i915_gem_context_is_default(ctx)) {
2541 DRM_DEBUG("context hanging too fast, banning!\n");
2543 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2544 if (i915_stop_ring_allow_warn(dev_priv))
2545 DRM_ERROR("gpu hanging too fast, banning!\n");
2553 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2554 struct intel_context *ctx,
2557 struct i915_ctx_hang_stats *hs;
2562 hs = &ctx->hang_stats;
2565 hs->banned = i915_context_is_banned(dev_priv, ctx);
2567 hs->guilty_ts = get_seconds();
2569 hs->batch_pending++;
2573 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2575 list_del(&request->list);
2576 i915_gem_request_remove_from_client(request);
2578 put_pid(request->pid);
2580 i915_gem_request_unreference(request);
2583 void i915_gem_request_free(struct kref *req_ref)
2585 struct drm_i915_gem_request *req = container_of(req_ref,
2587 struct intel_context *ctx = req->ctx;
2590 if (i915.enable_execlists) {
2591 struct intel_engine_cs *ring = req->ring;
2593 if (ctx != ring->default_context)
2594 intel_lr_context_unpin(ring, ctx);
2597 i915_gem_context_unreference(ctx);
2603 struct drm_i915_gem_request *
2604 i915_gem_find_active_request(struct intel_engine_cs *ring)
2606 struct drm_i915_gem_request *request;
2608 list_for_each_entry(request, &ring->request_list, list) {
2609 if (i915_gem_request_completed(request, false))
2618 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2619 struct intel_engine_cs *ring)
2621 struct drm_i915_gem_request *request;
2624 request = i915_gem_find_active_request(ring);
2626 if (request == NULL)
2629 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2631 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2633 list_for_each_entry_continue(request, &ring->request_list, list)
2634 i915_set_reset_status(dev_priv, request->ctx, false);
2637 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2638 struct intel_engine_cs *ring)
2640 while (!list_empty(&ring->active_list)) {
2641 struct drm_i915_gem_object *obj;
2643 obj = list_first_entry(&ring->active_list,
2644 struct drm_i915_gem_object,
2647 i915_gem_object_move_to_inactive(obj);
2651 * Clear the execlists queue up before freeing the requests, as those
2652 * are the ones that keep the context and ringbuffer backing objects
2655 while (!list_empty(&ring->execlist_queue)) {
2656 struct drm_i915_gem_request *submit_req;
2658 submit_req = list_first_entry(&ring->execlist_queue,
2659 struct drm_i915_gem_request,
2661 list_del(&submit_req->execlist_link);
2662 intel_runtime_pm_put(dev_priv);
2664 if (submit_req->ctx != ring->default_context)
2665 intel_lr_context_unpin(ring, submit_req->ctx);
2667 i915_gem_context_unreference(submit_req->ctx);
2672 * We must free the requests after all the corresponding objects have
2673 * been moved off active lists. Which is the same order as the normal
2674 * retire_requests function does. This is important if object hold
2675 * implicit references on things like e.g. ppgtt address spaces through
2678 while (!list_empty(&ring->request_list)) {
2679 struct drm_i915_gem_request *request;
2681 request = list_first_entry(&ring->request_list,
2682 struct drm_i915_gem_request,
2685 i915_gem_free_request(request);
2688 /* This may not have been flushed before the reset, so clean it now */
2689 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2692 void i915_gem_restore_fences(struct drm_device *dev)
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2697 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2698 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2701 * Commit delayed tiling changes if we have an object still
2702 * attached to the fence, otherwise just clear the fence.
2705 i915_gem_object_update_fence(reg->obj, reg,
2706 reg->obj->tiling_mode);
2708 i915_gem_write_fence(dev, i, NULL);
2713 void i915_gem_reset(struct drm_device *dev)
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 struct intel_engine_cs *ring;
2720 * Before we free the objects from the requests, we need to inspect
2721 * them for finding the guilty party. As the requests only borrow
2722 * their reference to the objects, the inspection must be done first.
2724 for_each_ring(ring, dev_priv, i)
2725 i915_gem_reset_ring_status(dev_priv, ring);
2727 for_each_ring(ring, dev_priv, i)
2728 i915_gem_reset_ring_cleanup(dev_priv, ring);
2730 i915_gem_context_reset(dev);
2732 i915_gem_restore_fences(dev);
2736 * This function clears the request list as sequence numbers are passed.
2739 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2741 if (list_empty(&ring->request_list))
2744 WARN_ON(i915_verify_lists(ring->dev));
2746 /* Move any buffers on the active list that are no longer referenced
2747 * by the ringbuffer to the flushing/inactive lists as appropriate,
2748 * before we free the context associated with the requests.
2750 while (!list_empty(&ring->active_list)) {
2751 struct drm_i915_gem_object *obj;
2753 obj = list_first_entry(&ring->active_list,
2754 struct drm_i915_gem_object,
2757 if (!i915_gem_request_completed(obj->last_read_req, true))
2760 i915_gem_object_move_to_inactive(obj);
2764 while (!list_empty(&ring->request_list)) {
2765 struct drm_i915_gem_request *request;
2767 request = list_first_entry(&ring->request_list,
2768 struct drm_i915_gem_request,
2771 if (!i915_gem_request_completed(request, true))
2774 trace_i915_gem_request_retire(request);
2776 /* We know the GPU must have read the request to have
2777 * sent us the seqno + interrupt, so use the position
2778 * of tail of the request to update the last known position
2781 request->ringbuf->last_retired_head = request->postfix;
2783 i915_gem_free_request(request);
2786 if (unlikely(ring->trace_irq_req &&
2787 i915_gem_request_completed(ring->trace_irq_req, true))) {
2788 ring->irq_put(ring);
2789 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2792 WARN_ON(i915_verify_lists(ring->dev));
2796 i915_gem_retire_requests(struct drm_device *dev)
2798 struct drm_i915_private *dev_priv = dev->dev_private;
2799 struct intel_engine_cs *ring;
2803 for_each_ring(ring, dev_priv, i) {
2804 i915_gem_retire_requests_ring(ring);
2805 idle &= list_empty(&ring->request_list);
2806 if (i915.enable_execlists) {
2807 unsigned long flags;
2809 spin_lock_irqsave(&ring->execlist_lock, flags);
2810 idle &= list_empty(&ring->execlist_queue);
2811 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2813 intel_execlists_retire_requests(ring);
2818 mod_delayed_work(dev_priv->wq,
2819 &dev_priv->mm.idle_work,
2820 msecs_to_jiffies(100));
2826 i915_gem_retire_work_handler(struct work_struct *work)
2828 struct drm_i915_private *dev_priv =
2829 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2830 struct drm_device *dev = dev_priv->dev;
2833 /* Come back later if the device is busy... */
2835 if (mutex_trylock(&dev->struct_mutex)) {
2836 idle = i915_gem_retire_requests(dev);
2837 mutex_unlock(&dev->struct_mutex);
2840 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2841 round_jiffies_up_relative(HZ));
2845 i915_gem_idle_work_handler(struct work_struct *work)
2847 struct drm_i915_private *dev_priv =
2848 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2850 intel_mark_idle(dev_priv->dev);
2854 * Ensures that an object will eventually get non-busy by flushing any required
2855 * write domains, emitting any outstanding lazy request and retiring and
2856 * completed requests.
2859 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2861 struct intel_engine_cs *ring;
2865 ring = i915_gem_request_get_ring(obj->last_read_req);
2867 ret = i915_gem_check_olr(obj->last_read_req);
2871 i915_gem_retire_requests_ring(ring);
2878 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2879 * @DRM_IOCTL_ARGS: standard ioctl arguments
2881 * Returns 0 if successful, else an error is returned with the remaining time in
2882 * the timeout parameter.
2883 * -ETIME: object is still busy after timeout
2884 * -ERESTARTSYS: signal interrupted the wait
2885 * -ENONENT: object doesn't exist
2886 * Also possible, but rare:
2887 * -EAGAIN: GPU wedged
2889 * -ENODEV: Internal IRQ fail
2890 * -E?: The add request failed
2892 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2893 * non-zero timeout parameter the wait ioctl will wait for the given number of
2894 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2895 * without holding struct_mutex the object may become re-busied before this
2896 * function completes. A similar but shorter * race condition exists in the busy
2900 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct drm_i915_gem_wait *args = data;
2904 struct drm_i915_gem_object *obj;
2905 struct drm_i915_gem_request *req;
2906 unsigned reset_counter;
2909 if (args->flags != 0)
2912 ret = i915_mutex_lock_interruptible(dev);
2916 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2917 if (&obj->base == NULL) {
2918 mutex_unlock(&dev->struct_mutex);
2922 /* Need to make sure the object gets inactive eventually. */
2923 ret = i915_gem_object_flush_active(obj);
2927 if (!obj->active || !obj->last_read_req)
2930 req = obj->last_read_req;
2932 /* Do this after OLR check to make sure we make forward progress polling
2933 * on this IOCTL with a timeout <=0 (like busy ioctl)
2935 if (args->timeout_ns <= 0) {
2940 drm_gem_object_unreference(&obj->base);
2941 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2942 i915_gem_request_reference(req);
2943 mutex_unlock(&dev->struct_mutex);
2945 ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2947 mutex_lock(&dev->struct_mutex);
2948 i915_gem_request_unreference(req);
2949 mutex_unlock(&dev->struct_mutex);
2953 drm_gem_object_unreference(&obj->base);
2954 mutex_unlock(&dev->struct_mutex);
2959 * i915_gem_object_sync - sync an object to a ring.
2961 * @obj: object which may be in use on another ring.
2962 * @to: ring we wish to use the object on. May be NULL.
2964 * This code is meant to abstract object synchronization with the GPU.
2965 * Calling with NULL implies synchronizing the object with the CPU
2966 * rather than a particular GPU ring.
2968 * Returns 0 if successful, else propagates up the lower layer error.
2971 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2972 struct intel_engine_cs *to)
2974 struct intel_engine_cs *from;
2978 from = i915_gem_request_get_ring(obj->last_read_req);
2980 if (from == NULL || to == from)
2983 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2984 return i915_gem_object_wait_rendering(obj, false);
2986 idx = intel_ring_sync_index(from, to);
2988 seqno = i915_gem_request_get_seqno(obj->last_read_req);
2989 /* Optimization: Avoid semaphore sync when we are sure we already
2990 * waited for an object with higher seqno */
2991 if (seqno <= from->semaphore.sync_seqno[idx])
2994 ret = i915_gem_check_olr(obj->last_read_req);
2998 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
2999 ret = to->semaphore.sync_to(to, from, seqno);
3001 /* We use last_read_req because sync_to()
3002 * might have just caused seqno wrap under
3005 from->semaphore.sync_seqno[idx] =
3006 i915_gem_request_get_seqno(obj->last_read_req);
3011 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3013 u32 old_write_domain, old_read_domains;
3015 /* Force a pagefault for domain tracking on next user access */
3016 i915_gem_release_mmap(obj);
3018 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3021 /* Wait for any direct GTT access to complete */
3024 old_read_domains = obj->base.read_domains;
3025 old_write_domain = obj->base.write_domain;
3027 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3028 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3030 trace_i915_gem_object_change_domain(obj,
3035 int i915_vma_unbind(struct i915_vma *vma)
3037 struct drm_i915_gem_object *obj = vma->obj;
3038 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3041 if (list_empty(&vma->vma_link))
3044 if (!drm_mm_node_allocated(&vma->node)) {
3045 i915_gem_vma_destroy(vma);
3052 BUG_ON(obj->pages == NULL);
3054 ret = i915_gem_object_finish_gpu(obj);
3057 /* Continue on if we fail due to EIO, the GPU is hung so we
3058 * should be safe and we need to cleanup or else we might
3059 * cause memory corruption through use-after-free.
3062 if (i915_is_ggtt(vma->vm) &&
3063 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3064 i915_gem_object_finish_gtt(obj);
3066 /* release the fence reg _after_ flushing */
3067 ret = i915_gem_object_put_fence(obj);
3072 trace_i915_vma_unbind(vma);
3074 vma->unbind_vma(vma);
3076 list_del_init(&vma->mm_list);
3077 if (i915_is_ggtt(vma->vm)) {
3078 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3079 obj->map_and_fenceable = false;
3080 } else if (vma->ggtt_view.pages) {
3081 sg_free_table(vma->ggtt_view.pages);
3082 kfree(vma->ggtt_view.pages);
3083 vma->ggtt_view.pages = NULL;
3087 drm_mm_remove_node(&vma->node);
3088 i915_gem_vma_destroy(vma);
3090 /* Since the unbound list is global, only move to that list if
3091 * no more VMAs exist. */
3092 if (list_empty(&obj->vma_list)) {
3093 /* Throw away the active reference before
3094 * moving to the unbound list. */
3095 i915_gem_object_retire(obj);
3097 i915_gem_gtt_finish_object(obj);
3098 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3101 /* And finally now the object is completely decoupled from this vma,
3102 * we can drop its hold on the backing storage and allow it to be
3103 * reaped by the shrinker.
3105 i915_gem_object_unpin_pages(obj);
3110 int i915_gpu_idle(struct drm_device *dev)
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 struct intel_engine_cs *ring;
3116 /* Flush everything onto the inactive list. */
3117 for_each_ring(ring, dev_priv, i) {
3118 if (!i915.enable_execlists) {
3119 ret = i915_switch_context(ring, ring->default_context);
3124 ret = intel_ring_idle(ring);
3132 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3133 struct drm_i915_gem_object *obj)
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3137 int fence_pitch_shift;
3139 if (INTEL_INFO(dev)->gen >= 6) {
3140 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3141 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3143 fence_reg = FENCE_REG_965_0;
3144 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3147 fence_reg += reg * 8;
3149 /* To w/a incoherency with non-atomic 64-bit register updates,
3150 * we split the 64-bit update into two 32-bit writes. In order
3151 * for a partial fence not to be evaluated between writes, we
3152 * precede the update with write to turn off the fence register,
3153 * and only enable the fence as the last step.
3155 * For extra levels of paranoia, we make sure each step lands
3156 * before applying the next step.
3158 I915_WRITE(fence_reg, 0);
3159 POSTING_READ(fence_reg);
3162 u32 size = i915_gem_obj_ggtt_size(obj);
3165 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3167 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3168 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3169 if (obj->tiling_mode == I915_TILING_Y)
3170 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3171 val |= I965_FENCE_REG_VALID;
3173 I915_WRITE(fence_reg + 4, val >> 32);
3174 POSTING_READ(fence_reg + 4);
3176 I915_WRITE(fence_reg + 0, val);
3177 POSTING_READ(fence_reg);
3179 I915_WRITE(fence_reg + 4, 0);
3180 POSTING_READ(fence_reg + 4);
3184 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3185 struct drm_i915_gem_object *obj)
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3191 u32 size = i915_gem_obj_ggtt_size(obj);
3195 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3196 (size & -size) != size ||
3197 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3198 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3199 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3201 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3206 /* Note: pitch better be a power of two tile widths */
3207 pitch_val = obj->stride / tile_width;
3208 pitch_val = ffs(pitch_val) - 1;
3210 val = i915_gem_obj_ggtt_offset(obj);
3211 if (obj->tiling_mode == I915_TILING_Y)
3212 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3213 val |= I915_FENCE_SIZE_BITS(size);
3214 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3215 val |= I830_FENCE_REG_VALID;
3220 reg = FENCE_REG_830_0 + reg * 4;
3222 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3224 I915_WRITE(reg, val);
3228 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3229 struct drm_i915_gem_object *obj)
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3235 u32 size = i915_gem_obj_ggtt_size(obj);
3238 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3239 (size & -size) != size ||
3240 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3241 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3242 i915_gem_obj_ggtt_offset(obj), size);
3244 pitch_val = obj->stride / 128;
3245 pitch_val = ffs(pitch_val) - 1;
3247 val = i915_gem_obj_ggtt_offset(obj);
3248 if (obj->tiling_mode == I915_TILING_Y)
3249 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3250 val |= I830_FENCE_SIZE_BITS(size);
3251 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3252 val |= I830_FENCE_REG_VALID;
3256 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3257 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3260 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3262 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3265 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3266 struct drm_i915_gem_object *obj)
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3270 /* Ensure that all CPU reads are completed before installing a fence
3271 * and all writes before removing the fence.
3273 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3276 WARN(obj && (!obj->stride || !obj->tiling_mode),
3277 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3278 obj->stride, obj->tiling_mode);
3281 i830_write_fence_reg(dev, reg, obj);
3282 else if (IS_GEN3(dev))
3283 i915_write_fence_reg(dev, reg, obj);
3284 else if (INTEL_INFO(dev)->gen >= 4)
3285 i965_write_fence_reg(dev, reg, obj);
3287 /* And similarly be paranoid that no direct access to this region
3288 * is reordered to before the fence is installed.
3290 if (i915_gem_object_needs_mb(obj))
3294 static inline int fence_number(struct drm_i915_private *dev_priv,
3295 struct drm_i915_fence_reg *fence)
3297 return fence - dev_priv->fence_regs;
3300 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3301 struct drm_i915_fence_reg *fence,
3304 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3305 int reg = fence_number(dev_priv, fence);
3307 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3310 obj->fence_reg = reg;
3312 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3314 obj->fence_reg = I915_FENCE_REG_NONE;
3316 list_del_init(&fence->lru_list);
3318 obj->fence_dirty = false;
3322 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3324 if (obj->last_fenced_req) {
3325 int ret = i915_wait_request(obj->last_fenced_req);
3329 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3336 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3338 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3339 struct drm_i915_fence_reg *fence;
3342 ret = i915_gem_object_wait_fence(obj);
3346 if (obj->fence_reg == I915_FENCE_REG_NONE)
3349 fence = &dev_priv->fence_regs[obj->fence_reg];
3351 if (WARN_ON(fence->pin_count))
3354 i915_gem_object_fence_lost(obj);
3355 i915_gem_object_update_fence(obj, fence, false);
3360 static struct drm_i915_fence_reg *
3361 i915_find_fence_reg(struct drm_device *dev)
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct drm_i915_fence_reg *reg, *avail;
3367 /* First try to find a free reg */
3369 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3370 reg = &dev_priv->fence_regs[i];
3374 if (!reg->pin_count)
3381 /* None available, try to steal one or wait for a user to finish */
3382 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3390 /* Wait for completion of pending flips which consume fences */
3391 if (intel_has_pending_fb_unpin(dev))
3392 return ERR_PTR(-EAGAIN);
3394 return ERR_PTR(-EDEADLK);
3398 * i915_gem_object_get_fence - set up fencing for an object
3399 * @obj: object to map through a fence reg
3401 * When mapping objects through the GTT, userspace wants to be able to write
3402 * to them without having to worry about swizzling if the object is tiled.
3403 * This function walks the fence regs looking for a free one for @obj,
3404 * stealing one if it can't find any.
3406 * It then sets up the reg based on the object's properties: address, pitch
3407 * and tiling format.
3409 * For an untiled surface, this removes any existing fence.
3412 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3414 struct drm_device *dev = obj->base.dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 bool enable = obj->tiling_mode != I915_TILING_NONE;
3417 struct drm_i915_fence_reg *reg;
3420 /* Have we updated the tiling parameters upon the object and so
3421 * will need to serialise the write to the associated fence register?
3423 if (obj->fence_dirty) {
3424 ret = i915_gem_object_wait_fence(obj);
3429 /* Just update our place in the LRU if our fence is getting reused. */
3430 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3431 reg = &dev_priv->fence_regs[obj->fence_reg];
3432 if (!obj->fence_dirty) {
3433 list_move_tail(®->lru_list,
3434 &dev_priv->mm.fence_list);
3437 } else if (enable) {
3438 if (WARN_ON(!obj->map_and_fenceable))
3441 reg = i915_find_fence_reg(dev);
3443 return PTR_ERR(reg);
3446 struct drm_i915_gem_object *old = reg->obj;
3448 ret = i915_gem_object_wait_fence(old);
3452 i915_gem_object_fence_lost(old);
3457 i915_gem_object_update_fence(obj, reg, enable);
3462 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3463 unsigned long cache_level)
3465 struct drm_mm_node *gtt_space = &vma->node;
3466 struct drm_mm_node *other;
3469 * On some machines we have to be careful when putting differing types
3470 * of snoopable memory together to avoid the prefetcher crossing memory
3471 * domains and dying. During vm initialisation, we decide whether or not
3472 * these constraints apply and set the drm_mm.color_adjust
3475 if (vma->vm->mm.color_adjust == NULL)
3478 if (!drm_mm_node_allocated(gtt_space))
3481 if (list_empty(>t_space->node_list))
3484 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3485 if (other->allocated && !other->hole_follows && other->color != cache_level)
3488 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3489 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3496 * Finds free space in the GTT aperture and binds the object there.
3498 static struct i915_vma *
3499 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3500 struct i915_address_space *vm,
3503 const struct i915_ggtt_view *view)
3505 struct drm_device *dev = obj->base.dev;
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 u32 size, fence_size, fence_alignment, unfenced_alignment;
3508 unsigned long start =
3509 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3511 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3512 struct i915_vma *vma;
3515 fence_size = i915_gem_get_gtt_size(dev,
3518 fence_alignment = i915_gem_get_gtt_alignment(dev,
3520 obj->tiling_mode, true);
3521 unfenced_alignment =
3522 i915_gem_get_gtt_alignment(dev,
3524 obj->tiling_mode, false);
3527 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3529 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3530 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3531 return ERR_PTR(-EINVAL);
3534 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3536 /* If the object is bigger than the entire aperture, reject it early
3537 * before evicting everything in a vain attempt to find space.
3539 if (obj->base.size > end) {
3540 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3542 flags & PIN_MAPPABLE ? "mappable" : "total",
3544 return ERR_PTR(-E2BIG);
3547 ret = i915_gem_object_get_pages(obj);
3549 return ERR_PTR(ret);
3551 i915_gem_object_pin_pages(obj);
3553 vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view);
3558 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3562 DRM_MM_SEARCH_DEFAULT,
3563 DRM_MM_CREATE_DEFAULT);
3565 ret = i915_gem_evict_something(dev, vm, size, alignment,
3574 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3576 goto err_remove_node;
3579 ret = i915_gem_gtt_prepare_object(obj);
3581 goto err_remove_node;
3583 trace_i915_vma_bind(vma, flags);
3584 ret = i915_vma_bind(vma, obj->cache_level,
3585 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3587 goto err_finish_gtt;
3589 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3590 list_add_tail(&vma->mm_list, &vm->inactive_list);
3595 i915_gem_gtt_finish_object(obj);
3597 drm_mm_remove_node(&vma->node);
3599 i915_gem_vma_destroy(vma);
3602 i915_gem_object_unpin_pages(obj);
3607 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3610 /* If we don't have a page list set up, then we're not pinned
3611 * to GPU, and we can ignore the cache flush because it'll happen
3612 * again at bind time.
3614 if (obj->pages == NULL)
3618 * Stolen memory is always coherent with the GPU as it is explicitly
3619 * marked as wc by the system, or the system is cache-coherent.
3621 if (obj->stolen || obj->phys_handle)
3624 /* If the GPU is snooping the contents of the CPU cache,
3625 * we do not need to manually clear the CPU cache lines. However,
3626 * the caches are only snooped when the render cache is
3627 * flushed/invalidated. As we always have to emit invalidations
3628 * and flushes when moving into and out of the RENDER domain, correct
3629 * snooping behaviour occurs naturally as the result of our domain
3632 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3633 obj->cache_dirty = true;
3637 trace_i915_gem_object_clflush(obj);
3638 drm_clflush_sg(obj->pages);
3639 obj->cache_dirty = false;
3644 /** Flushes the GTT write domain for the object if it's dirty. */
3646 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3648 uint32_t old_write_domain;
3650 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3653 /* No actual flushing is required for the GTT write domain. Writes
3654 * to it immediately go to main memory as far as we know, so there's
3655 * no chipset flush. It also doesn't land in render cache.
3657 * However, we do have to enforce the order so that all writes through
3658 * the GTT land before any writes to the device, such as updates to
3663 old_write_domain = obj->base.write_domain;
3664 obj->base.write_domain = 0;
3666 intel_fb_obj_flush(obj, false);
3668 trace_i915_gem_object_change_domain(obj,
3669 obj->base.read_domains,
3673 /** Flushes the CPU write domain for the object if it's dirty. */
3675 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3677 uint32_t old_write_domain;
3679 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3682 if (i915_gem_clflush_object(obj, obj->pin_display))
3683 i915_gem_chipset_flush(obj->base.dev);
3685 old_write_domain = obj->base.write_domain;
3686 obj->base.write_domain = 0;
3688 intel_fb_obj_flush(obj, false);
3690 trace_i915_gem_object_change_domain(obj,
3691 obj->base.read_domains,
3696 * Moves a single object to the GTT read, and possibly write domain.
3698 * This function returns when the move is complete, including waiting on
3702 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3704 uint32_t old_write_domain, old_read_domains;
3705 struct i915_vma *vma;
3708 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3711 ret = i915_gem_object_wait_rendering(obj, !write);
3715 i915_gem_object_retire(obj);
3717 /* Flush and acquire obj->pages so that we are coherent through
3718 * direct access in memory with previous cached writes through
3719 * shmemfs and that our cache domain tracking remains valid.
3720 * For example, if the obj->filp was moved to swap without us
3721 * being notified and releasing the pages, we would mistakenly
3722 * continue to assume that the obj remained out of the CPU cached
3725 ret = i915_gem_object_get_pages(obj);
3729 i915_gem_object_flush_cpu_write_domain(obj);
3731 /* Serialise direct access to this object with the barriers for
3732 * coherent writes from the GPU, by effectively invalidating the
3733 * GTT domain upon first access.
3735 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3738 old_write_domain = obj->base.write_domain;
3739 old_read_domains = obj->base.read_domains;
3741 /* It should now be out of any other write domains, and we can update
3742 * the domain values for our changes.
3744 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3745 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3747 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3748 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3753 intel_fb_obj_invalidate(obj, NULL);
3755 trace_i915_gem_object_change_domain(obj,
3759 /* And bump the LRU for this access */
3760 vma = i915_gem_obj_to_ggtt(obj);
3761 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3762 list_move_tail(&vma->mm_list,
3763 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3768 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3769 enum i915_cache_level cache_level)
3771 struct drm_device *dev = obj->base.dev;
3772 struct i915_vma *vma, *next;
3775 if (obj->cache_level == cache_level)
3778 if (i915_gem_obj_is_pinned(obj)) {
3779 DRM_DEBUG("can not change the cache level of pinned objects\n");
3783 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3784 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3785 ret = i915_vma_unbind(vma);
3791 if (i915_gem_obj_bound_any(obj)) {
3792 ret = i915_gem_object_finish_gpu(obj);
3796 i915_gem_object_finish_gtt(obj);
3798 /* Before SandyBridge, you could not use tiling or fence
3799 * registers with snooped memory, so relinquish any fences
3800 * currently pointing to our region in the aperture.
3802 if (INTEL_INFO(dev)->gen < 6) {
3803 ret = i915_gem_object_put_fence(obj);
3808 list_for_each_entry(vma, &obj->vma_list, vma_link)
3809 if (drm_mm_node_allocated(&vma->node)) {
3810 ret = i915_vma_bind(vma, cache_level,
3811 vma->bound & GLOBAL_BIND);
3817 list_for_each_entry(vma, &obj->vma_list, vma_link)
3818 vma->node.color = cache_level;
3819 obj->cache_level = cache_level;
3821 if (obj->cache_dirty &&
3822 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3823 cpu_write_needs_clflush(obj)) {
3824 if (i915_gem_clflush_object(obj, true))
3825 i915_gem_chipset_flush(obj->base.dev);
3831 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3832 struct drm_file *file)
3834 struct drm_i915_gem_caching *args = data;
3835 struct drm_i915_gem_object *obj;
3838 ret = i915_mutex_lock_interruptible(dev);
3842 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3843 if (&obj->base == NULL) {
3848 switch (obj->cache_level) {
3849 case I915_CACHE_LLC:
3850 case I915_CACHE_L3_LLC:
3851 args->caching = I915_CACHING_CACHED;
3855 args->caching = I915_CACHING_DISPLAY;
3859 args->caching = I915_CACHING_NONE;
3863 drm_gem_object_unreference(&obj->base);
3865 mutex_unlock(&dev->struct_mutex);
3869 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3870 struct drm_file *file)
3872 struct drm_i915_gem_caching *args = data;
3873 struct drm_i915_gem_object *obj;
3874 enum i915_cache_level level;
3877 switch (args->caching) {
3878 case I915_CACHING_NONE:
3879 level = I915_CACHE_NONE;
3881 case I915_CACHING_CACHED:
3882 level = I915_CACHE_LLC;
3884 case I915_CACHING_DISPLAY:
3885 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3891 ret = i915_mutex_lock_interruptible(dev);
3895 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3896 if (&obj->base == NULL) {
3901 ret = i915_gem_object_set_cache_level(obj, level);
3903 drm_gem_object_unreference(&obj->base);
3905 mutex_unlock(&dev->struct_mutex);
3909 static bool is_pin_display(struct drm_i915_gem_object *obj)
3911 struct i915_vma *vma;
3913 vma = i915_gem_obj_to_ggtt(obj);
3917 /* There are 2 sources that pin objects:
3918 * 1. The display engine (scanouts, sprites, cursors);
3919 * 2. Reservations for execbuffer;
3921 * We can ignore reservations as we hold the struct_mutex and
3922 * are only called outside of the reservation path.
3924 return vma->pin_count;
3928 * Prepare buffer for display plane (scanout, cursors, etc).
3929 * Can be called from an uninterruptible phase (modesetting) and allows
3930 * any flushes to be pipelined (for pageflips).
3933 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3935 struct intel_engine_cs *pipelined)
3937 u32 old_read_domains, old_write_domain;
3938 bool was_pin_display;
3941 if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3942 ret = i915_gem_object_sync(obj, pipelined);
3947 /* Mark the pin_display early so that we account for the
3948 * display coherency whilst setting up the cache domains.
3950 was_pin_display = obj->pin_display;
3951 obj->pin_display = true;
3953 /* The display engine is not coherent with the LLC cache on gen6. As
3954 * a result, we make sure that the pinning that is about to occur is
3955 * done with uncached PTEs. This is lowest common denominator for all
3958 * However for gen6+, we could do better by using the GFDT bit instead
3959 * of uncaching, which would allow us to flush all the LLC-cached data
3960 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3962 ret = i915_gem_object_set_cache_level(obj,
3963 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3965 goto err_unpin_display;
3967 /* As the user may map the buffer once pinned in the display plane
3968 * (e.g. libkms for the bootup splash), we have to ensure that we
3969 * always use map_and_fenceable for all scanout buffers.
3971 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3973 goto err_unpin_display;
3975 i915_gem_object_flush_cpu_write_domain(obj);
3977 old_write_domain = obj->base.write_domain;
3978 old_read_domains = obj->base.read_domains;
3980 /* It should now be out of any other write domains, and we can update
3981 * the domain values for our changes.
3983 obj->base.write_domain = 0;
3984 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3986 trace_i915_gem_object_change_domain(obj,
3993 WARN_ON(was_pin_display != is_pin_display(obj));
3994 obj->pin_display = was_pin_display;
3999 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4001 i915_gem_object_ggtt_unpin(obj);
4002 obj->pin_display = is_pin_display(obj);
4006 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4010 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4013 ret = i915_gem_object_wait_rendering(obj, false);
4017 /* Ensure that we invalidate the GPU's caches and TLBs. */
4018 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4023 * Moves a single object to the CPU read, and possibly write domain.
4025 * This function returns when the move is complete, including waiting on
4029 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4031 uint32_t old_write_domain, old_read_domains;
4034 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4037 ret = i915_gem_object_wait_rendering(obj, !write);
4041 i915_gem_object_retire(obj);
4042 i915_gem_object_flush_gtt_write_domain(obj);
4044 old_write_domain = obj->base.write_domain;
4045 old_read_domains = obj->base.read_domains;
4047 /* Flush the CPU cache if it's still invalid. */
4048 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4049 i915_gem_clflush_object(obj, false);
4051 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4054 /* It should now be out of any other write domains, and we can update
4055 * the domain values for our changes.
4057 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4059 /* If we're writing through the CPU, then the GPU read domains will
4060 * need to be invalidated at next use.
4063 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4064 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4068 intel_fb_obj_invalidate(obj, NULL);
4070 trace_i915_gem_object_change_domain(obj,
4077 /* Throttle our rendering by waiting until the ring has completed our requests
4078 * emitted over 20 msec ago.
4080 * Note that if we were to use the current jiffies each time around the loop,
4081 * we wouldn't escape the function with any frames outstanding if the time to
4082 * render a frame was over 20ms.
4084 * This should get us reasonable parallelism between CPU and GPU but also
4085 * relatively low latency when blocking on a particular request to finish.
4088 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4090 struct drm_i915_private *dev_priv = dev->dev_private;
4091 struct drm_i915_file_private *file_priv = file->driver_priv;
4092 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4093 struct drm_i915_gem_request *request, *target = NULL;
4094 unsigned reset_counter;
4097 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4101 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4105 spin_lock(&file_priv->mm.lock);
4106 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4107 if (time_after_eq(request->emitted_jiffies, recent_enough))
4112 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4114 i915_gem_request_reference(target);
4115 spin_unlock(&file_priv->mm.lock);
4120 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4122 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4124 mutex_lock(&dev->struct_mutex);
4125 i915_gem_request_unreference(target);
4126 mutex_unlock(&dev->struct_mutex);
4132 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4134 struct drm_i915_gem_object *obj = vma->obj;
4137 vma->node.start & (alignment - 1))
4140 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4143 if (flags & PIN_OFFSET_BIAS &&
4144 vma->node.start < (flags & PIN_OFFSET_MASK))
4151 i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
4152 struct i915_address_space *vm,
4155 const struct i915_ggtt_view *view)
4157 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4158 struct i915_vma *vma;
4162 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4165 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4168 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4171 vma = i915_gem_obj_to_vma_view(obj, vm, view);
4173 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4176 if (i915_vma_misplaced(vma, alignment, flags)) {
4177 WARN(vma->pin_count,
4178 "bo is already pinned with incorrect alignment:"
4179 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4180 " obj->map_and_fenceable=%d\n",
4181 i915_gem_obj_offset_view(obj, vm, view->type),
4183 !!(flags & PIN_MAPPABLE),
4184 obj->map_and_fenceable);
4185 ret = i915_vma_unbind(vma);
4193 bound = vma ? vma->bound : 0;
4194 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4195 vma = i915_gem_object_bind_to_vm(obj, vm, alignment,
4198 return PTR_ERR(vma);
4201 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) {
4202 ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
4207 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4208 bool mappable, fenceable;
4209 u32 fence_size, fence_alignment;
4211 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4214 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4219 fenceable = (vma->node.size == fence_size &&
4220 (vma->node.start & (fence_alignment - 1)) == 0);
4222 mappable = (vma->node.start + obj->base.size <=
4223 dev_priv->gtt.mappable_end);
4225 obj->map_and_fenceable = mappable && fenceable;
4228 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4231 if (flags & PIN_MAPPABLE)
4232 obj->pin_mappable |= true;
4238 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4240 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4243 BUG_ON(vma->pin_count == 0);
4244 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4246 if (--vma->pin_count == 0)
4247 obj->pin_mappable = false;
4251 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4253 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4254 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4255 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4257 WARN_ON(!ggtt_vma ||
4258 dev_priv->fence_regs[obj->fence_reg].pin_count >
4259 ggtt_vma->pin_count);
4260 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4267 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4269 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4270 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4271 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4272 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4277 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4278 struct drm_file *file)
4280 struct drm_i915_gem_busy *args = data;
4281 struct drm_i915_gem_object *obj;
4284 ret = i915_mutex_lock_interruptible(dev);
4288 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4289 if (&obj->base == NULL) {
4294 /* Count all active objects as busy, even if they are currently not used
4295 * by the gpu. Users of this interface expect objects to eventually
4296 * become non-busy without any further actions, therefore emit any
4297 * necessary flushes here.
4299 ret = i915_gem_object_flush_active(obj);
4301 args->busy = obj->active;
4302 if (obj->last_read_req) {
4303 struct intel_engine_cs *ring;
4304 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4305 ring = i915_gem_request_get_ring(obj->last_read_req);
4306 args->busy |= intel_ring_flag(ring) << 16;
4309 drm_gem_object_unreference(&obj->base);
4311 mutex_unlock(&dev->struct_mutex);
4316 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4317 struct drm_file *file_priv)
4319 return i915_gem_ring_throttle(dev, file_priv);
4323 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4324 struct drm_file *file_priv)
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 struct drm_i915_gem_madvise *args = data;
4328 struct drm_i915_gem_object *obj;
4331 switch (args->madv) {
4332 case I915_MADV_DONTNEED:
4333 case I915_MADV_WILLNEED:
4339 ret = i915_mutex_lock_interruptible(dev);
4343 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4344 if (&obj->base == NULL) {
4349 if (i915_gem_obj_is_pinned(obj)) {
4355 obj->tiling_mode != I915_TILING_NONE &&
4356 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4357 if (obj->madv == I915_MADV_WILLNEED)
4358 i915_gem_object_unpin_pages(obj);
4359 if (args->madv == I915_MADV_WILLNEED)
4360 i915_gem_object_pin_pages(obj);
4363 if (obj->madv != __I915_MADV_PURGED)
4364 obj->madv = args->madv;
4366 /* if the object is no longer attached, discard its backing storage */
4367 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4368 i915_gem_object_truncate(obj);
4370 args->retained = obj->madv != __I915_MADV_PURGED;
4373 drm_gem_object_unreference(&obj->base);
4375 mutex_unlock(&dev->struct_mutex);
4379 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4380 const struct drm_i915_gem_object_ops *ops)
4382 INIT_LIST_HEAD(&obj->global_list);
4383 INIT_LIST_HEAD(&obj->ring_list);
4384 INIT_LIST_HEAD(&obj->obj_exec_link);
4385 INIT_LIST_HEAD(&obj->vma_list);
4386 INIT_LIST_HEAD(&obj->batch_pool_list);
4390 obj->fence_reg = I915_FENCE_REG_NONE;
4391 obj->madv = I915_MADV_WILLNEED;
4393 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4396 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4397 .get_pages = i915_gem_object_get_pages_gtt,
4398 .put_pages = i915_gem_object_put_pages_gtt,
4401 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4404 struct drm_i915_gem_object *obj;
4405 struct address_space *mapping;
4408 obj = i915_gem_object_alloc(dev);
4412 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4413 i915_gem_object_free(obj);
4417 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4418 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4419 /* 965gm cannot relocate objects above 4GiB. */
4420 mask &= ~__GFP_HIGHMEM;
4421 mask |= __GFP_DMA32;
4424 mapping = file_inode(obj->base.filp)->i_mapping;
4425 mapping_set_gfp_mask(mapping, mask);
4427 i915_gem_object_init(obj, &i915_gem_object_ops);
4429 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4430 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4433 /* On some devices, we can have the GPU use the LLC (the CPU
4434 * cache) for about a 10% performance improvement
4435 * compared to uncached. Graphics requests other than
4436 * display scanout are coherent with the CPU in
4437 * accessing this cache. This means in this mode we
4438 * don't need to clflush on the CPU side, and on the
4439 * GPU side we only need to flush internal caches to
4440 * get data visible to the CPU.
4442 * However, we maintain the display planes as UC, and so
4443 * need to rebind when first used as such.
4445 obj->cache_level = I915_CACHE_LLC;
4447 obj->cache_level = I915_CACHE_NONE;
4449 trace_i915_gem_object_create(obj);
4454 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4456 /* If we are the last user of the backing storage (be it shmemfs
4457 * pages or stolen etc), we know that the pages are going to be
4458 * immediately released. In this case, we can then skip copying
4459 * back the contents from the GPU.
4462 if (obj->madv != I915_MADV_WILLNEED)
4465 if (obj->base.filp == NULL)
4468 /* At first glance, this looks racy, but then again so would be
4469 * userspace racing mmap against close. However, the first external
4470 * reference to the filp can only be obtained through the
4471 * i915_gem_mmap_ioctl() which safeguards us against the user
4472 * acquiring such a reference whilst we are in the middle of
4473 * freeing the object.
4475 return atomic_long_read(&obj->base.filp->f_count) == 1;
4478 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4480 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4481 struct drm_device *dev = obj->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 struct i915_vma *vma, *next;
4485 intel_runtime_pm_get(dev_priv);
4487 trace_i915_gem_object_destroy(obj);
4489 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4493 ret = i915_vma_unbind(vma);
4494 if (WARN_ON(ret == -ERESTARTSYS)) {
4495 bool was_interruptible;
4497 was_interruptible = dev_priv->mm.interruptible;
4498 dev_priv->mm.interruptible = false;
4500 WARN_ON(i915_vma_unbind(vma));
4502 dev_priv->mm.interruptible = was_interruptible;
4506 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4507 * before progressing. */
4509 i915_gem_object_unpin_pages(obj);
4511 WARN_ON(obj->frontbuffer_bits);
4513 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4514 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4515 obj->tiling_mode != I915_TILING_NONE)
4516 i915_gem_object_unpin_pages(obj);
4518 if (WARN_ON(obj->pages_pin_count))
4519 obj->pages_pin_count = 0;
4520 if (discard_backing_storage(obj))
4521 obj->madv = I915_MADV_DONTNEED;
4522 i915_gem_object_put_pages(obj);
4523 i915_gem_object_free_mmap_offset(obj);
4527 if (obj->base.import_attach)
4528 drm_prime_gem_destroy(&obj->base, NULL);
4530 if (obj->ops->release)
4531 obj->ops->release(obj);
4533 drm_gem_object_release(&obj->base);
4534 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4537 i915_gem_object_free(obj);
4539 intel_runtime_pm_put(dev_priv);
4542 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
4543 struct i915_address_space *vm,
4544 const struct i915_ggtt_view *view)
4546 struct i915_vma *vma;
4547 list_for_each_entry(vma, &obj->vma_list, vma_link)
4548 if (vma->vm == vm && vma->ggtt_view.type == view->type)
4554 void i915_gem_vma_destroy(struct i915_vma *vma)
4556 struct i915_address_space *vm = NULL;
4557 WARN_ON(vma->node.allocated);
4559 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4560 if (!list_empty(&vma->exec_list))
4565 if (!i915_is_ggtt(vm))
4566 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4568 list_del(&vma->vma_link);
4574 i915_gem_stop_ringbuffers(struct drm_device *dev)
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct intel_engine_cs *ring;
4580 for_each_ring(ring, dev_priv, i)
4581 dev_priv->gt.stop_ring(ring);
4585 i915_gem_suspend(struct drm_device *dev)
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4590 mutex_lock(&dev->struct_mutex);
4591 ret = i915_gpu_idle(dev);
4595 i915_gem_retire_requests(dev);
4597 i915_gem_stop_ringbuffers(dev);
4598 mutex_unlock(&dev->struct_mutex);
4600 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4601 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4602 flush_delayed_work(&dev_priv->mm.idle_work);
4604 /* Assert that we sucessfully flushed all the work and
4605 * reset the GPU back to its idle, low power state.
4607 WARN_ON(dev_priv->mm.busy);
4612 mutex_unlock(&dev->struct_mutex);
4616 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4618 struct drm_device *dev = ring->dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4621 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4624 if (!HAS_L3_DPF(dev) || !remap_info)
4627 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4632 * Note: We do not worry about the concurrent register cacheline hang
4633 * here because no other code should access these registers other than
4634 * at initialization time.
4636 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4637 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4638 intel_ring_emit(ring, reg_base + i);
4639 intel_ring_emit(ring, remap_info[i/4]);
4642 intel_ring_advance(ring);
4647 void i915_gem_init_swizzling(struct drm_device *dev)
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4651 if (INTEL_INFO(dev)->gen < 5 ||
4652 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4655 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4656 DISP_TILE_SURFACE_SWIZZLING);
4661 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4663 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4664 else if (IS_GEN7(dev))
4665 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4666 else if (IS_GEN8(dev))
4667 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4673 intel_enable_blt(struct drm_device *dev)
4678 /* The blitter was dysfunctional on early prototypes */
4679 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4680 DRM_INFO("BLT not supported on this pre-production hardware;"
4681 " graphics performance will be degraded.\n");
4688 static void init_unused_ring(struct drm_device *dev, u32 base)
4690 struct drm_i915_private *dev_priv = dev->dev_private;
4692 I915_WRITE(RING_CTL(base), 0);
4693 I915_WRITE(RING_HEAD(base), 0);
4694 I915_WRITE(RING_TAIL(base), 0);
4695 I915_WRITE(RING_START(base), 0);
4698 static void init_unused_rings(struct drm_device *dev)
4701 init_unused_ring(dev, PRB1_BASE);
4702 init_unused_ring(dev, SRB0_BASE);
4703 init_unused_ring(dev, SRB1_BASE);
4704 init_unused_ring(dev, SRB2_BASE);
4705 init_unused_ring(dev, SRB3_BASE);
4706 } else if (IS_GEN2(dev)) {
4707 init_unused_ring(dev, SRB0_BASE);
4708 init_unused_ring(dev, SRB1_BASE);
4709 } else if (IS_GEN3(dev)) {
4710 init_unused_ring(dev, PRB1_BASE);
4711 init_unused_ring(dev, PRB2_BASE);
4715 int i915_gem_init_rings(struct drm_device *dev)
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4720 ret = intel_init_render_ring_buffer(dev);
4725 ret = intel_init_bsd_ring_buffer(dev);
4727 goto cleanup_render_ring;
4730 if (intel_enable_blt(dev)) {
4731 ret = intel_init_blt_ring_buffer(dev);
4733 goto cleanup_bsd_ring;
4736 if (HAS_VEBOX(dev)) {
4737 ret = intel_init_vebox_ring_buffer(dev);
4739 goto cleanup_blt_ring;
4742 if (HAS_BSD2(dev)) {
4743 ret = intel_init_bsd2_ring_buffer(dev);
4745 goto cleanup_vebox_ring;
4748 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4750 goto cleanup_bsd2_ring;
4755 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4757 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4759 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4761 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4762 cleanup_render_ring:
4763 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4769 i915_gem_init_hw(struct drm_device *dev)
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4772 struct intel_engine_cs *ring;
4775 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4778 if (dev_priv->ellc_size)
4779 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4781 if (IS_HASWELL(dev))
4782 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4783 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4785 if (HAS_PCH_NOP(dev)) {
4786 if (IS_IVYBRIDGE(dev)) {
4787 u32 temp = I915_READ(GEN7_MSG_CTL);
4788 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4789 I915_WRITE(GEN7_MSG_CTL, temp);
4790 } else if (INTEL_INFO(dev)->gen >= 7) {
4791 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4792 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4793 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4797 i915_gem_init_swizzling(dev);
4800 * At least 830 can leave some of the unused rings
4801 * "active" (ie. head != tail) after resume which
4802 * will prevent c3 entry. Makes sure all unused rings
4805 init_unused_rings(dev);
4807 for_each_ring(ring, dev_priv, i) {
4808 ret = ring->init_hw(ring);
4813 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4814 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4817 * XXX: Contexts should only be initialized once. Doing a switch to the
4818 * default context switch however is something we'd like to do after
4819 * reset or thaw (the latter may not actually be necessary for HW, but
4820 * goes with our code better). Context switching requires rings (for
4821 * the do_switch), but before enabling PPGTT. So don't move this.
4823 ret = i915_gem_context_enable(dev_priv);
4824 if (ret && ret != -EIO) {
4825 DRM_ERROR("Context enable failed %d\n", ret);
4826 i915_gem_cleanup_ringbuffer(dev);
4831 ret = i915_ppgtt_init_hw(dev);
4832 if (ret && ret != -EIO) {
4833 DRM_ERROR("PPGTT enable failed %d\n", ret);
4834 i915_gem_cleanup_ringbuffer(dev);
4840 int i915_gem_init(struct drm_device *dev)
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4845 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4846 i915.enable_execlists);
4848 mutex_lock(&dev->struct_mutex);
4850 if (IS_VALLEYVIEW(dev)) {
4851 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4852 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4853 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4854 VLV_GTLC_ALLOWWAKEACK), 10))
4855 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4858 if (!i915.enable_execlists) {
4859 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4860 dev_priv->gt.init_rings = i915_gem_init_rings;
4861 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4862 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4864 dev_priv->gt.do_execbuf = intel_execlists_submission;
4865 dev_priv->gt.init_rings = intel_logical_rings_init;
4866 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4867 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4870 ret = i915_gem_init_userptr(dev);
4874 i915_gem_init_global_gtt(dev);
4876 ret = i915_gem_context_init(dev);
4880 ret = dev_priv->gt.init_rings(dev);
4884 ret = i915_gem_init_hw(dev);
4886 /* Allow ring initialisation to fail by marking the GPU as
4887 * wedged. But we only want to do this where the GPU is angry,
4888 * for all other failure, such as an allocation failure, bail.
4890 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4891 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4896 mutex_unlock(&dev->struct_mutex);
4902 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4905 struct intel_engine_cs *ring;
4908 for_each_ring(ring, dev_priv, i)
4909 dev_priv->gt.cleanup_ring(ring);
4913 init_ring_lists(struct intel_engine_cs *ring)
4915 INIT_LIST_HEAD(&ring->active_list);
4916 INIT_LIST_HEAD(&ring->request_list);
4919 void i915_init_vm(struct drm_i915_private *dev_priv,
4920 struct i915_address_space *vm)
4922 if (!i915_is_ggtt(vm))
4923 drm_mm_init(&vm->mm, vm->start, vm->total);
4924 vm->dev = dev_priv->dev;
4925 INIT_LIST_HEAD(&vm->active_list);
4926 INIT_LIST_HEAD(&vm->inactive_list);
4927 INIT_LIST_HEAD(&vm->global_link);
4928 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4932 i915_gem_load(struct drm_device *dev)
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4938 kmem_cache_create("i915_gem_object",
4939 sizeof(struct drm_i915_gem_object), 0,
4943 INIT_LIST_HEAD(&dev_priv->vm_list);
4944 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4946 INIT_LIST_HEAD(&dev_priv->context_list);
4947 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4948 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4949 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4950 for (i = 0; i < I915_NUM_RINGS; i++)
4951 init_ring_lists(&dev_priv->ring[i]);
4952 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4953 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4954 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4955 i915_gem_retire_work_handler);
4956 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4957 i915_gem_idle_work_handler);
4958 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4960 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4962 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4963 dev_priv->num_fence_regs = 32;
4964 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4965 dev_priv->num_fence_regs = 16;
4967 dev_priv->num_fence_regs = 8;
4969 if (intel_vgpu_active(dev))
4970 dev_priv->num_fence_regs =
4971 I915_READ(vgtif_reg(avail_rs.fence_num));
4973 /* Initialize fence registers to zero */
4974 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4975 i915_gem_restore_fences(dev);
4977 i915_gem_detect_bit_6_swizzle(dev);
4978 init_waitqueue_head(&dev_priv->pending_flip_queue);
4980 dev_priv->mm.interruptible = true;
4982 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4983 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4984 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4985 register_shrinker(&dev_priv->mm.shrinker);
4987 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4988 register_oom_notifier(&dev_priv->mm.oom_notifier);
4990 i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool);
4992 mutex_init(&dev_priv->fb_tracking.lock);
4995 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4997 struct drm_i915_file_private *file_priv = file->driver_priv;
4999 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5001 /* Clean up our request list when the client is going away, so that
5002 * later retire_requests won't dereference our soon-to-be-gone
5005 spin_lock(&file_priv->mm.lock);
5006 while (!list_empty(&file_priv->mm.request_list)) {
5007 struct drm_i915_gem_request *request;
5009 request = list_first_entry(&file_priv->mm.request_list,
5010 struct drm_i915_gem_request,
5012 list_del(&request->client_list);
5013 request->file_priv = NULL;
5015 spin_unlock(&file_priv->mm.lock);
5019 i915_gem_file_idle_work_handler(struct work_struct *work)
5021 struct drm_i915_file_private *file_priv =
5022 container_of(work, typeof(*file_priv), mm.idle_work.work);
5024 atomic_set(&file_priv->rps_wait_boost, false);
5027 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5029 struct drm_i915_file_private *file_priv;
5032 DRM_DEBUG_DRIVER("\n");
5034 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5038 file->driver_priv = file_priv;
5039 file_priv->dev_priv = dev->dev_private;
5040 file_priv->file = file;
5042 spin_lock_init(&file_priv->mm.lock);
5043 INIT_LIST_HEAD(&file_priv->mm.request_list);
5044 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5045 i915_gem_file_idle_work_handler);
5047 ret = i915_gem_context_open(dev, file);
5055 * i915_gem_track_fb - update frontbuffer tracking
5056 * old: current GEM buffer for the frontbuffer slots
5057 * new: new GEM buffer for the frontbuffer slots
5058 * frontbuffer_bits: bitmask of frontbuffer slots
5060 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5061 * from @old and setting them in @new. Both @old and @new can be NULL.
5063 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5064 struct drm_i915_gem_object *new,
5065 unsigned frontbuffer_bits)
5068 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5069 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5070 old->frontbuffer_bits &= ~frontbuffer_bits;
5074 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5075 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5076 new->frontbuffer_bits |= frontbuffer_bits;
5080 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5082 if (!mutex_is_locked(mutex))
5085 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5086 return mutex->owner == task;
5088 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5093 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5095 if (!mutex_trylock(&dev->struct_mutex)) {
5096 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5099 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5109 static int num_vma_bound(struct drm_i915_gem_object *obj)
5111 struct i915_vma *vma;
5114 list_for_each_entry(vma, &obj->vma_list, vma_link)
5115 if (drm_mm_node_allocated(&vma->node))
5121 static unsigned long
5122 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5124 struct drm_i915_private *dev_priv =
5125 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5126 struct drm_device *dev = dev_priv->dev;
5127 struct drm_i915_gem_object *obj;
5128 unsigned long count;
5131 if (!i915_gem_shrinker_lock(dev, &unlock))
5135 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5136 if (obj->pages_pin_count == 0)
5137 count += obj->base.size >> PAGE_SHIFT;
5139 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5140 if (!i915_gem_obj_is_pinned(obj) &&
5141 obj->pages_pin_count == num_vma_bound(obj))
5142 count += obj->base.size >> PAGE_SHIFT;
5146 mutex_unlock(&dev->struct_mutex);
5151 /* All the new VM stuff */
5152 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
5153 struct i915_address_space *vm,
5154 enum i915_ggtt_view_type view)
5156 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5157 struct i915_vma *vma;
5159 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5161 list_for_each_entry(vma, &o->vma_list, vma_link) {
5162 if (vma->vm == vm && vma->ggtt_view.type == view)
5163 return vma->node.start;
5166 WARN(1, "%s vma for this object not found.\n",
5167 i915_is_ggtt(vm) ? "global" : "ppgtt");
5171 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
5172 struct i915_address_space *vm,
5173 enum i915_ggtt_view_type view)
5175 struct i915_vma *vma;
5177 list_for_each_entry(vma, &o->vma_list, vma_link)
5178 if (vma->vm == vm &&
5179 vma->ggtt_view.type == view &&
5180 drm_mm_node_allocated(&vma->node))
5186 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5188 struct i915_vma *vma;
5190 list_for_each_entry(vma, &o->vma_list, vma_link)
5191 if (drm_mm_node_allocated(&vma->node))
5197 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5198 struct i915_address_space *vm)
5200 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5201 struct i915_vma *vma;
5203 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5205 BUG_ON(list_empty(&o->vma_list));
5207 list_for_each_entry(vma, &o->vma_list, vma_link)
5209 return vma->node.size;
5214 static unsigned long
5215 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5217 struct drm_i915_private *dev_priv =
5218 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5219 struct drm_device *dev = dev_priv->dev;
5220 unsigned long freed;
5223 if (!i915_gem_shrinker_lock(dev, &unlock))
5226 freed = i915_gem_shrink(dev_priv,
5229 I915_SHRINK_UNBOUND |
5230 I915_SHRINK_PURGEABLE);
5231 if (freed < sc->nr_to_scan)
5232 freed += i915_gem_shrink(dev_priv,
5233 sc->nr_to_scan - freed,
5235 I915_SHRINK_UNBOUND);
5237 mutex_unlock(&dev->struct_mutex);
5243 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5245 struct drm_i915_private *dev_priv =
5246 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5247 struct drm_device *dev = dev_priv->dev;
5248 struct drm_i915_gem_object *obj;
5249 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5250 unsigned long pinned, bound, unbound, freed_pages;
5251 bool was_interruptible;
5254 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5255 schedule_timeout_killable(1);
5256 if (fatal_signal_pending(current))
5260 pr_err("Unable to purge GPU memory due lock contention.\n");
5264 was_interruptible = dev_priv->mm.interruptible;
5265 dev_priv->mm.interruptible = false;
5267 freed_pages = i915_gem_shrink_all(dev_priv);
5269 dev_priv->mm.interruptible = was_interruptible;
5271 /* Because we may be allocating inside our own driver, we cannot
5272 * assert that there are no objects with pinned pages that are not
5273 * being pointed to by hardware.
5275 unbound = bound = pinned = 0;
5276 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5277 if (!obj->base.filp) /* not backed by a freeable object */
5280 if (obj->pages_pin_count)
5281 pinned += obj->base.size;
5283 unbound += obj->base.size;
5285 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5286 if (!obj->base.filp)
5289 if (obj->pages_pin_count)
5290 pinned += obj->base.size;
5292 bound += obj->base.size;
5296 mutex_unlock(&dev->struct_mutex);
5298 if (freed_pages || unbound || bound)
5299 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5300 freed_pages << PAGE_SHIFT, pinned);
5301 if (unbound || bound)
5302 pr_err("%lu and %lu bytes still available in the "
5303 "bound and unbound GPU page lists.\n",
5306 *(unsigned long *)ptr += freed_pages;
5310 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5312 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5313 struct i915_vma *vma;
5315 list_for_each_entry(vma, &obj->vma_list, vma_link)
5316 if (vma->vm == ggtt &&
5317 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)