2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_get_aperture *args = data;
168 struct drm_i915_gem_object *obj;
172 mutex_lock(&dev->struct_mutex);
173 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
174 if (i915_gem_obj_is_pinned(obj))
175 pinned += i915_gem_obj_ggtt_size(obj);
176 mutex_unlock(&dev->struct_mutex);
178 args->aper_size = dev_priv->gtt.base.total;
179 args->aper_available_size = args->aper_size - pinned;
185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
187 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
188 char *vaddr = obj->phys_handle->vaddr;
190 struct scatterlist *sg;
193 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
196 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
200 page = shmem_read_mapping_page(mapping, i);
202 return PTR_ERR(page);
204 src = kmap_atomic(page);
205 memcpy(vaddr, src, PAGE_SIZE);
206 drm_clflush_virt_range(vaddr, PAGE_SIZE);
209 page_cache_release(page);
213 i915_gem_chipset_flush(obj->base.dev);
215 st = kmalloc(sizeof(*st), GFP_KERNEL);
219 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
226 sg->length = obj->base.size;
228 sg_dma_address(sg) = obj->phys_handle->busaddr;
229 sg_dma_len(sg) = obj->base.size;
232 obj->has_dma_mapping = true;
237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
241 BUG_ON(obj->madv == __I915_MADV_PURGED);
243 ret = i915_gem_object_set_to_cpu_domain(obj, true);
245 /* In the event of a disaster, abandon all caches and
248 WARN_ON(ret != -EIO);
249 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
252 if (obj->madv == I915_MADV_DONTNEED)
256 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
257 char *vaddr = obj->phys_handle->vaddr;
260 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
264 page = shmem_read_mapping_page(mapping, i);
268 dst = kmap_atomic(page);
269 drm_clflush_virt_range(vaddr, PAGE_SIZE);
270 memcpy(dst, vaddr, PAGE_SIZE);
273 set_page_dirty(page);
274 if (obj->madv == I915_MADV_WILLNEED)
275 mark_page_accessed(page);
276 page_cache_release(page);
282 sg_free_table(obj->pages);
285 obj->has_dma_mapping = false;
289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
291 drm_pci_free(obj->base.dev, obj->phys_handle);
294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
295 .get_pages = i915_gem_object_get_pages_phys,
296 .put_pages = i915_gem_object_put_pages_phys,
297 .release = i915_gem_object_release_phys,
301 drop_pages(struct drm_i915_gem_object *obj)
303 struct i915_vma *vma, *next;
306 drm_gem_object_reference(&obj->base);
307 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
308 if (i915_vma_unbind(vma))
311 ret = i915_gem_object_put_pages(obj);
312 drm_gem_object_unreference(&obj->base);
318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
321 drm_dma_handle_t *phys;
324 if (obj->phys_handle) {
325 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
331 if (obj->madv != I915_MADV_WILLNEED)
334 if (obj->base.filp == NULL)
337 ret = drop_pages(obj);
341 /* create a new object */
342 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
346 obj->phys_handle = phys;
347 obj->ops = &i915_gem_phys_ops;
349 return i915_gem_object_get_pages(obj);
353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
354 struct drm_i915_gem_pwrite *args,
355 struct drm_file *file_priv)
357 struct drm_device *dev = obj->base.dev;
358 void *vaddr = obj->phys_handle->vaddr + args->offset;
359 char __user *user_data = to_user_ptr(args->data_ptr);
362 /* We manually control the domain here and pretend that it
363 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
365 ret = i915_gem_object_wait_rendering(obj, false);
369 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
370 unsigned long unwritten;
372 /* The physical object once assigned is fixed for the lifetime
373 * of the obj, so we can safely drop the lock and continue
376 mutex_unlock(&dev->struct_mutex);
377 unwritten = copy_from_user(vaddr, user_data, args->size);
378 mutex_lock(&dev->struct_mutex);
383 drm_clflush_virt_range(vaddr, args->size);
384 i915_gem_chipset_flush(dev);
388 void *i915_gem_object_alloc(struct drm_device *dev)
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
396 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
397 kmem_cache_free(dev_priv->slab, obj);
401 i915_gem_create(struct drm_file *file,
402 struct drm_device *dev,
407 struct drm_i915_gem_object *obj;
411 size = roundup(size, PAGE_SIZE);
415 /* Allocate the new object */
416 obj = i915_gem_alloc_object(dev, size);
420 obj->base.dumb = dumb;
421 ret = drm_gem_handle_create(file, &obj->base, &handle);
422 /* drop reference from allocate - handle holds it now */
423 drm_gem_object_unreference_unlocked(&obj->base);
432 i915_gem_dumb_create(struct drm_file *file,
433 struct drm_device *dev,
434 struct drm_mode_create_dumb *args)
436 /* have to work out size/pitch and return them */
437 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
438 args->size = args->pitch * args->height;
439 return i915_gem_create(file, dev,
440 args->size, true, &args->handle);
444 * Creates a new mm object and returns a handle to it.
447 i915_gem_create_ioctl(struct drm_device *dev, void *data,
448 struct drm_file *file)
450 struct drm_i915_gem_create *args = data;
452 return i915_gem_create(file, dev,
453 args->size, false, &args->handle);
457 __copy_to_user_swizzled(char __user *cpu_vaddr,
458 const char *gpu_vaddr, int gpu_offset,
461 int ret, cpu_offset = 0;
464 int cacheline_end = ALIGN(gpu_offset + 1, 64);
465 int this_length = min(cacheline_end - gpu_offset, length);
466 int swizzled_gpu_offset = gpu_offset ^ 64;
468 ret = __copy_to_user(cpu_vaddr + cpu_offset,
469 gpu_vaddr + swizzled_gpu_offset,
474 cpu_offset += this_length;
475 gpu_offset += this_length;
476 length -= this_length;
483 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
484 const char __user *cpu_vaddr,
487 int ret, cpu_offset = 0;
490 int cacheline_end = ALIGN(gpu_offset + 1, 64);
491 int this_length = min(cacheline_end - gpu_offset, length);
492 int swizzled_gpu_offset = gpu_offset ^ 64;
494 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
495 cpu_vaddr + cpu_offset,
500 cpu_offset += this_length;
501 gpu_offset += this_length;
502 length -= this_length;
509 * Pins the specified object's pages and synchronizes the object with
510 * GPU accesses. Sets needs_clflush to non-zero if the caller should
511 * flush the object from the CPU cache.
513 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
523 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
524 /* If we're not in the cpu read domain, set ourself into the gtt
525 * read domain and manually flush cachelines (if required). This
526 * optimizes for the case when the gpu will dirty the data
527 * anyway again before the next pread happens. */
528 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
530 ret = i915_gem_object_wait_rendering(obj, true);
534 i915_gem_object_retire(obj);
537 ret = i915_gem_object_get_pages(obj);
541 i915_gem_object_pin_pages(obj);
546 /* Per-page copy function for the shmem pread fastpath.
547 * Flushes invalid cachelines before reading the target if
548 * needs_clflush is set. */
550 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
551 char __user *user_data,
552 bool page_do_bit17_swizzling, bool needs_clflush)
557 if (unlikely(page_do_bit17_swizzling))
560 vaddr = kmap_atomic(page);
562 drm_clflush_virt_range(vaddr + shmem_page_offset,
564 ret = __copy_to_user_inatomic(user_data,
565 vaddr + shmem_page_offset,
567 kunmap_atomic(vaddr);
569 return ret ? -EFAULT : 0;
573 shmem_clflush_swizzled_range(char *addr, unsigned long length,
576 if (unlikely(swizzled)) {
577 unsigned long start = (unsigned long) addr;
578 unsigned long end = (unsigned long) addr + length;
580 /* For swizzling simply ensure that we always flush both
581 * channels. Lame, but simple and it works. Swizzled
582 * pwrite/pread is far from a hotpath - current userspace
583 * doesn't use it at all. */
584 start = round_down(start, 128);
585 end = round_up(end, 128);
587 drm_clflush_virt_range((void *)start, end - start);
589 drm_clflush_virt_range(addr, length);
594 /* Only difference to the fast-path function is that this can handle bit17
595 * and uses non-atomic copy and kmap functions. */
597 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
598 char __user *user_data,
599 bool page_do_bit17_swizzling, bool needs_clflush)
606 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
608 page_do_bit17_swizzling);
610 if (page_do_bit17_swizzling)
611 ret = __copy_to_user_swizzled(user_data,
612 vaddr, shmem_page_offset,
615 ret = __copy_to_user(user_data,
616 vaddr + shmem_page_offset,
620 return ret ? - EFAULT : 0;
624 i915_gem_shmem_pread(struct drm_device *dev,
625 struct drm_i915_gem_object *obj,
626 struct drm_i915_gem_pread *args,
627 struct drm_file *file)
629 char __user *user_data;
632 int shmem_page_offset, page_length, ret = 0;
633 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
635 int needs_clflush = 0;
636 struct sg_page_iter sg_iter;
638 user_data = to_user_ptr(args->data_ptr);
641 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
643 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
647 offset = args->offset;
649 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
650 offset >> PAGE_SHIFT) {
651 struct page *page = sg_page_iter_page(&sg_iter);
656 /* Operation in this page
658 * shmem_page_offset = offset within page in shmem file
659 * page_length = bytes to copy for this page
661 shmem_page_offset = offset_in_page(offset);
662 page_length = remain;
663 if ((shmem_page_offset + page_length) > PAGE_SIZE)
664 page_length = PAGE_SIZE - shmem_page_offset;
666 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
667 (page_to_phys(page) & (1 << 17)) != 0;
669 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
670 user_data, page_do_bit17_swizzling,
675 mutex_unlock(&dev->struct_mutex);
677 if (likely(!i915.prefault_disable) && !prefaulted) {
678 ret = fault_in_multipages_writeable(user_data, remain);
679 /* Userspace is tricking us, but we've already clobbered
680 * its pages with the prefault and promised to write the
681 * data up to the first fault. Hence ignore any errors
682 * and just continue. */
687 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
688 user_data, page_do_bit17_swizzling,
691 mutex_lock(&dev->struct_mutex);
697 remain -= page_length;
698 user_data += page_length;
699 offset += page_length;
703 i915_gem_object_unpin_pages(obj);
709 * Reads data from the object referenced by handle.
711 * On error, the contents of *data are undefined.
714 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *file)
717 struct drm_i915_gem_pread *args = data;
718 struct drm_i915_gem_object *obj;
724 if (!access_ok(VERIFY_WRITE,
725 to_user_ptr(args->data_ptr),
729 ret = i915_mutex_lock_interruptible(dev);
733 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
734 if (&obj->base == NULL) {
739 /* Bounds check source. */
740 if (args->offset > obj->base.size ||
741 args->size > obj->base.size - args->offset) {
746 /* prime objects have no backing filp to GEM pread/pwrite
749 if (!obj->base.filp) {
754 trace_i915_gem_object_pread(obj, args->offset, args->size);
756 ret = i915_gem_shmem_pread(dev, obj, args, file);
759 drm_gem_object_unreference(&obj->base);
761 mutex_unlock(&dev->struct_mutex);
765 /* This is the fast write path which cannot handle
766 * page faults in the source data
770 fast_user_write(struct io_mapping *mapping,
771 loff_t page_base, int page_offset,
772 char __user *user_data,
775 void __iomem *vaddr_atomic;
777 unsigned long unwritten;
779 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
780 /* We can use the cpu mem copy function because this is X86. */
781 vaddr = (void __force*)vaddr_atomic + page_offset;
782 unwritten = __copy_from_user_inatomic_nocache(vaddr,
784 io_mapping_unmap_atomic(vaddr_atomic);
789 * This is the fast pwrite path, where we copy the data directly from the
790 * user into the GTT, uncached.
793 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
794 struct drm_i915_gem_object *obj,
795 struct drm_i915_gem_pwrite *args,
796 struct drm_file *file)
798 struct drm_i915_private *dev_priv = dev->dev_private;
800 loff_t offset, page_base;
801 char __user *user_data;
802 int page_offset, page_length, ret;
804 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
808 ret = i915_gem_object_set_to_gtt_domain(obj, true);
812 ret = i915_gem_object_put_fence(obj);
816 user_data = to_user_ptr(args->data_ptr);
819 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
822 /* Operation in this page
824 * page_base = page offset within aperture
825 * page_offset = offset within page
826 * page_length = bytes to copy for this page
828 page_base = offset & PAGE_MASK;
829 page_offset = offset_in_page(offset);
830 page_length = remain;
831 if ((page_offset + remain) > PAGE_SIZE)
832 page_length = PAGE_SIZE - page_offset;
834 /* If we get a fault while copying data, then (presumably) our
835 * source page isn't available. Return the error and we'll
836 * retry in the slow path.
838 if (fast_user_write(dev_priv->gtt.mappable, page_base,
839 page_offset, user_data, page_length)) {
844 remain -= page_length;
845 user_data += page_length;
846 offset += page_length;
850 i915_gem_object_ggtt_unpin(obj);
855 /* Per-page copy function for the shmem pwrite fastpath.
856 * Flushes invalid cachelines before writing to the target if
857 * needs_clflush_before is set and flushes out any written cachelines after
858 * writing if needs_clflush is set. */
860 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
861 char __user *user_data,
862 bool page_do_bit17_swizzling,
863 bool needs_clflush_before,
864 bool needs_clflush_after)
869 if (unlikely(page_do_bit17_swizzling))
872 vaddr = kmap_atomic(page);
873 if (needs_clflush_before)
874 drm_clflush_virt_range(vaddr + shmem_page_offset,
876 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
877 user_data, page_length);
878 if (needs_clflush_after)
879 drm_clflush_virt_range(vaddr + shmem_page_offset,
881 kunmap_atomic(vaddr);
883 return ret ? -EFAULT : 0;
886 /* Only difference to the fast-path function is that this can handle bit17
887 * and uses non-atomic copy and kmap functions. */
889 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
890 char __user *user_data,
891 bool page_do_bit17_swizzling,
892 bool needs_clflush_before,
893 bool needs_clflush_after)
899 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
900 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
902 page_do_bit17_swizzling);
903 if (page_do_bit17_swizzling)
904 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
908 ret = __copy_from_user(vaddr + shmem_page_offset,
911 if (needs_clflush_after)
912 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
914 page_do_bit17_swizzling);
917 return ret ? -EFAULT : 0;
921 i915_gem_shmem_pwrite(struct drm_device *dev,
922 struct drm_i915_gem_object *obj,
923 struct drm_i915_gem_pwrite *args,
924 struct drm_file *file)
928 char __user *user_data;
929 int shmem_page_offset, page_length, ret = 0;
930 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
931 int hit_slowpath = 0;
932 int needs_clflush_after = 0;
933 int needs_clflush_before = 0;
934 struct sg_page_iter sg_iter;
936 user_data = to_user_ptr(args->data_ptr);
939 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
941 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
942 /* If we're not in the cpu write domain, set ourself into the gtt
943 * write domain and manually flush cachelines (if required). This
944 * optimizes for the case when the gpu will use the data
945 * right away and we therefore have to clflush anyway. */
946 needs_clflush_after = cpu_write_needs_clflush(obj);
947 ret = i915_gem_object_wait_rendering(obj, false);
951 i915_gem_object_retire(obj);
953 /* Same trick applies to invalidate partially written cachelines read
955 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
956 needs_clflush_before =
957 !cpu_cache_is_coherent(dev, obj->cache_level);
959 ret = i915_gem_object_get_pages(obj);
963 i915_gem_object_pin_pages(obj);
965 offset = args->offset;
968 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
969 offset >> PAGE_SHIFT) {
970 struct page *page = sg_page_iter_page(&sg_iter);
971 int partial_cacheline_write;
976 /* Operation in this page
978 * shmem_page_offset = offset within page in shmem file
979 * page_length = bytes to copy for this page
981 shmem_page_offset = offset_in_page(offset);
983 page_length = remain;
984 if ((shmem_page_offset + page_length) > PAGE_SIZE)
985 page_length = PAGE_SIZE - shmem_page_offset;
987 /* If we don't overwrite a cacheline completely we need to be
988 * careful to have up-to-date data by first clflushing. Don't
989 * overcomplicate things and flush the entire patch. */
990 partial_cacheline_write = needs_clflush_before &&
991 ((shmem_page_offset | page_length)
992 & (boot_cpu_data.x86_clflush_size - 1));
994 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
995 (page_to_phys(page) & (1 << 17)) != 0;
997 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
998 user_data, page_do_bit17_swizzling,
999 partial_cacheline_write,
1000 needs_clflush_after);
1005 mutex_unlock(&dev->struct_mutex);
1006 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1007 user_data, page_do_bit17_swizzling,
1008 partial_cacheline_write,
1009 needs_clflush_after);
1011 mutex_lock(&dev->struct_mutex);
1017 remain -= page_length;
1018 user_data += page_length;
1019 offset += page_length;
1023 i915_gem_object_unpin_pages(obj);
1027 * Fixup: Flush cpu caches in case we didn't flush the dirty
1028 * cachelines in-line while writing and the object moved
1029 * out of the cpu write domain while we've dropped the lock.
1031 if (!needs_clflush_after &&
1032 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1033 if (i915_gem_clflush_object(obj, obj->pin_display))
1034 i915_gem_chipset_flush(dev);
1038 if (needs_clflush_after)
1039 i915_gem_chipset_flush(dev);
1045 * Writes data to the object referenced by handle.
1047 * On error, the contents of the buffer that were to be modified are undefined.
1050 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *file)
1053 struct drm_i915_gem_pwrite *args = data;
1054 struct drm_i915_gem_object *obj;
1057 if (args->size == 0)
1060 if (!access_ok(VERIFY_READ,
1061 to_user_ptr(args->data_ptr),
1065 if (likely(!i915.prefault_disable)) {
1066 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1072 ret = i915_mutex_lock_interruptible(dev);
1076 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1077 if (&obj->base == NULL) {
1082 /* Bounds check destination. */
1083 if (args->offset > obj->base.size ||
1084 args->size > obj->base.size - args->offset) {
1089 /* prime objects have no backing filp to GEM pread/pwrite
1092 if (!obj->base.filp) {
1097 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1100 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1101 * it would end up going through the fenced access, and we'll get
1102 * different detiling behavior between reading and writing.
1103 * pread/pwrite currently are reading and writing from the CPU
1104 * perspective, requiring manual detiling by the client.
1106 if (obj->tiling_mode == I915_TILING_NONE &&
1107 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1108 cpu_write_needs_clflush(obj)) {
1109 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1110 /* Note that the gtt paths might fail with non-page-backed user
1111 * pointers (e.g. gtt mappings when moving data between
1112 * textures). Fallback to the shmem path in that case. */
1115 if (ret == -EFAULT || ret == -ENOSPC) {
1116 if (obj->phys_handle)
1117 ret = i915_gem_phys_pwrite(obj, args, file);
1119 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1123 drm_gem_object_unreference(&obj->base);
1125 mutex_unlock(&dev->struct_mutex);
1130 i915_gem_check_wedge(struct i915_gpu_error *error,
1133 if (i915_reset_in_progress(error)) {
1134 /* Non-interruptible callers can't handle -EAGAIN, hence return
1135 * -EIO unconditionally for these. */
1139 /* Recovery complete, but the reset failed ... */
1140 if (i915_terminally_wedged(error))
1144 * Check if GPU Reset is in progress - we need intel_ring_begin
1145 * to work properly to reinit the hw state while the gpu is
1146 * still marked as reset-in-progress. Handle this with a flag.
1148 if (!error->reload_in_reset)
1156 * Compare arbitrary request against outstanding lazy request. Emit on match.
1159 i915_gem_check_olr(struct drm_i915_gem_request *req)
1163 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1166 if (req == req->ring->outstanding_lazy_request)
1167 ret = i915_add_request(req->ring);
1172 static void fake_irq(unsigned long data)
1174 wake_up_process((struct task_struct *)data);
1177 static bool missed_irq(struct drm_i915_private *dev_priv,
1178 struct intel_engine_cs *ring)
1180 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1183 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1185 if (file_priv == NULL)
1188 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1192 * __i915_wait_request - wait until execution of request has finished
1194 * @reset_counter: reset sequence associated with the given request
1195 * @interruptible: do an interruptible wait (normally yes)
1196 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1198 * Note: It is of utmost importance that the passed in seqno and reset_counter
1199 * values have been read by the caller in an smp safe manner. Where read-side
1200 * locks are involved, it is sufficient to read the reset_counter before
1201 * unlocking the lock that protects the seqno. For lockless tricks, the
1202 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1205 * Returns 0 if the request was found within the alloted time. Else returns the
1206 * errno with remaining time filled in timeout argument.
1208 int __i915_wait_request(struct drm_i915_gem_request *req,
1209 unsigned reset_counter,
1212 struct drm_i915_file_private *file_priv)
1214 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1215 struct drm_device *dev = ring->dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 const bool irq_test_in_progress =
1218 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1220 unsigned long timeout_expire;
1224 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1226 if (i915_gem_request_completed(req, true))
1229 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1231 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1232 gen6_rps_boost(dev_priv);
1234 mod_delayed_work(dev_priv->wq,
1235 &file_priv->mm.idle_work,
1236 msecs_to_jiffies(100));
1239 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1242 /* Record current time in case interrupted by signal, or wedged */
1243 trace_i915_gem_request_wait_begin(req);
1244 before = ktime_get_raw_ns();
1246 struct timer_list timer;
1248 prepare_to_wait(&ring->irq_queue, &wait,
1249 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1251 /* We need to check whether any gpu reset happened in between
1252 * the caller grabbing the seqno and now ... */
1253 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1254 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1255 * is truely gone. */
1256 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1262 if (i915_gem_request_completed(req, false)) {
1267 if (interruptible && signal_pending(current)) {
1272 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1277 timer.function = NULL;
1278 if (timeout || missed_irq(dev_priv, ring)) {
1279 unsigned long expire;
1281 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1282 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1283 mod_timer(&timer, expire);
1288 if (timer.function) {
1289 del_singleshot_timer_sync(&timer);
1290 destroy_timer_on_stack(&timer);
1293 now = ktime_get_raw_ns();
1294 trace_i915_gem_request_wait_end(req);
1296 if (!irq_test_in_progress)
1297 ring->irq_put(ring);
1299 finish_wait(&ring->irq_queue, &wait);
1302 s64 tres = *timeout - (now - before);
1304 *timeout = tres < 0 ? 0 : tres;
1311 * Waits for a request to be signaled, and cleans up the
1312 * request and object lists appropriately for that event.
1315 i915_wait_request(struct drm_i915_gem_request *req)
1317 struct drm_device *dev;
1318 struct drm_i915_private *dev_priv;
1320 unsigned reset_counter;
1323 BUG_ON(req == NULL);
1325 dev = req->ring->dev;
1326 dev_priv = dev->dev_private;
1327 interruptible = dev_priv->mm.interruptible;
1329 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1331 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1335 ret = i915_gem_check_olr(req);
1339 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1340 i915_gem_request_reference(req);
1341 ret = __i915_wait_request(req, reset_counter,
1342 interruptible, NULL, NULL);
1343 i915_gem_request_unreference(req);
1348 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1353 /* Manually manage the write flush as we may have not yet
1354 * retired the buffer.
1356 * Note that the last_write_req is always the earlier of
1357 * the two (read/write) requests, so if we haved successfully waited,
1358 * we know we have passed the last write.
1360 i915_gem_request_assign(&obj->last_write_req, NULL);
1366 * Ensures that all rendering to the object has completed and the object is
1367 * safe to unbind from the GTT or access from the CPU.
1369 static __must_check int
1370 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1373 struct drm_i915_gem_request *req;
1376 req = readonly ? obj->last_write_req : obj->last_read_req;
1380 ret = i915_wait_request(req);
1384 return i915_gem_object_wait_rendering__tail(obj);
1387 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1388 * as the object state may change during this call.
1390 static __must_check int
1391 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1392 struct drm_i915_file_private *file_priv,
1395 struct drm_i915_gem_request *req;
1396 struct drm_device *dev = obj->base.dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 unsigned reset_counter;
1401 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1402 BUG_ON(!dev_priv->mm.interruptible);
1404 req = readonly ? obj->last_write_req : obj->last_read_req;
1408 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1412 ret = i915_gem_check_olr(req);
1416 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1417 i915_gem_request_reference(req);
1418 mutex_unlock(&dev->struct_mutex);
1419 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1420 mutex_lock(&dev->struct_mutex);
1421 i915_gem_request_unreference(req);
1425 return i915_gem_object_wait_rendering__tail(obj);
1429 * Called when user space prepares to use an object with the CPU, either
1430 * through the mmap ioctl's mapping or a GTT mapping.
1433 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1434 struct drm_file *file)
1436 struct drm_i915_gem_set_domain *args = data;
1437 struct drm_i915_gem_object *obj;
1438 uint32_t read_domains = args->read_domains;
1439 uint32_t write_domain = args->write_domain;
1442 /* Only handle setting domains to types used by the CPU. */
1443 if (write_domain & I915_GEM_GPU_DOMAINS)
1446 if (read_domains & I915_GEM_GPU_DOMAINS)
1449 /* Having something in the write domain implies it's in the read
1450 * domain, and only that read domain. Enforce that in the request.
1452 if (write_domain != 0 && read_domains != write_domain)
1455 ret = i915_mutex_lock_interruptible(dev);
1459 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1460 if (&obj->base == NULL) {
1465 /* Try to flush the object off the GPU without holding the lock.
1466 * We will repeat the flush holding the lock in the normal manner
1467 * to catch cases where we are gazumped.
1469 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1475 if (read_domains & I915_GEM_DOMAIN_GTT) {
1476 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1478 /* Silently promote "you're not bound, there was nothing to do"
1479 * to success, since the client was just asking us to
1480 * make sure everything was done.
1485 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1489 drm_gem_object_unreference(&obj->base);
1491 mutex_unlock(&dev->struct_mutex);
1496 * Called when user space has done writes to this buffer
1499 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file)
1502 struct drm_i915_gem_sw_finish *args = data;
1503 struct drm_i915_gem_object *obj;
1506 ret = i915_mutex_lock_interruptible(dev);
1510 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1511 if (&obj->base == NULL) {
1516 /* Pinned buffers may be scanout, so flush the cache */
1517 if (obj->pin_display)
1518 i915_gem_object_flush_cpu_write_domain(obj, true);
1520 drm_gem_object_unreference(&obj->base);
1522 mutex_unlock(&dev->struct_mutex);
1527 * Maps the contents of an object, returning the address it is mapped
1530 * While the mapping holds a reference on the contents of the object, it doesn't
1531 * imply a ref on the object itself.
1535 * DRM driver writers who look a this function as an example for how to do GEM
1536 * mmap support, please don't implement mmap support like here. The modern way
1537 * to implement DRM mmap support is with an mmap offset ioctl (like
1538 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539 * That way debug tooling like valgrind will understand what's going on, hiding
1540 * the mmap call in a driver private ioctl will break that. The i915 driver only
1541 * does cpu mmaps this way because we didn't know better.
1544 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1545 struct drm_file *file)
1547 struct drm_i915_gem_mmap *args = data;
1548 struct drm_gem_object *obj;
1551 obj = drm_gem_object_lookup(dev, file, args->handle);
1555 /* prime objects have no backing filp to GEM mmap
1559 drm_gem_object_unreference_unlocked(obj);
1563 addr = vm_mmap(obj->filp, 0, args->size,
1564 PROT_READ | PROT_WRITE, MAP_SHARED,
1566 drm_gem_object_unreference_unlocked(obj);
1567 if (IS_ERR((void *)addr))
1570 args->addr_ptr = (uint64_t) addr;
1576 * i915_gem_fault - fault a page into the GTT
1577 * vma: VMA in question
1580 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1581 * from userspace. The fault handler takes care of binding the object to
1582 * the GTT (if needed), allocating and programming a fence register (again,
1583 * only if needed based on whether the old reg is still valid or the object
1584 * is tiled) and inserting a new PTE into the faulting process.
1586 * Note that the faulting process may involve evicting existing objects
1587 * from the GTT and/or fence registers to make room. So performance may
1588 * suffer if the GTT working set is large or there are few fence registers
1591 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1593 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1594 struct drm_device *dev = obj->base.dev;
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 pgoff_t page_offset;
1599 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1601 intel_runtime_pm_get(dev_priv);
1603 /* We don't use vmf->pgoff since that has the fake offset */
1604 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1607 ret = i915_mutex_lock_interruptible(dev);
1611 trace_i915_gem_object_fault(obj, page_offset, true, write);
1613 /* Try to flush the object off the GPU first without holding the lock.
1614 * Upon reacquiring the lock, we will perform our sanity checks and then
1615 * repeat the flush holding the lock in the normal manner to catch cases
1616 * where we are gazumped.
1618 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1622 /* Access to snoopable pages through the GTT is incoherent. */
1623 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1628 /* Now bind it into the GTT if needed */
1629 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1633 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1637 ret = i915_gem_object_get_fence(obj);
1641 /* Finally, remap it using the new GTT offset */
1642 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1645 if (!obj->fault_mappable) {
1646 unsigned long size = min_t(unsigned long,
1647 vma->vm_end - vma->vm_start,
1651 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1652 ret = vm_insert_pfn(vma,
1653 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1659 obj->fault_mappable = true;
1661 ret = vm_insert_pfn(vma,
1662 (unsigned long)vmf->virtual_address,
1665 i915_gem_object_ggtt_unpin(obj);
1667 mutex_unlock(&dev->struct_mutex);
1672 * We eat errors when the gpu is terminally wedged to avoid
1673 * userspace unduly crashing (gl has no provisions for mmaps to
1674 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1675 * and so needs to be reported.
1677 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1678 ret = VM_FAULT_SIGBUS;
1683 * EAGAIN means the gpu is hung and we'll wait for the error
1684 * handler to reset everything when re-faulting in
1685 * i915_mutex_lock_interruptible.
1692 * EBUSY is ok: this just means that another thread
1693 * already did the job.
1695 ret = VM_FAULT_NOPAGE;
1702 ret = VM_FAULT_SIGBUS;
1705 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1706 ret = VM_FAULT_SIGBUS;
1710 intel_runtime_pm_put(dev_priv);
1715 * i915_gem_release_mmap - remove physical page mappings
1716 * @obj: obj in question
1718 * Preserve the reservation of the mmapping with the DRM core code, but
1719 * relinquish ownership of the pages back to the system.
1721 * It is vital that we remove the page mapping if we have mapped a tiled
1722 * object through the GTT and then lose the fence register due to
1723 * resource pressure. Similarly if the object has been moved out of the
1724 * aperture, than pages mapped into userspace must be revoked. Removing the
1725 * mapping will then trigger a page fault on the next user access, allowing
1726 * fixup by i915_gem_fault().
1729 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1731 if (!obj->fault_mappable)
1734 drm_vma_node_unmap(&obj->base.vma_node,
1735 obj->base.dev->anon_inode->i_mapping);
1736 obj->fault_mappable = false;
1740 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1742 struct drm_i915_gem_object *obj;
1744 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1745 i915_gem_release_mmap(obj);
1749 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1753 if (INTEL_INFO(dev)->gen >= 4 ||
1754 tiling_mode == I915_TILING_NONE)
1757 /* Previous chips need a power-of-two fence region when tiling */
1758 if (INTEL_INFO(dev)->gen == 3)
1759 gtt_size = 1024*1024;
1761 gtt_size = 512*1024;
1763 while (gtt_size < size)
1770 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1771 * @obj: object to check
1773 * Return the required GTT alignment for an object, taking into account
1774 * potential fence register mapping.
1777 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1778 int tiling_mode, bool fenced)
1781 * Minimum alignment is 4k (GTT page size), but might be greater
1782 * if a fence register is needed for the object.
1784 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1785 tiling_mode == I915_TILING_NONE)
1789 * Previous chips need to be aligned to the size of the smallest
1790 * fence register that can contain the object.
1792 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1795 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1797 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1800 if (drm_vma_node_has_offset(&obj->base.vma_node))
1803 dev_priv->mm.shrinker_no_lock_stealing = true;
1805 ret = drm_gem_create_mmap_offset(&obj->base);
1809 /* Badly fragmented mmap space? The only way we can recover
1810 * space is by destroying unwanted objects. We can't randomly release
1811 * mmap_offsets as userspace expects them to be persistent for the
1812 * lifetime of the objects. The closest we can is to release the
1813 * offsets on purgeable objects by truncating it and marking it purged,
1814 * which prevents userspace from ever using that object again.
1816 i915_gem_shrink(dev_priv,
1817 obj->base.size >> PAGE_SHIFT,
1819 I915_SHRINK_UNBOUND |
1820 I915_SHRINK_PURGEABLE);
1821 ret = drm_gem_create_mmap_offset(&obj->base);
1825 i915_gem_shrink_all(dev_priv);
1826 ret = drm_gem_create_mmap_offset(&obj->base);
1828 dev_priv->mm.shrinker_no_lock_stealing = false;
1833 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1835 drm_gem_free_mmap_offset(&obj->base);
1839 i915_gem_mmap_gtt(struct drm_file *file,
1840 struct drm_device *dev,
1841 uint32_t handle, bool dumb,
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 struct drm_i915_gem_object *obj;
1848 ret = i915_mutex_lock_interruptible(dev);
1852 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1853 if (&obj->base == NULL) {
1859 * We don't allow dumb mmaps on objects created using another
1862 WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
1863 "Illegal dumb map of accelerated buffer.\n");
1865 if (obj->base.size > dev_priv->gtt.mappable_end) {
1870 if (obj->madv != I915_MADV_WILLNEED) {
1871 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1876 ret = i915_gem_object_create_mmap_offset(obj);
1880 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1883 drm_gem_object_unreference(&obj->base);
1885 mutex_unlock(&dev->struct_mutex);
1890 i915_gem_dumb_map_offset(struct drm_file *file,
1891 struct drm_device *dev,
1895 return i915_gem_mmap_gtt(file, dev, handle, true, offset);
1899 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1901 * @data: GTT mapping ioctl data
1902 * @file: GEM object info
1904 * Simply returns the fake offset to userspace so it can mmap it.
1905 * The mmap call will end up in drm_gem_mmap(), which will set things
1906 * up so we can get faults in the handler above.
1908 * The fault handler will take care of binding the object into the GTT
1909 * (since it may have been evicted to make room for something), allocating
1910 * a fence register, and mapping the appropriate aperture address into
1914 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1915 struct drm_file *file)
1917 struct drm_i915_gem_mmap_gtt *args = data;
1919 return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
1923 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1925 return obj->madv == I915_MADV_DONTNEED;
1928 /* Immediately discard the backing storage */
1930 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1932 i915_gem_object_free_mmap_offset(obj);
1934 if (obj->base.filp == NULL)
1937 /* Our goal here is to return as much of the memory as
1938 * is possible back to the system as we are called from OOM.
1939 * To do this we must instruct the shmfs to drop all of its
1940 * backing pages, *now*.
1942 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1943 obj->madv = __I915_MADV_PURGED;
1946 /* Try to discard unwanted pages */
1948 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1950 struct address_space *mapping;
1952 switch (obj->madv) {
1953 case I915_MADV_DONTNEED:
1954 i915_gem_object_truncate(obj);
1955 case __I915_MADV_PURGED:
1959 if (obj->base.filp == NULL)
1962 mapping = file_inode(obj->base.filp)->i_mapping,
1963 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1967 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1969 struct sg_page_iter sg_iter;
1972 BUG_ON(obj->madv == __I915_MADV_PURGED);
1974 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1976 /* In the event of a disaster, abandon all caches and
1977 * hope for the best.
1979 WARN_ON(ret != -EIO);
1980 i915_gem_clflush_object(obj, true);
1981 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1984 if (i915_gem_object_needs_bit17_swizzle(obj))
1985 i915_gem_object_save_bit_17_swizzle(obj);
1987 if (obj->madv == I915_MADV_DONTNEED)
1990 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1991 struct page *page = sg_page_iter_page(&sg_iter);
1994 set_page_dirty(page);
1996 if (obj->madv == I915_MADV_WILLNEED)
1997 mark_page_accessed(page);
1999 page_cache_release(page);
2003 sg_free_table(obj->pages);
2008 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2010 const struct drm_i915_gem_object_ops *ops = obj->ops;
2012 if (obj->pages == NULL)
2015 if (obj->pages_pin_count)
2018 BUG_ON(i915_gem_obj_bound_any(obj));
2020 /* ->put_pages might need to allocate memory for the bit17 swizzle
2021 * array, hence protect them from being reaped by removing them from gtt
2023 list_del(&obj->global_list);
2025 ops->put_pages(obj);
2028 i915_gem_object_invalidate(obj);
2034 i915_gem_shrink(struct drm_i915_private *dev_priv,
2035 long target, unsigned flags)
2038 struct list_head *list;
2041 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2042 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2045 unsigned long count = 0;
2048 * As we may completely rewrite the (un)bound list whilst unbinding
2049 * (due to retiring requests) we have to strictly process only
2050 * one element of the list at the time, and recheck the list
2051 * on every iteration.
2053 * In particular, we must hold a reference whilst removing the
2054 * object as we may end up waiting for and/or retiring the objects.
2055 * This might release the final reference (held by the active list)
2056 * and result in the object being freed from under us. This is
2057 * similar to the precautions the eviction code must take whilst
2060 * Also note that although these lists do not hold a reference to
2061 * the object we can safely grab one here: The final object
2062 * unreferencing and the bound_list are both protected by the
2063 * dev->struct_mutex and so we won't ever be able to observe an
2064 * object on the bound_list with a reference count equals 0.
2066 for (phase = phases; phase->list; phase++) {
2067 struct list_head still_in_list;
2069 if ((flags & phase->bit) == 0)
2072 INIT_LIST_HEAD(&still_in_list);
2073 while (count < target && !list_empty(phase->list)) {
2074 struct drm_i915_gem_object *obj;
2075 struct i915_vma *vma, *v;
2077 obj = list_first_entry(phase->list,
2078 typeof(*obj), global_list);
2079 list_move_tail(&obj->global_list, &still_in_list);
2081 if (flags & I915_SHRINK_PURGEABLE &&
2082 !i915_gem_object_is_purgeable(obj))
2085 drm_gem_object_reference(&obj->base);
2087 /* For the unbound phase, this should be a no-op! */
2088 list_for_each_entry_safe(vma, v,
2089 &obj->vma_list, vma_link)
2090 if (i915_vma_unbind(vma))
2093 if (i915_gem_object_put_pages(obj) == 0)
2094 count += obj->base.size >> PAGE_SHIFT;
2096 drm_gem_object_unreference(&obj->base);
2098 list_splice(&still_in_list, phase->list);
2104 static unsigned long
2105 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2107 i915_gem_evict_everything(dev_priv->dev);
2108 return i915_gem_shrink(dev_priv, LONG_MAX,
2109 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2113 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2115 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2117 struct address_space *mapping;
2118 struct sg_table *st;
2119 struct scatterlist *sg;
2120 struct sg_page_iter sg_iter;
2122 unsigned long last_pfn = 0; /* suppress gcc warning */
2125 /* Assert that the object is not currently in any GPU domain. As it
2126 * wasn't in the GTT, there shouldn't be any way it could have been in
2129 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2130 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2132 st = kmalloc(sizeof(*st), GFP_KERNEL);
2136 page_count = obj->base.size / PAGE_SIZE;
2137 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2142 /* Get the list of pages out of our struct file. They'll be pinned
2143 * at this point until we release them.
2145 * Fail silently without starting the shrinker
2147 mapping = file_inode(obj->base.filp)->i_mapping;
2148 gfp = mapping_gfp_mask(mapping);
2149 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2150 gfp &= ~(__GFP_IO | __GFP_WAIT);
2153 for (i = 0; i < page_count; i++) {
2154 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2156 i915_gem_shrink(dev_priv,
2159 I915_SHRINK_UNBOUND |
2160 I915_SHRINK_PURGEABLE);
2161 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2164 /* We've tried hard to allocate the memory by reaping
2165 * our own buffer, now let the real VM do its job and
2166 * go down in flames if truly OOM.
2168 i915_gem_shrink_all(dev_priv);
2169 page = shmem_read_mapping_page(mapping, i);
2173 #ifdef CONFIG_SWIOTLB
2174 if (swiotlb_nr_tbl()) {
2176 sg_set_page(sg, page, PAGE_SIZE, 0);
2181 if (!i || page_to_pfn(page) != last_pfn + 1) {
2185 sg_set_page(sg, page, PAGE_SIZE, 0);
2187 sg->length += PAGE_SIZE;
2189 last_pfn = page_to_pfn(page);
2191 /* Check that the i965g/gm workaround works. */
2192 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2194 #ifdef CONFIG_SWIOTLB
2195 if (!swiotlb_nr_tbl())
2200 if (i915_gem_object_needs_bit17_swizzle(obj))
2201 i915_gem_object_do_bit_17_swizzle(obj);
2203 if (obj->tiling_mode != I915_TILING_NONE &&
2204 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2205 i915_gem_object_pin_pages(obj);
2211 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2212 page_cache_release(sg_page_iter_page(&sg_iter));
2216 /* shmemfs first checks if there is enough memory to allocate the page
2217 * and reports ENOSPC should there be insufficient, along with the usual
2218 * ENOMEM for a genuine allocation failure.
2220 * We use ENOSPC in our driver to mean that we have run out of aperture
2221 * space and so want to translate the error from shmemfs back to our
2222 * usual understanding of ENOMEM.
2224 if (PTR_ERR(page) == -ENOSPC)
2227 return PTR_ERR(page);
2230 /* Ensure that the associated pages are gathered from the backing storage
2231 * and pinned into our object. i915_gem_object_get_pages() may be called
2232 * multiple times before they are released by a single call to
2233 * i915_gem_object_put_pages() - once the pages are no longer referenced
2234 * either as a result of memory pressure (reaping pages under the shrinker)
2235 * or as the object is itself released.
2238 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 const struct drm_i915_gem_object_ops *ops = obj->ops;
2247 if (obj->madv != I915_MADV_WILLNEED) {
2248 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2252 BUG_ON(obj->pages_pin_count);
2254 ret = ops->get_pages(obj);
2258 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2263 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2264 struct intel_engine_cs *ring)
2266 struct drm_i915_gem_request *req;
2267 struct intel_engine_cs *old_ring;
2269 BUG_ON(ring == NULL);
2271 req = intel_ring_get_request(ring);
2272 old_ring = i915_gem_request_get_ring(obj->last_read_req);
2274 if (old_ring != ring && obj->last_write_req) {
2275 /* Keep the request relative to the current ring */
2276 i915_gem_request_assign(&obj->last_write_req, req);
2279 /* Add a reference if we're newly entering the active list. */
2281 drm_gem_object_reference(&obj->base);
2285 list_move_tail(&obj->ring_list, &ring->active_list);
2287 i915_gem_request_assign(&obj->last_read_req, req);
2290 void i915_vma_move_to_active(struct i915_vma *vma,
2291 struct intel_engine_cs *ring)
2293 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2294 return i915_gem_object_move_to_active(vma->obj, ring);
2298 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2300 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2301 struct i915_address_space *vm;
2302 struct i915_vma *vma;
2304 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2305 BUG_ON(!obj->active);
2307 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2308 vma = i915_gem_obj_to_vma(obj, vm);
2309 if (vma && !list_empty(&vma->mm_list))
2310 list_move_tail(&vma->mm_list, &vm->inactive_list);
2313 intel_fb_obj_flush(obj, true);
2315 list_del_init(&obj->ring_list);
2317 i915_gem_request_assign(&obj->last_read_req, NULL);
2318 i915_gem_request_assign(&obj->last_write_req, NULL);
2319 obj->base.write_domain = 0;
2321 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2324 drm_gem_object_unreference(&obj->base);
2326 WARN_ON(i915_verify_lists(dev));
2330 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2332 if (obj->last_read_req == NULL)
2335 if (i915_gem_request_completed(obj->last_read_req, true))
2336 i915_gem_object_move_to_inactive(obj);
2340 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct intel_engine_cs *ring;
2346 /* Carefully retire all requests without writing to the rings */
2347 for_each_ring(ring, dev_priv, i) {
2348 ret = intel_ring_idle(ring);
2352 i915_gem_retire_requests(dev);
2354 /* Finally reset hw state */
2355 for_each_ring(ring, dev_priv, i) {
2356 intel_ring_init_seqno(ring, seqno);
2358 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2359 ring->semaphore.sync_seqno[j] = 0;
2365 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2373 /* HWS page needs to be set less than what we
2374 * will inject to ring
2376 ret = i915_gem_init_seqno(dev, seqno - 1);
2380 /* Carefully set the last_seqno value so that wrap
2381 * detection still works
2383 dev_priv->next_seqno = seqno;
2384 dev_priv->last_seqno = seqno - 1;
2385 if (dev_priv->last_seqno == 0)
2386 dev_priv->last_seqno--;
2392 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2396 /* reserve 0 for non-seqno */
2397 if (dev_priv->next_seqno == 0) {
2398 int ret = i915_gem_init_seqno(dev, 0);
2402 dev_priv->next_seqno = 1;
2405 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2409 int __i915_add_request(struct intel_engine_cs *ring,
2410 struct drm_file *file,
2411 struct drm_i915_gem_object *obj)
2413 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2414 struct drm_i915_gem_request *request;
2415 struct intel_ringbuffer *ringbuf;
2416 u32 request_ring_position, request_start;
2419 request = ring->outstanding_lazy_request;
2420 if (WARN_ON(request == NULL))
2423 if (i915.enable_execlists) {
2424 struct intel_context *ctx = request->ctx;
2425 ringbuf = ctx->engine[ring->id].ringbuf;
2427 ringbuf = ring->buffer;
2429 request_start = intel_ring_get_tail(ringbuf);
2431 * Emit any outstanding flushes - execbuf can fail to emit the flush
2432 * after having emitted the batchbuffer command. Hence we need to fix
2433 * things up similar to emitting the lazy request. The difference here
2434 * is that the flush _must_ happen before the next request, no matter
2437 if (i915.enable_execlists) {
2438 ret = logical_ring_flush_all_caches(ringbuf);
2442 ret = intel_ring_flush_all_caches(ring);
2447 /* Record the position of the start of the request so that
2448 * should we detect the updated seqno part-way through the
2449 * GPU processing the request, we never over-estimate the
2450 * position of the head.
2452 request_ring_position = intel_ring_get_tail(ringbuf);
2454 if (i915.enable_execlists) {
2455 ret = ring->emit_request(ringbuf);
2459 ret = ring->add_request(ring);
2464 request->head = request_start;
2465 request->tail = request_ring_position;
2467 /* Whilst this request exists, batch_obj will be on the
2468 * active_list, and so will hold the active reference. Only when this
2469 * request is retired will the the batch_obj be moved onto the
2470 * inactive_list and lose its active reference. Hence we do not need
2471 * to explicitly hold another reference here.
2473 request->batch_obj = obj;
2475 if (!i915.enable_execlists) {
2476 /* Hold a reference to the current context so that we can inspect
2477 * it later in case a hangcheck error event fires.
2479 request->ctx = ring->last_context;
2481 i915_gem_context_reference(request->ctx);
2484 request->emitted_jiffies = jiffies;
2485 list_add_tail(&request->list, &ring->request_list);
2486 request->file_priv = NULL;
2489 struct drm_i915_file_private *file_priv = file->driver_priv;
2491 spin_lock(&file_priv->mm.lock);
2492 request->file_priv = file_priv;
2493 list_add_tail(&request->client_list,
2494 &file_priv->mm.request_list);
2495 spin_unlock(&file_priv->mm.lock);
2498 trace_i915_gem_request_add(request);
2499 ring->outstanding_lazy_request = NULL;
2501 i915_queue_hangcheck(ring->dev);
2503 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2504 queue_delayed_work(dev_priv->wq,
2505 &dev_priv->mm.retire_work,
2506 round_jiffies_up_relative(HZ));
2507 intel_mark_busy(dev_priv->dev);
2513 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2515 struct drm_i915_file_private *file_priv = request->file_priv;
2520 spin_lock(&file_priv->mm.lock);
2521 list_del(&request->client_list);
2522 request->file_priv = NULL;
2523 spin_unlock(&file_priv->mm.lock);
2526 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2527 const struct intel_context *ctx)
2529 unsigned long elapsed;
2531 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2533 if (ctx->hang_stats.banned)
2536 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2537 if (!i915_gem_context_is_default(ctx)) {
2538 DRM_DEBUG("context hanging too fast, banning!\n");
2540 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2541 if (i915_stop_ring_allow_warn(dev_priv))
2542 DRM_ERROR("gpu hanging too fast, banning!\n");
2550 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2551 struct intel_context *ctx,
2554 struct i915_ctx_hang_stats *hs;
2559 hs = &ctx->hang_stats;
2562 hs->banned = i915_context_is_banned(dev_priv, ctx);
2564 hs->guilty_ts = get_seconds();
2566 hs->batch_pending++;
2570 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2572 list_del(&request->list);
2573 i915_gem_request_remove_from_client(request);
2575 i915_gem_request_unreference(request);
2578 void i915_gem_request_free(struct kref *req_ref)
2580 struct drm_i915_gem_request *req = container_of(req_ref,
2582 struct intel_context *ctx = req->ctx;
2585 if (i915.enable_execlists) {
2586 struct intel_engine_cs *ring = req->ring;
2588 if (ctx != ring->default_context)
2589 intel_lr_context_unpin(ring, ctx);
2592 i915_gem_context_unreference(ctx);
2598 struct drm_i915_gem_request *
2599 i915_gem_find_active_request(struct intel_engine_cs *ring)
2601 struct drm_i915_gem_request *request;
2603 list_for_each_entry(request, &ring->request_list, list) {
2604 if (i915_gem_request_completed(request, false))
2613 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2614 struct intel_engine_cs *ring)
2616 struct drm_i915_gem_request *request;
2619 request = i915_gem_find_active_request(ring);
2621 if (request == NULL)
2624 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2626 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2628 list_for_each_entry_continue(request, &ring->request_list, list)
2629 i915_set_reset_status(dev_priv, request->ctx, false);
2632 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2633 struct intel_engine_cs *ring)
2635 while (!list_empty(&ring->active_list)) {
2636 struct drm_i915_gem_object *obj;
2638 obj = list_first_entry(&ring->active_list,
2639 struct drm_i915_gem_object,
2642 i915_gem_object_move_to_inactive(obj);
2646 * Clear the execlists queue up before freeing the requests, as those
2647 * are the ones that keep the context and ringbuffer backing objects
2650 while (!list_empty(&ring->execlist_queue)) {
2651 struct intel_ctx_submit_request *submit_req;
2653 submit_req = list_first_entry(&ring->execlist_queue,
2654 struct intel_ctx_submit_request,
2656 list_del(&submit_req->execlist_link);
2657 intel_runtime_pm_put(dev_priv);
2658 i915_gem_context_unreference(submit_req->ctx);
2663 * We must free the requests after all the corresponding objects have
2664 * been moved off active lists. Which is the same order as the normal
2665 * retire_requests function does. This is important if object hold
2666 * implicit references on things like e.g. ppgtt address spaces through
2669 while (!list_empty(&ring->request_list)) {
2670 struct drm_i915_gem_request *request;
2672 request = list_first_entry(&ring->request_list,
2673 struct drm_i915_gem_request,
2676 i915_gem_free_request(request);
2679 /* This may not have been flushed before the reset, so clean it now */
2680 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2683 void i915_gem_restore_fences(struct drm_device *dev)
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2688 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2689 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2692 * Commit delayed tiling changes if we have an object still
2693 * attached to the fence, otherwise just clear the fence.
2696 i915_gem_object_update_fence(reg->obj, reg,
2697 reg->obj->tiling_mode);
2699 i915_gem_write_fence(dev, i, NULL);
2704 void i915_gem_reset(struct drm_device *dev)
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 struct intel_engine_cs *ring;
2711 * Before we free the objects from the requests, we need to inspect
2712 * them for finding the guilty party. As the requests only borrow
2713 * their reference to the objects, the inspection must be done first.
2715 for_each_ring(ring, dev_priv, i)
2716 i915_gem_reset_ring_status(dev_priv, ring);
2718 for_each_ring(ring, dev_priv, i)
2719 i915_gem_reset_ring_cleanup(dev_priv, ring);
2721 i915_gem_context_reset(dev);
2723 i915_gem_restore_fences(dev);
2727 * This function clears the request list as sequence numbers are passed.
2730 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2732 if (list_empty(&ring->request_list))
2735 WARN_ON(i915_verify_lists(ring->dev));
2737 /* Move any buffers on the active list that are no longer referenced
2738 * by the ringbuffer to the flushing/inactive lists as appropriate,
2739 * before we free the context associated with the requests.
2741 while (!list_empty(&ring->active_list)) {
2742 struct drm_i915_gem_object *obj;
2744 obj = list_first_entry(&ring->active_list,
2745 struct drm_i915_gem_object,
2748 if (!i915_gem_request_completed(obj->last_read_req, true))
2751 i915_gem_object_move_to_inactive(obj);
2755 while (!list_empty(&ring->request_list)) {
2756 struct drm_i915_gem_request *request;
2757 struct intel_ringbuffer *ringbuf;
2759 request = list_first_entry(&ring->request_list,
2760 struct drm_i915_gem_request,
2763 if (!i915_gem_request_completed(request, true))
2766 trace_i915_gem_request_retire(request);
2768 /* This is one of the few common intersection points
2769 * between legacy ringbuffer submission and execlists:
2770 * we need to tell them apart in order to find the correct
2771 * ringbuffer to which the request belongs to.
2773 if (i915.enable_execlists) {
2774 struct intel_context *ctx = request->ctx;
2775 ringbuf = ctx->engine[ring->id].ringbuf;
2777 ringbuf = ring->buffer;
2779 /* We know the GPU must have read the request to have
2780 * sent us the seqno + interrupt, so use the position
2781 * of tail of the request to update the last known position
2784 ringbuf->last_retired_head = request->tail;
2786 i915_gem_free_request(request);
2789 if (unlikely(ring->trace_irq_req &&
2790 i915_gem_request_completed(ring->trace_irq_req, true))) {
2791 ring->irq_put(ring);
2792 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2795 WARN_ON(i915_verify_lists(ring->dev));
2799 i915_gem_retire_requests(struct drm_device *dev)
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 struct intel_engine_cs *ring;
2806 for_each_ring(ring, dev_priv, i) {
2807 i915_gem_retire_requests_ring(ring);
2808 idle &= list_empty(&ring->request_list);
2809 if (i915.enable_execlists) {
2810 unsigned long flags;
2812 spin_lock_irqsave(&ring->execlist_lock, flags);
2813 idle &= list_empty(&ring->execlist_queue);
2814 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2816 intel_execlists_retire_requests(ring);
2821 mod_delayed_work(dev_priv->wq,
2822 &dev_priv->mm.idle_work,
2823 msecs_to_jiffies(100));
2829 i915_gem_retire_work_handler(struct work_struct *work)
2831 struct drm_i915_private *dev_priv =
2832 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2833 struct drm_device *dev = dev_priv->dev;
2836 /* Come back later if the device is busy... */
2838 if (mutex_trylock(&dev->struct_mutex)) {
2839 idle = i915_gem_retire_requests(dev);
2840 mutex_unlock(&dev->struct_mutex);
2843 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2844 round_jiffies_up_relative(HZ));
2848 i915_gem_idle_work_handler(struct work_struct *work)
2850 struct drm_i915_private *dev_priv =
2851 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2853 intel_mark_idle(dev_priv->dev);
2857 * Ensures that an object will eventually get non-busy by flushing any required
2858 * write domains, emitting any outstanding lazy request and retiring and
2859 * completed requests.
2862 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2864 struct intel_engine_cs *ring;
2868 ring = i915_gem_request_get_ring(obj->last_read_req);
2870 ret = i915_gem_check_olr(obj->last_read_req);
2874 i915_gem_retire_requests_ring(ring);
2881 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2882 * @DRM_IOCTL_ARGS: standard ioctl arguments
2884 * Returns 0 if successful, else an error is returned with the remaining time in
2885 * the timeout parameter.
2886 * -ETIME: object is still busy after timeout
2887 * -ERESTARTSYS: signal interrupted the wait
2888 * -ENONENT: object doesn't exist
2889 * Also possible, but rare:
2890 * -EAGAIN: GPU wedged
2892 * -ENODEV: Internal IRQ fail
2893 * -E?: The add request failed
2895 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2896 * non-zero timeout parameter the wait ioctl will wait for the given number of
2897 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2898 * without holding struct_mutex the object may become re-busied before this
2899 * function completes. A similar but shorter * race condition exists in the busy
2903 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906 struct drm_i915_gem_wait *args = data;
2907 struct drm_i915_gem_object *obj;
2908 struct drm_i915_gem_request *req;
2909 unsigned reset_counter;
2912 if (args->flags != 0)
2915 ret = i915_mutex_lock_interruptible(dev);
2919 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2920 if (&obj->base == NULL) {
2921 mutex_unlock(&dev->struct_mutex);
2925 /* Need to make sure the object gets inactive eventually. */
2926 ret = i915_gem_object_flush_active(obj);
2930 if (!obj->active || !obj->last_read_req)
2933 req = obj->last_read_req;
2935 /* Do this after OLR check to make sure we make forward progress polling
2936 * on this IOCTL with a timeout <=0 (like busy ioctl)
2938 if (args->timeout_ns <= 0) {
2943 drm_gem_object_unreference(&obj->base);
2944 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2945 i915_gem_request_reference(req);
2946 mutex_unlock(&dev->struct_mutex);
2948 ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2950 mutex_lock(&dev->struct_mutex);
2951 i915_gem_request_unreference(req);
2952 mutex_unlock(&dev->struct_mutex);
2956 drm_gem_object_unreference(&obj->base);
2957 mutex_unlock(&dev->struct_mutex);
2962 * i915_gem_object_sync - sync an object to a ring.
2964 * @obj: object which may be in use on another ring.
2965 * @to: ring we wish to use the object on. May be NULL.
2967 * This code is meant to abstract object synchronization with the GPU.
2968 * Calling with NULL implies synchronizing the object with the CPU
2969 * rather than a particular GPU ring.
2971 * Returns 0 if successful, else propagates up the lower layer error.
2974 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2975 struct intel_engine_cs *to)
2977 struct intel_engine_cs *from;
2981 from = i915_gem_request_get_ring(obj->last_read_req);
2983 if (from == NULL || to == from)
2986 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2987 return i915_gem_object_wait_rendering(obj, false);
2989 idx = intel_ring_sync_index(from, to);
2991 seqno = i915_gem_request_get_seqno(obj->last_read_req);
2992 /* Optimization: Avoid semaphore sync when we are sure we already
2993 * waited for an object with higher seqno */
2994 if (seqno <= from->semaphore.sync_seqno[idx])
2997 ret = i915_gem_check_olr(obj->last_read_req);
3001 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
3002 ret = to->semaphore.sync_to(to, from, seqno);
3004 /* We use last_read_req because sync_to()
3005 * might have just caused seqno wrap under
3008 from->semaphore.sync_seqno[idx] =
3009 i915_gem_request_get_seqno(obj->last_read_req);
3014 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3016 u32 old_write_domain, old_read_domains;
3018 /* Force a pagefault for domain tracking on next user access */
3019 i915_gem_release_mmap(obj);
3021 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3024 /* Wait for any direct GTT access to complete */
3027 old_read_domains = obj->base.read_domains;
3028 old_write_domain = obj->base.write_domain;
3030 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3031 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3033 trace_i915_gem_object_change_domain(obj,
3038 int i915_vma_unbind(struct i915_vma *vma)
3040 struct drm_i915_gem_object *obj = vma->obj;
3041 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3044 if (list_empty(&vma->vma_link))
3047 if (!drm_mm_node_allocated(&vma->node)) {
3048 i915_gem_vma_destroy(vma);
3055 BUG_ON(obj->pages == NULL);
3057 ret = i915_gem_object_finish_gpu(obj);
3060 /* Continue on if we fail due to EIO, the GPU is hung so we
3061 * should be safe and we need to cleanup or else we might
3062 * cause memory corruption through use-after-free.
3065 /* Throw away the active reference before moving to the unbound list */
3066 i915_gem_object_retire(obj);
3068 if (i915_is_ggtt(vma->vm)) {
3069 i915_gem_object_finish_gtt(obj);
3071 /* release the fence reg _after_ flushing */
3072 ret = i915_gem_object_put_fence(obj);
3077 trace_i915_vma_unbind(vma);
3079 vma->unbind_vma(vma);
3081 list_del_init(&vma->mm_list);
3082 if (i915_is_ggtt(vma->vm))
3083 obj->map_and_fenceable = false;
3085 drm_mm_remove_node(&vma->node);
3086 i915_gem_vma_destroy(vma);
3088 /* Since the unbound list is global, only move to that list if
3089 * no more VMAs exist. */
3090 if (list_empty(&obj->vma_list)) {
3091 i915_gem_gtt_finish_object(obj);
3092 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3095 /* And finally now the object is completely decoupled from this vma,
3096 * we can drop its hold on the backing storage and allow it to be
3097 * reaped by the shrinker.
3099 i915_gem_object_unpin_pages(obj);
3104 int i915_gpu_idle(struct drm_device *dev)
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_engine_cs *ring;
3110 /* Flush everything onto the inactive list. */
3111 for_each_ring(ring, dev_priv, i) {
3112 if (!i915.enable_execlists) {
3113 ret = i915_switch_context(ring, ring->default_context);
3118 ret = intel_ring_idle(ring);
3126 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3127 struct drm_i915_gem_object *obj)
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3131 int fence_pitch_shift;
3133 if (INTEL_INFO(dev)->gen >= 6) {
3134 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3135 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3137 fence_reg = FENCE_REG_965_0;
3138 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3141 fence_reg += reg * 8;
3143 /* To w/a incoherency with non-atomic 64-bit register updates,
3144 * we split the 64-bit update into two 32-bit writes. In order
3145 * for a partial fence not to be evaluated between writes, we
3146 * precede the update with write to turn off the fence register,
3147 * and only enable the fence as the last step.
3149 * For extra levels of paranoia, we make sure each step lands
3150 * before applying the next step.
3152 I915_WRITE(fence_reg, 0);
3153 POSTING_READ(fence_reg);
3156 u32 size = i915_gem_obj_ggtt_size(obj);
3159 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3161 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3162 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3163 if (obj->tiling_mode == I915_TILING_Y)
3164 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3165 val |= I965_FENCE_REG_VALID;
3167 I915_WRITE(fence_reg + 4, val >> 32);
3168 POSTING_READ(fence_reg + 4);
3170 I915_WRITE(fence_reg + 0, val);
3171 POSTING_READ(fence_reg);
3173 I915_WRITE(fence_reg + 4, 0);
3174 POSTING_READ(fence_reg + 4);
3178 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3179 struct drm_i915_gem_object *obj)
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3185 u32 size = i915_gem_obj_ggtt_size(obj);
3189 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3190 (size & -size) != size ||
3191 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3192 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3193 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3195 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3200 /* Note: pitch better be a power of two tile widths */
3201 pitch_val = obj->stride / tile_width;
3202 pitch_val = ffs(pitch_val) - 1;
3204 val = i915_gem_obj_ggtt_offset(obj);
3205 if (obj->tiling_mode == I915_TILING_Y)
3206 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3207 val |= I915_FENCE_SIZE_BITS(size);
3208 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3209 val |= I830_FENCE_REG_VALID;
3214 reg = FENCE_REG_830_0 + reg * 4;
3216 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3218 I915_WRITE(reg, val);
3222 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3223 struct drm_i915_gem_object *obj)
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3229 u32 size = i915_gem_obj_ggtt_size(obj);
3232 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3233 (size & -size) != size ||
3234 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3235 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3236 i915_gem_obj_ggtt_offset(obj), size);
3238 pitch_val = obj->stride / 128;
3239 pitch_val = ffs(pitch_val) - 1;
3241 val = i915_gem_obj_ggtt_offset(obj);
3242 if (obj->tiling_mode == I915_TILING_Y)
3243 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3244 val |= I830_FENCE_SIZE_BITS(size);
3245 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3246 val |= I830_FENCE_REG_VALID;
3250 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3251 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3254 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3256 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3259 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3260 struct drm_i915_gem_object *obj)
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3264 /* Ensure that all CPU reads are completed before installing a fence
3265 * and all writes before removing the fence.
3267 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3270 WARN(obj && (!obj->stride || !obj->tiling_mode),
3271 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3272 obj->stride, obj->tiling_mode);
3274 switch (INTEL_INFO(dev)->gen) {
3280 case 4: i965_write_fence_reg(dev, reg, obj); break;
3281 case 3: i915_write_fence_reg(dev, reg, obj); break;
3282 case 2: i830_write_fence_reg(dev, reg, obj); break;
3286 /* And similarly be paranoid that no direct access to this region
3287 * is reordered to before the fence is installed.
3289 if (i915_gem_object_needs_mb(obj))
3293 static inline int fence_number(struct drm_i915_private *dev_priv,
3294 struct drm_i915_fence_reg *fence)
3296 return fence - dev_priv->fence_regs;
3299 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3300 struct drm_i915_fence_reg *fence,
3303 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3304 int reg = fence_number(dev_priv, fence);
3306 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3309 obj->fence_reg = reg;
3311 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3313 obj->fence_reg = I915_FENCE_REG_NONE;
3315 list_del_init(&fence->lru_list);
3317 obj->fence_dirty = false;
3321 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3323 if (obj->last_fenced_req) {
3324 int ret = i915_wait_request(obj->last_fenced_req);
3328 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3335 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3337 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3338 struct drm_i915_fence_reg *fence;
3341 ret = i915_gem_object_wait_fence(obj);
3345 if (obj->fence_reg == I915_FENCE_REG_NONE)
3348 fence = &dev_priv->fence_regs[obj->fence_reg];
3350 if (WARN_ON(fence->pin_count))
3353 i915_gem_object_fence_lost(obj);
3354 i915_gem_object_update_fence(obj, fence, false);
3359 static struct drm_i915_fence_reg *
3360 i915_find_fence_reg(struct drm_device *dev)
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 struct drm_i915_fence_reg *reg, *avail;
3366 /* First try to find a free reg */
3368 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3369 reg = &dev_priv->fence_regs[i];
3373 if (!reg->pin_count)
3380 /* None available, try to steal one or wait for a user to finish */
3381 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3389 /* Wait for completion of pending flips which consume fences */
3390 if (intel_has_pending_fb_unpin(dev))
3391 return ERR_PTR(-EAGAIN);
3393 return ERR_PTR(-EDEADLK);
3397 * i915_gem_object_get_fence - set up fencing for an object
3398 * @obj: object to map through a fence reg
3400 * When mapping objects through the GTT, userspace wants to be able to write
3401 * to them without having to worry about swizzling if the object is tiled.
3402 * This function walks the fence regs looking for a free one for @obj,
3403 * stealing one if it can't find any.
3405 * It then sets up the reg based on the object's properties: address, pitch
3406 * and tiling format.
3408 * For an untiled surface, this removes any existing fence.
3411 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3413 struct drm_device *dev = obj->base.dev;
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 bool enable = obj->tiling_mode != I915_TILING_NONE;
3416 struct drm_i915_fence_reg *reg;
3419 /* Have we updated the tiling parameters upon the object and so
3420 * will need to serialise the write to the associated fence register?
3422 if (obj->fence_dirty) {
3423 ret = i915_gem_object_wait_fence(obj);
3428 /* Just update our place in the LRU if our fence is getting reused. */
3429 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3430 reg = &dev_priv->fence_regs[obj->fence_reg];
3431 if (!obj->fence_dirty) {
3432 list_move_tail(®->lru_list,
3433 &dev_priv->mm.fence_list);
3436 } else if (enable) {
3437 if (WARN_ON(!obj->map_and_fenceable))
3440 reg = i915_find_fence_reg(dev);
3442 return PTR_ERR(reg);
3445 struct drm_i915_gem_object *old = reg->obj;
3447 ret = i915_gem_object_wait_fence(old);
3451 i915_gem_object_fence_lost(old);
3456 i915_gem_object_update_fence(obj, reg, enable);
3461 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3462 unsigned long cache_level)
3464 struct drm_mm_node *gtt_space = &vma->node;
3465 struct drm_mm_node *other;
3468 * On some machines we have to be careful when putting differing types
3469 * of snoopable memory together to avoid the prefetcher crossing memory
3470 * domains and dying. During vm initialisation, we decide whether or not
3471 * these constraints apply and set the drm_mm.color_adjust
3474 if (vma->vm->mm.color_adjust == NULL)
3477 if (!drm_mm_node_allocated(gtt_space))
3480 if (list_empty(>t_space->node_list))
3483 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3484 if (other->allocated && !other->hole_follows && other->color != cache_level)
3487 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3488 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3495 * Finds free space in the GTT aperture and binds the object there.
3497 static struct i915_vma *
3498 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3499 struct i915_address_space *vm,
3503 struct drm_device *dev = obj->base.dev;
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 u32 size, fence_size, fence_alignment, unfenced_alignment;
3506 unsigned long start =
3507 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3509 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3510 struct i915_vma *vma;
3513 fence_size = i915_gem_get_gtt_size(dev,
3516 fence_alignment = i915_gem_get_gtt_alignment(dev,
3518 obj->tiling_mode, true);
3519 unfenced_alignment =
3520 i915_gem_get_gtt_alignment(dev,
3522 obj->tiling_mode, false);
3525 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3527 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3528 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3529 return ERR_PTR(-EINVAL);
3532 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3534 /* If the object is bigger than the entire aperture, reject it early
3535 * before evicting everything in a vain attempt to find space.
3537 if (obj->base.size > end) {
3538 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3540 flags & PIN_MAPPABLE ? "mappable" : "total",
3542 return ERR_PTR(-E2BIG);
3545 ret = i915_gem_object_get_pages(obj);
3547 return ERR_PTR(ret);
3549 i915_gem_object_pin_pages(obj);
3551 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3556 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3560 DRM_MM_SEARCH_DEFAULT,
3561 DRM_MM_CREATE_DEFAULT);
3563 ret = i915_gem_evict_something(dev, vm, size, alignment,
3572 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3574 goto err_remove_node;
3577 ret = i915_gem_gtt_prepare_object(obj);
3579 goto err_remove_node;
3581 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3582 list_add_tail(&vma->mm_list, &vm->inactive_list);
3584 trace_i915_vma_bind(vma, flags);
3585 vma->bind_vma(vma, obj->cache_level,
3586 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3591 drm_mm_remove_node(&vma->node);
3593 i915_gem_vma_destroy(vma);
3596 i915_gem_object_unpin_pages(obj);
3601 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3604 /* If we don't have a page list set up, then we're not pinned
3605 * to GPU, and we can ignore the cache flush because it'll happen
3606 * again at bind time.
3608 if (obj->pages == NULL)
3612 * Stolen memory is always coherent with the GPU as it is explicitly
3613 * marked as wc by the system, or the system is cache-coherent.
3615 if (obj->stolen || obj->phys_handle)
3618 /* If the GPU is snooping the contents of the CPU cache,
3619 * we do not need to manually clear the CPU cache lines. However,
3620 * the caches are only snooped when the render cache is
3621 * flushed/invalidated. As we always have to emit invalidations
3622 * and flushes when moving into and out of the RENDER domain, correct
3623 * snooping behaviour occurs naturally as the result of our domain
3626 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3629 trace_i915_gem_object_clflush(obj);
3630 drm_clflush_sg(obj->pages);
3635 /** Flushes the GTT write domain for the object if it's dirty. */
3637 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3639 uint32_t old_write_domain;
3641 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3644 /* No actual flushing is required for the GTT write domain. Writes
3645 * to it immediately go to main memory as far as we know, so there's
3646 * no chipset flush. It also doesn't land in render cache.
3648 * However, we do have to enforce the order so that all writes through
3649 * the GTT land before any writes to the device, such as updates to
3654 old_write_domain = obj->base.write_domain;
3655 obj->base.write_domain = 0;
3657 intel_fb_obj_flush(obj, false);
3659 trace_i915_gem_object_change_domain(obj,
3660 obj->base.read_domains,
3664 /** Flushes the CPU write domain for the object if it's dirty. */
3666 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3669 uint32_t old_write_domain;
3671 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3674 if (i915_gem_clflush_object(obj, force))
3675 i915_gem_chipset_flush(obj->base.dev);
3677 old_write_domain = obj->base.write_domain;
3678 obj->base.write_domain = 0;
3680 intel_fb_obj_flush(obj, false);
3682 trace_i915_gem_object_change_domain(obj,
3683 obj->base.read_domains,
3688 * Moves a single object to the GTT read, and possibly write domain.
3690 * This function returns when the move is complete, including waiting on
3694 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3696 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3697 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3698 uint32_t old_write_domain, old_read_domains;
3701 /* Not valid to be called on unbound objects. */
3705 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3708 ret = i915_gem_object_wait_rendering(obj, !write);
3712 i915_gem_object_retire(obj);
3713 i915_gem_object_flush_cpu_write_domain(obj, false);
3715 /* Serialise direct access to this object with the barriers for
3716 * coherent writes from the GPU, by effectively invalidating the
3717 * GTT domain upon first access.
3719 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3722 old_write_domain = obj->base.write_domain;
3723 old_read_domains = obj->base.read_domains;
3725 /* It should now be out of any other write domains, and we can update
3726 * the domain values for our changes.
3728 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3729 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3731 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3732 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3737 intel_fb_obj_invalidate(obj, NULL);
3739 trace_i915_gem_object_change_domain(obj,
3743 /* And bump the LRU for this access */
3744 if (i915_gem_object_is_inactive(obj))
3745 list_move_tail(&vma->mm_list,
3746 &dev_priv->gtt.base.inactive_list);
3751 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3752 enum i915_cache_level cache_level)
3754 struct drm_device *dev = obj->base.dev;
3755 struct i915_vma *vma, *next;
3758 if (obj->cache_level == cache_level)
3761 if (i915_gem_obj_is_pinned(obj)) {
3762 DRM_DEBUG("can not change the cache level of pinned objects\n");
3766 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3767 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3768 ret = i915_vma_unbind(vma);
3774 if (i915_gem_obj_bound_any(obj)) {
3775 ret = i915_gem_object_finish_gpu(obj);
3779 i915_gem_object_finish_gtt(obj);
3781 /* Before SandyBridge, you could not use tiling or fence
3782 * registers with snooped memory, so relinquish any fences
3783 * currently pointing to our region in the aperture.
3785 if (INTEL_INFO(dev)->gen < 6) {
3786 ret = i915_gem_object_put_fence(obj);
3791 list_for_each_entry(vma, &obj->vma_list, vma_link)
3792 if (drm_mm_node_allocated(&vma->node))
3793 vma->bind_vma(vma, cache_level,
3794 vma->bound & GLOBAL_BIND);
3797 list_for_each_entry(vma, &obj->vma_list, vma_link)
3798 vma->node.color = cache_level;
3799 obj->cache_level = cache_level;
3801 if (cpu_write_needs_clflush(obj)) {
3802 u32 old_read_domains, old_write_domain;
3804 /* If we're coming from LLC cached, then we haven't
3805 * actually been tracking whether the data is in the
3806 * CPU cache or not, since we only allow one bit set
3807 * in obj->write_domain and have been skipping the clflushes.
3808 * Just set it to the CPU cache for now.
3810 i915_gem_object_retire(obj);
3811 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3813 old_read_domains = obj->base.read_domains;
3814 old_write_domain = obj->base.write_domain;
3816 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3817 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3819 trace_i915_gem_object_change_domain(obj,
3827 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3828 struct drm_file *file)
3830 struct drm_i915_gem_caching *args = data;
3831 struct drm_i915_gem_object *obj;
3834 ret = i915_mutex_lock_interruptible(dev);
3838 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3839 if (&obj->base == NULL) {
3844 switch (obj->cache_level) {
3845 case I915_CACHE_LLC:
3846 case I915_CACHE_L3_LLC:
3847 args->caching = I915_CACHING_CACHED;
3851 args->caching = I915_CACHING_DISPLAY;
3855 args->caching = I915_CACHING_NONE;
3859 drm_gem_object_unreference(&obj->base);
3861 mutex_unlock(&dev->struct_mutex);
3865 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3866 struct drm_file *file)
3868 struct drm_i915_gem_caching *args = data;
3869 struct drm_i915_gem_object *obj;
3870 enum i915_cache_level level;
3873 switch (args->caching) {
3874 case I915_CACHING_NONE:
3875 level = I915_CACHE_NONE;
3877 case I915_CACHING_CACHED:
3878 level = I915_CACHE_LLC;
3880 case I915_CACHING_DISPLAY:
3881 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3887 ret = i915_mutex_lock_interruptible(dev);
3891 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3892 if (&obj->base == NULL) {
3897 ret = i915_gem_object_set_cache_level(obj, level);
3899 drm_gem_object_unreference(&obj->base);
3901 mutex_unlock(&dev->struct_mutex);
3905 static bool is_pin_display(struct drm_i915_gem_object *obj)
3907 struct i915_vma *vma;
3909 vma = i915_gem_obj_to_ggtt(obj);
3913 /* There are 2 sources that pin objects:
3914 * 1. The display engine (scanouts, sprites, cursors);
3915 * 2. Reservations for execbuffer;
3917 * We can ignore reservations as we hold the struct_mutex and
3918 * are only called outside of the reservation path.
3920 return vma->pin_count;
3924 * Prepare buffer for display plane (scanout, cursors, etc).
3925 * Can be called from an uninterruptible phase (modesetting) and allows
3926 * any flushes to be pipelined (for pageflips).
3929 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3931 struct intel_engine_cs *pipelined)
3933 u32 old_read_domains, old_write_domain;
3934 bool was_pin_display;
3937 if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3938 ret = i915_gem_object_sync(obj, pipelined);
3943 /* Mark the pin_display early so that we account for the
3944 * display coherency whilst setting up the cache domains.
3946 was_pin_display = obj->pin_display;
3947 obj->pin_display = true;
3949 /* The display engine is not coherent with the LLC cache on gen6. As
3950 * a result, we make sure that the pinning that is about to occur is
3951 * done with uncached PTEs. This is lowest common denominator for all
3954 * However for gen6+, we could do better by using the GFDT bit instead
3955 * of uncaching, which would allow us to flush all the LLC-cached data
3956 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3958 ret = i915_gem_object_set_cache_level(obj,
3959 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3961 goto err_unpin_display;
3963 /* As the user may map the buffer once pinned in the display plane
3964 * (e.g. libkms for the bootup splash), we have to ensure that we
3965 * always use map_and_fenceable for all scanout buffers.
3967 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3969 goto err_unpin_display;
3971 i915_gem_object_flush_cpu_write_domain(obj, true);
3973 old_write_domain = obj->base.write_domain;
3974 old_read_domains = obj->base.read_domains;
3976 /* It should now be out of any other write domains, and we can update
3977 * the domain values for our changes.
3979 obj->base.write_domain = 0;
3980 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3982 trace_i915_gem_object_change_domain(obj,
3989 WARN_ON(was_pin_display != is_pin_display(obj));
3990 obj->pin_display = was_pin_display;
3995 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3997 i915_gem_object_ggtt_unpin(obj);
3998 obj->pin_display = is_pin_display(obj);
4002 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4006 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4009 ret = i915_gem_object_wait_rendering(obj, false);
4013 /* Ensure that we invalidate the GPU's caches and TLBs. */
4014 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4019 * Moves a single object to the CPU read, and possibly write domain.
4021 * This function returns when the move is complete, including waiting on
4025 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4027 uint32_t old_write_domain, old_read_domains;
4030 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4033 ret = i915_gem_object_wait_rendering(obj, !write);
4037 i915_gem_object_retire(obj);
4038 i915_gem_object_flush_gtt_write_domain(obj);
4040 old_write_domain = obj->base.write_domain;
4041 old_read_domains = obj->base.read_domains;
4043 /* Flush the CPU cache if it's still invalid. */
4044 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4045 i915_gem_clflush_object(obj, false);
4047 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4050 /* It should now be out of any other write domains, and we can update
4051 * the domain values for our changes.
4053 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4055 /* If we're writing through the CPU, then the GPU read domains will
4056 * need to be invalidated at next use.
4059 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4060 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4064 intel_fb_obj_invalidate(obj, NULL);
4066 trace_i915_gem_object_change_domain(obj,
4073 /* Throttle our rendering by waiting until the ring has completed our requests
4074 * emitted over 20 msec ago.
4076 * Note that if we were to use the current jiffies each time around the loop,
4077 * we wouldn't escape the function with any frames outstanding if the time to
4078 * render a frame was over 20ms.
4080 * This should get us reasonable parallelism between CPU and GPU but also
4081 * relatively low latency when blocking on a particular request to finish.
4084 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct drm_i915_file_private *file_priv = file->driver_priv;
4088 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4089 struct drm_i915_gem_request *request, *target = NULL;
4090 unsigned reset_counter;
4093 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4097 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4101 spin_lock(&file_priv->mm.lock);
4102 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4103 if (time_after_eq(request->emitted_jiffies, recent_enough))
4108 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4110 i915_gem_request_reference(target);
4111 spin_unlock(&file_priv->mm.lock);
4116 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4118 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4120 mutex_lock(&dev->struct_mutex);
4121 i915_gem_request_unreference(target);
4122 mutex_unlock(&dev->struct_mutex);
4128 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4130 struct drm_i915_gem_object *obj = vma->obj;
4133 vma->node.start & (alignment - 1))
4136 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4139 if (flags & PIN_OFFSET_BIAS &&
4140 vma->node.start < (flags & PIN_OFFSET_MASK))
4147 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4148 struct i915_address_space *vm,
4152 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4153 struct i915_vma *vma;
4157 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4160 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4163 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4166 vma = i915_gem_obj_to_vma(obj, vm);
4168 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4171 if (i915_vma_misplaced(vma, alignment, flags)) {
4172 WARN(vma->pin_count,
4173 "bo is already pinned with incorrect alignment:"
4174 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4175 " obj->map_and_fenceable=%d\n",
4176 i915_gem_obj_offset(obj, vm), alignment,
4177 !!(flags & PIN_MAPPABLE),
4178 obj->map_and_fenceable);
4179 ret = i915_vma_unbind(vma);
4187 bound = vma ? vma->bound : 0;
4188 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4189 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4191 return PTR_ERR(vma);
4194 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4195 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4197 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4198 bool mappable, fenceable;
4199 u32 fence_size, fence_alignment;
4201 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4204 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4209 fenceable = (vma->node.size == fence_size &&
4210 (vma->node.start & (fence_alignment - 1)) == 0);
4212 mappable = (vma->node.start + obj->base.size <=
4213 dev_priv->gtt.mappable_end);
4215 obj->map_and_fenceable = mappable && fenceable;
4218 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4221 if (flags & PIN_MAPPABLE)
4222 obj->pin_mappable |= true;
4228 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4230 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4233 BUG_ON(vma->pin_count == 0);
4234 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4236 if (--vma->pin_count == 0)
4237 obj->pin_mappable = false;
4241 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4243 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4244 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4245 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4247 WARN_ON(!ggtt_vma ||
4248 dev_priv->fence_regs[obj->fence_reg].pin_count >
4249 ggtt_vma->pin_count);
4250 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4257 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4259 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4260 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4261 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4262 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4267 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4268 struct drm_file *file)
4270 struct drm_i915_gem_busy *args = data;
4271 struct drm_i915_gem_object *obj;
4274 ret = i915_mutex_lock_interruptible(dev);
4278 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4279 if (&obj->base == NULL) {
4284 /* Count all active objects as busy, even if they are currently not used
4285 * by the gpu. Users of this interface expect objects to eventually
4286 * become non-busy without any further actions, therefore emit any
4287 * necessary flushes here.
4289 ret = i915_gem_object_flush_active(obj);
4291 args->busy = obj->active;
4292 if (obj->last_read_req) {
4293 struct intel_engine_cs *ring;
4294 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4295 ring = i915_gem_request_get_ring(obj->last_read_req);
4296 args->busy |= intel_ring_flag(ring) << 16;
4299 drm_gem_object_unreference(&obj->base);
4301 mutex_unlock(&dev->struct_mutex);
4306 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4307 struct drm_file *file_priv)
4309 return i915_gem_ring_throttle(dev, file_priv);
4313 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4314 struct drm_file *file_priv)
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 struct drm_i915_gem_madvise *args = data;
4318 struct drm_i915_gem_object *obj;
4321 switch (args->madv) {
4322 case I915_MADV_DONTNEED:
4323 case I915_MADV_WILLNEED:
4329 ret = i915_mutex_lock_interruptible(dev);
4333 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4334 if (&obj->base == NULL) {
4339 if (i915_gem_obj_is_pinned(obj)) {
4345 obj->tiling_mode != I915_TILING_NONE &&
4346 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4347 if (obj->madv == I915_MADV_WILLNEED)
4348 i915_gem_object_unpin_pages(obj);
4349 if (args->madv == I915_MADV_WILLNEED)
4350 i915_gem_object_pin_pages(obj);
4353 if (obj->madv != __I915_MADV_PURGED)
4354 obj->madv = args->madv;
4356 /* if the object is no longer attached, discard its backing storage */
4357 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4358 i915_gem_object_truncate(obj);
4360 args->retained = obj->madv != __I915_MADV_PURGED;
4363 drm_gem_object_unreference(&obj->base);
4365 mutex_unlock(&dev->struct_mutex);
4369 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4370 const struct drm_i915_gem_object_ops *ops)
4372 INIT_LIST_HEAD(&obj->global_list);
4373 INIT_LIST_HEAD(&obj->ring_list);
4374 INIT_LIST_HEAD(&obj->obj_exec_link);
4375 INIT_LIST_HEAD(&obj->vma_list);
4379 obj->fence_reg = I915_FENCE_REG_NONE;
4380 obj->madv = I915_MADV_WILLNEED;
4382 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4385 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4386 .get_pages = i915_gem_object_get_pages_gtt,
4387 .put_pages = i915_gem_object_put_pages_gtt,
4390 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4393 struct drm_i915_gem_object *obj;
4394 struct address_space *mapping;
4397 obj = i915_gem_object_alloc(dev);
4401 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4402 i915_gem_object_free(obj);
4406 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4407 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4408 /* 965gm cannot relocate objects above 4GiB. */
4409 mask &= ~__GFP_HIGHMEM;
4410 mask |= __GFP_DMA32;
4413 mapping = file_inode(obj->base.filp)->i_mapping;
4414 mapping_set_gfp_mask(mapping, mask);
4416 i915_gem_object_init(obj, &i915_gem_object_ops);
4418 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4419 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4422 /* On some devices, we can have the GPU use the LLC (the CPU
4423 * cache) for about a 10% performance improvement
4424 * compared to uncached. Graphics requests other than
4425 * display scanout are coherent with the CPU in
4426 * accessing this cache. This means in this mode we
4427 * don't need to clflush on the CPU side, and on the
4428 * GPU side we only need to flush internal caches to
4429 * get data visible to the CPU.
4431 * However, we maintain the display planes as UC, and so
4432 * need to rebind when first used as such.
4434 obj->cache_level = I915_CACHE_LLC;
4436 obj->cache_level = I915_CACHE_NONE;
4438 trace_i915_gem_object_create(obj);
4443 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4445 /* If we are the last user of the backing storage (be it shmemfs
4446 * pages or stolen etc), we know that the pages are going to be
4447 * immediately released. In this case, we can then skip copying
4448 * back the contents from the GPU.
4451 if (obj->madv != I915_MADV_WILLNEED)
4454 if (obj->base.filp == NULL)
4457 /* At first glance, this looks racy, but then again so would be
4458 * userspace racing mmap against close. However, the first external
4459 * reference to the filp can only be obtained through the
4460 * i915_gem_mmap_ioctl() which safeguards us against the user
4461 * acquiring such a reference whilst we are in the middle of
4462 * freeing the object.
4464 return atomic_long_read(&obj->base.filp->f_count) == 1;
4467 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4469 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4470 struct drm_device *dev = obj->base.dev;
4471 struct drm_i915_private *dev_priv = dev->dev_private;
4472 struct i915_vma *vma, *next;
4474 intel_runtime_pm_get(dev_priv);
4476 trace_i915_gem_object_destroy(obj);
4478 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4482 ret = i915_vma_unbind(vma);
4483 if (WARN_ON(ret == -ERESTARTSYS)) {
4484 bool was_interruptible;
4486 was_interruptible = dev_priv->mm.interruptible;
4487 dev_priv->mm.interruptible = false;
4489 WARN_ON(i915_vma_unbind(vma));
4491 dev_priv->mm.interruptible = was_interruptible;
4495 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4496 * before progressing. */
4498 i915_gem_object_unpin_pages(obj);
4500 WARN_ON(obj->frontbuffer_bits);
4502 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4503 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4504 obj->tiling_mode != I915_TILING_NONE)
4505 i915_gem_object_unpin_pages(obj);
4507 if (WARN_ON(obj->pages_pin_count))
4508 obj->pages_pin_count = 0;
4509 if (discard_backing_storage(obj))
4510 obj->madv = I915_MADV_DONTNEED;
4511 i915_gem_object_put_pages(obj);
4512 i915_gem_object_free_mmap_offset(obj);
4516 if (obj->base.import_attach)
4517 drm_prime_gem_destroy(&obj->base, NULL);
4519 if (obj->ops->release)
4520 obj->ops->release(obj);
4522 drm_gem_object_release(&obj->base);
4523 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4526 i915_gem_object_free(obj);
4528 intel_runtime_pm_put(dev_priv);
4531 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4532 struct i915_address_space *vm)
4534 struct i915_vma *vma;
4535 list_for_each_entry(vma, &obj->vma_list, vma_link)
4542 void i915_gem_vma_destroy(struct i915_vma *vma)
4544 struct i915_address_space *vm = NULL;
4545 WARN_ON(vma->node.allocated);
4547 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4548 if (!list_empty(&vma->exec_list))
4553 if (!i915_is_ggtt(vm))
4554 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4556 list_del(&vma->vma_link);
4562 i915_gem_stop_ringbuffers(struct drm_device *dev)
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565 struct intel_engine_cs *ring;
4568 for_each_ring(ring, dev_priv, i)
4569 dev_priv->gt.stop_ring(ring);
4573 i915_gem_suspend(struct drm_device *dev)
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4578 mutex_lock(&dev->struct_mutex);
4579 ret = i915_gpu_idle(dev);
4583 i915_gem_retire_requests(dev);
4585 /* Under UMS, be paranoid and evict. */
4586 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4587 i915_gem_evict_everything(dev);
4589 i915_gem_stop_ringbuffers(dev);
4590 mutex_unlock(&dev->struct_mutex);
4592 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4593 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4594 flush_delayed_work(&dev_priv->mm.idle_work);
4596 /* Assert that we sucessfully flushed all the work and
4597 * reset the GPU back to its idle, low power state.
4599 WARN_ON(dev_priv->mm.busy);
4604 mutex_unlock(&dev->struct_mutex);
4608 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4610 struct drm_device *dev = ring->dev;
4611 struct drm_i915_private *dev_priv = dev->dev_private;
4612 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4613 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4616 if (!HAS_L3_DPF(dev) || !remap_info)
4619 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4624 * Note: We do not worry about the concurrent register cacheline hang
4625 * here because no other code should access these registers other than
4626 * at initialization time.
4628 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4629 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4630 intel_ring_emit(ring, reg_base + i);
4631 intel_ring_emit(ring, remap_info[i/4]);
4634 intel_ring_advance(ring);
4639 void i915_gem_init_swizzling(struct drm_device *dev)
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4643 if (INTEL_INFO(dev)->gen < 5 ||
4644 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4647 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4648 DISP_TILE_SURFACE_SWIZZLING);
4653 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4655 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4656 else if (IS_GEN7(dev))
4657 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4658 else if (IS_GEN8(dev))
4659 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4665 intel_enable_blt(struct drm_device *dev)
4670 /* The blitter was dysfunctional on early prototypes */
4671 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4672 DRM_INFO("BLT not supported on this pre-production hardware;"
4673 " graphics performance will be degraded.\n");
4680 static void init_unused_ring(struct drm_device *dev, u32 base)
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4684 I915_WRITE(RING_CTL(base), 0);
4685 I915_WRITE(RING_HEAD(base), 0);
4686 I915_WRITE(RING_TAIL(base), 0);
4687 I915_WRITE(RING_START(base), 0);
4690 static void init_unused_rings(struct drm_device *dev)
4693 init_unused_ring(dev, PRB1_BASE);
4694 init_unused_ring(dev, SRB0_BASE);
4695 init_unused_ring(dev, SRB1_BASE);
4696 init_unused_ring(dev, SRB2_BASE);
4697 init_unused_ring(dev, SRB3_BASE);
4698 } else if (IS_GEN2(dev)) {
4699 init_unused_ring(dev, SRB0_BASE);
4700 init_unused_ring(dev, SRB1_BASE);
4701 } else if (IS_GEN3(dev)) {
4702 init_unused_ring(dev, PRB1_BASE);
4703 init_unused_ring(dev, PRB2_BASE);
4707 int i915_gem_init_rings(struct drm_device *dev)
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4712 ret = intel_init_render_ring_buffer(dev);
4717 ret = intel_init_bsd_ring_buffer(dev);
4719 goto cleanup_render_ring;
4722 if (intel_enable_blt(dev)) {
4723 ret = intel_init_blt_ring_buffer(dev);
4725 goto cleanup_bsd_ring;
4728 if (HAS_VEBOX(dev)) {
4729 ret = intel_init_vebox_ring_buffer(dev);
4731 goto cleanup_blt_ring;
4734 if (HAS_BSD2(dev)) {
4735 ret = intel_init_bsd2_ring_buffer(dev);
4737 goto cleanup_vebox_ring;
4740 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4742 goto cleanup_bsd2_ring;
4747 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4749 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4751 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4753 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4754 cleanup_render_ring:
4755 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4761 i915_gem_init_hw(struct drm_device *dev)
4763 struct drm_i915_private *dev_priv = dev->dev_private;
4764 struct intel_engine_cs *ring;
4767 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4770 if (dev_priv->ellc_size)
4771 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4773 if (IS_HASWELL(dev))
4774 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4775 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4777 if (HAS_PCH_NOP(dev)) {
4778 if (IS_IVYBRIDGE(dev)) {
4779 u32 temp = I915_READ(GEN7_MSG_CTL);
4780 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4781 I915_WRITE(GEN7_MSG_CTL, temp);
4782 } else if (INTEL_INFO(dev)->gen >= 7) {
4783 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4784 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4785 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4789 i915_gem_init_swizzling(dev);
4792 * At least 830 can leave some of the unused rings
4793 * "active" (ie. head != tail) after resume which
4794 * will prevent c3 entry. Makes sure all unused rings
4797 init_unused_rings(dev);
4799 for_each_ring(ring, dev_priv, i) {
4800 ret = ring->init_hw(ring);
4805 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4806 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4809 * XXX: Contexts should only be initialized once. Doing a switch to the
4810 * default context switch however is something we'd like to do after
4811 * reset or thaw (the latter may not actually be necessary for HW, but
4812 * goes with our code better). Context switching requires rings (for
4813 * the do_switch), but before enabling PPGTT. So don't move this.
4815 ret = i915_gem_context_enable(dev_priv);
4816 if (ret && ret != -EIO) {
4817 DRM_ERROR("Context enable failed %d\n", ret);
4818 i915_gem_cleanup_ringbuffer(dev);
4823 ret = i915_ppgtt_init_hw(dev);
4824 if (ret && ret != -EIO) {
4825 DRM_ERROR("PPGTT enable failed %d\n", ret);
4826 i915_gem_cleanup_ringbuffer(dev);
4832 int i915_gem_init(struct drm_device *dev)
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4837 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4838 i915.enable_execlists);
4840 mutex_lock(&dev->struct_mutex);
4842 if (IS_VALLEYVIEW(dev)) {
4843 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4844 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4845 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4846 VLV_GTLC_ALLOWWAKEACK), 10))
4847 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4850 if (!i915.enable_execlists) {
4851 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4852 dev_priv->gt.init_rings = i915_gem_init_rings;
4853 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4854 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4856 dev_priv->gt.do_execbuf = intel_execlists_submission;
4857 dev_priv->gt.init_rings = intel_logical_rings_init;
4858 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4859 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4862 ret = i915_gem_init_userptr(dev);
4864 mutex_unlock(&dev->struct_mutex);
4868 i915_gem_init_global_gtt(dev);
4870 ret = i915_gem_context_init(dev);
4872 mutex_unlock(&dev->struct_mutex);
4876 ret = dev_priv->gt.init_rings(dev);
4880 ret = i915_gem_init_hw(dev);
4882 /* Allow ring initialisation to fail by marking the GPU as
4883 * wedged. But we only want to do this where the GPU is angry,
4884 * for all other failure, such as an allocation failure, bail.
4886 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4887 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4890 mutex_unlock(&dev->struct_mutex);
4896 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4899 struct intel_engine_cs *ring;
4902 for_each_ring(ring, dev_priv, i)
4903 dev_priv->gt.cleanup_ring(ring);
4907 init_ring_lists(struct intel_engine_cs *ring)
4909 INIT_LIST_HEAD(&ring->active_list);
4910 INIT_LIST_HEAD(&ring->request_list);
4913 void i915_init_vm(struct drm_i915_private *dev_priv,
4914 struct i915_address_space *vm)
4916 if (!i915_is_ggtt(vm))
4917 drm_mm_init(&vm->mm, vm->start, vm->total);
4918 vm->dev = dev_priv->dev;
4919 INIT_LIST_HEAD(&vm->active_list);
4920 INIT_LIST_HEAD(&vm->inactive_list);
4921 INIT_LIST_HEAD(&vm->global_link);
4922 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4926 i915_gem_load(struct drm_device *dev)
4928 struct drm_i915_private *dev_priv = dev->dev_private;
4932 kmem_cache_create("i915_gem_object",
4933 sizeof(struct drm_i915_gem_object), 0,
4937 INIT_LIST_HEAD(&dev_priv->vm_list);
4938 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4940 INIT_LIST_HEAD(&dev_priv->context_list);
4941 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4942 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4943 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4944 for (i = 0; i < I915_NUM_RINGS; i++)
4945 init_ring_lists(&dev_priv->ring[i]);
4946 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4947 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4948 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4949 i915_gem_retire_work_handler);
4950 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4951 i915_gem_idle_work_handler);
4952 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4954 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4955 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4956 I915_WRITE(MI_ARB_STATE,
4957 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4960 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4962 /* Old X drivers will take 0-2 for front, back, depth buffers */
4963 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4964 dev_priv->fence_reg_start = 3;
4966 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4967 dev_priv->num_fence_regs = 32;
4968 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4969 dev_priv->num_fence_regs = 16;
4971 dev_priv->num_fence_regs = 8;
4973 /* Initialize fence registers to zero */
4974 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4975 i915_gem_restore_fences(dev);
4977 i915_gem_detect_bit_6_swizzle(dev);
4978 init_waitqueue_head(&dev_priv->pending_flip_queue);
4980 dev_priv->mm.interruptible = true;
4982 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4983 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4984 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4985 register_shrinker(&dev_priv->mm.shrinker);
4987 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4988 register_oom_notifier(&dev_priv->mm.oom_notifier);
4990 mutex_init(&dev_priv->fb_tracking.lock);
4993 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4995 struct drm_i915_file_private *file_priv = file->driver_priv;
4997 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4999 /* Clean up our request list when the client is going away, so that
5000 * later retire_requests won't dereference our soon-to-be-gone
5003 spin_lock(&file_priv->mm.lock);
5004 while (!list_empty(&file_priv->mm.request_list)) {
5005 struct drm_i915_gem_request *request;
5007 request = list_first_entry(&file_priv->mm.request_list,
5008 struct drm_i915_gem_request,
5010 list_del(&request->client_list);
5011 request->file_priv = NULL;
5013 spin_unlock(&file_priv->mm.lock);
5017 i915_gem_file_idle_work_handler(struct work_struct *work)
5019 struct drm_i915_file_private *file_priv =
5020 container_of(work, typeof(*file_priv), mm.idle_work.work);
5022 atomic_set(&file_priv->rps_wait_boost, false);
5025 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5027 struct drm_i915_file_private *file_priv;
5030 DRM_DEBUG_DRIVER("\n");
5032 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5036 file->driver_priv = file_priv;
5037 file_priv->dev_priv = dev->dev_private;
5038 file_priv->file = file;
5040 spin_lock_init(&file_priv->mm.lock);
5041 INIT_LIST_HEAD(&file_priv->mm.request_list);
5042 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5043 i915_gem_file_idle_work_handler);
5045 ret = i915_gem_context_open(dev, file);
5053 * i915_gem_track_fb - update frontbuffer tracking
5054 * old: current GEM buffer for the frontbuffer slots
5055 * new: new GEM buffer for the frontbuffer slots
5056 * frontbuffer_bits: bitmask of frontbuffer slots
5058 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5059 * from @old and setting them in @new. Both @old and @new can be NULL.
5061 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5062 struct drm_i915_gem_object *new,
5063 unsigned frontbuffer_bits)
5066 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5067 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5068 old->frontbuffer_bits &= ~frontbuffer_bits;
5072 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5073 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5074 new->frontbuffer_bits |= frontbuffer_bits;
5078 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5080 if (!mutex_is_locked(mutex))
5083 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5084 return mutex->owner == task;
5086 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5091 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5093 if (!mutex_trylock(&dev->struct_mutex)) {
5094 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5097 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5107 static int num_vma_bound(struct drm_i915_gem_object *obj)
5109 struct i915_vma *vma;
5112 list_for_each_entry(vma, &obj->vma_list, vma_link)
5113 if (drm_mm_node_allocated(&vma->node))
5119 static unsigned long
5120 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5122 struct drm_i915_private *dev_priv =
5123 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5124 struct drm_device *dev = dev_priv->dev;
5125 struct drm_i915_gem_object *obj;
5126 unsigned long count;
5129 if (!i915_gem_shrinker_lock(dev, &unlock))
5133 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5134 if (obj->pages_pin_count == 0)
5135 count += obj->base.size >> PAGE_SHIFT;
5137 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5138 if (!i915_gem_obj_is_pinned(obj) &&
5139 obj->pages_pin_count == num_vma_bound(obj))
5140 count += obj->base.size >> PAGE_SHIFT;
5144 mutex_unlock(&dev->struct_mutex);
5149 /* All the new VM stuff */
5150 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5151 struct i915_address_space *vm)
5153 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5154 struct i915_vma *vma;
5156 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5158 list_for_each_entry(vma, &o->vma_list, vma_link) {
5160 return vma->node.start;
5163 WARN(1, "%s vma for this object not found.\n",
5164 i915_is_ggtt(vm) ? "global" : "ppgtt");
5168 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5169 struct i915_address_space *vm)
5171 struct i915_vma *vma;
5173 list_for_each_entry(vma, &o->vma_list, vma_link)
5174 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5180 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5182 struct i915_vma *vma;
5184 list_for_each_entry(vma, &o->vma_list, vma_link)
5185 if (drm_mm_node_allocated(&vma->node))
5191 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5192 struct i915_address_space *vm)
5194 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5195 struct i915_vma *vma;
5197 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5199 BUG_ON(list_empty(&o->vma_list));
5201 list_for_each_entry(vma, &o->vma_list, vma_link)
5203 return vma->node.size;
5208 static unsigned long
5209 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5211 struct drm_i915_private *dev_priv =
5212 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5213 struct drm_device *dev = dev_priv->dev;
5214 unsigned long freed;
5217 if (!i915_gem_shrinker_lock(dev, &unlock))
5220 freed = i915_gem_shrink(dev_priv,
5223 I915_SHRINK_UNBOUND |
5224 I915_SHRINK_PURGEABLE);
5225 if (freed < sc->nr_to_scan)
5226 freed += i915_gem_shrink(dev_priv,
5227 sc->nr_to_scan - freed,
5229 I915_SHRINK_UNBOUND);
5231 mutex_unlock(&dev->struct_mutex);
5237 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5239 struct drm_i915_private *dev_priv =
5240 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5241 struct drm_device *dev = dev_priv->dev;
5242 struct drm_i915_gem_object *obj;
5243 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5244 unsigned long pinned, bound, unbound, freed_pages;
5245 bool was_interruptible;
5248 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5249 schedule_timeout_killable(1);
5250 if (fatal_signal_pending(current))
5254 pr_err("Unable to purge GPU memory due lock contention.\n");
5258 was_interruptible = dev_priv->mm.interruptible;
5259 dev_priv->mm.interruptible = false;
5261 freed_pages = i915_gem_shrink_all(dev_priv);
5263 dev_priv->mm.interruptible = was_interruptible;
5265 /* Because we may be allocating inside our own driver, we cannot
5266 * assert that there are no objects with pinned pages that are not
5267 * being pointed to by hardware.
5269 unbound = bound = pinned = 0;
5270 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5271 if (!obj->base.filp) /* not backed by a freeable object */
5274 if (obj->pages_pin_count)
5275 pinned += obj->base.size;
5277 unbound += obj->base.size;
5279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5280 if (!obj->base.filp)
5283 if (obj->pages_pin_count)
5284 pinned += obj->base.size;
5286 bound += obj->base.size;
5290 mutex_unlock(&dev->struct_mutex);
5292 if (freed_pages || unbound || bound)
5293 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5294 freed_pages << PAGE_SHIFT, pinned);
5295 if (unbound || bound)
5296 pr_err("%lu and %lu bytes still available in the "
5297 "bound and unbound GPU page lists.\n",
5300 *(unsigned long *)ptr += freed_pages;
5304 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5306 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5307 struct i915_vma *vma;
5309 list_for_each_entry(vma, &obj->vma_list, vma_link) {
5310 if (vma->vm == ggtt)