2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct drm_device *dev)
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct completion *x = &dev_priv->error_completion;
97 if (!atomic_read(&dev_priv->mm.wedged))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret < 0) {
113 if (atomic_read(&dev_priv->mm.wedged)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x->wait.lock, flags);
121 spin_unlock_irqrestore(&x->wait.lock, flags);
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
130 ret = i915_gem_wait_for_error(dev);
134 ret = mutex_lock_interruptible(&dev->struct_mutex);
138 WARN_ON(i915_verify_lists(dev));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
145 return obj->gtt_space && !obj->active;
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file)
152 struct drm_i915_gem_init *args = data;
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev)->gen >= 5)
165 mutex_lock(&dev->struct_mutex);
166 i915_gem_init_global_gtt(dev, args->gtt_start,
167 args->gtt_end, args->gtt_end);
168 mutex_unlock(&dev->struct_mutex);
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175 struct drm_file *file)
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct drm_i915_gem_get_aperture *args = data;
179 struct drm_i915_gem_object *obj;
183 mutex_lock(&dev->struct_mutex);
184 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
186 pinned += obj->gtt_space->size;
187 mutex_unlock(&dev->struct_mutex);
189 args->aper_size = dev_priv->mm.gtt_total;
190 args->aper_available_size = args->aper_size - pinned;
195 void *i915_gem_object_alloc(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
201 void i915_gem_object_free(struct drm_i915_gem_object *obj)
203 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
204 kmem_cache_free(dev_priv->slab, obj);
208 i915_gem_create(struct drm_file *file,
209 struct drm_device *dev,
213 struct drm_i915_gem_object *obj;
217 size = roundup(size, PAGE_SIZE);
221 /* Allocate the new object */
222 obj = i915_gem_alloc_object(dev, size);
226 ret = drm_gem_handle_create(file, &obj->base, &handle);
228 drm_gem_object_release(&obj->base);
229 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
230 i915_gem_object_free(obj);
234 /* drop reference from allocate - handle holds it now */
235 drm_gem_object_unreference(&obj->base);
236 trace_i915_gem_object_create(obj);
243 i915_gem_dumb_create(struct drm_file *file,
244 struct drm_device *dev,
245 struct drm_mode_create_dumb *args)
247 /* have to work out size/pitch and return them */
248 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
249 args->size = args->pitch * args->height;
250 return i915_gem_create(file, dev,
251 args->size, &args->handle);
254 int i915_gem_dumb_destroy(struct drm_file *file,
255 struct drm_device *dev,
258 return drm_gem_handle_delete(file, handle);
262 * Creates a new mm object and returns a handle to it.
265 i915_gem_create_ioctl(struct drm_device *dev, void *data,
266 struct drm_file *file)
268 struct drm_i915_gem_create *args = data;
270 return i915_gem_create(file, dev,
271 args->size, &args->handle);
275 __copy_to_user_swizzled(char __user *cpu_vaddr,
276 const char *gpu_vaddr, int gpu_offset,
279 int ret, cpu_offset = 0;
282 int cacheline_end = ALIGN(gpu_offset + 1, 64);
283 int this_length = min(cacheline_end - gpu_offset, length);
284 int swizzled_gpu_offset = gpu_offset ^ 64;
286 ret = __copy_to_user(cpu_vaddr + cpu_offset,
287 gpu_vaddr + swizzled_gpu_offset,
292 cpu_offset += this_length;
293 gpu_offset += this_length;
294 length -= this_length;
301 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
302 const char __user *cpu_vaddr,
305 int ret, cpu_offset = 0;
308 int cacheline_end = ALIGN(gpu_offset + 1, 64);
309 int this_length = min(cacheline_end - gpu_offset, length);
310 int swizzled_gpu_offset = gpu_offset ^ 64;
312 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
313 cpu_vaddr + cpu_offset,
318 cpu_offset += this_length;
319 gpu_offset += this_length;
320 length -= this_length;
326 /* Per-page copy function for the shmem pread fastpath.
327 * Flushes invalid cachelines before reading the target if
328 * needs_clflush is set. */
330 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
331 char __user *user_data,
332 bool page_do_bit17_swizzling, bool needs_clflush)
337 if (unlikely(page_do_bit17_swizzling))
340 vaddr = kmap_atomic(page);
342 drm_clflush_virt_range(vaddr + shmem_page_offset,
344 ret = __copy_to_user_inatomic(user_data,
345 vaddr + shmem_page_offset,
347 kunmap_atomic(vaddr);
349 return ret ? -EFAULT : 0;
353 shmem_clflush_swizzled_range(char *addr, unsigned long length,
356 if (unlikely(swizzled)) {
357 unsigned long start = (unsigned long) addr;
358 unsigned long end = (unsigned long) addr + length;
360 /* For swizzling simply ensure that we always flush both
361 * channels. Lame, but simple and it works. Swizzled
362 * pwrite/pread is far from a hotpath - current userspace
363 * doesn't use it at all. */
364 start = round_down(start, 128);
365 end = round_up(end, 128);
367 drm_clflush_virt_range((void *)start, end - start);
369 drm_clflush_virt_range(addr, length);
374 /* Only difference to the fast-path function is that this can handle bit17
375 * and uses non-atomic copy and kmap functions. */
377 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
378 char __user *user_data,
379 bool page_do_bit17_swizzling, bool needs_clflush)
386 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
388 page_do_bit17_swizzling);
390 if (page_do_bit17_swizzling)
391 ret = __copy_to_user_swizzled(user_data,
392 vaddr, shmem_page_offset,
395 ret = __copy_to_user(user_data,
396 vaddr + shmem_page_offset,
400 return ret ? - EFAULT : 0;
404 i915_gem_shmem_pread(struct drm_device *dev,
405 struct drm_i915_gem_object *obj,
406 struct drm_i915_gem_pread *args,
407 struct drm_file *file)
409 char __user *user_data;
412 int shmem_page_offset, page_length, ret = 0;
413 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
415 int needs_clflush = 0;
416 struct scatterlist *sg;
419 user_data = (char __user *) (uintptr_t) args->data_ptr;
422 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
424 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
425 /* If we're not in the cpu read domain, set ourself into the gtt
426 * read domain and manually flush cachelines (if required). This
427 * optimizes for the case when the gpu will dirty the data
428 * anyway again before the next pread happens. */
429 if (obj->cache_level == I915_CACHE_NONE)
431 if (obj->gtt_space) {
432 ret = i915_gem_object_set_to_gtt_domain(obj, false);
438 ret = i915_gem_object_get_pages(obj);
442 i915_gem_object_pin_pages(obj);
444 offset = args->offset;
446 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
449 if (i < offset >> PAGE_SHIFT)
455 /* Operation in this page
457 * shmem_page_offset = offset within page in shmem file
458 * page_length = bytes to copy for this page
460 shmem_page_offset = offset_in_page(offset);
461 page_length = remain;
462 if ((shmem_page_offset + page_length) > PAGE_SIZE)
463 page_length = PAGE_SIZE - shmem_page_offset;
466 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
467 (page_to_phys(page) & (1 << 17)) != 0;
469 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
470 user_data, page_do_bit17_swizzling,
475 mutex_unlock(&dev->struct_mutex);
478 ret = fault_in_multipages_writeable(user_data, remain);
479 /* Userspace is tricking us, but we've already clobbered
480 * its pages with the prefault and promised to write the
481 * data up to the first fault. Hence ignore any errors
482 * and just continue. */
487 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
488 user_data, page_do_bit17_swizzling,
491 mutex_lock(&dev->struct_mutex);
494 mark_page_accessed(page);
499 remain -= page_length;
500 user_data += page_length;
501 offset += page_length;
505 i915_gem_object_unpin_pages(obj);
511 * Reads data from the object referenced by handle.
513 * On error, the contents of *data are undefined.
516 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
517 struct drm_file *file)
519 struct drm_i915_gem_pread *args = data;
520 struct drm_i915_gem_object *obj;
526 if (!access_ok(VERIFY_WRITE,
527 (char __user *)(uintptr_t)args->data_ptr,
531 ret = i915_mutex_lock_interruptible(dev);
535 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
536 if (&obj->base == NULL) {
541 /* Bounds check source. */
542 if (args->offset > obj->base.size ||
543 args->size > obj->base.size - args->offset) {
548 /* prime objects have no backing filp to GEM pread/pwrite
551 if (!obj->base.filp) {
556 trace_i915_gem_object_pread(obj, args->offset, args->size);
558 ret = i915_gem_shmem_pread(dev, obj, args, file);
561 drm_gem_object_unreference(&obj->base);
563 mutex_unlock(&dev->struct_mutex);
567 /* This is the fast write path which cannot handle
568 * page faults in the source data
572 fast_user_write(struct io_mapping *mapping,
573 loff_t page_base, int page_offset,
574 char __user *user_data,
577 void __iomem *vaddr_atomic;
579 unsigned long unwritten;
581 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
582 /* We can use the cpu mem copy function because this is X86. */
583 vaddr = (void __force*)vaddr_atomic + page_offset;
584 unwritten = __copy_from_user_inatomic_nocache(vaddr,
586 io_mapping_unmap_atomic(vaddr_atomic);
591 * This is the fast pwrite path, where we copy the data directly from the
592 * user into the GTT, uncached.
595 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
596 struct drm_i915_gem_object *obj,
597 struct drm_i915_gem_pwrite *args,
598 struct drm_file *file)
600 drm_i915_private_t *dev_priv = dev->dev_private;
602 loff_t offset, page_base;
603 char __user *user_data;
604 int page_offset, page_length, ret;
606 ret = i915_gem_object_pin(obj, 0, true, true);
610 ret = i915_gem_object_set_to_gtt_domain(obj, true);
614 ret = i915_gem_object_put_fence(obj);
618 user_data = (char __user *) (uintptr_t) args->data_ptr;
621 offset = obj->gtt_offset + args->offset;
624 /* Operation in this page
626 * page_base = page offset within aperture
627 * page_offset = offset within page
628 * page_length = bytes to copy for this page
630 page_base = offset & PAGE_MASK;
631 page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((page_offset + remain) > PAGE_SIZE)
634 page_length = PAGE_SIZE - page_offset;
636 /* If we get a fault while copying data, then (presumably) our
637 * source page isn't available. Return the error and we'll
638 * retry in the slow path.
640 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
641 page_offset, user_data, page_length)) {
646 remain -= page_length;
647 user_data += page_length;
648 offset += page_length;
652 i915_gem_object_unpin(obj);
657 /* Per-page copy function for the shmem pwrite fastpath.
658 * Flushes invalid cachelines before writing to the target if
659 * needs_clflush_before is set and flushes out any written cachelines after
660 * writing if needs_clflush is set. */
662 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
663 char __user *user_data,
664 bool page_do_bit17_swizzling,
665 bool needs_clflush_before,
666 bool needs_clflush_after)
671 if (unlikely(page_do_bit17_swizzling))
674 vaddr = kmap_atomic(page);
675 if (needs_clflush_before)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
678 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
681 if (needs_clflush_after)
682 drm_clflush_virt_range(vaddr + shmem_page_offset,
684 kunmap_atomic(vaddr);
686 return ret ? -EFAULT : 0;
689 /* Only difference to the fast-path function is that this can handle bit17
690 * and uses non-atomic copy and kmap functions. */
692 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
693 char __user *user_data,
694 bool page_do_bit17_swizzling,
695 bool needs_clflush_before,
696 bool needs_clflush_after)
702 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
703 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
705 page_do_bit17_swizzling);
706 if (page_do_bit17_swizzling)
707 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
711 ret = __copy_from_user(vaddr + shmem_page_offset,
714 if (needs_clflush_after)
715 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
717 page_do_bit17_swizzling);
720 return ret ? -EFAULT : 0;
724 i915_gem_shmem_pwrite(struct drm_device *dev,
725 struct drm_i915_gem_object *obj,
726 struct drm_i915_gem_pwrite *args,
727 struct drm_file *file)
731 char __user *user_data;
732 int shmem_page_offset, page_length, ret = 0;
733 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
734 int hit_slowpath = 0;
735 int needs_clflush_after = 0;
736 int needs_clflush_before = 0;
738 struct scatterlist *sg;
740 user_data = (char __user *) (uintptr_t) args->data_ptr;
743 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
745 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
746 /* If we're not in the cpu write domain, set ourself into the gtt
747 * write domain and manually flush cachelines (if required). This
748 * optimizes for the case when the gpu will use the data
749 * right away and we therefore have to clflush anyway. */
750 if (obj->cache_level == I915_CACHE_NONE)
751 needs_clflush_after = 1;
752 if (obj->gtt_space) {
753 ret = i915_gem_object_set_to_gtt_domain(obj, true);
758 /* Same trick applies for invalidate partially written cachelines before
760 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
761 && obj->cache_level == I915_CACHE_NONE)
762 needs_clflush_before = 1;
764 ret = i915_gem_object_get_pages(obj);
768 i915_gem_object_pin_pages(obj);
770 offset = args->offset;
773 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
775 int partial_cacheline_write;
777 if (i < offset >> PAGE_SHIFT)
783 /* Operation in this page
785 * shmem_page_offset = offset within page in shmem file
786 * page_length = bytes to copy for this page
788 shmem_page_offset = offset_in_page(offset);
790 page_length = remain;
791 if ((shmem_page_offset + page_length) > PAGE_SIZE)
792 page_length = PAGE_SIZE - shmem_page_offset;
794 /* If we don't overwrite a cacheline completely we need to be
795 * careful to have up-to-date data by first clflushing. Don't
796 * overcomplicate things and flush the entire patch. */
797 partial_cacheline_write = needs_clflush_before &&
798 ((shmem_page_offset | page_length)
799 & (boot_cpu_data.x86_clflush_size - 1));
802 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
803 (page_to_phys(page) & (1 << 17)) != 0;
805 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
806 user_data, page_do_bit17_swizzling,
807 partial_cacheline_write,
808 needs_clflush_after);
813 mutex_unlock(&dev->struct_mutex);
814 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
815 user_data, page_do_bit17_swizzling,
816 partial_cacheline_write,
817 needs_clflush_after);
819 mutex_lock(&dev->struct_mutex);
822 set_page_dirty(page);
823 mark_page_accessed(page);
828 remain -= page_length;
829 user_data += page_length;
830 offset += page_length;
834 i915_gem_object_unpin_pages(obj);
838 * Fixup: Flush cpu caches in case we didn't flush the dirty
839 * cachelines in-line while writing and the object moved
840 * out of the cpu write domain while we've dropped the lock.
842 if (!needs_clflush_after &&
843 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
844 i915_gem_clflush_object(obj);
845 i915_gem_chipset_flush(dev);
849 if (needs_clflush_after)
850 i915_gem_chipset_flush(dev);
856 * Writes data to the object referenced by handle.
858 * On error, the contents of the buffer that were to be modified are undefined.
861 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *file)
864 struct drm_i915_gem_pwrite *args = data;
865 struct drm_i915_gem_object *obj;
871 if (!access_ok(VERIFY_READ,
872 (char __user *)(uintptr_t)args->data_ptr,
876 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
881 ret = i915_mutex_lock_interruptible(dev);
885 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
886 if (&obj->base == NULL) {
891 /* Bounds check destination. */
892 if (args->offset > obj->base.size ||
893 args->size > obj->base.size - args->offset) {
898 /* prime objects have no backing filp to GEM pread/pwrite
901 if (!obj->base.filp) {
906 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
909 /* We can only do the GTT pwrite on untiled buffers, as otherwise
910 * it would end up going through the fenced access, and we'll get
911 * different detiling behavior between reading and writing.
912 * pread/pwrite currently are reading and writing from the CPU
913 * perspective, requiring manual detiling by the client.
916 ret = i915_gem_phys_pwrite(dev, obj, args, file);
920 if (obj->cache_level == I915_CACHE_NONE &&
921 obj->tiling_mode == I915_TILING_NONE &&
922 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
923 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
924 /* Note that the gtt paths might fail with non-page-backed user
925 * pointers (e.g. gtt mappings when moving data between
926 * textures). Fallback to the shmem path in that case. */
929 if (ret == -EFAULT || ret == -ENOSPC)
930 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
933 drm_gem_object_unreference(&obj->base);
935 mutex_unlock(&dev->struct_mutex);
940 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
943 if (atomic_read(&dev_priv->mm.wedged)) {
944 struct completion *x = &dev_priv->error_completion;
945 bool recovery_complete;
948 /* Give the error handler a chance to run. */
949 spin_lock_irqsave(&x->wait.lock, flags);
950 recovery_complete = x->done > 0;
951 spin_unlock_irqrestore(&x->wait.lock, flags);
953 /* Non-interruptible callers can't handle -EAGAIN, hence return
954 * -EIO unconditionally for these. */
958 /* Recovery complete, but still wedged means reset failure. */
959 if (recovery_complete)
969 * Compare seqno against outstanding lazy request. Emit a request if they are
973 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
977 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
980 if (seqno == ring->outstanding_lazy_request)
981 ret = i915_add_request(ring, NULL, NULL);
987 * __wait_seqno - wait until execution of seqno has finished
988 * @ring: the ring expected to report seqno
990 * @interruptible: do an interruptible wait (normally yes)
991 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
993 * Returns 0 if the seqno was found within the alloted time. Else returns the
994 * errno with remaining time filled in timeout argument.
996 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
997 bool interruptible, struct timespec *timeout)
999 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1000 struct timespec before, now, wait_time={1,0};
1001 unsigned long timeout_jiffies;
1003 bool wait_forever = true;
1006 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1009 trace_i915_gem_request_wait_begin(ring, seqno);
1011 if (timeout != NULL) {
1012 wait_time = *timeout;
1013 wait_forever = false;
1016 timeout_jiffies = timespec_to_jiffies(&wait_time);
1018 if (WARN_ON(!ring->irq_get(ring)))
1021 /* Record current time in case interrupted by signal, or wedged * */
1022 getrawmonotonic(&before);
1025 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1026 atomic_read(&dev_priv->mm.wedged))
1029 end = wait_event_interruptible_timeout(ring->irq_queue,
1033 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1036 ret = i915_gem_check_wedge(dev_priv, interruptible);
1039 } while (end == 0 && wait_forever);
1041 getrawmonotonic(&now);
1043 ring->irq_put(ring);
1044 trace_i915_gem_request_wait_end(ring, seqno);
1048 struct timespec sleep_time = timespec_sub(now, before);
1049 *timeout = timespec_sub(*timeout, sleep_time);
1054 case -EAGAIN: /* Wedged */
1055 case -ERESTARTSYS: /* Signal */
1057 case 0: /* Timeout */
1059 set_normalized_timespec(timeout, 0, 0);
1061 default: /* Completed */
1062 WARN_ON(end < 0); /* We're not aware of other errors */
1068 * Waits for a sequence number to be signaled, and cleans up the
1069 * request and object lists appropriately for that event.
1072 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1074 struct drm_device *dev = ring->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 bool interruptible = dev_priv->mm.interruptible;
1079 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1082 ret = i915_gem_check_wedge(dev_priv, interruptible);
1086 ret = i915_gem_check_olr(ring, seqno);
1090 return __wait_seqno(ring, seqno, interruptible, NULL);
1094 * Ensures that all rendering to the object has completed and the object is
1095 * safe to unbind from the GTT or access from the CPU.
1097 static __must_check int
1098 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1101 struct intel_ring_buffer *ring = obj->ring;
1105 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109 ret = i915_wait_seqno(ring, seqno);
1113 i915_gem_retire_requests_ring(ring);
1115 /* Manually manage the write flush as we may have not yet
1116 * retired the buffer.
1118 if (obj->last_write_seqno &&
1119 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1120 obj->last_write_seqno = 0;
1121 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1127 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1128 * as the object state may change during this call.
1130 static __must_check int
1131 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1134 struct drm_device *dev = obj->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 struct intel_ring_buffer *ring = obj->ring;
1140 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1141 BUG_ON(!dev_priv->mm.interruptible);
1143 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147 ret = i915_gem_check_wedge(dev_priv, true);
1151 ret = i915_gem_check_olr(ring, seqno);
1155 mutex_unlock(&dev->struct_mutex);
1156 ret = __wait_seqno(ring, seqno, true, NULL);
1157 mutex_lock(&dev->struct_mutex);
1159 i915_gem_retire_requests_ring(ring);
1161 /* Manually manage the write flush as we may have not yet
1162 * retired the buffer.
1164 if (obj->last_write_seqno &&
1165 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1166 obj->last_write_seqno = 0;
1167 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file)
1181 struct drm_i915_gem_set_domain *args = data;
1182 struct drm_i915_gem_object *obj;
1183 uint32_t read_domains = args->read_domains;
1184 uint32_t write_domain = args->write_domain;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain & I915_GEM_GPU_DOMAINS)
1191 if (read_domains & I915_GEM_GPU_DOMAINS)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain != 0 && read_domains != write_domain)
1200 ret = i915_mutex_lock_interruptible(dev);
1204 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1205 if (&obj->base == NULL) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218 if (read_domains & I915_GEM_DOMAIN_GTT) {
1219 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 drm_gem_object_unreference(&obj->base);
1234 mutex_unlock(&dev->struct_mutex);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file)
1245 struct drm_i915_gem_sw_finish *args = data;
1246 struct drm_i915_gem_object *obj;
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj);
1263 drm_gem_object_unreference(&obj->base);
1265 mutex_unlock(&dev->struct_mutex);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file)
1280 struct drm_i915_gem_mmap *args = data;
1281 struct drm_gem_object *obj;
1284 obj = drm_gem_object_lookup(dev, file, args->handle);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj);
1296 addr = vm_mmap(obj->filp, 0, args->size,
1297 PROT_READ | PROT_WRITE, MAP_SHARED,
1299 drm_gem_object_unreference_unlocked(obj);
1300 if (IS_ERR((void *)addr))
1303 args->addr_ptr = (uint64_t) addr;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1326 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1327 struct drm_device *dev = obj->base.dev;
1328 drm_i915_private_t *dev_priv = dev->dev_private;
1329 pgoff_t page_offset;
1332 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1338 ret = i915_mutex_lock_interruptible(dev);
1342 trace_i915_gem_object_fault(obj, page_offset, true, write);
1344 /* Now bind it into the GTT if needed */
1345 ret = i915_gem_object_pin(obj, 0, true, false);
1349 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1353 ret = i915_gem_object_get_fence(obj);
1357 obj->fault_mappable = true;
1359 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1362 /* Finally, remap it using the new GTT offset */
1363 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1365 i915_gem_object_unpin(obj);
1367 mutex_unlock(&dev->struct_mutex);
1371 /* If this -EIO is due to a gpu hang, give the reset code a
1372 * chance to clean up the mess. Otherwise return the proper
1374 if (!atomic_read(&dev_priv->mm.wedged))
1375 return VM_FAULT_SIGBUS;
1377 /* Give the error handler a chance to run and move the
1378 * objects off the GPU active list. Next time we service the
1379 * fault, we should be able to transition the page into the
1380 * GTT without touching the GPU (and so avoid further
1381 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1382 * with coherency, just lost writes.
1390 * EBUSY is ok: this just means that another thread
1391 * already did the job.
1393 return VM_FAULT_NOPAGE;
1395 return VM_FAULT_OOM;
1397 return VM_FAULT_SIGBUS;
1399 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1400 return VM_FAULT_SIGBUS;
1405 * i915_gem_release_mmap - remove physical page mappings
1406 * @obj: obj in question
1408 * Preserve the reservation of the mmapping with the DRM core code, but
1409 * relinquish ownership of the pages back to the system.
1411 * It is vital that we remove the page mapping if we have mapped a tiled
1412 * object through the GTT and then lose the fence register due to
1413 * resource pressure. Similarly if the object has been moved out of the
1414 * aperture, than pages mapped into userspace must be revoked. Removing the
1415 * mapping will then trigger a page fault on the next user access, allowing
1416 * fixup by i915_gem_fault().
1419 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1421 if (!obj->fault_mappable)
1424 if (obj->base.dev->dev_mapping)
1425 unmap_mapping_range(obj->base.dev->dev_mapping,
1426 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1429 obj->fault_mappable = false;
1433 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1437 if (INTEL_INFO(dev)->gen >= 4 ||
1438 tiling_mode == I915_TILING_NONE)
1441 /* Previous chips need a power-of-two fence region when tiling */
1442 if (INTEL_INFO(dev)->gen == 3)
1443 gtt_size = 1024*1024;
1445 gtt_size = 512*1024;
1447 while (gtt_size < size)
1454 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1455 * @obj: object to check
1457 * Return the required GTT alignment for an object, taking into account
1458 * potential fence register mapping.
1461 i915_gem_get_gtt_alignment(struct drm_device *dev,
1466 * Minimum alignment is 4k (GTT page size), but might be greater
1467 * if a fence register is needed for the object.
1469 if (INTEL_INFO(dev)->gen >= 4 ||
1470 tiling_mode == I915_TILING_NONE)
1474 * Previous chips need to be aligned to the size of the smallest
1475 * fence register that can contain the object.
1477 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1484 * @size: size of the object
1485 * @tiling_mode: tiling mode of the object
1487 * Return the required GTT alignment for an object, only taking into account
1488 * unfenced tiled surface requirements.
1491 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1496 * Minimum alignment is 4k (GTT page size) for sane hw.
1498 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1499 tiling_mode == I915_TILING_NONE)
1502 /* Previous hardware however needs to be aligned to a power-of-two
1503 * tile height. The simplest method for determining this is to reuse
1504 * the power-of-tile object size.
1506 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1509 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1511 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1514 if (obj->base.map_list.map)
1517 ret = drm_gem_create_mmap_offset(&obj->base);
1521 /* Badly fragmented mmap space? The only way we can recover
1522 * space is by destroying unwanted objects. We can't randomly release
1523 * mmap_offsets as userspace expects them to be persistent for the
1524 * lifetime of the objects. The closest we can is to release the
1525 * offsets on purgeable objects by truncating it and marking it purged,
1526 * which prevents userspace from ever using that object again.
1528 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1529 ret = drm_gem_create_mmap_offset(&obj->base);
1533 i915_gem_shrink_all(dev_priv);
1534 return drm_gem_create_mmap_offset(&obj->base);
1537 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1539 if (!obj->base.map_list.map)
1542 drm_gem_free_mmap_offset(&obj->base);
1546 i915_gem_mmap_gtt(struct drm_file *file,
1547 struct drm_device *dev,
1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 struct drm_i915_gem_object *obj;
1555 ret = i915_mutex_lock_interruptible(dev);
1559 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1560 if (&obj->base == NULL) {
1565 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1570 if (obj->madv != I915_MADV_WILLNEED) {
1571 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1576 ret = i915_gem_object_create_mmap_offset(obj);
1580 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1583 drm_gem_object_unreference(&obj->base);
1585 mutex_unlock(&dev->struct_mutex);
1590 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1592 * @data: GTT mapping ioctl data
1593 * @file: GEM object info
1595 * Simply returns the fake offset to userspace so it can mmap it.
1596 * The mmap call will end up in drm_gem_mmap(), which will set things
1597 * up so we can get faults in the handler above.
1599 * The fault handler will take care of binding the object into the GTT
1600 * (since it may have been evicted to make room for something), allocating
1601 * a fence register, and mapping the appropriate aperture address into
1605 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1606 struct drm_file *file)
1608 struct drm_i915_gem_mmap_gtt *args = data;
1610 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1613 /* Immediately discard the backing storage */
1615 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1617 struct inode *inode;
1619 i915_gem_object_free_mmap_offset(obj);
1621 if (obj->base.filp == NULL)
1624 /* Our goal here is to return as much of the memory as
1625 * is possible back to the system as we are called from OOM.
1626 * To do this we must instruct the shmfs to drop all of its
1627 * backing pages, *now*.
1629 inode = obj->base.filp->f_path.dentry->d_inode;
1630 shmem_truncate_range(inode, 0, (loff_t)-1);
1632 obj->madv = __I915_MADV_PURGED;
1636 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1638 return obj->madv == I915_MADV_DONTNEED;
1642 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1644 int page_count = obj->base.size / PAGE_SIZE;
1645 struct scatterlist *sg;
1648 BUG_ON(obj->madv == __I915_MADV_PURGED);
1650 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1652 /* In the event of a disaster, abandon all caches and
1653 * hope for the best.
1655 WARN_ON(ret != -EIO);
1656 i915_gem_clflush_object(obj);
1657 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1660 if (i915_gem_object_needs_bit17_swizzle(obj))
1661 i915_gem_object_save_bit_17_swizzle(obj);
1663 if (obj->madv == I915_MADV_DONTNEED)
1666 for_each_sg(obj->pages->sgl, sg, page_count, i) {
1667 struct page *page = sg_page(sg);
1670 set_page_dirty(page);
1672 if (obj->madv == I915_MADV_WILLNEED)
1673 mark_page_accessed(page);
1675 page_cache_release(page);
1679 sg_free_table(obj->pages);
1684 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1686 const struct drm_i915_gem_object_ops *ops = obj->ops;
1688 if (obj->pages == NULL)
1691 BUG_ON(obj->gtt_space);
1693 if (obj->pages_pin_count)
1696 ops->put_pages(obj);
1699 list_del(&obj->gtt_list);
1700 if (i915_gem_object_is_purgeable(obj))
1701 i915_gem_object_truncate(obj);
1707 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1709 struct drm_i915_gem_object *obj, *next;
1712 list_for_each_entry_safe(obj, next,
1713 &dev_priv->mm.unbound_list,
1715 if (i915_gem_object_is_purgeable(obj) &&
1716 i915_gem_object_put_pages(obj) == 0) {
1717 count += obj->base.size >> PAGE_SHIFT;
1718 if (count >= target)
1723 list_for_each_entry_safe(obj, next,
1724 &dev_priv->mm.inactive_list,
1726 if (i915_gem_object_is_purgeable(obj) &&
1727 i915_gem_object_unbind(obj) == 0 &&
1728 i915_gem_object_put_pages(obj) == 0) {
1729 count += obj->base.size >> PAGE_SHIFT;
1730 if (count >= target)
1739 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1741 struct drm_i915_gem_object *obj, *next;
1743 i915_gem_evict_everything(dev_priv->dev);
1745 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1746 i915_gem_object_put_pages(obj);
1750 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1752 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1754 struct address_space *mapping;
1755 struct sg_table *st;
1756 struct scatterlist *sg;
1760 /* Assert that the object is not currently in any GPU domain. As it
1761 * wasn't in the GTT, there shouldn't be any way it could have been in
1764 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1765 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1767 st = kmalloc(sizeof(*st), GFP_KERNEL);
1771 page_count = obj->base.size / PAGE_SIZE;
1772 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1778 /* Get the list of pages out of our struct file. They'll be pinned
1779 * at this point until we release them.
1781 * Fail silently without starting the shrinker
1783 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1784 gfp = mapping_gfp_mask(mapping);
1785 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1786 gfp &= ~(__GFP_IO | __GFP_WAIT);
1787 for_each_sg(st->sgl, sg, page_count, i) {
1788 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1790 i915_gem_purge(dev_priv, page_count);
1791 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1794 /* We've tried hard to allocate the memory by reaping
1795 * our own buffer, now let the real VM do its job and
1796 * go down in flames if truly OOM.
1798 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1799 gfp |= __GFP_IO | __GFP_WAIT;
1801 i915_gem_shrink_all(dev_priv);
1802 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1806 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1807 gfp &= ~(__GFP_IO | __GFP_WAIT);
1810 sg_set_page(sg, page, PAGE_SIZE, 0);
1815 if (i915_gem_object_needs_bit17_swizzle(obj))
1816 i915_gem_object_do_bit_17_swizzle(obj);
1821 for_each_sg(st->sgl, sg, i, page_count)
1822 page_cache_release(sg_page(sg));
1825 return PTR_ERR(page);
1828 /* Ensure that the associated pages are gathered from the backing storage
1829 * and pinned into our object. i915_gem_object_get_pages() may be called
1830 * multiple times before they are released by a single call to
1831 * i915_gem_object_put_pages() - once the pages are no longer referenced
1832 * either as a result of memory pressure (reaping pages under the shrinker)
1833 * or as the object is itself released.
1836 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1838 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1839 const struct drm_i915_gem_object_ops *ops = obj->ops;
1845 BUG_ON(obj->pages_pin_count);
1847 ret = ops->get_pages(obj);
1851 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1856 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1857 struct intel_ring_buffer *ring)
1859 struct drm_device *dev = obj->base.dev;
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861 u32 seqno = intel_ring_get_seqno(ring);
1863 BUG_ON(ring == NULL);
1866 /* Add a reference if we're newly entering the active list. */
1868 drm_gem_object_reference(&obj->base);
1872 /* Move from whatever list we were on to the tail of execution. */
1873 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1874 list_move_tail(&obj->ring_list, &ring->active_list);
1876 obj->last_read_seqno = seqno;
1878 if (obj->fenced_gpu_access) {
1879 obj->last_fenced_seqno = seqno;
1881 /* Bump MRU to take account of the delayed flush */
1882 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1883 struct drm_i915_fence_reg *reg;
1885 reg = &dev_priv->fence_regs[obj->fence_reg];
1886 list_move_tail(®->lru_list,
1887 &dev_priv->mm.fence_list);
1893 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1895 struct drm_device *dev = obj->base.dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1898 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1899 BUG_ON(!obj->active);
1901 if (obj->pin_count) /* are we a framebuffer? */
1902 intel_mark_fb_idle(obj);
1904 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1906 list_del_init(&obj->ring_list);
1909 obj->last_read_seqno = 0;
1910 obj->last_write_seqno = 0;
1911 obj->base.write_domain = 0;
1913 obj->last_fenced_seqno = 0;
1914 obj->fenced_gpu_access = false;
1917 drm_gem_object_unreference(&obj->base);
1919 WARN_ON(i915_verify_lists(dev));
1923 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_ring_buffer *ring;
1929 /* The hardware uses various monotonic 32-bit counters, if we
1930 * detect that they will wraparound we need to idle the GPU
1931 * and reset those counters.
1934 for_each_ring(ring, dev_priv, i) {
1935 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1936 ret |= ring->sync_seqno[j] != 0;
1941 ret = i915_gpu_idle(dev);
1945 i915_gem_retire_requests(dev);
1946 for_each_ring(ring, dev_priv, i) {
1947 ret = intel_ring_handle_seqno_wrap(ring);
1951 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1952 ring->sync_seqno[j] = 0;
1959 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1963 /* reserve 0 for non-seqno */
1964 if (dev_priv->next_seqno == 0) {
1965 int ret = i915_gem_handle_seqno_wrap(dev);
1969 dev_priv->next_seqno = 1;
1972 *seqno = dev_priv->next_seqno++;
1977 i915_add_request(struct intel_ring_buffer *ring,
1978 struct drm_file *file,
1981 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1982 struct drm_i915_gem_request *request;
1983 u32 request_ring_position;
1988 * Emit any outstanding flushes - execbuf can fail to emit the flush
1989 * after having emitted the batchbuffer command. Hence we need to fix
1990 * things up similar to emitting the lazy request. The difference here
1991 * is that the flush _must_ happen before the next request, no matter
1994 ret = intel_ring_flush_all_caches(ring);
1998 request = kmalloc(sizeof(*request), GFP_KERNEL);
1999 if (request == NULL)
2003 /* Record the position of the start of the request so that
2004 * should we detect the updated seqno part-way through the
2005 * GPU processing the request, we never over-estimate the
2006 * position of the head.
2008 request_ring_position = intel_ring_get_tail(ring);
2010 ret = ring->add_request(ring);
2016 request->seqno = intel_ring_get_seqno(ring);
2017 request->ring = ring;
2018 request->tail = request_ring_position;
2019 request->emitted_jiffies = jiffies;
2020 was_empty = list_empty(&ring->request_list);
2021 list_add_tail(&request->list, &ring->request_list);
2022 request->file_priv = NULL;
2025 struct drm_i915_file_private *file_priv = file->driver_priv;
2027 spin_lock(&file_priv->mm.lock);
2028 request->file_priv = file_priv;
2029 list_add_tail(&request->client_list,
2030 &file_priv->mm.request_list);
2031 spin_unlock(&file_priv->mm.lock);
2034 trace_i915_gem_request_add(ring, request->seqno);
2035 ring->outstanding_lazy_request = 0;
2037 if (!dev_priv->mm.suspended) {
2038 if (i915_enable_hangcheck) {
2039 mod_timer(&dev_priv->hangcheck_timer,
2040 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2043 queue_delayed_work(dev_priv->wq,
2044 &dev_priv->mm.retire_work,
2045 round_jiffies_up_relative(HZ));
2046 intel_mark_busy(dev_priv->dev);
2051 *out_seqno = request->seqno;
2056 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2058 struct drm_i915_file_private *file_priv = request->file_priv;
2063 spin_lock(&file_priv->mm.lock);
2064 if (request->file_priv) {
2065 list_del(&request->client_list);
2066 request->file_priv = NULL;
2068 spin_unlock(&file_priv->mm.lock);
2071 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2072 struct intel_ring_buffer *ring)
2074 while (!list_empty(&ring->request_list)) {
2075 struct drm_i915_gem_request *request;
2077 request = list_first_entry(&ring->request_list,
2078 struct drm_i915_gem_request,
2081 list_del(&request->list);
2082 i915_gem_request_remove_from_client(request);
2086 while (!list_empty(&ring->active_list)) {
2087 struct drm_i915_gem_object *obj;
2089 obj = list_first_entry(&ring->active_list,
2090 struct drm_i915_gem_object,
2093 i915_gem_object_move_to_inactive(obj);
2097 static void i915_gem_reset_fences(struct drm_device *dev)
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2102 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2103 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2105 i915_gem_write_fence(dev, i, NULL);
2108 i915_gem_object_fence_lost(reg->obj);
2112 INIT_LIST_HEAD(®->lru_list);
2115 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2118 void i915_gem_reset(struct drm_device *dev)
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 struct drm_i915_gem_object *obj;
2122 struct intel_ring_buffer *ring;
2125 for_each_ring(ring, dev_priv, i)
2126 i915_gem_reset_ring_lists(dev_priv, ring);
2128 /* Move everything out of the GPU domains to ensure we do any
2129 * necessary invalidation upon reuse.
2131 list_for_each_entry(obj,
2132 &dev_priv->mm.inactive_list,
2135 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2138 /* The fence registers are invalidated so clear them out */
2139 i915_gem_reset_fences(dev);
2143 * This function clears the request list as sequence numbers are passed.
2146 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2150 if (list_empty(&ring->request_list))
2153 WARN_ON(i915_verify_lists(ring->dev));
2155 seqno = ring->get_seqno(ring, true);
2157 while (!list_empty(&ring->request_list)) {
2158 struct drm_i915_gem_request *request;
2160 request = list_first_entry(&ring->request_list,
2161 struct drm_i915_gem_request,
2164 if (!i915_seqno_passed(seqno, request->seqno))
2167 trace_i915_gem_request_retire(ring, request->seqno);
2168 /* We know the GPU must have read the request to have
2169 * sent us the seqno + interrupt, so use the position
2170 * of tail of the request to update the last known position
2173 ring->last_retired_head = request->tail;
2175 list_del(&request->list);
2176 i915_gem_request_remove_from_client(request);
2180 /* Move any buffers on the active list that are no longer referenced
2181 * by the ringbuffer to the flushing/inactive lists as appropriate.
2183 while (!list_empty(&ring->active_list)) {
2184 struct drm_i915_gem_object *obj;
2186 obj = list_first_entry(&ring->active_list,
2187 struct drm_i915_gem_object,
2190 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2193 i915_gem_object_move_to_inactive(obj);
2196 if (unlikely(ring->trace_irq_seqno &&
2197 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2198 ring->irq_put(ring);
2199 ring->trace_irq_seqno = 0;
2202 WARN_ON(i915_verify_lists(ring->dev));
2206 i915_gem_retire_requests(struct drm_device *dev)
2208 drm_i915_private_t *dev_priv = dev->dev_private;
2209 struct intel_ring_buffer *ring;
2212 for_each_ring(ring, dev_priv, i)
2213 i915_gem_retire_requests_ring(ring);
2217 i915_gem_retire_work_handler(struct work_struct *work)
2219 drm_i915_private_t *dev_priv;
2220 struct drm_device *dev;
2221 struct intel_ring_buffer *ring;
2225 dev_priv = container_of(work, drm_i915_private_t,
2226 mm.retire_work.work);
2227 dev = dev_priv->dev;
2229 /* Come back later if the device is busy... */
2230 if (!mutex_trylock(&dev->struct_mutex)) {
2231 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2232 round_jiffies_up_relative(HZ));
2236 i915_gem_retire_requests(dev);
2238 /* Send a periodic flush down the ring so we don't hold onto GEM
2239 * objects indefinitely.
2242 for_each_ring(ring, dev_priv, i) {
2243 if (ring->gpu_caches_dirty)
2244 i915_add_request(ring, NULL, NULL);
2246 idle &= list_empty(&ring->request_list);
2249 if (!dev_priv->mm.suspended && !idle)
2250 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2251 round_jiffies_up_relative(HZ));
2253 intel_mark_idle(dev);
2255 mutex_unlock(&dev->struct_mutex);
2259 * Ensures that an object will eventually get non-busy by flushing any required
2260 * write domains, emitting any outstanding lazy request and retiring and
2261 * completed requests.
2264 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2269 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2273 i915_gem_retire_requests_ring(obj->ring);
2280 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2281 * @DRM_IOCTL_ARGS: standard ioctl arguments
2283 * Returns 0 if successful, else an error is returned with the remaining time in
2284 * the timeout parameter.
2285 * -ETIME: object is still busy after timeout
2286 * -ERESTARTSYS: signal interrupted the wait
2287 * -ENONENT: object doesn't exist
2288 * Also possible, but rare:
2289 * -EAGAIN: GPU wedged
2291 * -ENODEV: Internal IRQ fail
2292 * -E?: The add request failed
2294 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2295 * non-zero timeout parameter the wait ioctl will wait for the given number of
2296 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2297 * without holding struct_mutex the object may become re-busied before this
2298 * function completes. A similar but shorter * race condition exists in the busy
2302 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2304 struct drm_i915_gem_wait *args = data;
2305 struct drm_i915_gem_object *obj;
2306 struct intel_ring_buffer *ring = NULL;
2307 struct timespec timeout_stack, *timeout = NULL;
2311 if (args->timeout_ns >= 0) {
2312 timeout_stack = ns_to_timespec(args->timeout_ns);
2313 timeout = &timeout_stack;
2316 ret = i915_mutex_lock_interruptible(dev);
2320 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2321 if (&obj->base == NULL) {
2322 mutex_unlock(&dev->struct_mutex);
2326 /* Need to make sure the object gets inactive eventually. */
2327 ret = i915_gem_object_flush_active(obj);
2332 seqno = obj->last_read_seqno;
2339 /* Do this after OLR check to make sure we make forward progress polling
2340 * on this IOCTL with a 0 timeout (like busy ioctl)
2342 if (!args->timeout_ns) {
2347 drm_gem_object_unreference(&obj->base);
2348 mutex_unlock(&dev->struct_mutex);
2350 ret = __wait_seqno(ring, seqno, true, timeout);
2352 WARN_ON(!timespec_valid(timeout));
2353 args->timeout_ns = timespec_to_ns(timeout);
2358 drm_gem_object_unreference(&obj->base);
2359 mutex_unlock(&dev->struct_mutex);
2364 * i915_gem_object_sync - sync an object to a ring.
2366 * @obj: object which may be in use on another ring.
2367 * @to: ring we wish to use the object on. May be NULL.
2369 * This code is meant to abstract object synchronization with the GPU.
2370 * Calling with NULL implies synchronizing the object with the CPU
2371 * rather than a particular GPU ring.
2373 * Returns 0 if successful, else propagates up the lower layer error.
2376 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2377 struct intel_ring_buffer *to)
2379 struct intel_ring_buffer *from = obj->ring;
2383 if (from == NULL || to == from)
2386 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2387 return i915_gem_object_wait_rendering(obj, false);
2389 idx = intel_ring_sync_index(from, to);
2391 seqno = obj->last_read_seqno;
2392 if (seqno <= from->sync_seqno[idx])
2395 ret = i915_gem_check_olr(obj->ring, seqno);
2399 ret = to->sync_to(to, from, seqno);
2401 /* We use last_read_seqno because sync_to()
2402 * might have just caused seqno wrap under
2405 from->sync_seqno[idx] = obj->last_read_seqno;
2410 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2412 u32 old_write_domain, old_read_domains;
2414 /* Act a barrier for all accesses through the GTT */
2417 /* Force a pagefault for domain tracking on next user access */
2418 i915_gem_release_mmap(obj);
2420 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2423 old_read_domains = obj->base.read_domains;
2424 old_write_domain = obj->base.write_domain;
2426 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2427 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2429 trace_i915_gem_object_change_domain(obj,
2435 * Unbinds an object from the GTT aperture.
2438 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2440 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2443 if (obj->gtt_space == NULL)
2449 BUG_ON(obj->pages == NULL);
2451 ret = i915_gem_object_finish_gpu(obj);
2454 /* Continue on if we fail due to EIO, the GPU is hung so we
2455 * should be safe and we need to cleanup or else we might
2456 * cause memory corruption through use-after-free.
2459 i915_gem_object_finish_gtt(obj);
2461 /* release the fence reg _after_ flushing */
2462 ret = i915_gem_object_put_fence(obj);
2466 trace_i915_gem_object_unbind(obj);
2468 if (obj->has_global_gtt_mapping)
2469 i915_gem_gtt_unbind_object(obj);
2470 if (obj->has_aliasing_ppgtt_mapping) {
2471 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2472 obj->has_aliasing_ppgtt_mapping = 0;
2474 i915_gem_gtt_finish_object(obj);
2476 list_del(&obj->mm_list);
2477 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2478 /* Avoid an unnecessary call to unbind on rebind. */
2479 obj->map_and_fenceable = true;
2481 drm_mm_put_block(obj->gtt_space);
2482 obj->gtt_space = NULL;
2483 obj->gtt_offset = 0;
2488 int i915_gpu_idle(struct drm_device *dev)
2490 drm_i915_private_t *dev_priv = dev->dev_private;
2491 struct intel_ring_buffer *ring;
2494 /* Flush everything onto the inactive list. */
2495 for_each_ring(ring, dev_priv, i) {
2496 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2500 ret = intel_ring_idle(ring);
2508 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2509 struct drm_i915_gem_object *obj)
2511 drm_i915_private_t *dev_priv = dev->dev_private;
2515 u32 size = obj->gtt_space->size;
2517 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2519 val |= obj->gtt_offset & 0xfffff000;
2520 val |= (uint64_t)((obj->stride / 128) - 1) <<
2521 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2523 if (obj->tiling_mode == I915_TILING_Y)
2524 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2525 val |= I965_FENCE_REG_VALID;
2529 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2530 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2533 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2534 struct drm_i915_gem_object *obj)
2536 drm_i915_private_t *dev_priv = dev->dev_private;
2540 u32 size = obj->gtt_space->size;
2542 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2544 val |= obj->gtt_offset & 0xfffff000;
2545 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2546 if (obj->tiling_mode == I915_TILING_Y)
2547 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2548 val |= I965_FENCE_REG_VALID;
2552 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2553 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2556 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2557 struct drm_i915_gem_object *obj)
2559 drm_i915_private_t *dev_priv = dev->dev_private;
2563 u32 size = obj->gtt_space->size;
2567 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2568 (size & -size) != size ||
2569 (obj->gtt_offset & (size - 1)),
2570 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2571 obj->gtt_offset, obj->map_and_fenceable, size);
2573 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2578 /* Note: pitch better be a power of two tile widths */
2579 pitch_val = obj->stride / tile_width;
2580 pitch_val = ffs(pitch_val) - 1;
2582 val = obj->gtt_offset;
2583 if (obj->tiling_mode == I915_TILING_Y)
2584 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2585 val |= I915_FENCE_SIZE_BITS(size);
2586 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2587 val |= I830_FENCE_REG_VALID;
2592 reg = FENCE_REG_830_0 + reg * 4;
2594 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2596 I915_WRITE(reg, val);
2600 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2601 struct drm_i915_gem_object *obj)
2603 drm_i915_private_t *dev_priv = dev->dev_private;
2607 u32 size = obj->gtt_space->size;
2610 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2611 (size & -size) != size ||
2612 (obj->gtt_offset & (size - 1)),
2613 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2614 obj->gtt_offset, size);
2616 pitch_val = obj->stride / 128;
2617 pitch_val = ffs(pitch_val) - 1;
2619 val = obj->gtt_offset;
2620 if (obj->tiling_mode == I915_TILING_Y)
2621 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2622 val |= I830_FENCE_SIZE_BITS(size);
2623 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2624 val |= I830_FENCE_REG_VALID;
2628 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2629 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2632 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2633 struct drm_i915_gem_object *obj)
2635 switch (INTEL_INFO(dev)->gen) {
2637 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2639 case 4: i965_write_fence_reg(dev, reg, obj); break;
2640 case 3: i915_write_fence_reg(dev, reg, obj); break;
2641 case 2: i830_write_fence_reg(dev, reg, obj); break;
2646 static inline int fence_number(struct drm_i915_private *dev_priv,
2647 struct drm_i915_fence_reg *fence)
2649 return fence - dev_priv->fence_regs;
2652 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2653 struct drm_i915_fence_reg *fence,
2656 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2657 int reg = fence_number(dev_priv, fence);
2659 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2662 obj->fence_reg = reg;
2664 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2666 obj->fence_reg = I915_FENCE_REG_NONE;
2668 list_del_init(&fence->lru_list);
2673 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2675 if (obj->last_fenced_seqno) {
2676 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2680 obj->last_fenced_seqno = 0;
2683 /* Ensure that all CPU reads are completed before installing a fence
2684 * and all writes before removing the fence.
2686 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2689 obj->fenced_gpu_access = false;
2694 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2696 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2699 ret = i915_gem_object_flush_fence(obj);
2703 if (obj->fence_reg == I915_FENCE_REG_NONE)
2706 i915_gem_object_update_fence(obj,
2707 &dev_priv->fence_regs[obj->fence_reg],
2709 i915_gem_object_fence_lost(obj);
2714 static struct drm_i915_fence_reg *
2715 i915_find_fence_reg(struct drm_device *dev)
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 struct drm_i915_fence_reg *reg, *avail;
2721 /* First try to find a free reg */
2723 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2724 reg = &dev_priv->fence_regs[i];
2728 if (!reg->pin_count)
2735 /* None available, try to steal one or wait for a user to finish */
2736 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2747 * i915_gem_object_get_fence - set up fencing for an object
2748 * @obj: object to map through a fence reg
2750 * When mapping objects through the GTT, userspace wants to be able to write
2751 * to them without having to worry about swizzling if the object is tiled.
2752 * This function walks the fence regs looking for a free one for @obj,
2753 * stealing one if it can't find any.
2755 * It then sets up the reg based on the object's properties: address, pitch
2756 * and tiling format.
2758 * For an untiled surface, this removes any existing fence.
2761 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2763 struct drm_device *dev = obj->base.dev;
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 bool enable = obj->tiling_mode != I915_TILING_NONE;
2766 struct drm_i915_fence_reg *reg;
2769 /* Have we updated the tiling parameters upon the object and so
2770 * will need to serialise the write to the associated fence register?
2772 if (obj->fence_dirty) {
2773 ret = i915_gem_object_flush_fence(obj);
2778 /* Just update our place in the LRU if our fence is getting reused. */
2779 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2780 reg = &dev_priv->fence_regs[obj->fence_reg];
2781 if (!obj->fence_dirty) {
2782 list_move_tail(®->lru_list,
2783 &dev_priv->mm.fence_list);
2786 } else if (enable) {
2787 reg = i915_find_fence_reg(dev);
2792 struct drm_i915_gem_object *old = reg->obj;
2794 ret = i915_gem_object_flush_fence(old);
2798 i915_gem_object_fence_lost(old);
2803 i915_gem_object_update_fence(obj, reg, enable);
2804 obj->fence_dirty = false;
2809 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2810 struct drm_mm_node *gtt_space,
2811 unsigned long cache_level)
2813 struct drm_mm_node *other;
2815 /* On non-LLC machines we have to be careful when putting differing
2816 * types of snoopable memory together to avoid the prefetcher
2817 * crossing memory domains and dying.
2822 if (gtt_space == NULL)
2825 if (list_empty(>t_space->node_list))
2828 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2829 if (other->allocated && !other->hole_follows && other->color != cache_level)
2832 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2833 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2839 static void i915_gem_verify_gtt(struct drm_device *dev)
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 struct drm_i915_gem_object *obj;
2846 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2847 if (obj->gtt_space == NULL) {
2848 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2853 if (obj->cache_level != obj->gtt_space->color) {
2854 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2855 obj->gtt_space->start,
2856 obj->gtt_space->start + obj->gtt_space->size,
2858 obj->gtt_space->color);
2863 if (!i915_gem_valid_gtt_space(dev,
2865 obj->cache_level)) {
2866 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2867 obj->gtt_space->start,
2868 obj->gtt_space->start + obj->gtt_space->size,
2880 * Finds free space in the GTT aperture and binds the object there.
2883 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2885 bool map_and_fenceable,
2888 struct drm_device *dev = obj->base.dev;
2889 drm_i915_private_t *dev_priv = dev->dev_private;
2890 struct drm_mm_node *free_space;
2891 u32 size, fence_size, fence_alignment, unfenced_alignment;
2892 bool mappable, fenceable;
2895 if (obj->madv != I915_MADV_WILLNEED) {
2896 DRM_ERROR("Attempting to bind a purgeable object\n");
2900 fence_size = i915_gem_get_gtt_size(dev,
2903 fence_alignment = i915_gem_get_gtt_alignment(dev,
2906 unfenced_alignment =
2907 i915_gem_get_unfenced_gtt_alignment(dev,
2912 alignment = map_and_fenceable ? fence_alignment :
2914 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2915 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2919 size = map_and_fenceable ? fence_size : obj->base.size;
2921 /* If the object is bigger than the entire aperture, reject it early
2922 * before evicting everything in a vain attempt to find space.
2924 if (obj->base.size >
2925 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2926 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2930 ret = i915_gem_object_get_pages(obj);
2934 i915_gem_object_pin_pages(obj);
2937 if (map_and_fenceable)
2938 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2939 size, alignment, obj->cache_level,
2940 0, dev_priv->mm.gtt_mappable_end,
2943 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2944 size, alignment, obj->cache_level,
2947 if (free_space != NULL) {
2948 if (map_and_fenceable)
2950 drm_mm_get_block_range_generic(free_space,
2951 size, alignment, obj->cache_level,
2952 0, dev_priv->mm.gtt_mappable_end,
2956 drm_mm_get_block_generic(free_space,
2957 size, alignment, obj->cache_level,
2960 if (free_space == NULL) {
2961 ret = i915_gem_evict_something(dev, size, alignment,
2966 i915_gem_object_unpin_pages(obj);
2972 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2974 obj->cache_level))) {
2975 i915_gem_object_unpin_pages(obj);
2976 drm_mm_put_block(free_space);
2980 ret = i915_gem_gtt_prepare_object(obj);
2982 i915_gem_object_unpin_pages(obj);
2983 drm_mm_put_block(free_space);
2987 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2988 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2990 obj->gtt_space = free_space;
2991 obj->gtt_offset = free_space->start;
2994 free_space->size == fence_size &&
2995 (free_space->start & (fence_alignment - 1)) == 0;
2998 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3000 obj->map_and_fenceable = mappable && fenceable;
3002 i915_gem_object_unpin_pages(obj);
3003 trace_i915_gem_object_bind(obj, map_and_fenceable);
3004 i915_gem_verify_gtt(dev);
3009 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3011 /* If we don't have a page list set up, then we're not pinned
3012 * to GPU, and we can ignore the cache flush because it'll happen
3013 * again at bind time.
3015 if (obj->pages == NULL)
3018 /* If the GPU is snooping the contents of the CPU cache,
3019 * we do not need to manually clear the CPU cache lines. However,
3020 * the caches are only snooped when the render cache is
3021 * flushed/invalidated. As we always have to emit invalidations
3022 * and flushes when moving into and out of the RENDER domain, correct
3023 * snooping behaviour occurs naturally as the result of our domain
3026 if (obj->cache_level != I915_CACHE_NONE)
3029 trace_i915_gem_object_clflush(obj);
3031 drm_clflush_sg(obj->pages);
3034 /** Flushes the GTT write domain for the object if it's dirty. */
3036 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3038 uint32_t old_write_domain;
3040 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3043 /* No actual flushing is required for the GTT write domain. Writes
3044 * to it immediately go to main memory as far as we know, so there's
3045 * no chipset flush. It also doesn't land in render cache.
3047 * However, we do have to enforce the order so that all writes through
3048 * the GTT land before any writes to the device, such as updates to
3053 old_write_domain = obj->base.write_domain;
3054 obj->base.write_domain = 0;
3056 trace_i915_gem_object_change_domain(obj,
3057 obj->base.read_domains,
3061 /** Flushes the CPU write domain for the object if it's dirty. */
3063 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3065 uint32_t old_write_domain;
3067 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3070 i915_gem_clflush_object(obj);
3071 i915_gem_chipset_flush(obj->base.dev);
3072 old_write_domain = obj->base.write_domain;
3073 obj->base.write_domain = 0;
3075 trace_i915_gem_object_change_domain(obj,
3076 obj->base.read_domains,
3081 * Moves a single object to the GTT read, and possibly write domain.
3083 * This function returns when the move is complete, including waiting on
3087 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3089 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3090 uint32_t old_write_domain, old_read_domains;
3093 /* Not valid to be called on unbound objects. */
3094 if (obj->gtt_space == NULL)
3097 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3100 ret = i915_gem_object_wait_rendering(obj, !write);
3104 i915_gem_object_flush_cpu_write_domain(obj);
3106 old_write_domain = obj->base.write_domain;
3107 old_read_domains = obj->base.read_domains;
3109 /* It should now be out of any other write domains, and we can update
3110 * the domain values for our changes.
3112 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3113 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3115 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3116 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3120 trace_i915_gem_object_change_domain(obj,
3124 /* And bump the LRU for this access */
3125 if (i915_gem_object_is_inactive(obj))
3126 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3131 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3132 enum i915_cache_level cache_level)
3134 struct drm_device *dev = obj->base.dev;
3135 drm_i915_private_t *dev_priv = dev->dev_private;
3138 if (obj->cache_level == cache_level)
3141 if (obj->pin_count) {
3142 DRM_DEBUG("can not change the cache level of pinned objects\n");
3146 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3147 ret = i915_gem_object_unbind(obj);
3152 if (obj->gtt_space) {
3153 ret = i915_gem_object_finish_gpu(obj);
3157 i915_gem_object_finish_gtt(obj);
3159 /* Before SandyBridge, you could not use tiling or fence
3160 * registers with snooped memory, so relinquish any fences
3161 * currently pointing to our region in the aperture.
3163 if (INTEL_INFO(dev)->gen < 6) {
3164 ret = i915_gem_object_put_fence(obj);
3169 if (obj->has_global_gtt_mapping)
3170 i915_gem_gtt_bind_object(obj, cache_level);
3171 if (obj->has_aliasing_ppgtt_mapping)
3172 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3175 obj->gtt_space->color = cache_level;
3178 if (cache_level == I915_CACHE_NONE) {
3179 u32 old_read_domains, old_write_domain;
3181 /* If we're coming from LLC cached, then we haven't
3182 * actually been tracking whether the data is in the
3183 * CPU cache or not, since we only allow one bit set
3184 * in obj->write_domain and have been skipping the clflushes.
3185 * Just set it to the CPU cache for now.
3187 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3188 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3190 old_read_domains = obj->base.read_domains;
3191 old_write_domain = obj->base.write_domain;
3193 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3194 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3196 trace_i915_gem_object_change_domain(obj,
3201 obj->cache_level = cache_level;
3202 i915_gem_verify_gtt(dev);
3206 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3207 struct drm_file *file)
3209 struct drm_i915_gem_caching *args = data;
3210 struct drm_i915_gem_object *obj;
3213 ret = i915_mutex_lock_interruptible(dev);
3217 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3218 if (&obj->base == NULL) {
3223 args->caching = obj->cache_level != I915_CACHE_NONE;
3225 drm_gem_object_unreference(&obj->base);
3227 mutex_unlock(&dev->struct_mutex);
3231 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3232 struct drm_file *file)
3234 struct drm_i915_gem_caching *args = data;
3235 struct drm_i915_gem_object *obj;
3236 enum i915_cache_level level;
3239 switch (args->caching) {
3240 case I915_CACHING_NONE:
3241 level = I915_CACHE_NONE;
3243 case I915_CACHING_CACHED:
3244 level = I915_CACHE_LLC;
3250 ret = i915_mutex_lock_interruptible(dev);
3254 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3255 if (&obj->base == NULL) {
3260 ret = i915_gem_object_set_cache_level(obj, level);
3262 drm_gem_object_unreference(&obj->base);
3264 mutex_unlock(&dev->struct_mutex);
3269 * Prepare buffer for display plane (scanout, cursors, etc).
3270 * Can be called from an uninterruptible phase (modesetting) and allows
3271 * any flushes to be pipelined (for pageflips).
3274 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3276 struct intel_ring_buffer *pipelined)
3278 u32 old_read_domains, old_write_domain;
3281 if (pipelined != obj->ring) {
3282 ret = i915_gem_object_sync(obj, pipelined);
3287 /* The display engine is not coherent with the LLC cache on gen6. As
3288 * a result, we make sure that the pinning that is about to occur is
3289 * done with uncached PTEs. This is lowest common denominator for all
3292 * However for gen6+, we could do better by using the GFDT bit instead
3293 * of uncaching, which would allow us to flush all the LLC-cached data
3294 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3296 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3300 /* As the user may map the buffer once pinned in the display plane
3301 * (e.g. libkms for the bootup splash), we have to ensure that we
3302 * always use map_and_fenceable for all scanout buffers.
3304 ret = i915_gem_object_pin(obj, alignment, true, false);
3308 i915_gem_object_flush_cpu_write_domain(obj);
3310 old_write_domain = obj->base.write_domain;
3311 old_read_domains = obj->base.read_domains;
3313 /* It should now be out of any other write domains, and we can update
3314 * the domain values for our changes.
3316 obj->base.write_domain = 0;
3317 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3319 trace_i915_gem_object_change_domain(obj,
3327 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3331 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3334 ret = i915_gem_object_wait_rendering(obj, false);
3338 /* Ensure that we invalidate the GPU's caches and TLBs. */
3339 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3344 * Moves a single object to the CPU read, and possibly write domain.
3346 * This function returns when the move is complete, including waiting on
3350 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3352 uint32_t old_write_domain, old_read_domains;
3355 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3358 ret = i915_gem_object_wait_rendering(obj, !write);
3362 i915_gem_object_flush_gtt_write_domain(obj);
3364 old_write_domain = obj->base.write_domain;
3365 old_read_domains = obj->base.read_domains;
3367 /* Flush the CPU cache if it's still invalid. */
3368 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3369 i915_gem_clflush_object(obj);
3371 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3374 /* It should now be out of any other write domains, and we can update
3375 * the domain values for our changes.
3377 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3379 /* If we're writing through the CPU, then the GPU read domains will
3380 * need to be invalidated at next use.
3383 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3384 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3387 trace_i915_gem_object_change_domain(obj,
3394 /* Throttle our rendering by waiting until the ring has completed our requests
3395 * emitted over 20 msec ago.
3397 * Note that if we were to use the current jiffies each time around the loop,
3398 * we wouldn't escape the function with any frames outstanding if the time to
3399 * render a frame was over 20ms.
3401 * This should get us reasonable parallelism between CPU and GPU but also
3402 * relatively low latency when blocking on a particular request to finish.
3405 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 struct drm_i915_file_private *file_priv = file->driver_priv;
3409 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3410 struct drm_i915_gem_request *request;
3411 struct intel_ring_buffer *ring = NULL;
3415 if (atomic_read(&dev_priv->mm.wedged))
3418 spin_lock(&file_priv->mm.lock);
3419 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3420 if (time_after_eq(request->emitted_jiffies, recent_enough))
3423 ring = request->ring;
3424 seqno = request->seqno;
3426 spin_unlock(&file_priv->mm.lock);
3431 ret = __wait_seqno(ring, seqno, true, NULL);
3433 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3439 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3441 bool map_and_fenceable,
3446 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3449 if (obj->gtt_space != NULL) {
3450 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3451 (map_and_fenceable && !obj->map_and_fenceable)) {
3452 WARN(obj->pin_count,
3453 "bo is already pinned with incorrect alignment:"
3454 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3455 " obj->map_and_fenceable=%d\n",
3456 obj->gtt_offset, alignment,
3458 obj->map_and_fenceable);
3459 ret = i915_gem_object_unbind(obj);
3465 if (obj->gtt_space == NULL) {
3466 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3468 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3474 if (!dev_priv->mm.aliasing_ppgtt)
3475 i915_gem_gtt_bind_object(obj, obj->cache_level);
3478 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3479 i915_gem_gtt_bind_object(obj, obj->cache_level);
3482 obj->pin_mappable |= map_and_fenceable;
3488 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3490 BUG_ON(obj->pin_count == 0);
3491 BUG_ON(obj->gtt_space == NULL);
3493 if (--obj->pin_count == 0)
3494 obj->pin_mappable = false;
3498 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3499 struct drm_file *file)
3501 struct drm_i915_gem_pin *args = data;
3502 struct drm_i915_gem_object *obj;
3505 ret = i915_mutex_lock_interruptible(dev);
3509 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3510 if (&obj->base == NULL) {
3515 if (obj->madv != I915_MADV_WILLNEED) {
3516 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3521 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3522 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3528 obj->user_pin_count++;
3529 obj->pin_filp = file;
3530 if (obj->user_pin_count == 1) {
3531 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3536 /* XXX - flush the CPU caches for pinned objects
3537 * as the X server doesn't manage domains yet
3539 i915_gem_object_flush_cpu_write_domain(obj);
3540 args->offset = obj->gtt_offset;
3542 drm_gem_object_unreference(&obj->base);
3544 mutex_unlock(&dev->struct_mutex);
3549 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3550 struct drm_file *file)
3552 struct drm_i915_gem_pin *args = data;
3553 struct drm_i915_gem_object *obj;
3556 ret = i915_mutex_lock_interruptible(dev);
3560 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3561 if (&obj->base == NULL) {
3566 if (obj->pin_filp != file) {
3567 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3572 obj->user_pin_count--;
3573 if (obj->user_pin_count == 0) {
3574 obj->pin_filp = NULL;
3575 i915_gem_object_unpin(obj);
3579 drm_gem_object_unreference(&obj->base);
3581 mutex_unlock(&dev->struct_mutex);
3586 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3587 struct drm_file *file)
3589 struct drm_i915_gem_busy *args = data;
3590 struct drm_i915_gem_object *obj;
3593 ret = i915_mutex_lock_interruptible(dev);
3597 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3598 if (&obj->base == NULL) {
3603 /* Count all active objects as busy, even if they are currently not used
3604 * by the gpu. Users of this interface expect objects to eventually
3605 * become non-busy without any further actions, therefore emit any
3606 * necessary flushes here.
3608 ret = i915_gem_object_flush_active(obj);
3610 args->busy = obj->active;
3612 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3613 args->busy |= intel_ring_flag(obj->ring) << 16;
3616 drm_gem_object_unreference(&obj->base);
3618 mutex_unlock(&dev->struct_mutex);
3623 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3624 struct drm_file *file_priv)
3626 return i915_gem_ring_throttle(dev, file_priv);
3630 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3631 struct drm_file *file_priv)
3633 struct drm_i915_gem_madvise *args = data;
3634 struct drm_i915_gem_object *obj;
3637 switch (args->madv) {
3638 case I915_MADV_DONTNEED:
3639 case I915_MADV_WILLNEED:
3645 ret = i915_mutex_lock_interruptible(dev);
3649 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3650 if (&obj->base == NULL) {
3655 if (obj->pin_count) {
3660 if (obj->madv != __I915_MADV_PURGED)
3661 obj->madv = args->madv;
3663 /* if the object is no longer attached, discard its backing storage */
3664 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3665 i915_gem_object_truncate(obj);
3667 args->retained = obj->madv != __I915_MADV_PURGED;
3670 drm_gem_object_unreference(&obj->base);
3672 mutex_unlock(&dev->struct_mutex);
3676 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3677 const struct drm_i915_gem_object_ops *ops)
3679 INIT_LIST_HEAD(&obj->mm_list);
3680 INIT_LIST_HEAD(&obj->gtt_list);
3681 INIT_LIST_HEAD(&obj->ring_list);
3682 INIT_LIST_HEAD(&obj->exec_list);
3686 obj->fence_reg = I915_FENCE_REG_NONE;
3687 obj->madv = I915_MADV_WILLNEED;
3688 /* Avoid an unnecessary call to unbind on the first bind. */
3689 obj->map_and_fenceable = true;
3691 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3694 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3695 .get_pages = i915_gem_object_get_pages_gtt,
3696 .put_pages = i915_gem_object_put_pages_gtt,
3699 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3702 struct drm_i915_gem_object *obj;
3703 struct address_space *mapping;
3706 obj = i915_gem_object_alloc(dev);
3710 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3711 i915_gem_object_free(obj);
3715 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3716 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3717 /* 965gm cannot relocate objects above 4GiB. */
3718 mask &= ~__GFP_HIGHMEM;
3719 mask |= __GFP_DMA32;
3722 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3723 mapping_set_gfp_mask(mapping, mask);
3725 i915_gem_object_init(obj, &i915_gem_object_ops);
3727 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3728 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3731 /* On some devices, we can have the GPU use the LLC (the CPU
3732 * cache) for about a 10% performance improvement
3733 * compared to uncached. Graphics requests other than
3734 * display scanout are coherent with the CPU in
3735 * accessing this cache. This means in this mode we
3736 * don't need to clflush on the CPU side, and on the
3737 * GPU side we only need to flush internal caches to
3738 * get data visible to the CPU.
3740 * However, we maintain the display planes as UC, and so
3741 * need to rebind when first used as such.
3743 obj->cache_level = I915_CACHE_LLC;
3745 obj->cache_level = I915_CACHE_NONE;
3750 int i915_gem_init_object(struct drm_gem_object *obj)
3757 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3759 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3760 struct drm_device *dev = obj->base.dev;
3761 drm_i915_private_t *dev_priv = dev->dev_private;
3763 trace_i915_gem_object_destroy(obj);
3766 i915_gem_detach_phys_object(dev, obj);
3769 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3770 bool was_interruptible;
3772 was_interruptible = dev_priv->mm.interruptible;
3773 dev_priv->mm.interruptible = false;
3775 WARN_ON(i915_gem_object_unbind(obj));
3777 dev_priv->mm.interruptible = was_interruptible;
3780 obj->pages_pin_count = 0;
3781 i915_gem_object_put_pages(obj);
3782 i915_gem_object_free_mmap_offset(obj);
3783 i915_gem_object_release_stolen(obj);
3787 if (obj->base.import_attach)
3788 drm_prime_gem_destroy(&obj->base, NULL);
3790 drm_gem_object_release(&obj->base);
3791 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3794 i915_gem_object_free(obj);
3798 i915_gem_idle(struct drm_device *dev)
3800 drm_i915_private_t *dev_priv = dev->dev_private;
3803 mutex_lock(&dev->struct_mutex);
3805 if (dev_priv->mm.suspended) {
3806 mutex_unlock(&dev->struct_mutex);
3810 ret = i915_gpu_idle(dev);
3812 mutex_unlock(&dev->struct_mutex);
3815 i915_gem_retire_requests(dev);
3817 /* Under UMS, be paranoid and evict. */
3818 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3819 i915_gem_evict_everything(dev);
3821 i915_gem_reset_fences(dev);
3823 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3824 * We need to replace this with a semaphore, or something.
3825 * And not confound mm.suspended!
3827 dev_priv->mm.suspended = 1;
3828 del_timer_sync(&dev_priv->hangcheck_timer);
3830 i915_kernel_lost_context(dev);
3831 i915_gem_cleanup_ringbuffer(dev);
3833 mutex_unlock(&dev->struct_mutex);
3835 /* Cancel the retire work handler, which should be idle now. */
3836 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3841 void i915_gem_l3_remap(struct drm_device *dev)
3843 drm_i915_private_t *dev_priv = dev->dev_private;
3847 if (!IS_IVYBRIDGE(dev))
3850 if (!dev_priv->l3_parity.remap_info)
3853 misccpctl = I915_READ(GEN7_MISCCPCTL);
3854 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3855 POSTING_READ(GEN7_MISCCPCTL);
3857 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3858 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3859 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3860 DRM_DEBUG("0x%x was already programmed to %x\n",
3861 GEN7_L3LOG_BASE + i, remap);
3862 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3863 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3864 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3867 /* Make sure all the writes land before disabling dop clock gating */
3868 POSTING_READ(GEN7_L3LOG_BASE);
3870 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3873 void i915_gem_init_swizzling(struct drm_device *dev)
3875 drm_i915_private_t *dev_priv = dev->dev_private;
3877 if (INTEL_INFO(dev)->gen < 5 ||
3878 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3881 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3882 DISP_TILE_SURFACE_SWIZZLING);
3887 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3889 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3891 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3895 intel_enable_blt(struct drm_device *dev)
3900 /* The blitter was dysfunctional on early prototypes */
3901 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3902 DRM_INFO("BLT not supported on this pre-production hardware;"
3903 " graphics performance will be degraded.\n");
3911 i915_gem_init_hw(struct drm_device *dev)
3913 drm_i915_private_t *dev_priv = dev->dev_private;
3916 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3919 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3920 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3922 i915_gem_l3_remap(dev);
3924 i915_gem_init_swizzling(dev);
3926 ret = intel_init_render_ring_buffer(dev);
3931 ret = intel_init_bsd_ring_buffer(dev);
3933 goto cleanup_render_ring;
3936 if (intel_enable_blt(dev)) {
3937 ret = intel_init_blt_ring_buffer(dev);
3939 goto cleanup_bsd_ring;
3942 dev_priv->next_seqno = 1;
3945 * XXX: There was some w/a described somewhere suggesting loading
3946 * contexts before PPGTT.
3948 i915_gem_context_init(dev);
3949 i915_gem_init_ppgtt(dev);
3954 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3955 cleanup_render_ring:
3956 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3961 intel_enable_ppgtt(struct drm_device *dev)
3963 if (i915_enable_ppgtt >= 0)
3964 return i915_enable_ppgtt;
3966 #ifdef CONFIG_INTEL_IOMMU
3967 /* Disable ppgtt on SNB if VT-d is on. */
3968 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3975 int i915_gem_init(struct drm_device *dev)
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 unsigned long gtt_size, mappable_size;
3981 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3982 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3984 mutex_lock(&dev->struct_mutex);
3985 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3986 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3987 * aperture accordingly when using aliasing ppgtt. */
3988 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3990 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3992 ret = i915_gem_init_aliasing_ppgtt(dev);
3994 mutex_unlock(&dev->struct_mutex);
3998 /* Let GEM Manage all of the aperture.
4000 * However, leave one page at the end still bound to the scratch
4001 * page. There are a number of places where the hardware
4002 * apparently prefetches past the end of the object, and we've
4003 * seen multiple hangs with the GPU head pointer stuck in a
4004 * batchbuffer bound at the last page of the aperture. One page
4005 * should be enough to keep any prefetching inside of the
4008 i915_gem_init_global_gtt(dev, 0, mappable_size,
4012 ret = i915_gem_init_hw(dev);
4013 mutex_unlock(&dev->struct_mutex);
4015 i915_gem_cleanup_aliasing_ppgtt(dev);
4019 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4020 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4021 dev_priv->dri1.allow_batchbuffer = 1;
4026 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4028 drm_i915_private_t *dev_priv = dev->dev_private;
4029 struct intel_ring_buffer *ring;
4032 for_each_ring(ring, dev_priv, i)
4033 intel_cleanup_ring_buffer(ring);
4037 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4038 struct drm_file *file_priv)
4040 drm_i915_private_t *dev_priv = dev->dev_private;
4043 if (drm_core_check_feature(dev, DRIVER_MODESET))
4046 if (atomic_read(&dev_priv->mm.wedged)) {
4047 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4048 atomic_set(&dev_priv->mm.wedged, 0);
4051 mutex_lock(&dev->struct_mutex);
4052 dev_priv->mm.suspended = 0;
4054 ret = i915_gem_init_hw(dev);
4056 mutex_unlock(&dev->struct_mutex);
4060 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4061 mutex_unlock(&dev->struct_mutex);
4063 ret = drm_irq_install(dev);
4065 goto cleanup_ringbuffer;
4070 mutex_lock(&dev->struct_mutex);
4071 i915_gem_cleanup_ringbuffer(dev);
4072 dev_priv->mm.suspended = 1;
4073 mutex_unlock(&dev->struct_mutex);
4079 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4080 struct drm_file *file_priv)
4082 if (drm_core_check_feature(dev, DRIVER_MODESET))
4085 drm_irq_uninstall(dev);
4086 return i915_gem_idle(dev);
4090 i915_gem_lastclose(struct drm_device *dev)
4094 if (drm_core_check_feature(dev, DRIVER_MODESET))
4097 ret = i915_gem_idle(dev);
4099 DRM_ERROR("failed to idle hardware: %d\n", ret);
4103 init_ring_lists(struct intel_ring_buffer *ring)
4105 INIT_LIST_HEAD(&ring->active_list);
4106 INIT_LIST_HEAD(&ring->request_list);
4110 i915_gem_load(struct drm_device *dev)
4112 drm_i915_private_t *dev_priv = dev->dev_private;
4116 kmem_cache_create("i915_gem_object",
4117 sizeof(struct drm_i915_gem_object), 0,
4121 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4122 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4123 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4124 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4125 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4126 for (i = 0; i < I915_NUM_RINGS; i++)
4127 init_ring_lists(&dev_priv->ring[i]);
4128 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4129 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4130 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4131 i915_gem_retire_work_handler);
4132 init_completion(&dev_priv->error_completion);
4134 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4136 I915_WRITE(MI_ARB_STATE,
4137 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4140 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4142 /* Old X drivers will take 0-2 for front, back, depth buffers */
4143 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4144 dev_priv->fence_reg_start = 3;
4146 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4147 dev_priv->num_fence_regs = 16;
4149 dev_priv->num_fence_regs = 8;
4151 /* Initialize fence registers to zero */
4152 i915_gem_reset_fences(dev);
4154 i915_gem_detect_bit_6_swizzle(dev);
4155 init_waitqueue_head(&dev_priv->pending_flip_queue);
4157 dev_priv->mm.interruptible = true;
4159 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4160 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4161 register_shrinker(&dev_priv->mm.inactive_shrinker);
4165 * Create a physically contiguous memory object for this object
4166 * e.g. for cursor + overlay regs
4168 static int i915_gem_init_phys_object(struct drm_device *dev,
4169 int id, int size, int align)
4171 drm_i915_private_t *dev_priv = dev->dev_private;
4172 struct drm_i915_gem_phys_object *phys_obj;
4175 if (dev_priv->mm.phys_objs[id - 1] || !size)
4178 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4184 phys_obj->handle = drm_pci_alloc(dev, size, align);
4185 if (!phys_obj->handle) {
4190 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4193 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4201 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4203 drm_i915_private_t *dev_priv = dev->dev_private;
4204 struct drm_i915_gem_phys_object *phys_obj;
4206 if (!dev_priv->mm.phys_objs[id - 1])
4209 phys_obj = dev_priv->mm.phys_objs[id - 1];
4210 if (phys_obj->cur_obj) {
4211 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4215 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4217 drm_pci_free(dev, phys_obj->handle);
4219 dev_priv->mm.phys_objs[id - 1] = NULL;
4222 void i915_gem_free_all_phys_object(struct drm_device *dev)
4226 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4227 i915_gem_free_phys_object(dev, i);
4230 void i915_gem_detach_phys_object(struct drm_device *dev,
4231 struct drm_i915_gem_object *obj)
4233 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4240 vaddr = obj->phys_obj->handle->vaddr;
4242 page_count = obj->base.size / PAGE_SIZE;
4243 for (i = 0; i < page_count; i++) {
4244 struct page *page = shmem_read_mapping_page(mapping, i);
4245 if (!IS_ERR(page)) {
4246 char *dst = kmap_atomic(page);
4247 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4250 drm_clflush_pages(&page, 1);
4252 set_page_dirty(page);
4253 mark_page_accessed(page);
4254 page_cache_release(page);
4257 i915_gem_chipset_flush(dev);
4259 obj->phys_obj->cur_obj = NULL;
4260 obj->phys_obj = NULL;
4264 i915_gem_attach_phys_object(struct drm_device *dev,
4265 struct drm_i915_gem_object *obj,
4269 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4270 drm_i915_private_t *dev_priv = dev->dev_private;
4275 if (id > I915_MAX_PHYS_OBJECT)
4278 if (obj->phys_obj) {
4279 if (obj->phys_obj->id == id)
4281 i915_gem_detach_phys_object(dev, obj);
4284 /* create a new object */
4285 if (!dev_priv->mm.phys_objs[id - 1]) {
4286 ret = i915_gem_init_phys_object(dev, id,
4287 obj->base.size, align);
4289 DRM_ERROR("failed to init phys object %d size: %zu\n",
4290 id, obj->base.size);
4295 /* bind to the object */
4296 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4297 obj->phys_obj->cur_obj = obj;
4299 page_count = obj->base.size / PAGE_SIZE;
4301 for (i = 0; i < page_count; i++) {
4305 page = shmem_read_mapping_page(mapping, i);
4307 return PTR_ERR(page);
4309 src = kmap_atomic(page);
4310 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4311 memcpy(dst, src, PAGE_SIZE);
4314 mark_page_accessed(page);
4315 page_cache_release(page);
4322 i915_gem_phys_pwrite(struct drm_device *dev,
4323 struct drm_i915_gem_object *obj,
4324 struct drm_i915_gem_pwrite *args,
4325 struct drm_file *file_priv)
4327 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4328 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4330 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4331 unsigned long unwritten;
4333 /* The physical object once assigned is fixed for the lifetime
4334 * of the obj, so we can safely drop the lock and continue
4337 mutex_unlock(&dev->struct_mutex);
4338 unwritten = copy_from_user(vaddr, user_data, args->size);
4339 mutex_lock(&dev->struct_mutex);
4344 i915_gem_chipset_flush(dev);
4348 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4350 struct drm_i915_file_private *file_priv = file->driver_priv;
4352 /* Clean up our request list when the client is going away, so that
4353 * later retire_requests won't dereference our soon-to-be-gone
4356 spin_lock(&file_priv->mm.lock);
4357 while (!list_empty(&file_priv->mm.request_list)) {
4358 struct drm_i915_gem_request *request;
4360 request = list_first_entry(&file_priv->mm.request_list,
4361 struct drm_i915_gem_request,
4363 list_del(&request->client_list);
4364 request->file_priv = NULL;
4366 spin_unlock(&file_priv->mm.lock);
4369 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4371 if (!mutex_is_locked(mutex))
4374 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4375 return mutex->owner == task;
4377 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4383 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4385 struct drm_i915_private *dev_priv =
4386 container_of(shrinker,
4387 struct drm_i915_private,
4388 mm.inactive_shrinker);
4389 struct drm_device *dev = dev_priv->dev;
4390 struct drm_i915_gem_object *obj;
4391 int nr_to_scan = sc->nr_to_scan;
4395 if (!mutex_trylock(&dev->struct_mutex)) {
4396 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4403 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4405 i915_gem_shrink_all(dev_priv);
4409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4410 if (obj->pages_pin_count == 0)
4411 cnt += obj->base.size >> PAGE_SHIFT;
4412 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4413 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4414 cnt += obj->base.size >> PAGE_SHIFT;
4417 mutex_unlock(&dev->struct_mutex);