drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                                           bool write);
  43 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                                   uint64_t offset,
  45                                                                   uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                                     unsigned alignment,
  49                                                     bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     int nr_to_scan,
  60                                     gfp_t gfp_mask);
  61
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 static int
  79 i915_gem_wait_for_error(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         if (atomic_read(&dev_priv->mm.wedged)) {
  94                 /* GPU is hung, bump the completion count to account for
  95                  * the token we just consumed so that we never hit zero and
  96                  * end up waiting upon a subsequent completion event that
  97                  * will never happen.
  98                  */
  99                 spin_lock_irqsave(&x->wait.lock, flags);
 100                 x->done++;
 101                 spin_unlock_irqrestore(&x->wait.lock, flags);
 102         }
 103         return 0;
 104 }
 105
 106 int i915_mutex_lock_interruptible(struct drm_device *dev)
 107 {
 108         int ret;
 109
 110         ret = i915_gem_wait_for_error(dev);
 111         if (ret)
 112                 return ret;
 113
 114         ret = mutex_lock_interruptible(&dev->struct_mutex);
 115         if (ret)
 116                 return ret;
 117
 118         WARN_ON(i915_verify_lists(dev));
 119         return 0;
 120 }
 121
 122 static inline bool
 123 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 124 {
 125         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 126 }
 127
 128 void i915_gem_do_init(struct drm_device *dev,
 129                       unsigned long start,
 130                       unsigned long mappable_end,
 131                       unsigned long end)
 132 {
 133         drm_i915_private_t *dev_priv = dev->dev_private;
 134
 135         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 136
 137         dev_priv->mm.gtt_start = start;
 138         dev_priv->mm.gtt_mappable_end = mappable_end;
 139         dev_priv->mm.gtt_end = end;
 140         dev_priv->mm.gtt_total = end - start;
 141         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 142
 143         /* Take over this portion of the GTT */
 144         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 145 }
 146
 147 int
 148 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 149                     struct drm_file *file)
 150 {
 151         struct drm_i915_gem_init *args = data;
 152
 153         if (args->gtt_start >= args->gtt_end ||
 154             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 155                 return -EINVAL;
 156
 157         mutex_lock(&dev->struct_mutex);
 158         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 159         mutex_unlock(&dev->struct_mutex);
 160
 161         return 0;
 162 }
 163
 164 int
 165 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 166                             struct drm_file *file)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         struct drm_i915_gem_get_aperture *args = data;
 170         struct drm_i915_gem_object *obj;
 171         size_t pinned;
 172
 173         if (!(dev->driver->driver_features & DRIVER_GEM))
 174                 return -ENODEV;
 175
 176         pinned = 0;
 177         mutex_lock(&dev->struct_mutex);
 178         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 179                 pinned += obj->gtt_space->size;
 180         mutex_unlock(&dev->struct_mutex);
 181
 182         args->aper_size = dev_priv->mm.gtt_total;
 183         args->aper_available_size = args->aper_size -pinned;
 184
 185         return 0;
 186 }
 187
 188 static int
 189 i915_gem_create(struct drm_file *file,
 190                 struct drm_device *dev,
 191                 uint64_t size,
 192                 uint32_t *handle_p)
 193 {
 194         struct drm_i915_gem_object *obj;
 195         int ret;
 196         u32 handle;
 197
 198         size = roundup(size, PAGE_SIZE);
 199
 200         /* Allocate the new object */
 201         obj = i915_gem_alloc_object(dev, size);
 202         if (obj == NULL)
 203                 return -ENOMEM;
 204
 205         ret = drm_gem_handle_create(file, &obj->base, &handle);
 206         if (ret) {
 207                 drm_gem_object_release(&obj->base);
 208                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 209                 kfree(obj);
 210                 return ret;
 211         }
 212
 213         /* drop reference from allocate - handle holds it now */
 214         drm_gem_object_unreference(&obj->base);
 215         trace_i915_gem_object_create(obj);
 216
 217         *handle_p = handle;
 218         return 0;
 219 }
 220
 221 int
 222 i915_gem_dumb_create(struct drm_file *file,
 223                      struct drm_device *dev,
 224                      struct drm_mode_create_dumb *args)
 225 {
 226         /* have to work out size/pitch and return them */
 227         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 228         args->size = args->pitch * args->height;
 229         return i915_gem_create(file, dev,
 230                                args->size, &args->handle);
 231 }
 232
 233 int i915_gem_dumb_destroy(struct drm_file *file,
 234                           struct drm_device *dev,
 235                           uint32_t handle)
 236 {
 237         return drm_gem_handle_delete(file, handle);
 238 }
 239
 240 /**
 241  * Creates a new mm object and returns a handle to it.
 242  */
 243 int
 244 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 245                       struct drm_file *file)
 246 {
 247         struct drm_i915_gem_create *args = data;
 248         return i915_gem_create(file, dev,
 249                                args->size, &args->handle);
 250 }
 251
 252 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 253 {
 254         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 255
 256         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 257                 obj->tiling_mode != I915_TILING_NONE;
 258 }
 259
 260 static inline void
 261 slow_shmem_copy(struct page *dst_page,
 262                 int dst_offset,
 263                 struct page *src_page,
 264                 int src_offset,
 265                 int length)
 266 {
 267         char *dst_vaddr, *src_vaddr;
 268
 269         dst_vaddr = kmap(dst_page);
 270         src_vaddr = kmap(src_page);
 271
 272         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 273
 274         kunmap(src_page);
 275         kunmap(dst_page);
 276 }
 277
 278 static inline void
 279 slow_shmem_bit17_copy(struct page *gpu_page,
 280                       int gpu_offset,
 281                       struct page *cpu_page,
 282                       int cpu_offset,
 283                       int length,
 284                       int is_read)
 285 {
 286         char *gpu_vaddr, *cpu_vaddr;
 287
 288         /* Use the unswizzled path if this page isn't affected. */
 289         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 290                 if (is_read)
 291                         return slow_shmem_copy(cpu_page, cpu_offset,
 292                                                gpu_page, gpu_offset, length);
 293                 else
 294                         return slow_shmem_copy(gpu_page, gpu_offset,
 295                                                cpu_page, cpu_offset, length);
 296         }
 297
 298         gpu_vaddr = kmap(gpu_page);
 299         cpu_vaddr = kmap(cpu_page);
 300
 301         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 302          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 303          */
 304         while (length > 0) {
 305                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 306                 int this_length = min(cacheline_end - gpu_offset, length);
 307                 int swizzled_gpu_offset = gpu_offset ^ 64;
 308
 309                 if (is_read) {
 310                         memcpy(cpu_vaddr + cpu_offset,
 311                                gpu_vaddr + swizzled_gpu_offset,
 312                                this_length);
 313                 } else {
 314                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 315                                cpu_vaddr + cpu_offset,
 316                                this_length);
 317                 }
 318                 cpu_offset += this_length;
 319                 gpu_offset += this_length;
 320                 length -= this_length;
 321         }
 322
 323         kunmap(cpu_page);
 324         kunmap(gpu_page);
 325 }
 326
 327 /**
 328  * This is the fast shmem pread path, which attempts to copy_from_user directly
 329  * from the backing pages of the object to the user's address space.  On a
 330  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 331  */
 332 static int
 333 i915_gem_shmem_pread_fast(struct drm_device *dev,
 334                           struct drm_i915_gem_object *obj,
 335                           struct drm_i915_gem_pread *args,
 336                           struct drm_file *file)
 337 {
 338         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 339         ssize_t remain;
 340         loff_t offset;
 341         char __user *user_data;
 342         int page_offset, page_length;
 343
 344         user_data = (char __user *) (uintptr_t) args->data_ptr;
 345         remain = args->size;
 346
 347         offset = args->offset;
 348
 349         while (remain > 0) {
 350                 struct page *page;
 351                 char *vaddr;
 352                 int ret;
 353
 354                 /* Operation in this page
 355                  *
 356                  * page_offset = offset within page
 357                  * page_length = bytes to copy for this page
 358                  */
 359                 page_offset = offset & (PAGE_SIZE-1);
 360                 page_length = remain;
 361                 if ((page_offset + remain) > PAGE_SIZE)
 362                         page_length = PAGE_SIZE - page_offset;
 363
 364                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 365                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 366                 if (IS_ERR(page))
 367                         return PTR_ERR(page);
 368
 369                 vaddr = kmap_atomic(page);
 370                 ret = __copy_to_user_inatomic(user_data,
 371                                               vaddr + page_offset,
 372                                               page_length);
 373                 kunmap_atomic(vaddr);
 374
 375                 mark_page_accessed(page);
 376                 page_cache_release(page);
 377                 if (ret)
 378                         return -EFAULT;
 379
 380                 remain -= page_length;
 381                 user_data += page_length;
 382                 offset += page_length;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * This is the fallback shmem pread path, which allocates temporary storage
 390  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 391  * can copy out of the object's backing pages while holding the struct mutex
 392  * and not take page faults.
 393  */
 394 static int
 395 i915_gem_shmem_pread_slow(struct drm_device *dev,
 396                           struct drm_i915_gem_object *obj,
 397                           struct drm_i915_gem_pread *args,
 398                           struct drm_file *file)
 399 {
 400         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 401         struct mm_struct *mm = current->mm;
 402         struct page **user_pages;
 403         ssize_t remain;
 404         loff_t offset, pinned_pages, i;
 405         loff_t first_data_page, last_data_page, num_pages;
 406         int shmem_page_offset;
 407         int data_page_index, data_page_offset;
 408         int page_length;
 409         int ret;
 410         uint64_t data_ptr = args->data_ptr;
 411         int do_bit17_swizzling;
 412
 413         remain = args->size;
 414
 415         /* Pin the user pages containing the data.  We can't fault while
 416          * holding the struct mutex, yet we want to hold it while
 417          * dereferencing the user data.
 418          */
 419         first_data_page = data_ptr / PAGE_SIZE;
 420         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 421         num_pages = last_data_page - first_data_page + 1;
 422
 423         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 424         if (user_pages == NULL)
 425                 return -ENOMEM;
 426
 427         mutex_unlock(&dev->struct_mutex);
 428         down_read(&mm->mmap_sem);
 429         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 430                                       num_pages, 1, 0, user_pages, NULL);
 431         up_read(&mm->mmap_sem);
 432         mutex_lock(&dev->struct_mutex);
 433         if (pinned_pages < num_pages) {
 434                 ret = -EFAULT;
 435                 goto out;
 436         }
 437
 438         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 439                                                         args->offset,
 440                                                         args->size);
 441         if (ret)
 442                 goto out;
 443
 444         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 445
 446         offset = args->offset;
 447
 448         while (remain > 0) {
 449                 struct page *page;
 450
 451                 /* Operation in this page
 452                  *
 453                  * shmem_page_offset = offset within page in shmem file
 454                  * data_page_index = page number in get_user_pages return
 455                  * data_page_offset = offset with data_page_index page.
 456                  * page_length = bytes to copy for this page
 457                  */
 458                 shmem_page_offset = offset & ~PAGE_MASK;
 459                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 460                 data_page_offset = data_ptr & ~PAGE_MASK;
 461
 462                 page_length = remain;
 463                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 464                         page_length = PAGE_SIZE - shmem_page_offset;
 465                 if ((data_page_offset + page_length) > PAGE_SIZE)
 466                         page_length = PAGE_SIZE - data_page_offset;
 467
 468                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 469                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 470                 if (IS_ERR(page))
 471                         return PTR_ERR(page);
 472
 473                 if (do_bit17_swizzling) {
 474                         slow_shmem_bit17_copy(page,
 475                                               shmem_page_offset,
 476                                               user_pages[data_page_index],
 477                                               data_page_offset,
 478                                               page_length,
 479                                               1);
 480                 } else {
 481                         slow_shmem_copy(user_pages[data_page_index],
 482                                         data_page_offset,
 483                                         page,
 484                                         shmem_page_offset,
 485                                         page_length);
 486                 }
 487
 488                 mark_page_accessed(page);
 489                 page_cache_release(page);
 490
 491                 remain -= page_length;
 492                 data_ptr += page_length;
 493                 offset += page_length;
 494         }
 495
 496 out:
 497         for (i = 0; i < pinned_pages; i++) {
 498                 SetPageDirty(user_pages[i]);
 499                 mark_page_accessed(user_pages[i]);
 500                 page_cache_release(user_pages[i]);
 501         }
 502         drm_free_large(user_pages);
 503
 504         return ret;
 505 }
 506
 507 /**
 508  * Reads data from the object referenced by handle.
 509  *
 510  * On error, the contents of *data are undefined.
 511  */
 512 int
 513 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 514                      struct drm_file *file)
 515 {
 516         struct drm_i915_gem_pread *args = data;
 517         struct drm_i915_gem_object *obj;
 518         int ret = 0;
 519
 520         if (args->size == 0)
 521                 return 0;
 522
 523         if (!access_ok(VERIFY_WRITE,
 524                        (char __user *)(uintptr_t)args->data_ptr,
 525                        args->size))
 526                 return -EFAULT;
 527
 528         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 529                                        args->size);
 530         if (ret)
 531                 return -EFAULT;
 532
 533         ret = i915_mutex_lock_interruptible(dev);
 534         if (ret)
 535                 return ret;
 536
 537         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 538         if (&obj->base == NULL) {
 539                 ret = -ENOENT;
 540                 goto unlock;
 541         }
 542
 543         /* Bounds check source.  */
 544         if (args->offset > obj->base.size ||
 545             args->size > obj->base.size - args->offset) {
 546                 ret = -EINVAL;
 547                 goto out;
 548         }
 549
 550         trace_i915_gem_object_pread(obj, args->offset, args->size);
 551
 552         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 553                                                         args->offset,
 554                                                         args->size);
 555         if (ret)
 556                 goto out;
 557
 558         ret = -EFAULT;
 559         if (!i915_gem_object_needs_bit17_swizzle(obj))
 560                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 561         if (ret == -EFAULT)
 562                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 563
 564 out:
 565         drm_gem_object_unreference(&obj->base);
 566 unlock:
 567         mutex_unlock(&dev->struct_mutex);
 568         return ret;
 569 }
 570
 571 /* This is the fast write path which cannot handle
 572  * page faults in the source data
 573  */
 574
 575 static inline int
 576 fast_user_write(struct io_mapping *mapping,
 577                 loff_t page_base, int page_offset,
 578                 char __user *user_data,
 579                 int length)
 580 {
 581         char *vaddr_atomic;
 582         unsigned long unwritten;
 583
 584         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 585         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 586                                                       user_data, length);
 587         io_mapping_unmap_atomic(vaddr_atomic);
 588         return unwritten;
 589 }
 590
 591 /* Here's the write path which can sleep for
 592  * page faults
 593  */
 594
 595 static inline void
 596 slow_kernel_write(struct io_mapping *mapping,
 597                   loff_t gtt_base, int gtt_offset,
 598                   struct page *user_page, int user_offset,
 599                   int length)
 600 {
 601         char __iomem *dst_vaddr;
 602         char *src_vaddr;
 603
 604         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 605         src_vaddr = kmap(user_page);
 606
 607         memcpy_toio(dst_vaddr + gtt_offset,
 608                     src_vaddr + user_offset,
 609                     length);
 610
 611         kunmap(user_page);
 612         io_mapping_unmap(dst_vaddr);
 613 }
 614
 615 /**
 616  * This is the fast pwrite path, where we copy the data directly from the
 617  * user into the GTT, uncached.
 618  */
 619 static int
 620 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 621                          struct drm_i915_gem_object *obj,
 622                          struct drm_i915_gem_pwrite *args,
 623                          struct drm_file *file)
 624 {
 625         drm_i915_private_t *dev_priv = dev->dev_private;
 626         ssize_t remain;
 627         loff_t offset, page_base;
 628         char __user *user_data;
 629         int page_offset, page_length;
 630
 631         user_data = (char __user *) (uintptr_t) args->data_ptr;
 632         remain = args->size;
 633
 634         offset = obj->gtt_offset + args->offset;
 635
 636         while (remain > 0) {
 637                 /* Operation in this page
 638                  *
 639                  * page_base = page offset within aperture
 640                  * page_offset = offset within page
 641                  * page_length = bytes to copy for this page
 642                  */
 643                 page_base = (offset & ~(PAGE_SIZE-1));
 644                 page_offset = offset & (PAGE_SIZE-1);
 645                 page_length = remain;
 646                 if ((page_offset + remain) > PAGE_SIZE)
 647                         page_length = PAGE_SIZE - page_offset;
 648
 649                 /* If we get a fault while copying data, then (presumably) our
 650                  * source page isn't available.  Return the error and we'll
 651                  * retry in the slow path.
 652                  */
 653                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 654                                     page_offset, user_data, page_length))
 655
 656                         return -EFAULT;
 657
 658                 remain -= page_length;
 659                 user_data += page_length;
 660                 offset += page_length;
 661         }
 662
 663         return 0;
 664 }
 665
 666 /**
 667  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 668  * the memory and maps it using kmap_atomic for copying.
 669  *
 670  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 671  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 672  */
 673 static int
 674 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 675                          struct drm_i915_gem_object *obj,
 676                          struct drm_i915_gem_pwrite *args,
 677                          struct drm_file *file)
 678 {
 679         drm_i915_private_t *dev_priv = dev->dev_private;
 680         ssize_t remain;
 681         loff_t gtt_page_base, offset;
 682         loff_t first_data_page, last_data_page, num_pages;
 683         loff_t pinned_pages, i;
 684         struct page **user_pages;
 685         struct mm_struct *mm = current->mm;
 686         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 687         int ret;
 688         uint64_t data_ptr = args->data_ptr;
 689
 690         remain = args->size;
 691
 692         /* Pin the user pages containing the data.  We can't fault while
 693          * holding the struct mutex, and all of the pwrite implementations
 694          * want to hold it while dereferencing the user data.
 695          */
 696         first_data_page = data_ptr / PAGE_SIZE;
 697         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 698         num_pages = last_data_page - first_data_page + 1;
 699
 700         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 701         if (user_pages == NULL)
 702                 return -ENOMEM;
 703
 704         mutex_unlock(&dev->struct_mutex);
 705         down_read(&mm->mmap_sem);
 706         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 707                                       num_pages, 0, 0, user_pages, NULL);
 708         up_read(&mm->mmap_sem);
 709         mutex_lock(&dev->struct_mutex);
 710         if (pinned_pages < num_pages) {
 711                 ret = -EFAULT;
 712                 goto out_unpin_pages;
 713         }
 714
 715         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 716         if (ret)
 717                 goto out_unpin_pages;
 718
 719         ret = i915_gem_object_put_fence(obj);
 720         if (ret)
 721                 goto out_unpin_pages;
 722
 723         offset = obj->gtt_offset + args->offset;
 724
 725         while (remain > 0) {
 726                 /* Operation in this page
 727                  *
 728                  * gtt_page_base = page offset within aperture
 729                  * gtt_page_offset = offset within page in aperture
 730                  * data_page_index = page number in get_user_pages return
 731                  * data_page_offset = offset with data_page_index page.
 732                  * page_length = bytes to copy for this page
 733                  */
 734                 gtt_page_base = offset & PAGE_MASK;
 735                 gtt_page_offset = offset & ~PAGE_MASK;
 736                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 737                 data_page_offset = data_ptr & ~PAGE_MASK;
 738
 739                 page_length = remain;
 740                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 741                         page_length = PAGE_SIZE - gtt_page_offset;
 742                 if ((data_page_offset + page_length) > PAGE_SIZE)
 743                         page_length = PAGE_SIZE - data_page_offset;
 744
 745                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 746                                   gtt_page_base, gtt_page_offset,
 747                                   user_pages[data_page_index],
 748                                   data_page_offset,
 749                                   page_length);
 750
 751                 remain -= page_length;
 752                 offset += page_length;
 753                 data_ptr += page_length;
 754         }
 755
 756 out_unpin_pages:
 757         for (i = 0; i < pinned_pages; i++)
 758                 page_cache_release(user_pages[i]);
 759         drm_free_large(user_pages);
 760
 761         return ret;
 762 }
 763
 764 /**
 765  * This is the fast shmem pwrite path, which attempts to directly
 766  * copy_from_user into the kmapped pages backing the object.
 767  */
 768 static int
 769 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 770                            struct drm_i915_gem_object *obj,
 771                            struct drm_i915_gem_pwrite *args,
 772                            struct drm_file *file)
 773 {
 774         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 775         ssize_t remain;
 776         loff_t offset;
 777         char __user *user_data;
 778         int page_offset, page_length;
 779
 780         user_data = (char __user *) (uintptr_t) args->data_ptr;
 781         remain = args->size;
 782
 783         offset = args->offset;
 784         obj->dirty = 1;
 785
 786         while (remain > 0) {
 787                 struct page *page;
 788                 char *vaddr;
 789                 int ret;
 790
 791                 /* Operation in this page
 792                  *
 793                  * page_offset = offset within page
 794                  * page_length = bytes to copy for this page
 795                  */
 796                 page_offset = offset & (PAGE_SIZE-1);
 797                 page_length = remain;
 798                 if ((page_offset + remain) > PAGE_SIZE)
 799                         page_length = PAGE_SIZE - page_offset;
 800
 801                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 802                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 803                 if (IS_ERR(page))
 804                         return PTR_ERR(page);
 805
 806                 vaddr = kmap_atomic(page, KM_USER0);
 807                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 808                                                 user_data,
 809                                                 page_length);
 810                 kunmap_atomic(vaddr, KM_USER0);
 811
 812                 set_page_dirty(page);
 813                 mark_page_accessed(page);
 814                 page_cache_release(page);
 815
 816                 /* If we get a fault while copying data, then (presumably) our
 817                  * source page isn't available.  Return the error and we'll
 818                  * retry in the slow path.
 819                  */
 820                 if (ret)
 821                         return -EFAULT;
 822
 823                 remain -= page_length;
 824                 user_data += page_length;
 825                 offset += page_length;
 826         }
 827
 828         return 0;
 829 }
 830
 831 /**
 832  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 833  * the memory and maps it using kmap_atomic for copying.
 834  *
 835  * This avoids taking mmap_sem for faulting on the user's address while the
 836  * struct_mutex is held.
 837  */
 838 static int
 839 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 840                            struct drm_i915_gem_object *obj,
 841                            struct drm_i915_gem_pwrite *args,
 842                            struct drm_file *file)
 843 {
 844         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 845         struct mm_struct *mm = current->mm;
 846         struct page **user_pages;
 847         ssize_t remain;
 848         loff_t offset, pinned_pages, i;
 849         loff_t first_data_page, last_data_page, num_pages;
 850         int shmem_page_offset;
 851         int data_page_index,  data_page_offset;
 852         int page_length;
 853         int ret;
 854         uint64_t data_ptr = args->data_ptr;
 855         int do_bit17_swizzling;
 856
 857         remain = args->size;
 858
 859         /* Pin the user pages containing the data.  We can't fault while
 860          * holding the struct mutex, and all of the pwrite implementations
 861          * want to hold it while dereferencing the user data.
 862          */
 863         first_data_page = data_ptr / PAGE_SIZE;
 864         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 865         num_pages = last_data_page - first_data_page + 1;
 866
 867         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 868         if (user_pages == NULL)
 869                 return -ENOMEM;
 870
 871         mutex_unlock(&dev->struct_mutex);
 872         down_read(&mm->mmap_sem);
 873         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 874                                       num_pages, 0, 0, user_pages, NULL);
 875         up_read(&mm->mmap_sem);
 876         mutex_lock(&dev->struct_mutex);
 877         if (pinned_pages < num_pages) {
 878                 ret = -EFAULT;
 879                 goto out;
 880         }
 881
 882         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 883         if (ret)
 884                 goto out;
 885
 886         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 887
 888         offset = args->offset;
 889         obj->dirty = 1;
 890
 891         while (remain > 0) {
 892                 struct page *page;
 893
 894                 /* Operation in this page
 895                  *
 896                  * shmem_page_offset = offset within page in shmem file
 897                  * data_page_index = page number in get_user_pages return
 898                  * data_page_offset = offset with data_page_index page.
 899                  * page_length = bytes to copy for this page
 900                  */
 901                 shmem_page_offset = offset & ~PAGE_MASK;
 902                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 903                 data_page_offset = data_ptr & ~PAGE_MASK;
 904
 905                 page_length = remain;
 906                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 907                         page_length = PAGE_SIZE - shmem_page_offset;
 908                 if ((data_page_offset + page_length) > PAGE_SIZE)
 909                         page_length = PAGE_SIZE - data_page_offset;
 910
 911                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 912                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 913                 if (IS_ERR(page)) {
 914                         ret = PTR_ERR(page);
 915                         goto out;
 916                 }
 917
 918                 if (do_bit17_swizzling) {
 919                         slow_shmem_bit17_copy(page,
 920                                               shmem_page_offset,
 921                                               user_pages[data_page_index],
 922                                               data_page_offset,
 923                                               page_length,
 924                                               0);
 925                 } else {
 926                         slow_shmem_copy(page,
 927                                         shmem_page_offset,
 928                                         user_pages[data_page_index],
 929                                         data_page_offset,
 930                                         page_length);
 931                 }
 932
 933                 set_page_dirty(page);
 934                 mark_page_accessed(page);
 935                 page_cache_release(page);
 936
 937                 remain -= page_length;
 938                 data_ptr += page_length;
 939                 offset += page_length;
 940         }
 941
 942 out:
 943         for (i = 0; i < pinned_pages; i++)
 944                 page_cache_release(user_pages[i]);
 945         drm_free_large(user_pages);
 946
 947         return ret;
 948 }
 949
 950 /**
 951  * Writes data to the object referenced by handle.
 952  *
 953  * On error, the contents of the buffer that were to be modified are undefined.
 954  */
 955 int
 956 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 957                       struct drm_file *file)
 958 {
 959         struct drm_i915_gem_pwrite *args = data;
 960         struct drm_i915_gem_object *obj;
 961         int ret;
 962
 963         if (args->size == 0)
 964                 return 0;
 965
 966         if (!access_ok(VERIFY_READ,
 967                        (char __user *)(uintptr_t)args->data_ptr,
 968                        args->size))
 969                 return -EFAULT;
 970
 971         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 972                                       args->size);
 973         if (ret)
 974                 return -EFAULT;
 975
 976         ret = i915_mutex_lock_interruptible(dev);
 977         if (ret)
 978                 return ret;
 979
 980         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 981         if (&obj->base == NULL) {
 982                 ret = -ENOENT;
 983                 goto unlock;
 984         }
 985
 986         /* Bounds check destination. */
 987         if (args->offset > obj->base.size ||
 988             args->size > obj->base.size - args->offset) {
 989                 ret = -EINVAL;
 990                 goto out;
 991         }
 992
 993         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 994
 995         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 996          * it would end up going through the fenced access, and we'll get
 997          * different detiling behavior between reading and writing.
 998          * pread/pwrite currently are reading and writing from the CPU
 999          * perspective, requiring manual detiling by the client.
1000          */
1001         if (obj->phys_obj)
1002                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1003         else if (obj->gtt_space &&
1004                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1005                 ret = i915_gem_object_pin(obj, 0, true);
1006                 if (ret)
1007                         goto out;
1008
1009                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1010                 if (ret)
1011                         goto out_unpin;
1012
1013                 ret = i915_gem_object_put_fence(obj);
1014                 if (ret)
1015                         goto out_unpin;
1016
1017                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1018                 if (ret == -EFAULT)
1019                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1020
1021 out_unpin:
1022                 i915_gem_object_unpin(obj);
1023         } else {
1024                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1025                 if (ret)
1026                         goto out;
1027
1028                 ret = -EFAULT;
1029                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1030                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1031                 if (ret == -EFAULT)
1032                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1033         }
1034
1035 out:
1036         drm_gem_object_unreference(&obj->base);
1037 unlock:
1038         mutex_unlock(&dev->struct_mutex);
1039         return ret;
1040 }
1041
1042 /**
1043  * Called when user space prepares to use an object with the CPU, either
1044  * through the mmap ioctl's mapping or a GTT mapping.
1045  */
1046 int
1047 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1048                           struct drm_file *file)
1049 {
1050         struct drm_i915_gem_set_domain *args = data;
1051         struct drm_i915_gem_object *obj;
1052         uint32_t read_domains = args->read_domains;
1053         uint32_t write_domain = args->write_domain;
1054         int ret;
1055
1056         if (!(dev->driver->driver_features & DRIVER_GEM))
1057                 return -ENODEV;
1058
1059         /* Only handle setting domains to types used by the CPU. */
1060         if (write_domain & I915_GEM_GPU_DOMAINS)
1061                 return -EINVAL;
1062
1063         if (read_domains & I915_GEM_GPU_DOMAINS)
1064                 return -EINVAL;
1065
1066         /* Having something in the write domain implies it's in the read
1067          * domain, and only that read domain.  Enforce that in the request.
1068          */
1069         if (write_domain != 0 && read_domains != write_domain)
1070                 return -EINVAL;
1071
1072         ret = i915_mutex_lock_interruptible(dev);
1073         if (ret)
1074                 return ret;
1075
1076         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1077         if (&obj->base == NULL) {
1078                 ret = -ENOENT;
1079                 goto unlock;
1080         }
1081
1082         if (read_domains & I915_GEM_DOMAIN_GTT) {
1083                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1084
1085                 /* Silently promote "you're not bound, there was nothing to do"
1086                  * to success, since the client was just asking us to
1087                  * make sure everything was done.
1088                  */
1089                 if (ret == -EINVAL)
1090                         ret = 0;
1091         } else {
1092                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1093         }
1094
1095         drm_gem_object_unreference(&obj->base);
1096 unlock:
1097         mutex_unlock(&dev->struct_mutex);
1098         return ret;
1099 }
1100
1101 /**
1102  * Called when user space has done writes to this buffer
1103  */
1104 int
1105 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1106                          struct drm_file *file)
1107 {
1108         struct drm_i915_gem_sw_finish *args = data;
1109         struct drm_i915_gem_object *obj;
1110         int ret = 0;
1111
1112         if (!(dev->driver->driver_features & DRIVER_GEM))
1113                 return -ENODEV;
1114
1115         ret = i915_mutex_lock_interruptible(dev);
1116         if (ret)
1117                 return ret;
1118
1119         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1120         if (&obj->base == NULL) {
1121                 ret = -ENOENT;
1122                 goto unlock;
1123         }
1124
1125         /* Pinned buffers may be scanout, so flush the cache */
1126         if (obj->pin_count)
1127                 i915_gem_object_flush_cpu_write_domain(obj);
1128
1129         drm_gem_object_unreference(&obj->base);
1130 unlock:
1131         mutex_unlock(&dev->struct_mutex);
1132         return ret;
1133 }
1134
1135 /**
1136  * Maps the contents of an object, returning the address it is mapped
1137  * into.
1138  *
1139  * While the mapping holds a reference on the contents of the object, it doesn't
1140  * imply a ref on the object itself.
1141  */
1142 int
1143 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1144                     struct drm_file *file)
1145 {
1146         struct drm_i915_private *dev_priv = dev->dev_private;
1147         struct drm_i915_gem_mmap *args = data;
1148         struct drm_gem_object *obj;
1149         unsigned long addr;
1150
1151         if (!(dev->driver->driver_features & DRIVER_GEM))
1152                 return -ENODEV;
1153
1154         obj = drm_gem_object_lookup(dev, file, args->handle);
1155         if (obj == NULL)
1156                 return -ENOENT;
1157
1158         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1159                 drm_gem_object_unreference_unlocked(obj);
1160                 return -E2BIG;
1161         }
1162
1163         down_write(&current->mm->mmap_sem);
1164         addr = do_mmap(obj->filp, 0, args->size,
1165                        PROT_READ | PROT_WRITE, MAP_SHARED,
1166                        args->offset);
1167         up_write(&current->mm->mmap_sem);
1168         drm_gem_object_unreference_unlocked(obj);
1169         if (IS_ERR((void *)addr))
1170                 return addr;
1171
1172         args->addr_ptr = (uint64_t) addr;
1173
1174         return 0;
1175 }
1176
1177 /**
1178  * i915_gem_fault - fault a page into the GTT
1179  * vma: VMA in question
1180  * vmf: fault info
1181  *
1182  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1183  * from userspace.  The fault handler takes care of binding the object to
1184  * the GTT (if needed), allocating and programming a fence register (again,
1185  * only if needed based on whether the old reg is still valid or the object
1186  * is tiled) and inserting a new PTE into the faulting process.
1187  *
1188  * Note that the faulting process may involve evicting existing objects
1189  * from the GTT and/or fence registers to make room.  So performance may
1190  * suffer if the GTT working set is large or there are few fence registers
1191  * left.
1192  */
1193 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1194 {
1195         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1196         struct drm_device *dev = obj->base.dev;
1197         drm_i915_private_t *dev_priv = dev->dev_private;
1198         pgoff_t page_offset;
1199         unsigned long pfn;
1200         int ret = 0;
1201         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1202
1203         /* We don't use vmf->pgoff since that has the fake offset */
1204         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1205                 PAGE_SHIFT;
1206
1207         ret = i915_mutex_lock_interruptible(dev);
1208         if (ret)
1209                 goto out;
1210
1211         trace_i915_gem_object_fault(obj, page_offset, true, write);
1212
1213         /* Now bind it into the GTT if needed */
1214         if (!obj->map_and_fenceable) {
1215                 ret = i915_gem_object_unbind(obj);
1216                 if (ret)
1217                         goto unlock;
1218         }
1219         if (!obj->gtt_space) {
1220                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1221                 if (ret)
1222                         goto unlock;
1223         }
1224
1225         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1226         if (ret)
1227                 goto unlock;
1228
1229         if (obj->tiling_mode == I915_TILING_NONE)
1230                 ret = i915_gem_object_put_fence(obj);
1231         else
1232                 ret = i915_gem_object_get_fence(obj, NULL);
1233         if (ret)
1234                 goto unlock;
1235
1236         if (i915_gem_object_is_inactive(obj))
1237                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1238
1239         obj->fault_mappable = true;
1240
1241         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1242                 page_offset;
1243
1244         /* Finally, remap it using the new GTT offset */
1245         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1246 unlock:
1247         mutex_unlock(&dev->struct_mutex);
1248 out:
1249         switch (ret) {
1250         case -EIO:
1251         case -EAGAIN:
1252                 /* Give the error handler a chance to run and move the
1253                  * objects off the GPU active list. Next time we service the
1254                  * fault, we should be able to transition the page into the
1255                  * GTT without touching the GPU (and so avoid further
1256                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1257                  * with coherency, just lost writes.
1258                  */
1259                 set_need_resched();
1260         case 0:
1261         case -ERESTARTSYS:
1262         case -EINTR:
1263                 return VM_FAULT_NOPAGE;
1264         case -ENOMEM:
1265                 return VM_FAULT_OOM;
1266         default:
1267                 return VM_FAULT_SIGBUS;
1268         }
1269 }
1270
1271 /**
1272  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1273  * @obj: obj in question
1274  *
1275  * GEM memory mapping works by handing back to userspace a fake mmap offset
1276  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1277  * up the object based on the offset and sets up the various memory mapping
1278  * structures.
1279  *
1280  * This routine allocates and attaches a fake offset for @obj.
1281  */
1282 static int
1283 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1284 {
1285         struct drm_device *dev = obj->base.dev;
1286         struct drm_gem_mm *mm = dev->mm_private;
1287         struct drm_map_list *list;
1288         struct drm_local_map *map;
1289         int ret = 0;
1290
1291         /* Set the object up for mmap'ing */
1292         list = &obj->base.map_list;
1293         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1294         if (!list->map)
1295                 return -ENOMEM;
1296
1297         map = list->map;
1298         map->type = _DRM_GEM;
1299         map->size = obj->base.size;
1300         map->handle = obj;
1301
1302         /* Get a DRM GEM mmap offset allocated... */
1303         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1304                                                     obj->base.size / PAGE_SIZE,
1305                                                     0, 0);
1306         if (!list->file_offset_node) {
1307                 DRM_ERROR("failed to allocate offset for bo %d\n",
1308                           obj->base.name);
1309                 ret = -ENOSPC;
1310                 goto out_free_list;
1311         }
1312
1313         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1314                                                   obj->base.size / PAGE_SIZE,
1315                                                   0);
1316         if (!list->file_offset_node) {
1317                 ret = -ENOMEM;
1318                 goto out_free_list;
1319         }
1320
1321         list->hash.key = list->file_offset_node->start;
1322         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1323         if (ret) {
1324                 DRM_ERROR("failed to add to map hash\n");
1325                 goto out_free_mm;
1326         }
1327
1328         return 0;
1329
1330 out_free_mm:
1331         drm_mm_put_block(list->file_offset_node);
1332 out_free_list:
1333         kfree(list->map);
1334         list->map = NULL;
1335
1336         return ret;
1337 }
1338
1339 /**
1340  * i915_gem_release_mmap - remove physical page mappings
1341  * @obj: obj in question
1342  *
1343  * Preserve the reservation of the mmapping with the DRM core code, but
1344  * relinquish ownership of the pages back to the system.
1345  *
1346  * It is vital that we remove the page mapping if we have mapped a tiled
1347  * object through the GTT and then lose the fence register due to
1348  * resource pressure. Similarly if the object has been moved out of the
1349  * aperture, than pages mapped into userspace must be revoked. Removing the
1350  * mapping will then trigger a page fault on the next user access, allowing
1351  * fixup by i915_gem_fault().
1352  */
1353 void
1354 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1355 {
1356         if (!obj->fault_mappable)
1357                 return;
1358
1359         unmap_mapping_range(obj->base.dev->dev_mapping,
1360                             (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1361                             obj->base.size, 1);
1362
1363         obj->fault_mappable = false;
1364 }
1365
1366 static void
1367 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1368 {
1369         struct drm_device *dev = obj->base.dev;
1370         struct drm_gem_mm *mm = dev->mm_private;
1371         struct drm_map_list *list = &obj->base.map_list;
1372
1373         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1374         drm_mm_put_block(list->file_offset_node);
1375         kfree(list->map);
1376         list->map = NULL;
1377 }
1378
1379 static uint32_t
1380 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1381 {
1382         struct drm_device *dev = obj->base.dev;
1383         uint32_t size;
1384
1385         if (INTEL_INFO(dev)->gen >= 4 ||
1386             obj->tiling_mode == I915_TILING_NONE)
1387                 return obj->base.size;
1388
1389         /* Previous chips need a power-of-two fence region when tiling */
1390         if (INTEL_INFO(dev)->gen == 3)
1391                 size = 1024*1024;
1392         else
1393                 size = 512*1024;
1394
1395         while (size < obj->base.size)
1396                 size <<= 1;
1397
1398         return size;
1399 }
1400
1401 /**
1402  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1403  * @obj: object to check
1404  *
1405  * Return the required GTT alignment for an object, taking into account
1406  * potential fence register mapping.
1407  */
1408 static uint32_t
1409 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1410 {
1411         struct drm_device *dev = obj->base.dev;
1412
1413         /*
1414          * Minimum alignment is 4k (GTT page size), but might be greater
1415          * if a fence register is needed for the object.
1416          */
1417         if (INTEL_INFO(dev)->gen >= 4 ||
1418             obj->tiling_mode == I915_TILING_NONE)
1419                 return 4096;
1420
1421         /*
1422          * Previous chips need to be aligned to the size of the smallest
1423          * fence register that can contain the object.
1424          */
1425         return i915_gem_get_gtt_size(obj);
1426 }
1427
1428 /**
1429  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1430  *                                       unfenced object
1431  * @obj: object to check
1432  *
1433  * Return the required GTT alignment for an object, only taking into account
1434  * unfenced tiled surface requirements.
1435  */
1436 uint32_t
1437 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1438 {
1439         struct drm_device *dev = obj->base.dev;
1440         int tile_height;
1441
1442         /*
1443          * Minimum alignment is 4k (GTT page size) for sane hw.
1444          */
1445         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1446             obj->tiling_mode == I915_TILING_NONE)
1447                 return 4096;
1448
1449         /*
1450          * Older chips need unfenced tiled buffers to be aligned to the left
1451          * edge of an even tile row (where tile rows are counted as if the bo is
1452          * placed in a fenced gtt region).
1453          */
1454         if (IS_GEN2(dev) ||
1455             (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1456                 tile_height = 32;
1457         else
1458                 tile_height = 8;
1459
1460         return tile_height * obj->stride * 2;
1461 }
1462
1463 int
1464 i915_gem_mmap_gtt(struct drm_file *file,
1465                   struct drm_device *dev,
1466                   uint32_t handle,
1467                   uint64_t *offset)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470         struct drm_i915_gem_object *obj;
1471         int ret;
1472
1473         if (!(dev->driver->driver_features & DRIVER_GEM))
1474                 return -ENODEV;
1475
1476         ret = i915_mutex_lock_interruptible(dev);
1477         if (ret)
1478                 return ret;
1479
1480         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1481         if (&obj->base == NULL) {
1482                 ret = -ENOENT;
1483                 goto unlock;
1484         }
1485
1486         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1487                 ret = -E2BIG;
1488                 goto unlock;
1489         }
1490
1491         if (obj->madv != I915_MADV_WILLNEED) {
1492                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1493                 ret = -EINVAL;
1494                 goto out;
1495         }
1496
1497         if (!obj->base.map_list.map) {
1498                 ret = i915_gem_create_mmap_offset(obj);
1499                 if (ret)
1500                         goto out;
1501         }
1502
1503         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1504
1505 out:
1506         drm_gem_object_unreference(&obj->base);
1507 unlock:
1508         mutex_unlock(&dev->struct_mutex);
1509         return ret;
1510 }
1511
1512 /**
1513  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1514  * @dev: DRM device
1515  * @data: GTT mapping ioctl data
1516  * @file: GEM object info
1517  *
1518  * Simply returns the fake offset to userspace so it can mmap it.
1519  * The mmap call will end up in drm_gem_mmap(), which will set things
1520  * up so we can get faults in the handler above.
1521  *
1522  * The fault handler will take care of binding the object into the GTT
1523  * (since it may have been evicted to make room for something), allocating
1524  * a fence register, and mapping the appropriate aperture address into
1525  * userspace.
1526  */
1527 int
1528 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1529                         struct drm_file *file)
1530 {
1531         struct drm_i915_gem_mmap_gtt *args = data;
1532
1533         if (!(dev->driver->driver_features & DRIVER_GEM))
1534                 return -ENODEV;
1535
1536         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1537 }
1538
1539
1540 static int
1541 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1542                               gfp_t gfpmask)
1543 {
1544         int page_count, i;
1545         struct address_space *mapping;
1546         struct inode *inode;
1547         struct page *page;
1548
1549         /* Get the list of pages out of our struct file.  They'll be pinned
1550          * at this point until we release them.
1551          */
1552         page_count = obj->base.size / PAGE_SIZE;
1553         BUG_ON(obj->pages != NULL);
1554         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1555         if (obj->pages == NULL)
1556                 return -ENOMEM;
1557
1558         inode = obj->base.filp->f_path.dentry->d_inode;
1559         mapping = inode->i_mapping;
1560         for (i = 0; i < page_count; i++) {
1561                 page = read_cache_page_gfp(mapping, i,
1562                                            GFP_HIGHUSER |
1563                                            __GFP_COLD |
1564                                            __GFP_RECLAIMABLE |
1565                                            gfpmask);
1566                 if (IS_ERR(page))
1567                         goto err_pages;
1568
1569                 obj->pages[i] = page;
1570         }
1571
1572         if (obj->tiling_mode != I915_TILING_NONE)
1573                 i915_gem_object_do_bit_17_swizzle(obj);
1574
1575         return 0;
1576
1577 err_pages:
1578         while (i--)
1579                 page_cache_release(obj->pages[i]);
1580
1581         drm_free_large(obj->pages);
1582         obj->pages = NULL;
1583         return PTR_ERR(page);
1584 }
1585
1586 static void
1587 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1588 {
1589         int page_count = obj->base.size / PAGE_SIZE;
1590         int i;
1591
1592         BUG_ON(obj->madv == __I915_MADV_PURGED);
1593
1594         if (obj->tiling_mode != I915_TILING_NONE)
1595                 i915_gem_object_save_bit_17_swizzle(obj);
1596
1597         if (obj->madv == I915_MADV_DONTNEED)
1598                 obj->dirty = 0;
1599
1600         for (i = 0; i < page_count; i++) {
1601                 if (obj->dirty)
1602                         set_page_dirty(obj->pages[i]);
1603
1604                 if (obj->madv == I915_MADV_WILLNEED)
1605                         mark_page_accessed(obj->pages[i]);
1606
1607                 page_cache_release(obj->pages[i]);
1608         }
1609         obj->dirty = 0;
1610
1611         drm_free_large(obj->pages);
1612         obj->pages = NULL;
1613 }
1614
1615 void
1616 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1617                                struct intel_ring_buffer *ring,
1618                                u32 seqno)
1619 {
1620         struct drm_device *dev = obj->base.dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622
1623         BUG_ON(ring == NULL);
1624         obj->ring = ring;
1625
1626         /* Add a reference if we're newly entering the active list. */
1627         if (!obj->active) {
1628                 drm_gem_object_reference(&obj->base);
1629                 obj->active = 1;
1630         }
1631
1632         /* Move from whatever list we were on to the tail of execution. */
1633         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1634         list_move_tail(&obj->ring_list, &ring->active_list);
1635
1636         obj->last_rendering_seqno = seqno;
1637         if (obj->fenced_gpu_access) {
1638                 struct drm_i915_fence_reg *reg;
1639
1640                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1641
1642                 obj->last_fenced_seqno = seqno;
1643                 obj->last_fenced_ring = ring;
1644
1645                 reg = &dev_priv->fence_regs[obj->fence_reg];
1646                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1647         }
1648 }
1649
1650 static void
1651 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1652 {
1653         list_del_init(&obj->ring_list);
1654         obj->last_rendering_seqno = 0;
1655 }
1656
1657 static void
1658 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1659 {
1660         struct drm_device *dev = obj->base.dev;
1661         drm_i915_private_t *dev_priv = dev->dev_private;
1662
1663         BUG_ON(!obj->active);
1664         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1665
1666         i915_gem_object_move_off_active(obj);
1667 }
1668
1669 static void
1670 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1671 {
1672         struct drm_device *dev = obj->base.dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674
1675         if (obj->pin_count != 0)
1676                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1677         else
1678                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1679
1680         BUG_ON(!list_empty(&obj->gpu_write_list));
1681         BUG_ON(!obj->active);
1682         obj->ring = NULL;
1683
1684         i915_gem_object_move_off_active(obj);
1685         obj->fenced_gpu_access = false;
1686
1687         obj->active = 0;
1688         obj->pending_gpu_write = false;
1689         drm_gem_object_unreference(&obj->base);
1690
1691         WARN_ON(i915_verify_lists(dev));
1692 }
1693
1694 /* Immediately discard the backing storage */
1695 static void
1696 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1697 {
1698         struct inode *inode;
1699
1700         /* Our goal here is to return as much of the memory as
1701          * is possible back to the system as we are called from OOM.
1702          * To do this we must instruct the shmfs to drop all of its
1703          * backing pages, *now*. Here we mirror the actions taken
1704          * when by shmem_delete_inode() to release the backing store.
1705          */
1706         inode = obj->base.filp->f_path.dentry->d_inode;
1707         truncate_inode_pages(inode->i_mapping, 0);
1708         if (inode->i_op->truncate_range)
1709                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1710
1711         obj->madv = __I915_MADV_PURGED;
1712 }
1713
1714 static inline int
1715 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1716 {
1717         return obj->madv == I915_MADV_DONTNEED;
1718 }
1719
1720 static void
1721 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1722                                uint32_t flush_domains)
1723 {
1724         struct drm_i915_gem_object *obj, *next;
1725
1726         list_for_each_entry_safe(obj, next,
1727                                  &ring->gpu_write_list,
1728                                  gpu_write_list) {
1729                 if (obj->base.write_domain & flush_domains) {
1730                         uint32_t old_write_domain = obj->base.write_domain;
1731
1732                         obj->base.write_domain = 0;
1733                         list_del_init(&obj->gpu_write_list);
1734                         i915_gem_object_move_to_active(obj, ring,
1735                                                        i915_gem_next_request_seqno(ring));
1736
1737                         trace_i915_gem_object_change_domain(obj,
1738                                                             obj->base.read_domains,
1739                                                             old_write_domain);
1740                 }
1741         }
1742 }
1743
1744 int
1745 i915_add_request(struct intel_ring_buffer *ring,
1746                  struct drm_file *file,
1747                  struct drm_i915_gem_request *request)
1748 {
1749         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1750         uint32_t seqno;
1751         int was_empty;
1752         int ret;
1753
1754         BUG_ON(request == NULL);
1755
1756         ret = ring->add_request(ring, &seqno);
1757         if (ret)
1758             return ret;
1759
1760         trace_i915_gem_request_add(ring, seqno);
1761
1762         request->seqno = seqno;
1763         request->ring = ring;
1764         request->emitted_jiffies = jiffies;
1765         was_empty = list_empty(&ring->request_list);
1766         list_add_tail(&request->list, &ring->request_list);
1767
1768         if (file) {
1769                 struct drm_i915_file_private *file_priv = file->driver_priv;
1770
1771                 spin_lock(&file_priv->mm.lock);
1772                 request->file_priv = file_priv;
1773                 list_add_tail(&request->client_list,
1774                               &file_priv->mm.request_list);
1775                 spin_unlock(&file_priv->mm.lock);
1776         }
1777
1778         ring->outstanding_lazy_request = false;
1779
1780         if (!dev_priv->mm.suspended) {
1781                 mod_timer(&dev_priv->hangcheck_timer,
1782                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1783                 if (was_empty)
1784                         queue_delayed_work(dev_priv->wq,
1785                                            &dev_priv->mm.retire_work, HZ);
1786         }
1787         return 0;
1788 }
1789
1790 static inline void
1791 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1792 {
1793         struct drm_i915_file_private *file_priv = request->file_priv;
1794
1795         if (!file_priv)
1796                 return;
1797
1798         spin_lock(&file_priv->mm.lock);
1799         if (request->file_priv) {
1800                 list_del(&request->client_list);
1801                 request->file_priv = NULL;
1802         }
1803         spin_unlock(&file_priv->mm.lock);
1804 }
1805
1806 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1807                                       struct intel_ring_buffer *ring)
1808 {
1809         while (!list_empty(&ring->request_list)) {
1810                 struct drm_i915_gem_request *request;
1811
1812                 request = list_first_entry(&ring->request_list,
1813                                            struct drm_i915_gem_request,
1814                                            list);
1815
1816                 list_del(&request->list);
1817                 i915_gem_request_remove_from_client(request);
1818                 kfree(request);
1819         }
1820
1821         while (!list_empty(&ring->active_list)) {
1822                 struct drm_i915_gem_object *obj;
1823
1824                 obj = list_first_entry(&ring->active_list,
1825                                        struct drm_i915_gem_object,
1826                                        ring_list);
1827
1828                 obj->base.write_domain = 0;
1829                 list_del_init(&obj->gpu_write_list);
1830                 i915_gem_object_move_to_inactive(obj);
1831         }
1832 }
1833
1834 static void i915_gem_reset_fences(struct drm_device *dev)
1835 {
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         int i;
1838
1839         for (i = 0; i < 16; i++) {
1840                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1841                 struct drm_i915_gem_object *obj = reg->obj;
1842
1843                 if (!obj)
1844                         continue;
1845
1846                 if (obj->tiling_mode)
1847                         i915_gem_release_mmap(obj);
1848
1849                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1850                 reg->obj->fenced_gpu_access = false;
1851                 reg->obj->last_fenced_seqno = 0;
1852                 reg->obj->last_fenced_ring = NULL;
1853                 i915_gem_clear_fence_reg(dev, reg);
1854         }
1855 }
1856
1857 void i915_gem_reset(struct drm_device *dev)
1858 {
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct drm_i915_gem_object *obj;
1861         int i;
1862
1863         for (i = 0; i < I915_NUM_RINGS; i++)
1864                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1865
1866         /* Remove anything from the flushing lists. The GPU cache is likely
1867          * to be lost on reset along with the data, so simply move the
1868          * lost bo to the inactive list.
1869          */
1870         while (!list_empty(&dev_priv->mm.flushing_list)) {
1871                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1872                                       struct drm_i915_gem_object,
1873                                       mm_list);
1874
1875                 obj->base.write_domain = 0;
1876                 list_del_init(&obj->gpu_write_list);
1877                 i915_gem_object_move_to_inactive(obj);
1878         }
1879
1880         /* Move everything out of the GPU domains to ensure we do any
1881          * necessary invalidation upon reuse.
1882          */
1883         list_for_each_entry(obj,
1884                             &dev_priv->mm.inactive_list,
1885                             mm_list)
1886         {
1887                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1888         }
1889
1890         /* The fence registers are invalidated so clear them out */
1891         i915_gem_reset_fences(dev);
1892 }
1893
1894 /**
1895  * This function clears the request list as sequence numbers are passed.
1896  */
1897 static void
1898 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1899 {
1900         uint32_t seqno;
1901         int i;
1902
1903         if (list_empty(&ring->request_list))
1904                 return;
1905
1906         WARN_ON(i915_verify_lists(ring->dev));
1907
1908         seqno = ring->get_seqno(ring);
1909
1910         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1911                 if (seqno >= ring->sync_seqno[i])
1912                         ring->sync_seqno[i] = 0;
1913
1914         while (!list_empty(&ring->request_list)) {
1915                 struct drm_i915_gem_request *request;
1916
1917                 request = list_first_entry(&ring->request_list,
1918                                            struct drm_i915_gem_request,
1919                                            list);
1920
1921                 if (!i915_seqno_passed(seqno, request->seqno))
1922                         break;
1923
1924                 trace_i915_gem_request_retire(ring, request->seqno);
1925
1926                 list_del(&request->list);
1927                 i915_gem_request_remove_from_client(request);
1928                 kfree(request);
1929         }
1930
1931         /* Move any buffers on the active list that are no longer referenced
1932          * by the ringbuffer to the flushing/inactive lists as appropriate.
1933          */
1934         while (!list_empty(&ring->active_list)) {
1935                 struct drm_i915_gem_object *obj;
1936
1937                 obj= list_first_entry(&ring->active_list,
1938                                       struct drm_i915_gem_object,
1939                                       ring_list);
1940
1941                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1942                         break;
1943
1944                 if (obj->base.write_domain != 0)
1945                         i915_gem_object_move_to_flushing(obj);
1946                 else
1947                         i915_gem_object_move_to_inactive(obj);
1948         }
1949
1950         if (unlikely(ring->trace_irq_seqno &&
1951                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1952                 ring->irq_put(ring);
1953                 ring->trace_irq_seqno = 0;
1954         }
1955
1956         WARN_ON(i915_verify_lists(ring->dev));
1957 }
1958
1959 void
1960 i915_gem_retire_requests(struct drm_device *dev)
1961 {
1962         drm_i915_private_t *dev_priv = dev->dev_private;
1963         int i;
1964
1965         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1966             struct drm_i915_gem_object *obj, *next;
1967
1968             /* We must be careful that during unbind() we do not
1969              * accidentally infinitely recurse into retire requests.
1970              * Currently:
1971              *   retire -> free -> unbind -> wait -> retire_ring
1972              */
1973             list_for_each_entry_safe(obj, next,
1974                                      &dev_priv->mm.deferred_free_list,
1975                                      mm_list)
1976                     i915_gem_free_object_tail(obj);
1977         }
1978
1979         for (i = 0; i < I915_NUM_RINGS; i++)
1980                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1981 }
1982
1983 static void
1984 i915_gem_retire_work_handler(struct work_struct *work)
1985 {
1986         drm_i915_private_t *dev_priv;
1987         struct drm_device *dev;
1988         bool idle;
1989         int i;
1990
1991         dev_priv = container_of(work, drm_i915_private_t,
1992                                 mm.retire_work.work);
1993         dev = dev_priv->dev;
1994
1995         /* Come back later if the device is busy... */
1996         if (!mutex_trylock(&dev->struct_mutex)) {
1997                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1998                 return;
1999         }
2000
2001         i915_gem_retire_requests(dev);
2002
2003         /* Send a periodic flush down the ring so we don't hold onto GEM
2004          * objects indefinitely.
2005          */
2006         idle = true;
2007         for (i = 0; i < I915_NUM_RINGS; i++) {
2008                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2009
2010                 if (!list_empty(&ring->gpu_write_list)) {
2011                         struct drm_i915_gem_request *request;
2012                         int ret;
2013
2014                         ret = i915_gem_flush_ring(ring,
2015                                                   0, I915_GEM_GPU_DOMAINS);
2016                         request = kzalloc(sizeof(*request), GFP_KERNEL);
2017                         if (ret || request == NULL ||
2018                             i915_add_request(ring, NULL, request))
2019                             kfree(request);
2020                 }
2021
2022                 idle &= list_empty(&ring->request_list);
2023         }
2024
2025         if (!dev_priv->mm.suspended && !idle)
2026                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2027
2028         mutex_unlock(&dev->struct_mutex);
2029 }
2030
2031 /**
2032  * Waits for a sequence number to be signaled, and cleans up the
2033  * request and object lists appropriately for that event.
2034  */
2035 int
2036 i915_wait_request(struct intel_ring_buffer *ring,
2037                   uint32_t seqno)
2038 {
2039         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2040         u32 ier;
2041         int ret = 0;
2042
2043         BUG_ON(seqno == 0);
2044
2045         if (atomic_read(&dev_priv->mm.wedged)) {
2046                 struct completion *x = &dev_priv->error_completion;
2047                 bool recovery_complete;
2048                 unsigned long flags;
2049
2050                 /* Give the error handler a chance to run. */
2051                 spin_lock_irqsave(&x->wait.lock, flags);
2052                 recovery_complete = x->done > 0;
2053                 spin_unlock_irqrestore(&x->wait.lock, flags);
2054
2055                 return recovery_complete ? -EIO : -EAGAIN;
2056         }
2057
2058         if (seqno == ring->outstanding_lazy_request) {
2059                 struct drm_i915_gem_request *request;
2060
2061                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2062                 if (request == NULL)
2063                         return -ENOMEM;
2064
2065                 ret = i915_add_request(ring, NULL, request);
2066                 if (ret) {
2067                         kfree(request);
2068                         return ret;
2069                 }
2070
2071                 seqno = request->seqno;
2072         }
2073
2074         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2075                 if (HAS_PCH_SPLIT(ring->dev))
2076                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2077                 else
2078                         ier = I915_READ(IER);
2079                 if (!ier) {
2080                         DRM_ERROR("something (likely vbetool) disabled "
2081                                   "interrupts, re-enabling\n");
2082                         i915_driver_irq_preinstall(ring->dev);
2083                         i915_driver_irq_postinstall(ring->dev);
2084                 }
2085
2086                 trace_i915_gem_request_wait_begin(ring, seqno);
2087
2088                 ring->waiting_seqno = seqno;
2089                 if (ring->irq_get(ring)) {
2090                         if (dev_priv->mm.interruptible)
2091                                 ret = wait_event_interruptible(ring->irq_queue,
2092                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2093                                                                || atomic_read(&dev_priv->mm.wedged));
2094                         else
2095                                 wait_event(ring->irq_queue,
2096                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2097                                            || atomic_read(&dev_priv->mm.wedged));
2098
2099                         ring->irq_put(ring);
2100                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2101                                                       seqno) ||
2102                                     atomic_read(&dev_priv->mm.wedged), 3000))
2103                         ret = -EBUSY;
2104                 ring->waiting_seqno = 0;
2105
2106                 trace_i915_gem_request_wait_end(ring, seqno);
2107         }
2108         if (atomic_read(&dev_priv->mm.wedged))
2109                 ret = -EAGAIN;
2110
2111         if (ret && ret != -ERESTARTSYS)
2112                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2113                           __func__, ret, seqno, ring->get_seqno(ring),
2114                           dev_priv->next_seqno);
2115
2116         /* Directly dispatch request retiring.  While we have the work queue
2117          * to handle this, the waiter on a request often wants an associated
2118          * buffer to have made it to the inactive list, and we would need
2119          * a separate wait queue to handle that.
2120          */
2121         if (ret == 0)
2122                 i915_gem_retire_requests_ring(ring);
2123
2124         return ret;
2125 }
2126
2127 /**
2128  * Ensures that all rendering to the object has completed and the object is
2129  * safe to unbind from the GTT or access from the CPU.
2130  */
2131 int
2132 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2133 {
2134         int ret;
2135
2136         /* This function only exists to support waiting for existing rendering,
2137          * not for emitting required flushes.
2138          */
2139         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2140
2141         /* If there is rendering queued on the buffer being evicted, wait for
2142          * it.
2143          */
2144         if (obj->active) {
2145                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2146                 if (ret)
2147                         return ret;
2148         }
2149
2150         return 0;
2151 }
2152
2153 /**
2154  * Unbinds an object from the GTT aperture.
2155  */
2156 int
2157 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2158 {
2159         int ret = 0;
2160
2161         if (obj->gtt_space == NULL)
2162                 return 0;
2163
2164         if (obj->pin_count != 0) {
2165                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2166                 return -EINVAL;
2167         }
2168
2169         /* blow away mappings if mapped through GTT */
2170         i915_gem_release_mmap(obj);
2171
2172         /* Move the object to the CPU domain to ensure that
2173          * any possible CPU writes while it's not in the GTT
2174          * are flushed when we go to remap it. This will
2175          * also ensure that all pending GPU writes are finished
2176          * before we unbind.
2177          */
2178         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2179         if (ret == -ERESTARTSYS)
2180                 return ret;
2181         /* Continue on if we fail due to EIO, the GPU is hung so we
2182          * should be safe and we need to cleanup or else we might
2183          * cause memory corruption through use-after-free.
2184          */
2185         if (ret) {
2186                 i915_gem_clflush_object(obj);
2187                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2188         }
2189
2190         /* release the fence reg _after_ flushing */
2191         ret = i915_gem_object_put_fence(obj);
2192         if (ret == -ERESTARTSYS)
2193                 return ret;
2194
2195         trace_i915_gem_object_unbind(obj);
2196
2197         i915_gem_gtt_unbind_object(obj);
2198         i915_gem_object_put_pages_gtt(obj);
2199
2200         list_del_init(&obj->gtt_list);
2201         list_del_init(&obj->mm_list);
2202         /* Avoid an unnecessary call to unbind on rebind. */
2203         obj->map_and_fenceable = true;
2204
2205         drm_mm_put_block(obj->gtt_space);
2206         obj->gtt_space = NULL;
2207         obj->gtt_offset = 0;
2208
2209         if (i915_gem_object_is_purgeable(obj))
2210                 i915_gem_object_truncate(obj);
2211
2212         return ret;
2213 }
2214
2215 int
2216 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2217                     uint32_t invalidate_domains,
2218                     uint32_t flush_domains)
2219 {
2220         int ret;
2221
2222         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2223                 return 0;
2224
2225         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2226
2227         ret = ring->flush(ring, invalidate_domains, flush_domains);
2228         if (ret)
2229                 return ret;
2230
2231         if (flush_domains & I915_GEM_GPU_DOMAINS)
2232                 i915_gem_process_flushing_list(ring, flush_domains);
2233
2234         return 0;
2235 }
2236
2237 static int i915_ring_idle(struct intel_ring_buffer *ring)
2238 {
2239         int ret;
2240
2241         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2242                 return 0;
2243
2244         if (!list_empty(&ring->gpu_write_list)) {
2245                 ret = i915_gem_flush_ring(ring,
2246                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2247                 if (ret)
2248                         return ret;
2249         }
2250
2251         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2252 }
2253
2254 int
2255 i915_gpu_idle(struct drm_device *dev)
2256 {
2257         drm_i915_private_t *dev_priv = dev->dev_private;
2258         bool lists_empty;
2259         int ret, i;
2260
2261         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2262                        list_empty(&dev_priv->mm.active_list));
2263         if (lists_empty)
2264                 return 0;
2265
2266         /* Flush everything onto the inactive list. */
2267         for (i = 0; i < I915_NUM_RINGS; i++) {
2268                 ret = i915_ring_idle(&dev_priv->ring[i]);
2269                 if (ret)
2270                         return ret;
2271         }
2272
2273         return 0;
2274 }
2275
2276 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2277                                        struct intel_ring_buffer *pipelined)
2278 {
2279         struct drm_device *dev = obj->base.dev;
2280         drm_i915_private_t *dev_priv = dev->dev_private;
2281         u32 size = obj->gtt_space->size;
2282         int regnum = obj->fence_reg;
2283         uint64_t val;
2284
2285         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2286                          0xfffff000) << 32;
2287         val |= obj->gtt_offset & 0xfffff000;
2288         val |= (uint64_t)((obj->stride / 128) - 1) <<
2289                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2290
2291         if (obj->tiling_mode == I915_TILING_Y)
2292                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2293         val |= I965_FENCE_REG_VALID;
2294
2295         if (pipelined) {
2296                 int ret = intel_ring_begin(pipelined, 6);
2297                 if (ret)
2298                         return ret;
2299
2300                 intel_ring_emit(pipelined, MI_NOOP);
2301                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2302                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2303                 intel_ring_emit(pipelined, (u32)val);
2304                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2305                 intel_ring_emit(pipelined, (u32)(val >> 32));
2306                 intel_ring_advance(pipelined);
2307         } else
2308                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2309
2310         return 0;
2311 }
2312
2313 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2314                                 struct intel_ring_buffer *pipelined)
2315 {
2316         struct drm_device *dev = obj->base.dev;
2317         drm_i915_private_t *dev_priv = dev->dev_private;
2318         u32 size = obj->gtt_space->size;
2319         int regnum = obj->fence_reg;
2320         uint64_t val;
2321
2322         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2323                     0xfffff000) << 32;
2324         val |= obj->gtt_offset & 0xfffff000;
2325         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2326         if (obj->tiling_mode == I915_TILING_Y)
2327                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2328         val |= I965_FENCE_REG_VALID;
2329
2330         if (pipelined) {
2331                 int ret = intel_ring_begin(pipelined, 6);
2332                 if (ret)
2333                         return ret;
2334
2335                 intel_ring_emit(pipelined, MI_NOOP);
2336                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2337                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2338                 intel_ring_emit(pipelined, (u32)val);
2339                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2340                 intel_ring_emit(pipelined, (u32)(val >> 32));
2341                 intel_ring_advance(pipelined);
2342         } else
2343                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2344
2345         return 0;
2346 }
2347
2348 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2349                                 struct intel_ring_buffer *pipelined)
2350 {
2351         struct drm_device *dev = obj->base.dev;
2352         drm_i915_private_t *dev_priv = dev->dev_private;
2353         u32 size = obj->gtt_space->size;
2354         u32 fence_reg, val, pitch_val;
2355         int tile_width;
2356
2357         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2358                  (size & -size) != size ||
2359                  (obj->gtt_offset & (size - 1)),
2360                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2361                  obj->gtt_offset, obj->map_and_fenceable, size))
2362                 return -EINVAL;
2363
2364         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2365                 tile_width = 128;
2366         else
2367                 tile_width = 512;
2368
2369         /* Note: pitch better be a power of two tile widths */
2370         pitch_val = obj->stride / tile_width;
2371         pitch_val = ffs(pitch_val) - 1;
2372
2373         val = obj->gtt_offset;
2374         if (obj->tiling_mode == I915_TILING_Y)
2375                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2376         val |= I915_FENCE_SIZE_BITS(size);
2377         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2378         val |= I830_FENCE_REG_VALID;
2379
2380         fence_reg = obj->fence_reg;
2381         if (fence_reg < 8)
2382                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2383         else
2384                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2385
2386         if (pipelined) {
2387                 int ret = intel_ring_begin(pipelined, 4);
2388                 if (ret)
2389                         return ret;
2390
2391                 intel_ring_emit(pipelined, MI_NOOP);
2392                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2393                 intel_ring_emit(pipelined, fence_reg);
2394                 intel_ring_emit(pipelined, val);
2395                 intel_ring_advance(pipelined);
2396         } else
2397                 I915_WRITE(fence_reg, val);
2398
2399         return 0;
2400 }
2401
2402 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2403                                 struct intel_ring_buffer *pipelined)
2404 {
2405         struct drm_device *dev = obj->base.dev;
2406         drm_i915_private_t *dev_priv = dev->dev_private;
2407         u32 size = obj->gtt_space->size;
2408         int regnum = obj->fence_reg;
2409         uint32_t val;
2410         uint32_t pitch_val;
2411
2412         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2413                  (size & -size) != size ||
2414                  (obj->gtt_offset & (size - 1)),
2415                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2416                  obj->gtt_offset, size))
2417                 return -EINVAL;
2418
2419         pitch_val = obj->stride / 128;
2420         pitch_val = ffs(pitch_val) - 1;
2421
2422         val = obj->gtt_offset;
2423         if (obj->tiling_mode == I915_TILING_Y)
2424                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2425         val |= I830_FENCE_SIZE_BITS(size);
2426         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2427         val |= I830_FENCE_REG_VALID;
2428
2429         if (pipelined) {
2430                 int ret = intel_ring_begin(pipelined, 4);
2431                 if (ret)
2432                         return ret;
2433
2434                 intel_ring_emit(pipelined, MI_NOOP);
2435                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2436                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2437                 intel_ring_emit(pipelined, val);
2438                 intel_ring_advance(pipelined);
2439         } else
2440                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2441
2442         return 0;
2443 }
2444
2445 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2446 {
2447         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2448 }
2449
2450 static int
2451 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2452                             struct intel_ring_buffer *pipelined)
2453 {
2454         int ret;
2455
2456         if (obj->fenced_gpu_access) {
2457                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2458                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2459                                                   0, obj->base.write_domain);
2460                         if (ret)
2461                                 return ret;
2462                 }
2463
2464                 obj->fenced_gpu_access = false;
2465         }
2466
2467         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2468                 if (!ring_passed_seqno(obj->last_fenced_ring,
2469                                        obj->last_fenced_seqno)) {
2470                         ret = i915_wait_request(obj->last_fenced_ring,
2471                                                 obj->last_fenced_seqno);
2472                         if (ret)
2473                                 return ret;
2474                 }
2475
2476                 obj->last_fenced_seqno = 0;
2477                 obj->last_fenced_ring = NULL;
2478         }
2479
2480         /* Ensure that all CPU reads are completed before installing a fence
2481          * and all writes before removing the fence.
2482          */
2483         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2484                 mb();
2485
2486         return 0;
2487 }
2488
2489 int
2490 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2491 {
2492         int ret;
2493
2494         if (obj->tiling_mode)
2495                 i915_gem_release_mmap(obj);
2496
2497         ret = i915_gem_object_flush_fence(obj, NULL);
2498         if (ret)
2499                 return ret;
2500
2501         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2502                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2503                 i915_gem_clear_fence_reg(obj->base.dev,
2504                                          &dev_priv->fence_regs[obj->fence_reg]);
2505
2506                 obj->fence_reg = I915_FENCE_REG_NONE;
2507         }
2508
2509         return 0;
2510 }
2511
2512 static struct drm_i915_fence_reg *
2513 i915_find_fence_reg(struct drm_device *dev,
2514                     struct intel_ring_buffer *pipelined)
2515 {
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517         struct drm_i915_fence_reg *reg, *first, *avail;
2518         int i;
2519
2520         /* First try to find a free reg */
2521         avail = NULL;
2522         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2523                 reg = &dev_priv->fence_regs[i];
2524                 if (!reg->obj)
2525                         return reg;
2526
2527                 if (!reg->obj->pin_count)
2528                         avail = reg;
2529         }
2530
2531         if (avail == NULL)
2532                 return NULL;
2533
2534         /* None available, try to steal one or wait for a user to finish */
2535         avail = first = NULL;
2536         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2537                 if (reg->obj->pin_count)
2538                         continue;
2539
2540                 if (first == NULL)
2541                         first = reg;
2542
2543                 if (!pipelined ||
2544                     !reg->obj->last_fenced_ring ||
2545                     reg->obj->last_fenced_ring == pipelined) {
2546                         avail = reg;
2547                         break;
2548                 }
2549         }
2550
2551         if (avail == NULL)
2552                 avail = first;
2553
2554         return avail;
2555 }
2556
2557 /**
2558  * i915_gem_object_get_fence - set up a fence reg for an object
2559  * @obj: object to map through a fence reg
2560  * @pipelined: ring on which to queue the change, or NULL for CPU access
2561  * @interruptible: must we wait uninterruptibly for the register to retire?
2562  *
2563  * When mapping objects through the GTT, userspace wants to be able to write
2564  * to them without having to worry about swizzling if the object is tiled.
2565  *
2566  * This function walks the fence regs looking for a free one for @obj,
2567  * stealing one if it can't find any.
2568  *
2569  * It then sets up the reg based on the object's properties: address, pitch
2570  * and tiling format.
2571  */
2572 int
2573 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2574                           struct intel_ring_buffer *pipelined)
2575 {
2576         struct drm_device *dev = obj->base.dev;
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         struct drm_i915_fence_reg *reg;
2579         int ret;
2580
2581         /* XXX disable pipelining. There are bugs. Shocking. */
2582         pipelined = NULL;
2583
2584         /* Just update our place in the LRU if our fence is getting reused. */
2585         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2586                 reg = &dev_priv->fence_regs[obj->fence_reg];
2587                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2588
2589                 if (obj->tiling_changed) {
2590                         ret = i915_gem_object_flush_fence(obj, pipelined);
2591                         if (ret)
2592                                 return ret;
2593
2594                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2595                                 pipelined = NULL;
2596
2597                         if (pipelined) {
2598                                 reg->setup_seqno =
2599                                         i915_gem_next_request_seqno(pipelined);
2600                                 obj->last_fenced_seqno = reg->setup_seqno;
2601                                 obj->last_fenced_ring = pipelined;
2602                         }
2603
2604                         goto update;
2605                 }
2606
2607                 if (!pipelined) {
2608                         if (reg->setup_seqno) {
2609                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2610                                                        reg->setup_seqno)) {
2611                                         ret = i915_wait_request(obj->last_fenced_ring,
2612                                                                 reg->setup_seqno);
2613                                         if (ret)
2614                                                 return ret;
2615                                 }
2616
2617                                 reg->setup_seqno = 0;
2618                         }
2619                 } else if (obj->last_fenced_ring &&
2620                            obj->last_fenced_ring != pipelined) {
2621                         ret = i915_gem_object_flush_fence(obj, pipelined);
2622                         if (ret)
2623                                 return ret;
2624                 }
2625
2626                 return 0;
2627         }
2628
2629         reg = i915_find_fence_reg(dev, pipelined);
2630         if (reg == NULL)
2631                 return -ENOSPC;
2632
2633         ret = i915_gem_object_flush_fence(obj, pipelined);
2634         if (ret)
2635                 return ret;
2636
2637         if (reg->obj) {
2638                 struct drm_i915_gem_object *old = reg->obj;
2639
2640                 drm_gem_object_reference(&old->base);
2641
2642                 if (old->tiling_mode)
2643                         i915_gem_release_mmap(old);
2644
2645                 ret = i915_gem_object_flush_fence(old, pipelined);
2646                 if (ret) {
2647                         drm_gem_object_unreference(&old->base);
2648                         return ret;
2649                 }
2650
2651                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2652                         pipelined = NULL;
2653
2654                 old->fence_reg = I915_FENCE_REG_NONE;
2655                 old->last_fenced_ring = pipelined;
2656                 old->last_fenced_seqno =
2657                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2658
2659                 drm_gem_object_unreference(&old->base);
2660         } else if (obj->last_fenced_seqno == 0)
2661                 pipelined = NULL;
2662
2663         reg->obj = obj;
2664         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2665         obj->fence_reg = reg - dev_priv->fence_regs;
2666         obj->last_fenced_ring = pipelined;
2667
2668         reg->setup_seqno =
2669                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2670         obj->last_fenced_seqno = reg->setup_seqno;
2671
2672 update:
2673         obj->tiling_changed = false;
2674         switch (INTEL_INFO(dev)->gen) {
2675         case 6:
2676                 ret = sandybridge_write_fence_reg(obj, pipelined);
2677                 break;
2678         case 5:
2679         case 4:
2680                 ret = i965_write_fence_reg(obj, pipelined);
2681                 break;
2682         case 3:
2683                 ret = i915_write_fence_reg(obj, pipelined);
2684                 break;
2685         case 2:
2686                 ret = i830_write_fence_reg(obj, pipelined);
2687                 break;
2688         }
2689
2690         return ret;
2691 }
2692
2693 /**
2694  * i915_gem_clear_fence_reg - clear out fence register info
2695  * @obj: object to clear
2696  *
2697  * Zeroes out the fence register itself and clears out the associated
2698  * data structures in dev_priv and obj.
2699  */
2700 static void
2701 i915_gem_clear_fence_reg(struct drm_device *dev,
2702                          struct drm_i915_fence_reg *reg)
2703 {
2704         drm_i915_private_t *dev_priv = dev->dev_private;
2705         uint32_t fence_reg = reg - dev_priv->fence_regs;
2706
2707         switch (INTEL_INFO(dev)->gen) {
2708         case 6:
2709                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2710                 break;
2711         case 5:
2712         case 4:
2713                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2714                 break;
2715         case 3:
2716                 if (fence_reg >= 8)
2717                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2718                 else
2719         case 2:
2720                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2721
2722                 I915_WRITE(fence_reg, 0);
2723                 break;
2724         }
2725
2726         list_del_init(&reg->lru_list);
2727         reg->obj = NULL;
2728         reg->setup_seqno = 0;
2729 }
2730
2731 /**
2732  * Finds free space in the GTT aperture and binds the object there.
2733  */
2734 static int
2735 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2736                             unsigned alignment,
2737                             bool map_and_fenceable)
2738 {
2739         struct drm_device *dev = obj->base.dev;
2740         drm_i915_private_t *dev_priv = dev->dev_private;
2741         struct drm_mm_node *free_space;
2742         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2743         u32 size, fence_size, fence_alignment, unfenced_alignment;
2744         bool mappable, fenceable;
2745         int ret;
2746
2747         if (obj->madv != I915_MADV_WILLNEED) {
2748                 DRM_ERROR("Attempting to bind a purgeable object\n");
2749                 return -EINVAL;
2750         }
2751
2752         fence_size = i915_gem_get_gtt_size(obj);
2753         fence_alignment = i915_gem_get_gtt_alignment(obj);
2754         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2755
2756         if (alignment == 0)
2757                 alignment = map_and_fenceable ? fence_alignment :
2758                                                 unfenced_alignment;
2759         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2760                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2761                 return -EINVAL;
2762         }
2763
2764         size = map_and_fenceable ? fence_size : obj->base.size;
2765
2766         /* If the object is bigger than the entire aperture, reject it early
2767          * before evicting everything in a vain attempt to find space.
2768          */
2769         if (obj->base.size >
2770             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2771                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2772                 return -E2BIG;
2773         }
2774
2775  search_free:
2776         if (map_and_fenceable)
2777                 free_space =
2778                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2779                                                     size, alignment, 0,
2780                                                     dev_priv->mm.gtt_mappable_end,
2781                                                     0);
2782         else
2783                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2784                                                 size, alignment, 0);
2785
2786         if (free_space != NULL) {
2787                 if (map_and_fenceable)
2788                         obj->gtt_space =
2789                                 drm_mm_get_block_range_generic(free_space,
2790                                                                size, alignment, 0,
2791                                                                dev_priv->mm.gtt_mappable_end,
2792                                                                0);
2793                 else
2794                         obj->gtt_space =
2795                                 drm_mm_get_block(free_space, size, alignment);
2796         }
2797         if (obj->gtt_space == NULL) {
2798                 /* If the gtt is empty and we're still having trouble
2799                  * fitting our object in, we're out of memory.
2800                  */
2801                 ret = i915_gem_evict_something(dev, size, alignment,
2802                                                map_and_fenceable);
2803                 if (ret)
2804                         return ret;
2805
2806                 goto search_free;
2807         }
2808
2809         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2810         if (ret) {
2811                 drm_mm_put_block(obj->gtt_space);
2812                 obj->gtt_space = NULL;
2813
2814                 if (ret == -ENOMEM) {
2815                         /* first try to reclaim some memory by clearing the GTT */
2816                         ret = i915_gem_evict_everything(dev, false);
2817                         if (ret) {
2818                                 /* now try to shrink everyone else */
2819                                 if (gfpmask) {
2820                                         gfpmask = 0;
2821                                         goto search_free;
2822                                 }
2823
2824                                 return -ENOMEM;
2825                         }
2826
2827                         goto search_free;
2828                 }
2829
2830                 return ret;
2831         }
2832
2833         ret = i915_gem_gtt_bind_object(obj);
2834         if (ret) {
2835                 i915_gem_object_put_pages_gtt(obj);
2836                 drm_mm_put_block(obj->gtt_space);
2837                 obj->gtt_space = NULL;
2838
2839                 if (i915_gem_evict_everything(dev, false))
2840                         return ret;
2841
2842                 goto search_free;
2843         }
2844
2845         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2846         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2847
2848         /* Assert that the object is not currently in any GPU domain. As it
2849          * wasn't in the GTT, there shouldn't be any way it could have been in
2850          * a GPU cache
2851          */
2852         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2853         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2854
2855         obj->gtt_offset = obj->gtt_space->start;
2856
2857         fenceable =
2858                 obj->gtt_space->size == fence_size &&
2859                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2860
2861         mappable =
2862                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2863
2864         obj->map_and_fenceable = mappable && fenceable;
2865
2866         trace_i915_gem_object_bind(obj, map_and_fenceable);
2867         return 0;
2868 }
2869
2870 void
2871 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2872 {
2873         /* If we don't have a page list set up, then we're not pinned
2874          * to GPU, and we can ignore the cache flush because it'll happen
2875          * again at bind time.
2876          */
2877         if (obj->pages == NULL)
2878                 return;
2879
2880         trace_i915_gem_object_clflush(obj);
2881
2882         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2883 }
2884
2885 /** Flushes any GPU write domain for the object if it's dirty. */
2886 static int
2887 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2888 {
2889         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2890                 return 0;
2891
2892         /* Queue the GPU write cache flushing we need. */
2893         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2894 }
2895
2896 /** Flushes the GTT write domain for the object if it's dirty. */
2897 static void
2898 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2899 {
2900         uint32_t old_write_domain;
2901
2902         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2903                 return;
2904
2905         /* No actual flushing is required for the GTT write domain.  Writes
2906          * to it immediately go to main memory as far as we know, so there's
2907          * no chipset flush.  It also doesn't land in render cache.
2908          *
2909          * However, we do have to enforce the order so that all writes through
2910          * the GTT land before any writes to the device, such as updates to
2911          * the GATT itself.
2912          */
2913         wmb();
2914
2915         i915_gem_release_mmap(obj);
2916
2917         old_write_domain = obj->base.write_domain;
2918         obj->base.write_domain = 0;
2919
2920         trace_i915_gem_object_change_domain(obj,
2921                                             obj->base.read_domains,
2922                                             old_write_domain);
2923 }
2924
2925 /** Flushes the CPU write domain for the object if it's dirty. */
2926 static void
2927 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2928 {
2929         uint32_t old_write_domain;
2930
2931         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2932                 return;
2933
2934         i915_gem_clflush_object(obj);
2935         intel_gtt_chipset_flush();
2936         old_write_domain = obj->base.write_domain;
2937         obj->base.write_domain = 0;
2938
2939         trace_i915_gem_object_change_domain(obj,
2940                                             obj->base.read_domains,
2941                                             old_write_domain);
2942 }
2943
2944 /**
2945  * Moves a single object to the GTT read, and possibly write domain.
2946  *
2947  * This function returns when the move is complete, including waiting on
2948  * flushes to occur.
2949  */
2950 int
2951 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2952 {
2953         uint32_t old_write_domain, old_read_domains;
2954         int ret;
2955
2956         /* Not valid to be called on unbound objects. */
2957         if (obj->gtt_space == NULL)
2958                 return -EINVAL;
2959
2960         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2961                 return 0;
2962
2963         ret = i915_gem_object_flush_gpu_write_domain(obj);
2964         if (ret)
2965                 return ret;
2966
2967         if (obj->pending_gpu_write || write) {
2968                 ret = i915_gem_object_wait_rendering(obj);
2969                 if (ret)
2970                         return ret;
2971         }
2972
2973         i915_gem_object_flush_cpu_write_domain(obj);
2974
2975         old_write_domain = obj->base.write_domain;
2976         old_read_domains = obj->base.read_domains;
2977
2978         /* It should now be out of any other write domains, and we can update
2979          * the domain values for our changes.
2980          */
2981         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2982         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2983         if (write) {
2984                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2985                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2986                 obj->dirty = 1;
2987         }
2988
2989         trace_i915_gem_object_change_domain(obj,
2990                                             old_read_domains,
2991                                             old_write_domain);
2992
2993         return 0;
2994 }
2995
2996 /*
2997  * Prepare buffer for display plane. Use uninterruptible for possible flush
2998  * wait, as in modesetting process we're not supposed to be interrupted.
2999  */
3000 int
3001 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
3002                                      struct intel_ring_buffer *pipelined)
3003 {
3004         uint32_t old_read_domains;
3005         int ret;
3006
3007         /* Not valid to be called on unbound objects. */
3008         if (obj->gtt_space == NULL)
3009                 return -EINVAL;
3010
3011         ret = i915_gem_object_flush_gpu_write_domain(obj);
3012         if (ret)
3013                 return ret;
3014
3015
3016         /* Currently, we are always called from an non-interruptible context. */
3017         if (pipelined != obj->ring) {
3018                 ret = i915_gem_object_wait_rendering(obj);
3019                 if (ret)
3020                         return ret;
3021         }
3022
3023         i915_gem_object_flush_cpu_write_domain(obj);
3024
3025         old_read_domains = obj->base.read_domains;
3026         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3027
3028         trace_i915_gem_object_change_domain(obj,
3029                                             old_read_domains,
3030                                             obj->base.write_domain);
3031
3032         return 0;
3033 }
3034
3035 int
3036 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
3037 {
3038         int ret;
3039
3040         if (!obj->active)
3041                 return 0;
3042
3043         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3044                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3045                 if (ret)
3046                         return ret;
3047         }
3048
3049         return i915_gem_object_wait_rendering(obj);
3050 }
3051
3052 /**
3053  * Moves a single object to the CPU read, and possibly write domain.
3054  *
3055  * This function returns when the move is complete, including waiting on
3056  * flushes to occur.
3057  */
3058 static int
3059 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3060 {
3061         uint32_t old_write_domain, old_read_domains;
3062         int ret;
3063
3064         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3065                 return 0;
3066
3067         ret = i915_gem_object_flush_gpu_write_domain(obj);
3068         if (ret)
3069                 return ret;
3070
3071         ret = i915_gem_object_wait_rendering(obj);
3072         if (ret)
3073                 return ret;
3074
3075         i915_gem_object_flush_gtt_write_domain(obj);
3076
3077         /* If we have a partially-valid cache of the object in the CPU,
3078          * finish invalidating it and free the per-page flags.
3079          */
3080         i915_gem_object_set_to_full_cpu_read_domain(obj);
3081
3082         old_write_domain = obj->base.write_domain;
3083         old_read_domains = obj->base.read_domains;
3084
3085         /* Flush the CPU cache if it's still invalid. */
3086         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3087                 i915_gem_clflush_object(obj);
3088
3089                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3090         }
3091
3092         /* It should now be out of any other write domains, and we can update
3093          * the domain values for our changes.
3094          */
3095         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3096
3097         /* If we're writing through the CPU, then the GPU read domains will
3098          * need to be invalidated at next use.
3099          */
3100         if (write) {
3101                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3102                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3103         }
3104
3105         trace_i915_gem_object_change_domain(obj,
3106                                             old_read_domains,
3107                                             old_write_domain);
3108
3109         return 0;
3110 }
3111
3112 /**
3113  * Moves the object from a partially CPU read to a full one.
3114  *
3115  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3116  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3117  */
3118 static void
3119 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3120 {
3121         if (!obj->page_cpu_valid)
3122                 return;
3123
3124         /* If we're partially in the CPU read domain, finish moving it in.
3125          */
3126         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3127                 int i;
3128
3129                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3130                         if (obj->page_cpu_valid[i])
3131                                 continue;
3132                         drm_clflush_pages(obj->pages + i, 1);
3133                 }
3134         }
3135
3136         /* Free the page_cpu_valid mappings which are now stale, whether
3137          * or not we've got I915_GEM_DOMAIN_CPU.
3138          */
3139         kfree(obj->page_cpu_valid);
3140         obj->page_cpu_valid = NULL;
3141 }
3142
3143 /**
3144  * Set the CPU read domain on a range of the object.
3145  *
3146  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3147  * not entirely valid.  The page_cpu_valid member of the object flags which
3148  * pages have been flushed, and will be respected by
3149  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3150  * of the whole object.
3151  *
3152  * This function returns when the move is complete, including waiting on
3153  * flushes to occur.
3154  */
3155 static int
3156 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3157                                           uint64_t offset, uint64_t size)
3158 {
3159         uint32_t old_read_domains;
3160         int i, ret;
3161
3162         if (offset == 0 && size == obj->base.size)
3163                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3164
3165         ret = i915_gem_object_flush_gpu_write_domain(obj);
3166         if (ret)
3167                 return ret;
3168
3169         ret = i915_gem_object_wait_rendering(obj);
3170         if (ret)
3171                 return ret;
3172
3173         i915_gem_object_flush_gtt_write_domain(obj);
3174
3175         /* If we're already fully in the CPU read domain, we're done. */
3176         if (obj->page_cpu_valid == NULL &&
3177             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3178                 return 0;
3179
3180         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3181          * newly adding I915_GEM_DOMAIN_CPU
3182          */
3183         if (obj->page_cpu_valid == NULL) {
3184                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3185                                               GFP_KERNEL);
3186                 if (obj->page_cpu_valid == NULL)
3187                         return -ENOMEM;
3188         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3189                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3190
3191         /* Flush the cache on any pages that are still invalid from the CPU's
3192          * perspective.
3193          */
3194         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3195              i++) {
3196                 if (obj->page_cpu_valid[i])
3197                         continue;
3198
3199                 drm_clflush_pages(obj->pages + i, 1);
3200
3201                 obj->page_cpu_valid[i] = 1;
3202         }
3203
3204         /* It should now be out of any other write domains, and we can update
3205          * the domain values for our changes.
3206          */
3207         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3208
3209         old_read_domains = obj->base.read_domains;
3210         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3211
3212         trace_i915_gem_object_change_domain(obj,
3213                                             old_read_domains,
3214                                             obj->base.write_domain);
3215
3216         return 0;
3217 }
3218
3219 /* Throttle our rendering by waiting until the ring has completed our requests
3220  * emitted over 20 msec ago.
3221  *
3222  * Note that if we were to use the current jiffies each time around the loop,
3223  * we wouldn't escape the function with any frames outstanding if the time to
3224  * render a frame was over 20ms.
3225  *
3226  * This should get us reasonable parallelism between CPU and GPU but also
3227  * relatively low latency when blocking on a particular request to finish.
3228  */
3229 static int
3230 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3231 {
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233         struct drm_i915_file_private *file_priv = file->driver_priv;
3234         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3235         struct drm_i915_gem_request *request;
3236         struct intel_ring_buffer *ring = NULL;
3237         u32 seqno = 0;
3238         int ret;
3239
3240         if (atomic_read(&dev_priv->mm.wedged))
3241                 return -EIO;
3242
3243         spin_lock(&file_priv->mm.lock);
3244         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3245                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3246                         break;
3247
3248                 ring = request->ring;
3249                 seqno = request->seqno;
3250         }
3251         spin_unlock(&file_priv->mm.lock);
3252
3253         if (seqno == 0)
3254                 return 0;
3255
3256         ret = 0;
3257         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3258                 /* And wait for the seqno passing without holding any locks and
3259                  * causing extra latency for others. This is safe as the irq
3260                  * generation is designed to be run atomically and so is
3261                  * lockless.
3262                  */
3263                 if (ring->irq_get(ring)) {
3264                         ret = wait_event_interruptible(ring->irq_queue,
3265                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3266                                                        || atomic_read(&dev_priv->mm.wedged));
3267                         ring->irq_put(ring);
3268
3269                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3270                                 ret = -EIO;
3271                 }
3272         }
3273
3274         if (ret == 0)
3275                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3276
3277         return ret;
3278 }
3279
3280 int
3281 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3282                     uint32_t alignment,
3283                     bool map_and_fenceable)
3284 {
3285         struct drm_device *dev = obj->base.dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         int ret;
3288
3289         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3290         WARN_ON(i915_verify_lists(dev));
3291
3292         if (obj->gtt_space != NULL) {
3293                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3294                     (map_and_fenceable && !obj->map_and_fenceable)) {
3295                         WARN(obj->pin_count,
3296                              "bo is already pinned with incorrect alignment:"
3297                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3298                              " obj->map_and_fenceable=%d\n",
3299                              obj->gtt_offset, alignment,
3300                              map_and_fenceable,
3301                              obj->map_and_fenceable);
3302                         ret = i915_gem_object_unbind(obj);
3303                         if (ret)
3304                                 return ret;
3305                 }
3306         }
3307
3308         if (obj->gtt_space == NULL) {
3309                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3310                                                   map_and_fenceable);
3311                 if (ret)
3312                         return ret;
3313         }
3314
3315         if (obj->pin_count++ == 0) {
3316                 if (!obj->active)
3317                         list_move_tail(&obj->mm_list,
3318                                        &dev_priv->mm.pinned_list);
3319         }
3320         obj->pin_mappable |= map_and_fenceable;
3321
3322         WARN_ON(i915_verify_lists(dev));
3323         return 0;
3324 }
3325
3326 void
3327 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3328 {
3329         struct drm_device *dev = obj->base.dev;
3330         drm_i915_private_t *dev_priv = dev->dev_private;
3331
3332         WARN_ON(i915_verify_lists(dev));
3333         BUG_ON(obj->pin_count == 0);
3334         BUG_ON(obj->gtt_space == NULL);
3335
3336         if (--obj->pin_count == 0) {
3337                 if (!obj->active)
3338                         list_move_tail(&obj->mm_list,
3339                                        &dev_priv->mm.inactive_list);
3340                 obj->pin_mappable = false;
3341         }
3342         WARN_ON(i915_verify_lists(dev));
3343 }
3344
3345 int
3346 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3347                    struct drm_file *file)
3348 {
3349         struct drm_i915_gem_pin *args = data;
3350         struct drm_i915_gem_object *obj;
3351         int ret;
3352
3353         ret = i915_mutex_lock_interruptible(dev);
3354         if (ret)
3355                 return ret;
3356
3357         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3358         if (&obj->base == NULL) {
3359                 ret = -ENOENT;
3360                 goto unlock;
3361         }
3362
3363         if (obj->madv != I915_MADV_WILLNEED) {
3364                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3365                 ret = -EINVAL;
3366                 goto out;
3367         }
3368
3369         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3370                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3371                           args->handle);
3372                 ret = -EINVAL;
3373                 goto out;
3374         }
3375
3376         obj->user_pin_count++;
3377         obj->pin_filp = file;
3378         if (obj->user_pin_count == 1) {
3379                 ret = i915_gem_object_pin(obj, args->alignment, true);
3380                 if (ret)
3381                         goto out;
3382         }
3383
3384         /* XXX - flush the CPU caches for pinned objects
3385          * as the X server doesn't manage domains yet
3386          */
3387         i915_gem_object_flush_cpu_write_domain(obj);
3388         args->offset = obj->gtt_offset;
3389 out:
3390         drm_gem_object_unreference(&obj->base);
3391 unlock:
3392         mutex_unlock(&dev->struct_mutex);
3393         return ret;
3394 }
3395
3396 int
3397 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3398                      struct drm_file *file)
3399 {
3400         struct drm_i915_gem_pin *args = data;
3401         struct drm_i915_gem_object *obj;
3402         int ret;
3403
3404         ret = i915_mutex_lock_interruptible(dev);
3405         if (ret)
3406                 return ret;
3407
3408         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3409         if (&obj->base == NULL) {
3410                 ret = -ENOENT;
3411                 goto unlock;
3412         }
3413
3414         if (obj->pin_filp != file) {
3415                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3416                           args->handle);
3417                 ret = -EINVAL;
3418                 goto out;
3419         }
3420         obj->user_pin_count--;
3421         if (obj->user_pin_count == 0) {
3422                 obj->pin_filp = NULL;
3423                 i915_gem_object_unpin(obj);
3424         }
3425
3426 out:
3427         drm_gem_object_unreference(&obj->base);
3428 unlock:
3429         mutex_unlock(&dev->struct_mutex);
3430         return ret;
3431 }
3432
3433 int
3434 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3435                     struct drm_file *file)
3436 {
3437         struct drm_i915_gem_busy *args = data;
3438         struct drm_i915_gem_object *obj;
3439         int ret;
3440
3441         ret = i915_mutex_lock_interruptible(dev);
3442         if (ret)
3443                 return ret;
3444
3445         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3446         if (&obj->base == NULL) {
3447                 ret = -ENOENT;
3448                 goto unlock;
3449         }
3450
3451         /* Count all active objects as busy, even if they are currently not used
3452          * by the gpu. Users of this interface expect objects to eventually
3453          * become non-busy without any further actions, therefore emit any
3454          * necessary flushes here.
3455          */
3456         args->busy = obj->active;
3457         if (args->busy) {
3458                 /* Unconditionally flush objects, even when the gpu still uses this
3459                  * object. Userspace calling this function indicates that it wants to
3460                  * use this buffer rather sooner than later, so issuing the required
3461                  * flush earlier is beneficial.
3462                  */
3463                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3464                         ret = i915_gem_flush_ring(obj->ring,
3465                                                   0, obj->base.write_domain);
3466                 } else if (obj->ring->outstanding_lazy_request ==
3467                            obj->last_rendering_seqno) {
3468                         struct drm_i915_gem_request *request;
3469
3470                         /* This ring is not being cleared by active usage,
3471                          * so emit a request to do so.
3472                          */
3473                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3474                         if (request)
3475                                 ret = i915_add_request(obj->ring, NULL,request);
3476                         else
3477                                 ret = -ENOMEM;
3478                 }
3479
3480                 /* Update the active list for the hardware's current position.
3481                  * Otherwise this only updates on a delayed timer or when irqs
3482                  * are actually unmasked, and our working set ends up being
3483                  * larger than required.
3484                  */
3485                 i915_gem_retire_requests_ring(obj->ring);
3486
3487                 args->busy = obj->active;
3488         }
3489
3490         drm_gem_object_unreference(&obj->base);
3491 unlock:
3492         mutex_unlock(&dev->struct_mutex);
3493         return ret;
3494 }
3495
3496 int
3497 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3498                         struct drm_file *file_priv)
3499 {
3500     return i915_gem_ring_throttle(dev, file_priv);
3501 }
3502
3503 int
3504 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3505                        struct drm_file *file_priv)
3506 {
3507         struct drm_i915_gem_madvise *args = data;
3508         struct drm_i915_gem_object *obj;
3509         int ret;
3510
3511         switch (args->madv) {
3512         case I915_MADV_DONTNEED:
3513         case I915_MADV_WILLNEED:
3514             break;
3515         default:
3516             return -EINVAL;
3517         }
3518
3519         ret = i915_mutex_lock_interruptible(dev);
3520         if (ret)
3521                 return ret;
3522
3523         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3524         if (&obj->base == NULL) {
3525                 ret = -ENOENT;
3526                 goto unlock;
3527         }
3528
3529         if (obj->pin_count) {
3530                 ret = -EINVAL;
3531                 goto out;
3532         }
3533
3534         if (obj->madv != __I915_MADV_PURGED)
3535                 obj->madv = args->madv;
3536
3537         /* if the object is no longer bound, discard its backing storage */
3538         if (i915_gem_object_is_purgeable(obj) &&
3539             obj->gtt_space == NULL)
3540                 i915_gem_object_truncate(obj);
3541
3542         args->retained = obj->madv != __I915_MADV_PURGED;
3543
3544 out:
3545         drm_gem_object_unreference(&obj->base);
3546 unlock:
3547         mutex_unlock(&dev->struct_mutex);
3548         return ret;
3549 }
3550
3551 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3552                                                   size_t size)
3553 {
3554         struct drm_i915_private *dev_priv = dev->dev_private;
3555         struct drm_i915_gem_object *obj;
3556
3557         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3558         if (obj == NULL)
3559                 return NULL;
3560
3561         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3562                 kfree(obj);
3563                 return NULL;
3564         }
3565
3566         i915_gem_info_add_obj(dev_priv, size);
3567
3568         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3569         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3570
3571         obj->agp_type = AGP_USER_MEMORY;
3572         obj->base.driver_private = NULL;
3573         obj->fence_reg = I915_FENCE_REG_NONE;
3574         INIT_LIST_HEAD(&obj->mm_list);
3575         INIT_LIST_HEAD(&obj->gtt_list);
3576         INIT_LIST_HEAD(&obj->ring_list);
3577         INIT_LIST_HEAD(&obj->exec_list);
3578         INIT_LIST_HEAD(&obj->gpu_write_list);
3579         obj->madv = I915_MADV_WILLNEED;
3580         /* Avoid an unnecessary call to unbind on the first bind. */
3581         obj->map_and_fenceable = true;
3582
3583         return obj;
3584 }
3585
3586 int i915_gem_init_object(struct drm_gem_object *obj)
3587 {
3588         BUG();
3589
3590         return 0;
3591 }
3592
3593 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3594 {
3595         struct drm_device *dev = obj->base.dev;
3596         drm_i915_private_t *dev_priv = dev->dev_private;
3597         int ret;
3598
3599         ret = i915_gem_object_unbind(obj);
3600         if (ret == -ERESTARTSYS) {
3601                 list_move(&obj->mm_list,
3602                           &dev_priv->mm.deferred_free_list);
3603                 return;
3604         }
3605
3606         if (obj->base.map_list.map)
3607                 i915_gem_free_mmap_offset(obj);
3608
3609         drm_gem_object_release(&obj->base);
3610         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3611
3612         kfree(obj->page_cpu_valid);
3613         kfree(obj->bit_17);
3614         kfree(obj);
3615
3616         trace_i915_gem_object_destroy(obj);
3617 }
3618
3619 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3620 {
3621         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3622         struct drm_device *dev = obj->base.dev;
3623
3624         while (obj->pin_count > 0)
3625                 i915_gem_object_unpin(obj);
3626
3627         if (obj->phys_obj)
3628                 i915_gem_detach_phys_object(dev, obj);
3629
3630         i915_gem_free_object_tail(obj);
3631 }
3632
3633 int
3634 i915_gem_idle(struct drm_device *dev)
3635 {
3636         drm_i915_private_t *dev_priv = dev->dev_private;
3637         int ret;
3638
3639         mutex_lock(&dev->struct_mutex);
3640
3641         if (dev_priv->mm.suspended) {
3642                 mutex_unlock(&dev->struct_mutex);
3643                 return 0;
3644         }
3645
3646         ret = i915_gpu_idle(dev);
3647         if (ret) {
3648                 mutex_unlock(&dev->struct_mutex);
3649                 return ret;
3650         }
3651
3652         /* Under UMS, be paranoid and evict. */
3653         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3654                 ret = i915_gem_evict_inactive(dev, false);
3655                 if (ret) {
3656                         mutex_unlock(&dev->struct_mutex);
3657                         return ret;
3658                 }
3659         }
3660
3661         i915_gem_reset_fences(dev);
3662
3663         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3664          * We need to replace this with a semaphore, or something.
3665          * And not confound mm.suspended!
3666          */
3667         dev_priv->mm.suspended = 1;
3668         del_timer_sync(&dev_priv->hangcheck_timer);
3669
3670         i915_kernel_lost_context(dev);
3671         i915_gem_cleanup_ringbuffer(dev);
3672
3673         mutex_unlock(&dev->struct_mutex);
3674
3675         /* Cancel the retire work handler, which should be idle now. */
3676         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3677
3678         return 0;
3679 }
3680
3681 int
3682 i915_gem_init_ringbuffer(struct drm_device *dev)
3683 {
3684         drm_i915_private_t *dev_priv = dev->dev_private;
3685         int ret;
3686
3687         ret = intel_init_render_ring_buffer(dev);
3688         if (ret)
3689                 return ret;
3690
3691         if (HAS_BSD(dev)) {
3692                 ret = intel_init_bsd_ring_buffer(dev);
3693                 if (ret)
3694                         goto cleanup_render_ring;
3695         }
3696
3697         if (HAS_BLT(dev)) {
3698                 ret = intel_init_blt_ring_buffer(dev);
3699                 if (ret)
3700                         goto cleanup_bsd_ring;
3701         }
3702
3703         dev_priv->next_seqno = 1;
3704
3705         return 0;
3706
3707 cleanup_bsd_ring:
3708         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3709 cleanup_render_ring:
3710         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3711         return ret;
3712 }
3713
3714 void
3715 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3716 {
3717         drm_i915_private_t *dev_priv = dev->dev_private;
3718         int i;
3719
3720         for (i = 0; i < I915_NUM_RINGS; i++)
3721                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3722 }
3723
3724 int
3725 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3726                        struct drm_file *file_priv)
3727 {
3728         drm_i915_private_t *dev_priv = dev->dev_private;
3729         int ret, i;
3730
3731         if (drm_core_check_feature(dev, DRIVER_MODESET))
3732                 return 0;
3733
3734         if (atomic_read(&dev_priv->mm.wedged)) {
3735                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3736                 atomic_set(&dev_priv->mm.wedged, 0);
3737         }
3738
3739         mutex_lock(&dev->struct_mutex);
3740         dev_priv->mm.suspended = 0;
3741
3742         ret = i915_gem_init_ringbuffer(dev);
3743         if (ret != 0) {
3744                 mutex_unlock(&dev->struct_mutex);
3745                 return ret;
3746         }
3747
3748         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3749         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3750         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3751         for (i = 0; i < I915_NUM_RINGS; i++) {
3752                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3753                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3754         }
3755         mutex_unlock(&dev->struct_mutex);
3756
3757         ret = drm_irq_install(dev);
3758         if (ret)
3759                 goto cleanup_ringbuffer;
3760
3761         return 0;
3762
3763 cleanup_ringbuffer:
3764         mutex_lock(&dev->struct_mutex);
3765         i915_gem_cleanup_ringbuffer(dev);
3766         dev_priv->mm.suspended = 1;
3767         mutex_unlock(&dev->struct_mutex);
3768
3769         return ret;
3770 }
3771
3772 int
3773 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3774                        struct drm_file *file_priv)
3775 {
3776         if (drm_core_check_feature(dev, DRIVER_MODESET))
3777                 return 0;
3778
3779         drm_irq_uninstall(dev);
3780         return i915_gem_idle(dev);
3781 }
3782
3783 void
3784 i915_gem_lastclose(struct drm_device *dev)
3785 {
3786         int ret;
3787
3788         if (drm_core_check_feature(dev, DRIVER_MODESET))
3789                 return;
3790
3791         ret = i915_gem_idle(dev);
3792         if (ret)
3793                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3794 }
3795
3796 static void
3797 init_ring_lists(struct intel_ring_buffer *ring)
3798 {
3799         INIT_LIST_HEAD(&ring->active_list);
3800         INIT_LIST_HEAD(&ring->request_list);
3801         INIT_LIST_HEAD(&ring->gpu_write_list);
3802 }
3803
3804 void
3805 i915_gem_load(struct drm_device *dev)
3806 {
3807         int i;
3808         drm_i915_private_t *dev_priv = dev->dev_private;
3809
3810         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3811         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3812         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3813         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3814         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3815         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3816         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3817         for (i = 0; i < I915_NUM_RINGS; i++)
3818                 init_ring_lists(&dev_priv->ring[i]);
3819         for (i = 0; i < 16; i++)
3820                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3821         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3822                           i915_gem_retire_work_handler);
3823         init_completion(&dev_priv->error_completion);
3824
3825         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3826         if (IS_GEN3(dev)) {
3827                 u32 tmp = I915_READ(MI_ARB_STATE);
3828                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3829                         /* arb state is a masked write, so set bit + bit in mask */
3830                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3831                         I915_WRITE(MI_ARB_STATE, tmp);
3832                 }
3833         }
3834
3835         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3836
3837         /* Old X drivers will take 0-2 for front, back, depth buffers */
3838         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3839                 dev_priv->fence_reg_start = 3;
3840
3841         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3842                 dev_priv->num_fence_regs = 16;
3843         else
3844                 dev_priv->num_fence_regs = 8;
3845
3846         /* Initialize fence registers to zero */
3847         switch (INTEL_INFO(dev)->gen) {
3848         case 6:
3849                 for (i = 0; i < 16; i++)
3850                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3851                 break;
3852         case 5:
3853         case 4:
3854                 for (i = 0; i < 16; i++)
3855                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3856                 break;
3857         case 3:
3858                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3859                         for (i = 0; i < 8; i++)
3860                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3861         case 2:
3862                 for (i = 0; i < 8; i++)
3863                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3864                 break;
3865         }
3866         i915_gem_detect_bit_6_swizzle(dev);
3867         init_waitqueue_head(&dev_priv->pending_flip_queue);
3868
3869         dev_priv->mm.interruptible = true;
3870
3871         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3872         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3873         register_shrinker(&dev_priv->mm.inactive_shrinker);
3874 }
3875
3876 /*
3877  * Create a physically contiguous memory object for this object
3878  * e.g. for cursor + overlay regs
3879  */
3880 static int i915_gem_init_phys_object(struct drm_device *dev,
3881                                      int id, int size, int align)
3882 {
3883         drm_i915_private_t *dev_priv = dev->dev_private;
3884         struct drm_i915_gem_phys_object *phys_obj;
3885         int ret;
3886
3887         if (dev_priv->mm.phys_objs[id - 1] || !size)
3888                 return 0;
3889
3890         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3891         if (!phys_obj)
3892                 return -ENOMEM;
3893
3894         phys_obj->id = id;
3895
3896         phys_obj->handle = drm_pci_alloc(dev, size, align);
3897         if (!phys_obj->handle) {
3898                 ret = -ENOMEM;
3899                 goto kfree_obj;
3900         }
3901 #ifdef CONFIG_X86
3902         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3903 #endif
3904
3905         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3906
3907         return 0;
3908 kfree_obj:
3909         kfree(phys_obj);
3910         return ret;
3911 }
3912
3913 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3914 {
3915         drm_i915_private_t *dev_priv = dev->dev_private;
3916         struct drm_i915_gem_phys_object *phys_obj;
3917
3918         if (!dev_priv->mm.phys_objs[id - 1])
3919                 return;
3920
3921         phys_obj = dev_priv->mm.phys_objs[id - 1];
3922         if (phys_obj->cur_obj) {
3923                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3924         }
3925
3926 #ifdef CONFIG_X86
3927         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3928 #endif
3929         drm_pci_free(dev, phys_obj->handle);
3930         kfree(phys_obj);
3931         dev_priv->mm.phys_objs[id - 1] = NULL;
3932 }
3933
3934 void i915_gem_free_all_phys_object(struct drm_device *dev)
3935 {
3936         int i;
3937
3938         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3939                 i915_gem_free_phys_object(dev, i);
3940 }
3941
3942 void i915_gem_detach_phys_object(struct drm_device *dev,
3943                                  struct drm_i915_gem_object *obj)
3944 {
3945         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3946         char *vaddr;
3947         int i;
3948         int page_count;
3949
3950         if (!obj->phys_obj)
3951                 return;
3952         vaddr = obj->phys_obj->handle->vaddr;
3953
3954         page_count = obj->base.size / PAGE_SIZE;
3955         for (i = 0; i < page_count; i++) {
3956                 struct page *page = read_cache_page_gfp(mapping, i,
3957                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3958                 if (!IS_ERR(page)) {
3959                         char *dst = kmap_atomic(page);
3960                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3961                         kunmap_atomic(dst);
3962
3963                         drm_clflush_pages(&page, 1);
3964
3965                         set_page_dirty(page);
3966                         mark_page_accessed(page);
3967                         page_cache_release(page);
3968                 }
3969         }
3970         intel_gtt_chipset_flush();
3971
3972         obj->phys_obj->cur_obj = NULL;
3973         obj->phys_obj = NULL;
3974 }
3975
3976 int
3977 i915_gem_attach_phys_object(struct drm_device *dev,
3978                             struct drm_i915_gem_object *obj,
3979                             int id,
3980                             int align)
3981 {
3982         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3983         drm_i915_private_t *dev_priv = dev->dev_private;
3984         int ret = 0;
3985         int page_count;
3986         int i;
3987
3988         if (id > I915_MAX_PHYS_OBJECT)
3989                 return -EINVAL;
3990
3991         if (obj->phys_obj) {
3992                 if (obj->phys_obj->id == id)
3993                         return 0;
3994                 i915_gem_detach_phys_object(dev, obj);
3995         }
3996
3997         /* create a new object */
3998         if (!dev_priv->mm.phys_objs[id - 1]) {
3999                 ret = i915_gem_init_phys_object(dev, id,
4000                                                 obj->base.size, align);
4001                 if (ret) {
4002                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4003                                   id, obj->base.size);
4004                         return ret;
4005                 }
4006         }
4007
4008         /* bind to the object */
4009         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4010         obj->phys_obj->cur_obj = obj;
4011
4012         page_count = obj->base.size / PAGE_SIZE;
4013
4014         for (i = 0; i < page_count; i++) {
4015                 struct page *page;
4016                 char *dst, *src;
4017
4018                 page = read_cache_page_gfp(mapping, i,
4019                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
4020                 if (IS_ERR(page))
4021                         return PTR_ERR(page);
4022
4023                 src = kmap_atomic(page);
4024                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4025                 memcpy(dst, src, PAGE_SIZE);
4026                 kunmap_atomic(src);
4027
4028                 mark_page_accessed(page);
4029                 page_cache_release(page);
4030         }
4031
4032         return 0;
4033 }
4034
4035 static int
4036 i915_gem_phys_pwrite(struct drm_device *dev,
4037                      struct drm_i915_gem_object *obj,
4038                      struct drm_i915_gem_pwrite *args,
4039                      struct drm_file *file_priv)
4040 {
4041         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4042         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4043
4044         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4045                 unsigned long unwritten;
4046
4047                 /* The physical object once assigned is fixed for the lifetime
4048                  * of the obj, so we can safely drop the lock and continue
4049                  * to access vaddr.
4050                  */
4051                 mutex_unlock(&dev->struct_mutex);
4052                 unwritten = copy_from_user(vaddr, user_data, args->size);
4053                 mutex_lock(&dev->struct_mutex);
4054                 if (unwritten)
4055                         return -EFAULT;
4056         }
4057
4058         intel_gtt_chipset_flush();
4059         return 0;
4060 }
4061
4062 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4063 {
4064         struct drm_i915_file_private *file_priv = file->driver_priv;
4065
4066         /* Clean up our request list when the client is going away, so that
4067          * later retire_requests won't dereference our soon-to-be-gone
4068          * file_priv.
4069          */
4070         spin_lock(&file_priv->mm.lock);
4071         while (!list_empty(&file_priv->mm.request_list)) {
4072                 struct drm_i915_gem_request *request;
4073
4074                 request = list_first_entry(&file_priv->mm.request_list,
4075                                            struct drm_i915_gem_request,
4076                                            client_list);
4077                 list_del(&request->client_list);
4078                 request->file_priv = NULL;
4079         }
4080         spin_unlock(&file_priv->mm.lock);
4081 }
4082
4083 static int
4084 i915_gpu_is_active(struct drm_device *dev)
4085 {
4086         drm_i915_private_t *dev_priv = dev->dev_private;
4087         int lists_empty;
4088
4089         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4090                       list_empty(&dev_priv->mm.active_list);
4091
4092         return !lists_empty;
4093 }
4094
4095 static int
4096 i915_gem_inactive_shrink(struct shrinker *shrinker,
4097                          int nr_to_scan,
4098                          gfp_t gfp_mask)
4099 {
4100         struct drm_i915_private *dev_priv =
4101                 container_of(shrinker,
4102                              struct drm_i915_private,
4103                              mm.inactive_shrinker);
4104         struct drm_device *dev = dev_priv->dev;
4105         struct drm_i915_gem_object *obj, *next;
4106         int cnt;
4107
4108         if (!mutex_trylock(&dev->struct_mutex))
4109                 return 0;
4110
4111         /* "fast-path" to count number of available objects */
4112         if (nr_to_scan == 0) {
4113                 cnt = 0;
4114                 list_for_each_entry(obj,
4115                                     &dev_priv->mm.inactive_list,
4116                                     mm_list)
4117                         cnt++;
4118                 mutex_unlock(&dev->struct_mutex);
4119                 return cnt / 100 * sysctl_vfs_cache_pressure;
4120         }
4121
4122 rescan:
4123         /* first scan for clean buffers */
4124         i915_gem_retire_requests(dev);
4125
4126         list_for_each_entry_safe(obj, next,
4127                                  &dev_priv->mm.inactive_list,
4128                                  mm_list) {
4129                 if (i915_gem_object_is_purgeable(obj)) {
4130                         if (i915_gem_object_unbind(obj) == 0 &&
4131                             --nr_to_scan == 0)
4132                                 break;
4133                 }
4134         }
4135
4136         /* second pass, evict/count anything still on the inactive list */
4137         cnt = 0;
4138         list_for_each_entry_safe(obj, next,
4139                                  &dev_priv->mm.inactive_list,
4140                                  mm_list) {
4141                 if (nr_to_scan &&
4142                     i915_gem_object_unbind(obj) == 0)
4143                         nr_to_scan--;
4144                 else
4145                         cnt++;
4146         }
4147
4148         if (nr_to_scan && i915_gpu_is_active(dev)) {
4149                 /*
4150                  * We are desperate for pages, so as a last resort, wait
4151                  * for the GPU to finish and discard whatever we can.
4152                  * This has a dramatic impact to reduce the number of
4153                  * OOM-killer events whilst running the GPU aggressively.
4154                  */
4155                 if (i915_gpu_idle(dev) == 0)
4156                         goto rescan;
4157         }
4158         mutex_unlock(&dev->struct_mutex);
4159         return cnt / 100 * sysctl_vfs_cache_pressure;
4160 }