2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
47 i915_gem_object_retire(struct drm_i915_gem_object *obj);
49 static int i915_gem_phys_pwrite(struct drm_device *dev,
50 struct drm_i915_gem_object *obj,
51 struct drm_i915_gem_pwrite *args,
52 struct drm_file *file);
54 static void i915_gem_write_fence(struct drm_device *dev, int reg,
55 struct drm_i915_gem_object *obj);
56 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
57 struct drm_i915_fence_reg *fence,
60 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
61 struct shrink_control *sc);
62 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
63 struct shrink_control *sc);
64 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
65 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
66 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
68 static bool cpu_cache_is_coherent(struct drm_device *dev,
69 enum i915_cache_level level)
71 return HAS_LLC(dev) || level != I915_CACHE_NONE;
74 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
76 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
79 return obj->pin_display;
82 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
85 i915_gem_release_mmap(obj);
87 /* As we do not have an associated fence register, we will force
88 * a tiling change if we ever need to acquire one.
90 obj->fence_dirty = false;
91 obj->fence_reg = I915_FENCE_REG_NONE;
94 /* some bookkeeping */
95 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
98 spin_lock(&dev_priv->mm.object_stat_lock);
99 dev_priv->mm.object_count++;
100 dev_priv->mm.object_memory += size;
101 spin_unlock(&dev_priv->mm.object_stat_lock);
104 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
107 spin_lock(&dev_priv->mm.object_stat_lock);
108 dev_priv->mm.object_count--;
109 dev_priv->mm.object_memory -= size;
110 spin_unlock(&dev_priv->mm.object_stat_lock);
114 i915_gem_wait_for_error(struct i915_gpu_error *error)
118 #define EXIT_COND (!i915_reset_in_progress(error) || \
119 i915_terminally_wedged(error))
124 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
125 * userspace. If it takes that long something really bad is going on and
126 * we should simply try to bail out and fail as gracefully as possible.
128 ret = wait_event_interruptible_timeout(error->reset_queue,
132 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
134 } else if (ret < 0) {
142 int i915_mutex_lock_interruptible(struct drm_device *dev)
144 struct drm_i915_private *dev_priv = dev->dev_private;
147 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
151 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 WARN_ON(i915_verify_lists(dev));
160 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
162 return i915_gem_obj_bound_any(obj) && !obj->active;
166 i915_gem_init_ioctl(struct drm_device *dev, void *data,
167 struct drm_file *file)
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct drm_i915_gem_init *args = data;
172 if (drm_core_check_feature(dev, DRIVER_MODESET))
175 if (args->gtt_start >= args->gtt_end ||
176 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
179 /* GEM with user mode setting was never supported on ilk and later. */
180 if (INTEL_INFO(dev)->gen >= 5)
183 mutex_lock(&dev->struct_mutex);
184 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
186 dev_priv->gtt.mappable_end = args->gtt_end;
187 mutex_unlock(&dev->struct_mutex);
193 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
194 struct drm_file *file)
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 struct drm_i915_gem_get_aperture *args = data;
198 struct drm_i915_gem_object *obj;
202 mutex_lock(&dev->struct_mutex);
203 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
204 if (i915_gem_obj_is_pinned(obj))
205 pinned += i915_gem_obj_ggtt_size(obj);
206 mutex_unlock(&dev->struct_mutex);
208 args->aper_size = dev_priv->gtt.base.total;
209 args->aper_available_size = args->aper_size - pinned;
214 void *i915_gem_object_alloc(struct drm_device *dev)
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
220 void i915_gem_object_free(struct drm_i915_gem_object *obj)
222 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
223 kmem_cache_free(dev_priv->slab, obj);
227 i915_gem_create(struct drm_file *file,
228 struct drm_device *dev,
232 struct drm_i915_gem_object *obj;
236 size = roundup(size, PAGE_SIZE);
240 /* Allocate the new object */
241 obj = i915_gem_alloc_object(dev, size);
245 ret = drm_gem_handle_create(file, &obj->base, &handle);
246 /* drop reference from allocate - handle holds it now */
247 drm_gem_object_unreference_unlocked(&obj->base);
256 i915_gem_dumb_create(struct drm_file *file,
257 struct drm_device *dev,
258 struct drm_mode_create_dumb *args)
260 /* have to work out size/pitch and return them */
261 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
262 args->size = args->pitch * args->height;
263 return i915_gem_create(file, dev,
264 args->size, &args->handle);
268 * Creates a new mm object and returns a handle to it.
271 i915_gem_create_ioctl(struct drm_device *dev, void *data,
272 struct drm_file *file)
274 struct drm_i915_gem_create *args = data;
276 return i915_gem_create(file, dev,
277 args->size, &args->handle);
281 __copy_to_user_swizzled(char __user *cpu_vaddr,
282 const char *gpu_vaddr, int gpu_offset,
285 int ret, cpu_offset = 0;
288 int cacheline_end = ALIGN(gpu_offset + 1, 64);
289 int this_length = min(cacheline_end - gpu_offset, length);
290 int swizzled_gpu_offset = gpu_offset ^ 64;
292 ret = __copy_to_user(cpu_vaddr + cpu_offset,
293 gpu_vaddr + swizzled_gpu_offset,
298 cpu_offset += this_length;
299 gpu_offset += this_length;
300 length -= this_length;
307 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
308 const char __user *cpu_vaddr,
311 int ret, cpu_offset = 0;
314 int cacheline_end = ALIGN(gpu_offset + 1, 64);
315 int this_length = min(cacheline_end - gpu_offset, length);
316 int swizzled_gpu_offset = gpu_offset ^ 64;
318 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
319 cpu_vaddr + cpu_offset,
324 cpu_offset += this_length;
325 gpu_offset += this_length;
326 length -= this_length;
333 * Pins the specified object's pages and synchronizes the object with
334 * GPU accesses. Sets needs_clflush to non-zero if the caller should
335 * flush the object from the CPU cache.
337 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
347 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
348 /* If we're not in the cpu read domain, set ourself into the gtt
349 * read domain and manually flush cachelines (if required). This
350 * optimizes for the case when the gpu will dirty the data
351 * anyway again before the next pread happens. */
352 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
354 ret = i915_gem_object_wait_rendering(obj, true);
358 i915_gem_object_retire(obj);
361 ret = i915_gem_object_get_pages(obj);
365 i915_gem_object_pin_pages(obj);
370 /* Per-page copy function for the shmem pread fastpath.
371 * Flushes invalid cachelines before reading the target if
372 * needs_clflush is set. */
374 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
375 char __user *user_data,
376 bool page_do_bit17_swizzling, bool needs_clflush)
381 if (unlikely(page_do_bit17_swizzling))
384 vaddr = kmap_atomic(page);
386 drm_clflush_virt_range(vaddr + shmem_page_offset,
388 ret = __copy_to_user_inatomic(user_data,
389 vaddr + shmem_page_offset,
391 kunmap_atomic(vaddr);
393 return ret ? -EFAULT : 0;
397 shmem_clflush_swizzled_range(char *addr, unsigned long length,
400 if (unlikely(swizzled)) {
401 unsigned long start = (unsigned long) addr;
402 unsigned long end = (unsigned long) addr + length;
404 /* For swizzling simply ensure that we always flush both
405 * channels. Lame, but simple and it works. Swizzled
406 * pwrite/pread is far from a hotpath - current userspace
407 * doesn't use it at all. */
408 start = round_down(start, 128);
409 end = round_up(end, 128);
411 drm_clflush_virt_range((void *)start, end - start);
413 drm_clflush_virt_range(addr, length);
418 /* Only difference to the fast-path function is that this can handle bit17
419 * and uses non-atomic copy and kmap functions. */
421 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
422 char __user *user_data,
423 bool page_do_bit17_swizzling, bool needs_clflush)
430 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
432 page_do_bit17_swizzling);
434 if (page_do_bit17_swizzling)
435 ret = __copy_to_user_swizzled(user_data,
436 vaddr, shmem_page_offset,
439 ret = __copy_to_user(user_data,
440 vaddr + shmem_page_offset,
444 return ret ? - EFAULT : 0;
448 i915_gem_shmem_pread(struct drm_device *dev,
449 struct drm_i915_gem_object *obj,
450 struct drm_i915_gem_pread *args,
451 struct drm_file *file)
453 char __user *user_data;
456 int shmem_page_offset, page_length, ret = 0;
457 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
459 int needs_clflush = 0;
460 struct sg_page_iter sg_iter;
462 user_data = to_user_ptr(args->data_ptr);
465 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
467 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
471 offset = args->offset;
473 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
474 offset >> PAGE_SHIFT) {
475 struct page *page = sg_page_iter_page(&sg_iter);
480 /* Operation in this page
482 * shmem_page_offset = offset within page in shmem file
483 * page_length = bytes to copy for this page
485 shmem_page_offset = offset_in_page(offset);
486 page_length = remain;
487 if ((shmem_page_offset + page_length) > PAGE_SIZE)
488 page_length = PAGE_SIZE - shmem_page_offset;
490 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
491 (page_to_phys(page) & (1 << 17)) != 0;
493 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
494 user_data, page_do_bit17_swizzling,
499 mutex_unlock(&dev->struct_mutex);
501 if (likely(!i915.prefault_disable) && !prefaulted) {
502 ret = fault_in_multipages_writeable(user_data, remain);
503 /* Userspace is tricking us, but we've already clobbered
504 * its pages with the prefault and promised to write the
505 * data up to the first fault. Hence ignore any errors
506 * and just continue. */
511 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
512 user_data, page_do_bit17_swizzling,
515 mutex_lock(&dev->struct_mutex);
521 remain -= page_length;
522 user_data += page_length;
523 offset += page_length;
527 i915_gem_object_unpin_pages(obj);
533 * Reads data from the object referenced by handle.
535 * On error, the contents of *data are undefined.
538 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
539 struct drm_file *file)
541 struct drm_i915_gem_pread *args = data;
542 struct drm_i915_gem_object *obj;
548 if (!access_ok(VERIFY_WRITE,
549 to_user_ptr(args->data_ptr),
553 ret = i915_mutex_lock_interruptible(dev);
557 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
558 if (&obj->base == NULL) {
563 /* Bounds check source. */
564 if (args->offset > obj->base.size ||
565 args->size > obj->base.size - args->offset) {
570 /* prime objects have no backing filp to GEM pread/pwrite
573 if (!obj->base.filp) {
578 trace_i915_gem_object_pread(obj, args->offset, args->size);
580 ret = i915_gem_shmem_pread(dev, obj, args, file);
583 drm_gem_object_unreference(&obj->base);
585 mutex_unlock(&dev->struct_mutex);
589 /* This is the fast write path which cannot handle
590 * page faults in the source data
594 fast_user_write(struct io_mapping *mapping,
595 loff_t page_base, int page_offset,
596 char __user *user_data,
599 void __iomem *vaddr_atomic;
601 unsigned long unwritten;
603 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
604 /* We can use the cpu mem copy function because this is X86. */
605 vaddr = (void __force*)vaddr_atomic + page_offset;
606 unwritten = __copy_from_user_inatomic_nocache(vaddr,
608 io_mapping_unmap_atomic(vaddr_atomic);
613 * This is the fast pwrite path, where we copy the data directly from the
614 * user into the GTT, uncached.
617 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
618 struct drm_i915_gem_object *obj,
619 struct drm_i915_gem_pwrite *args,
620 struct drm_file *file)
622 struct drm_i915_private *dev_priv = dev->dev_private;
624 loff_t offset, page_base;
625 char __user *user_data;
626 int page_offset, page_length, ret;
628 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
632 ret = i915_gem_object_set_to_gtt_domain(obj, true);
636 ret = i915_gem_object_put_fence(obj);
640 user_data = to_user_ptr(args->data_ptr);
643 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
646 /* Operation in this page
648 * page_base = page offset within aperture
649 * page_offset = offset within page
650 * page_length = bytes to copy for this page
652 page_base = offset & PAGE_MASK;
653 page_offset = offset_in_page(offset);
654 page_length = remain;
655 if ((page_offset + remain) > PAGE_SIZE)
656 page_length = PAGE_SIZE - page_offset;
658 /* If we get a fault while copying data, then (presumably) our
659 * source page isn't available. Return the error and we'll
660 * retry in the slow path.
662 if (fast_user_write(dev_priv->gtt.mappable, page_base,
663 page_offset, user_data, page_length)) {
668 remain -= page_length;
669 user_data += page_length;
670 offset += page_length;
674 i915_gem_object_ggtt_unpin(obj);
679 /* Per-page copy function for the shmem pwrite fastpath.
680 * Flushes invalid cachelines before writing to the target if
681 * needs_clflush_before is set and flushes out any written cachelines after
682 * writing if needs_clflush is set. */
684 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
685 char __user *user_data,
686 bool page_do_bit17_swizzling,
687 bool needs_clflush_before,
688 bool needs_clflush_after)
693 if (unlikely(page_do_bit17_swizzling))
696 vaddr = kmap_atomic(page);
697 if (needs_clflush_before)
698 drm_clflush_virt_range(vaddr + shmem_page_offset,
700 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
701 user_data, page_length);
702 if (needs_clflush_after)
703 drm_clflush_virt_range(vaddr + shmem_page_offset,
705 kunmap_atomic(vaddr);
707 return ret ? -EFAULT : 0;
710 /* Only difference to the fast-path function is that this can handle bit17
711 * and uses non-atomic copy and kmap functions. */
713 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
714 char __user *user_data,
715 bool page_do_bit17_swizzling,
716 bool needs_clflush_before,
717 bool needs_clflush_after)
723 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
724 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
726 page_do_bit17_swizzling);
727 if (page_do_bit17_swizzling)
728 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
732 ret = __copy_from_user(vaddr + shmem_page_offset,
735 if (needs_clflush_after)
736 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
738 page_do_bit17_swizzling);
741 return ret ? -EFAULT : 0;
745 i915_gem_shmem_pwrite(struct drm_device *dev,
746 struct drm_i915_gem_object *obj,
747 struct drm_i915_gem_pwrite *args,
748 struct drm_file *file)
752 char __user *user_data;
753 int shmem_page_offset, page_length, ret = 0;
754 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
755 int hit_slowpath = 0;
756 int needs_clflush_after = 0;
757 int needs_clflush_before = 0;
758 struct sg_page_iter sg_iter;
760 user_data = to_user_ptr(args->data_ptr);
763 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
765 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
766 /* If we're not in the cpu write domain, set ourself into the gtt
767 * write domain and manually flush cachelines (if required). This
768 * optimizes for the case when the gpu will use the data
769 * right away and we therefore have to clflush anyway. */
770 needs_clflush_after = cpu_write_needs_clflush(obj);
771 ret = i915_gem_object_wait_rendering(obj, false);
775 i915_gem_object_retire(obj);
777 /* Same trick applies to invalidate partially written cachelines read
779 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
780 needs_clflush_before =
781 !cpu_cache_is_coherent(dev, obj->cache_level);
783 ret = i915_gem_object_get_pages(obj);
787 i915_gem_object_pin_pages(obj);
789 offset = args->offset;
792 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
793 offset >> PAGE_SHIFT) {
794 struct page *page = sg_page_iter_page(&sg_iter);
795 int partial_cacheline_write;
800 /* Operation in this page
802 * shmem_page_offset = offset within page in shmem file
803 * page_length = bytes to copy for this page
805 shmem_page_offset = offset_in_page(offset);
807 page_length = remain;
808 if ((shmem_page_offset + page_length) > PAGE_SIZE)
809 page_length = PAGE_SIZE - shmem_page_offset;
811 /* If we don't overwrite a cacheline completely we need to be
812 * careful to have up-to-date data by first clflushing. Don't
813 * overcomplicate things and flush the entire patch. */
814 partial_cacheline_write = needs_clflush_before &&
815 ((shmem_page_offset | page_length)
816 & (boot_cpu_data.x86_clflush_size - 1));
818 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
819 (page_to_phys(page) & (1 << 17)) != 0;
821 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
822 user_data, page_do_bit17_swizzling,
823 partial_cacheline_write,
824 needs_clflush_after);
829 mutex_unlock(&dev->struct_mutex);
830 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
831 user_data, page_do_bit17_swizzling,
832 partial_cacheline_write,
833 needs_clflush_after);
835 mutex_lock(&dev->struct_mutex);
841 remain -= page_length;
842 user_data += page_length;
843 offset += page_length;
847 i915_gem_object_unpin_pages(obj);
851 * Fixup: Flush cpu caches in case we didn't flush the dirty
852 * cachelines in-line while writing and the object moved
853 * out of the cpu write domain while we've dropped the lock.
855 if (!needs_clflush_after &&
856 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
857 if (i915_gem_clflush_object(obj, obj->pin_display))
858 i915_gem_chipset_flush(dev);
862 if (needs_clflush_after)
863 i915_gem_chipset_flush(dev);
869 * Writes data to the object referenced by handle.
871 * On error, the contents of the buffer that were to be modified are undefined.
874 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
875 struct drm_file *file)
877 struct drm_i915_gem_pwrite *args = data;
878 struct drm_i915_gem_object *obj;
884 if (!access_ok(VERIFY_READ,
885 to_user_ptr(args->data_ptr),
889 if (likely(!i915.prefault_disable)) {
890 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
896 ret = i915_mutex_lock_interruptible(dev);
900 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
901 if (&obj->base == NULL) {
906 /* Bounds check destination. */
907 if (args->offset > obj->base.size ||
908 args->size > obj->base.size - args->offset) {
913 /* prime objects have no backing filp to GEM pread/pwrite
916 if (!obj->base.filp) {
921 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
924 /* We can only do the GTT pwrite on untiled buffers, as otherwise
925 * it would end up going through the fenced access, and we'll get
926 * different detiling behavior between reading and writing.
927 * pread/pwrite currently are reading and writing from the CPU
928 * perspective, requiring manual detiling by the client.
931 ret = i915_gem_phys_pwrite(dev, obj, args, file);
935 if (obj->tiling_mode == I915_TILING_NONE &&
936 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
937 cpu_write_needs_clflush(obj)) {
938 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
939 /* Note that the gtt paths might fail with non-page-backed user
940 * pointers (e.g. gtt mappings when moving data between
941 * textures). Fallback to the shmem path in that case. */
944 if (ret == -EFAULT || ret == -ENOSPC)
945 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
948 drm_gem_object_unreference(&obj->base);
950 mutex_unlock(&dev->struct_mutex);
955 i915_gem_check_wedge(struct i915_gpu_error *error,
958 if (i915_reset_in_progress(error)) {
959 /* Non-interruptible callers can't handle -EAGAIN, hence return
960 * -EIO unconditionally for these. */
964 /* Recovery complete, but the reset failed ... */
965 if (i915_terminally_wedged(error))
975 * Compare seqno against outstanding lazy request. Emit a request if they are
979 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
983 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
986 if (seqno == ring->outstanding_lazy_seqno)
987 ret = i915_add_request(ring, NULL);
992 static void fake_irq(unsigned long data)
994 wake_up_process((struct task_struct *)data);
997 static bool missed_irq(struct drm_i915_private *dev_priv,
998 struct intel_ring_buffer *ring)
1000 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1003 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1005 if (file_priv == NULL)
1008 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1012 * __wait_seqno - wait until execution of seqno has finished
1013 * @ring: the ring expected to report seqno
1015 * @reset_counter: reset sequence associated with the given seqno
1016 * @interruptible: do an interruptible wait (normally yes)
1017 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1019 * Note: It is of utmost importance that the passed in seqno and reset_counter
1020 * values have been read by the caller in an smp safe manner. Where read-side
1021 * locks are involved, it is sufficient to read the reset_counter before
1022 * unlocking the lock that protects the seqno. For lockless tricks, the
1023 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1026 * Returns 0 if the seqno was found within the alloted time. Else returns the
1027 * errno with remaining time filled in timeout argument.
1029 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1030 unsigned reset_counter,
1032 struct timespec *timeout,
1033 struct drm_i915_file_private *file_priv)
1035 struct drm_device *dev = ring->dev;
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 const bool irq_test_in_progress =
1038 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1039 struct timespec before, now;
1041 unsigned long timeout_expire;
1044 WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1046 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1049 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1051 if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1052 gen6_rps_boost(dev_priv);
1054 mod_delayed_work(dev_priv->wq,
1055 &file_priv->mm.idle_work,
1056 msecs_to_jiffies(100));
1059 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1062 /* Record current time in case interrupted by signal, or wedged */
1063 trace_i915_gem_request_wait_begin(ring, seqno);
1064 getrawmonotonic(&before);
1066 struct timer_list timer;
1068 prepare_to_wait(&ring->irq_queue, &wait,
1069 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1071 /* We need to check whether any gpu reset happened in between
1072 * the caller grabbing the seqno and now ... */
1073 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1074 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1075 * is truely gone. */
1076 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1082 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1087 if (interruptible && signal_pending(current)) {
1092 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1097 timer.function = NULL;
1098 if (timeout || missed_irq(dev_priv, ring)) {
1099 unsigned long expire;
1101 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1102 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1103 mod_timer(&timer, expire);
1108 if (timer.function) {
1109 del_singleshot_timer_sync(&timer);
1110 destroy_timer_on_stack(&timer);
1113 getrawmonotonic(&now);
1114 trace_i915_gem_request_wait_end(ring, seqno);
1116 if (!irq_test_in_progress)
1117 ring->irq_put(ring);
1119 finish_wait(&ring->irq_queue, &wait);
1122 struct timespec sleep_time = timespec_sub(now, before);
1123 *timeout = timespec_sub(*timeout, sleep_time);
1124 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1125 set_normalized_timespec(timeout, 0, 0);
1132 * Waits for a sequence number to be signaled, and cleans up the
1133 * request and object lists appropriately for that event.
1136 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1138 struct drm_device *dev = ring->dev;
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 bool interruptible = dev_priv->mm.interruptible;
1143 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1146 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1150 ret = i915_gem_check_olr(ring, seqno);
1154 return __wait_seqno(ring, seqno,
1155 atomic_read(&dev_priv->gpu_error.reset_counter),
1156 interruptible, NULL, NULL);
1160 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1161 struct intel_ring_buffer *ring)
1166 /* Manually manage the write flush as we may have not yet
1167 * retired the buffer.
1169 * Note that the last_write_seqno is always the earlier of
1170 * the two (read/write) seqno, so if we haved successfully waited,
1171 * we know we have passed the last write.
1173 obj->last_write_seqno = 0;
1179 * Ensures that all rendering to the object has completed and the object is
1180 * safe to unbind from the GTT or access from the CPU.
1182 static __must_check int
1183 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1186 struct intel_ring_buffer *ring = obj->ring;
1190 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1194 ret = i915_wait_seqno(ring, seqno);
1198 return i915_gem_object_wait_rendering__tail(obj, ring);
1201 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1202 * as the object state may change during this call.
1204 static __must_check int
1205 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1206 struct drm_i915_file_private *file_priv,
1209 struct drm_device *dev = obj->base.dev;
1210 struct drm_i915_private *dev_priv = dev->dev_private;
1211 struct intel_ring_buffer *ring = obj->ring;
1212 unsigned reset_counter;
1216 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1217 BUG_ON(!dev_priv->mm.interruptible);
1219 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1223 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1227 ret = i915_gem_check_olr(ring, seqno);
1231 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1232 mutex_unlock(&dev->struct_mutex);
1233 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1234 mutex_lock(&dev->struct_mutex);
1238 return i915_gem_object_wait_rendering__tail(obj, ring);
1242 * Called when user space prepares to use an object with the CPU, either
1243 * through the mmap ioctl's mapping or a GTT mapping.
1246 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1247 struct drm_file *file)
1249 struct drm_i915_gem_set_domain *args = data;
1250 struct drm_i915_gem_object *obj;
1251 uint32_t read_domains = args->read_domains;
1252 uint32_t write_domain = args->write_domain;
1255 /* Only handle setting domains to types used by the CPU. */
1256 if (write_domain & I915_GEM_GPU_DOMAINS)
1259 if (read_domains & I915_GEM_GPU_DOMAINS)
1262 /* Having something in the write domain implies it's in the read
1263 * domain, and only that read domain. Enforce that in the request.
1265 if (write_domain != 0 && read_domains != write_domain)
1268 ret = i915_mutex_lock_interruptible(dev);
1272 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1273 if (&obj->base == NULL) {
1278 /* Try to flush the object off the GPU without holding the lock.
1279 * We will repeat the flush holding the lock in the normal manner
1280 * to catch cases where we are gazumped.
1282 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1288 if (read_domains & I915_GEM_DOMAIN_GTT) {
1289 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1291 /* Silently promote "you're not bound, there was nothing to do"
1292 * to success, since the client was just asking us to
1293 * make sure everything was done.
1298 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1302 drm_gem_object_unreference(&obj->base);
1304 mutex_unlock(&dev->struct_mutex);
1309 * Called when user space has done writes to this buffer
1312 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1313 struct drm_file *file)
1315 struct drm_i915_gem_sw_finish *args = data;
1316 struct drm_i915_gem_object *obj;
1319 ret = i915_mutex_lock_interruptible(dev);
1323 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1324 if (&obj->base == NULL) {
1329 /* Pinned buffers may be scanout, so flush the cache */
1330 if (obj->pin_display)
1331 i915_gem_object_flush_cpu_write_domain(obj, true);
1333 drm_gem_object_unreference(&obj->base);
1335 mutex_unlock(&dev->struct_mutex);
1340 * Maps the contents of an object, returning the address it is mapped
1343 * While the mapping holds a reference on the contents of the object, it doesn't
1344 * imply a ref on the object itself.
1347 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1348 struct drm_file *file)
1350 struct drm_i915_gem_mmap *args = data;
1351 struct drm_gem_object *obj;
1354 obj = drm_gem_object_lookup(dev, file, args->handle);
1358 /* prime objects have no backing filp to GEM mmap
1362 drm_gem_object_unreference_unlocked(obj);
1366 addr = vm_mmap(obj->filp, 0, args->size,
1367 PROT_READ | PROT_WRITE, MAP_SHARED,
1369 drm_gem_object_unreference_unlocked(obj);
1370 if (IS_ERR((void *)addr))
1373 args->addr_ptr = (uint64_t) addr;
1379 * i915_gem_fault - fault a page into the GTT
1380 * vma: VMA in question
1383 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1384 * from userspace. The fault handler takes care of binding the object to
1385 * the GTT (if needed), allocating and programming a fence register (again,
1386 * only if needed based on whether the old reg is still valid or the object
1387 * is tiled) and inserting a new PTE into the faulting process.
1389 * Note that the faulting process may involve evicting existing objects
1390 * from the GTT and/or fence registers to make room. So performance may
1391 * suffer if the GTT working set is large or there are few fence registers
1394 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1396 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1397 struct drm_device *dev = obj->base.dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 pgoff_t page_offset;
1402 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1404 intel_runtime_pm_get(dev_priv);
1406 /* We don't use vmf->pgoff since that has the fake offset */
1407 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1410 ret = i915_mutex_lock_interruptible(dev);
1414 trace_i915_gem_object_fault(obj, page_offset, true, write);
1416 /* Try to flush the object off the GPU first without holding the lock.
1417 * Upon reacquiring the lock, we will perform our sanity checks and then
1418 * repeat the flush holding the lock in the normal manner to catch cases
1419 * where we are gazumped.
1421 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1425 /* Access to snoopable pages through the GTT is incoherent. */
1426 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1431 /* Now bind it into the GTT if needed */
1432 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1436 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1440 ret = i915_gem_object_get_fence(obj);
1444 obj->fault_mappable = true;
1446 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1450 /* Finally, remap it using the new GTT offset */
1451 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1453 i915_gem_object_ggtt_unpin(obj);
1455 mutex_unlock(&dev->struct_mutex);
1459 /* If this -EIO is due to a gpu hang, give the reset code a
1460 * chance to clean up the mess. Otherwise return the proper
1462 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1463 ret = VM_FAULT_SIGBUS;
1468 * EAGAIN means the gpu is hung and we'll wait for the error
1469 * handler to reset everything when re-faulting in
1470 * i915_mutex_lock_interruptible.
1477 * EBUSY is ok: this just means that another thread
1478 * already did the job.
1480 ret = VM_FAULT_NOPAGE;
1487 ret = VM_FAULT_SIGBUS;
1490 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1491 ret = VM_FAULT_SIGBUS;
1495 intel_runtime_pm_put(dev_priv);
1499 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1501 struct i915_vma *vma;
1504 * Only the global gtt is relevant for gtt memory mappings, so restrict
1505 * list traversal to objects bound into the global address space. Note
1506 * that the active list should be empty, but better safe than sorry.
1508 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1509 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1510 i915_gem_release_mmap(vma->obj);
1511 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1512 i915_gem_release_mmap(vma->obj);
1516 * i915_gem_release_mmap - remove physical page mappings
1517 * @obj: obj in question
1519 * Preserve the reservation of the mmapping with the DRM core code, but
1520 * relinquish ownership of the pages back to the system.
1522 * It is vital that we remove the page mapping if we have mapped a tiled
1523 * object through the GTT and then lose the fence register due to
1524 * resource pressure. Similarly if the object has been moved out of the
1525 * aperture, than pages mapped into userspace must be revoked. Removing the
1526 * mapping will then trigger a page fault on the next user access, allowing
1527 * fixup by i915_gem_fault().
1530 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1532 if (!obj->fault_mappable)
1535 drm_vma_node_unmap(&obj->base.vma_node,
1536 obj->base.dev->anon_inode->i_mapping);
1537 obj->fault_mappable = false;
1541 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1545 if (INTEL_INFO(dev)->gen >= 4 ||
1546 tiling_mode == I915_TILING_NONE)
1549 /* Previous chips need a power-of-two fence region when tiling */
1550 if (INTEL_INFO(dev)->gen == 3)
1551 gtt_size = 1024*1024;
1553 gtt_size = 512*1024;
1555 while (gtt_size < size)
1562 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1563 * @obj: object to check
1565 * Return the required GTT alignment for an object, taking into account
1566 * potential fence register mapping.
1569 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1570 int tiling_mode, bool fenced)
1573 * Minimum alignment is 4k (GTT page size), but might be greater
1574 * if a fence register is needed for the object.
1576 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1577 tiling_mode == I915_TILING_NONE)
1581 * Previous chips need to be aligned to the size of the smallest
1582 * fence register that can contain the object.
1584 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1587 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1589 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1592 if (drm_vma_node_has_offset(&obj->base.vma_node))
1595 dev_priv->mm.shrinker_no_lock_stealing = true;
1597 ret = drm_gem_create_mmap_offset(&obj->base);
1601 /* Badly fragmented mmap space? The only way we can recover
1602 * space is by destroying unwanted objects. We can't randomly release
1603 * mmap_offsets as userspace expects them to be persistent for the
1604 * lifetime of the objects. The closest we can is to release the
1605 * offsets on purgeable objects by truncating it and marking it purged,
1606 * which prevents userspace from ever using that object again.
1608 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1609 ret = drm_gem_create_mmap_offset(&obj->base);
1613 i915_gem_shrink_all(dev_priv);
1614 ret = drm_gem_create_mmap_offset(&obj->base);
1616 dev_priv->mm.shrinker_no_lock_stealing = false;
1621 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1623 drm_gem_free_mmap_offset(&obj->base);
1627 i915_gem_mmap_gtt(struct drm_file *file,
1628 struct drm_device *dev,
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633 struct drm_i915_gem_object *obj;
1636 ret = i915_mutex_lock_interruptible(dev);
1640 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1641 if (&obj->base == NULL) {
1646 if (obj->base.size > dev_priv->gtt.mappable_end) {
1651 if (obj->madv != I915_MADV_WILLNEED) {
1652 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1657 ret = i915_gem_object_create_mmap_offset(obj);
1661 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1664 drm_gem_object_unreference(&obj->base);
1666 mutex_unlock(&dev->struct_mutex);
1671 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1673 * @data: GTT mapping ioctl data
1674 * @file: GEM object info
1676 * Simply returns the fake offset to userspace so it can mmap it.
1677 * The mmap call will end up in drm_gem_mmap(), which will set things
1678 * up so we can get faults in the handler above.
1680 * The fault handler will take care of binding the object into the GTT
1681 * (since it may have been evicted to make room for something), allocating
1682 * a fence register, and mapping the appropriate aperture address into
1686 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1687 struct drm_file *file)
1689 struct drm_i915_gem_mmap_gtt *args = data;
1691 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1694 /* Immediately discard the backing storage */
1696 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1698 struct inode *inode;
1700 i915_gem_object_free_mmap_offset(obj);
1702 if (obj->base.filp == NULL)
1705 /* Our goal here is to return as much of the memory as
1706 * is possible back to the system as we are called from OOM.
1707 * To do this we must instruct the shmfs to drop all of its
1708 * backing pages, *now*.
1710 inode = file_inode(obj->base.filp);
1711 shmem_truncate_range(inode, 0, (loff_t)-1);
1713 obj->madv = __I915_MADV_PURGED;
1717 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1719 return obj->madv == I915_MADV_DONTNEED;
1723 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1725 struct sg_page_iter sg_iter;
1728 BUG_ON(obj->madv == __I915_MADV_PURGED);
1730 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1732 /* In the event of a disaster, abandon all caches and
1733 * hope for the best.
1735 WARN_ON(ret != -EIO);
1736 i915_gem_clflush_object(obj, true);
1737 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1740 if (i915_gem_object_needs_bit17_swizzle(obj))
1741 i915_gem_object_save_bit_17_swizzle(obj);
1743 if (obj->madv == I915_MADV_DONTNEED)
1746 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1747 struct page *page = sg_page_iter_page(&sg_iter);
1750 set_page_dirty(page);
1752 if (obj->madv == I915_MADV_WILLNEED)
1753 mark_page_accessed(page);
1755 page_cache_release(page);
1759 sg_free_table(obj->pages);
1764 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1766 const struct drm_i915_gem_object_ops *ops = obj->ops;
1768 if (obj->pages == NULL)
1771 if (obj->pages_pin_count)
1774 BUG_ON(i915_gem_obj_bound_any(obj));
1776 /* ->put_pages might need to allocate memory for the bit17 swizzle
1777 * array, hence protect them from being reaped by removing them from gtt
1779 list_del(&obj->global_list);
1781 ops->put_pages(obj);
1784 if (i915_gem_object_is_purgeable(obj))
1785 i915_gem_object_truncate(obj);
1790 static unsigned long
1791 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1792 bool purgeable_only)
1794 struct list_head still_in_list;
1795 struct drm_i915_gem_object *obj;
1796 unsigned long count = 0;
1799 * As we may completely rewrite the (un)bound list whilst unbinding
1800 * (due to retiring requests) we have to strictly process only
1801 * one element of the list at the time, and recheck the list
1802 * on every iteration.
1804 * In particular, we must hold a reference whilst removing the
1805 * object as we may end up waiting for and/or retiring the objects.
1806 * This might release the final reference (held by the active list)
1807 * and result in the object being freed from under us. This is
1808 * similar to the precautions the eviction code must take whilst
1811 * Also note that although these lists do not hold a reference to
1812 * the object we can safely grab one here: The final object
1813 * unreferencing and the bound_list are both protected by the
1814 * dev->struct_mutex and so we won't ever be able to observe an
1815 * object on the bound_list with a reference count equals 0.
1817 INIT_LIST_HEAD(&still_in_list);
1818 while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1819 obj = list_first_entry(&dev_priv->mm.unbound_list,
1820 typeof(*obj), global_list);
1821 list_move_tail(&obj->global_list, &still_in_list);
1823 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1826 drm_gem_object_reference(&obj->base);
1828 if (i915_gem_object_put_pages(obj) == 0)
1829 count += obj->base.size >> PAGE_SHIFT;
1831 drm_gem_object_unreference(&obj->base);
1833 list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1835 INIT_LIST_HEAD(&still_in_list);
1836 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1837 struct i915_vma *vma, *v;
1839 obj = list_first_entry(&dev_priv->mm.bound_list,
1840 typeof(*obj), global_list);
1841 list_move_tail(&obj->global_list, &still_in_list);
1843 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1846 drm_gem_object_reference(&obj->base);
1848 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1849 if (i915_vma_unbind(vma))
1852 if (i915_gem_object_put_pages(obj) == 0)
1853 count += obj->base.size >> PAGE_SHIFT;
1855 drm_gem_object_unreference(&obj->base);
1857 list_splice(&still_in_list, &dev_priv->mm.bound_list);
1862 static unsigned long
1863 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1865 return __i915_gem_shrink(dev_priv, target, true);
1868 static unsigned long
1869 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1871 i915_gem_evict_everything(dev_priv->dev);
1872 return __i915_gem_shrink(dev_priv, LONG_MAX, false);
1876 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1878 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1880 struct address_space *mapping;
1881 struct sg_table *st;
1882 struct scatterlist *sg;
1883 struct sg_page_iter sg_iter;
1885 unsigned long last_pfn = 0; /* suppress gcc warning */
1888 /* Assert that the object is not currently in any GPU domain. As it
1889 * wasn't in the GTT, there shouldn't be any way it could have been in
1892 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1893 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1895 st = kmalloc(sizeof(*st), GFP_KERNEL);
1899 page_count = obj->base.size / PAGE_SIZE;
1900 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1905 /* Get the list of pages out of our struct file. They'll be pinned
1906 * at this point until we release them.
1908 * Fail silently without starting the shrinker
1910 mapping = file_inode(obj->base.filp)->i_mapping;
1911 gfp = mapping_gfp_mask(mapping);
1912 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1913 gfp &= ~(__GFP_IO | __GFP_WAIT);
1916 for (i = 0; i < page_count; i++) {
1917 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1919 i915_gem_purge(dev_priv, page_count);
1920 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1923 /* We've tried hard to allocate the memory by reaping
1924 * our own buffer, now let the real VM do its job and
1925 * go down in flames if truly OOM.
1927 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1928 gfp |= __GFP_IO | __GFP_WAIT;
1930 i915_gem_shrink_all(dev_priv);
1931 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1935 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1936 gfp &= ~(__GFP_IO | __GFP_WAIT);
1938 #ifdef CONFIG_SWIOTLB
1939 if (swiotlb_nr_tbl()) {
1941 sg_set_page(sg, page, PAGE_SIZE, 0);
1946 if (!i || page_to_pfn(page) != last_pfn + 1) {
1950 sg_set_page(sg, page, PAGE_SIZE, 0);
1952 sg->length += PAGE_SIZE;
1954 last_pfn = page_to_pfn(page);
1956 /* Check that the i965g/gm workaround works. */
1957 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
1959 #ifdef CONFIG_SWIOTLB
1960 if (!swiotlb_nr_tbl())
1965 if (i915_gem_object_needs_bit17_swizzle(obj))
1966 i915_gem_object_do_bit_17_swizzle(obj);
1972 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1973 page_cache_release(sg_page_iter_page(&sg_iter));
1977 /* shmemfs first checks if there is enough memory to allocate the page
1978 * and reports ENOSPC should there be insufficient, along with the usual
1979 * ENOMEM for a genuine allocation failure.
1981 * We use ENOSPC in our driver to mean that we have run out of aperture
1982 * space and so want to translate the error from shmemfs back to our
1983 * usual understanding of ENOMEM.
1985 if (PTR_ERR(page) == -ENOSPC)
1988 return PTR_ERR(page);
1991 /* Ensure that the associated pages are gathered from the backing storage
1992 * and pinned into our object. i915_gem_object_get_pages() may be called
1993 * multiple times before they are released by a single call to
1994 * i915_gem_object_put_pages() - once the pages are no longer referenced
1995 * either as a result of memory pressure (reaping pages under the shrinker)
1996 * or as the object is itself released.
1999 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2001 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2002 const struct drm_i915_gem_object_ops *ops = obj->ops;
2008 if (obj->madv != I915_MADV_WILLNEED) {
2009 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2013 BUG_ON(obj->pages_pin_count);
2015 ret = ops->get_pages(obj);
2019 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2024 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2025 struct intel_ring_buffer *ring)
2027 struct drm_device *dev = obj->base.dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 u32 seqno = intel_ring_get_seqno(ring);
2031 BUG_ON(ring == NULL);
2032 if (obj->ring != ring && obj->last_write_seqno) {
2033 /* Keep the seqno relative to the current ring */
2034 obj->last_write_seqno = seqno;
2038 /* Add a reference if we're newly entering the active list. */
2040 drm_gem_object_reference(&obj->base);
2044 list_move_tail(&obj->ring_list, &ring->active_list);
2046 obj->last_read_seqno = seqno;
2048 if (obj->fenced_gpu_access) {
2049 obj->last_fenced_seqno = seqno;
2051 /* Bump MRU to take account of the delayed flush */
2052 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2053 struct drm_i915_fence_reg *reg;
2055 reg = &dev_priv->fence_regs[obj->fence_reg];
2056 list_move_tail(®->lru_list,
2057 &dev_priv->mm.fence_list);
2062 void i915_vma_move_to_active(struct i915_vma *vma,
2063 struct intel_ring_buffer *ring)
2065 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2066 return i915_gem_object_move_to_active(vma->obj, ring);
2070 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2072 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2073 struct i915_address_space *vm;
2074 struct i915_vma *vma;
2076 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2077 BUG_ON(!obj->active);
2079 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2080 vma = i915_gem_obj_to_vma(obj, vm);
2081 if (vma && !list_empty(&vma->mm_list))
2082 list_move_tail(&vma->mm_list, &vm->inactive_list);
2085 list_del_init(&obj->ring_list);
2088 obj->last_read_seqno = 0;
2089 obj->last_write_seqno = 0;
2090 obj->base.write_domain = 0;
2092 obj->last_fenced_seqno = 0;
2093 obj->fenced_gpu_access = false;
2096 drm_gem_object_unreference(&obj->base);
2098 WARN_ON(i915_verify_lists(dev));
2102 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2104 struct intel_ring_buffer *ring = obj->ring;
2109 if (i915_seqno_passed(ring->get_seqno(ring, true),
2110 obj->last_read_seqno))
2111 i915_gem_object_move_to_inactive(obj);
2115 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 struct intel_ring_buffer *ring;
2121 /* Carefully retire all requests without writing to the rings */
2122 for_each_ring(ring, dev_priv, i) {
2123 ret = intel_ring_idle(ring);
2127 i915_gem_retire_requests(dev);
2129 /* Finally reset hw state */
2130 for_each_ring(ring, dev_priv, i) {
2131 intel_ring_init_seqno(ring, seqno);
2133 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2134 ring->semaphore.sync_seqno[j] = 0;
2140 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2142 struct drm_i915_private *dev_priv = dev->dev_private;
2148 /* HWS page needs to be set less than what we
2149 * will inject to ring
2151 ret = i915_gem_init_seqno(dev, seqno - 1);
2155 /* Carefully set the last_seqno value so that wrap
2156 * detection still works
2158 dev_priv->next_seqno = seqno;
2159 dev_priv->last_seqno = seqno - 1;
2160 if (dev_priv->last_seqno == 0)
2161 dev_priv->last_seqno--;
2167 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2171 /* reserve 0 for non-seqno */
2172 if (dev_priv->next_seqno == 0) {
2173 int ret = i915_gem_init_seqno(dev, 0);
2177 dev_priv->next_seqno = 1;
2180 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2184 int __i915_add_request(struct intel_ring_buffer *ring,
2185 struct drm_file *file,
2186 struct drm_i915_gem_object *obj,
2189 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2190 struct drm_i915_gem_request *request;
2191 u32 request_ring_position, request_start;
2194 request_start = intel_ring_get_tail(ring);
2196 * Emit any outstanding flushes - execbuf can fail to emit the flush
2197 * after having emitted the batchbuffer command. Hence we need to fix
2198 * things up similar to emitting the lazy request. The difference here
2199 * is that the flush _must_ happen before the next request, no matter
2202 ret = intel_ring_flush_all_caches(ring);
2206 request = ring->preallocated_lazy_request;
2207 if (WARN_ON(request == NULL))
2210 /* Record the position of the start of the request so that
2211 * should we detect the updated seqno part-way through the
2212 * GPU processing the request, we never over-estimate the
2213 * position of the head.
2215 request_ring_position = intel_ring_get_tail(ring);
2217 ret = ring->add_request(ring);
2221 request->seqno = intel_ring_get_seqno(ring);
2222 request->ring = ring;
2223 request->head = request_start;
2224 request->tail = request_ring_position;
2226 /* Whilst this request exists, batch_obj will be on the
2227 * active_list, and so will hold the active reference. Only when this
2228 * request is retired will the the batch_obj be moved onto the
2229 * inactive_list and lose its active reference. Hence we do not need
2230 * to explicitly hold another reference here.
2232 request->batch_obj = obj;
2234 /* Hold a reference to the current context so that we can inspect
2235 * it later in case a hangcheck error event fires.
2237 request->ctx = ring->last_context;
2239 i915_gem_context_reference(request->ctx);
2241 request->emitted_jiffies = jiffies;
2242 list_add_tail(&request->list, &ring->request_list);
2243 request->file_priv = NULL;
2246 struct drm_i915_file_private *file_priv = file->driver_priv;
2248 spin_lock(&file_priv->mm.lock);
2249 request->file_priv = file_priv;
2250 list_add_tail(&request->client_list,
2251 &file_priv->mm.request_list);
2252 spin_unlock(&file_priv->mm.lock);
2255 trace_i915_gem_request_add(ring, request->seqno);
2256 ring->outstanding_lazy_seqno = 0;
2257 ring->preallocated_lazy_request = NULL;
2259 if (!dev_priv->ums.mm_suspended) {
2260 i915_queue_hangcheck(ring->dev);
2262 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2263 queue_delayed_work(dev_priv->wq,
2264 &dev_priv->mm.retire_work,
2265 round_jiffies_up_relative(HZ));
2266 intel_mark_busy(dev_priv->dev);
2270 *out_seqno = request->seqno;
2275 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2277 struct drm_i915_file_private *file_priv = request->file_priv;
2282 spin_lock(&file_priv->mm.lock);
2283 list_del(&request->client_list);
2284 request->file_priv = NULL;
2285 spin_unlock(&file_priv->mm.lock);
2288 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2289 const struct i915_hw_context *ctx)
2291 unsigned long elapsed;
2293 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2295 if (ctx->hang_stats.banned)
2298 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2299 if (!i915_gem_context_is_default(ctx)) {
2300 DRM_DEBUG("context hanging too fast, banning!\n");
2302 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2303 if (i915_stop_ring_allow_warn(dev_priv))
2304 DRM_ERROR("gpu hanging too fast, banning!\n");
2312 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2313 struct i915_hw_context *ctx,
2316 struct i915_ctx_hang_stats *hs;
2321 hs = &ctx->hang_stats;
2324 hs->banned = i915_context_is_banned(dev_priv, ctx);
2326 hs->guilty_ts = get_seconds();
2328 hs->batch_pending++;
2332 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2334 list_del(&request->list);
2335 i915_gem_request_remove_from_client(request);
2338 i915_gem_context_unreference(request->ctx);
2343 struct drm_i915_gem_request *
2344 i915_gem_find_active_request(struct intel_ring_buffer *ring)
2346 struct drm_i915_gem_request *request;
2347 u32 completed_seqno;
2349 completed_seqno = ring->get_seqno(ring, false);
2351 list_for_each_entry(request, &ring->request_list, list) {
2352 if (i915_seqno_passed(completed_seqno, request->seqno))
2361 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2362 struct intel_ring_buffer *ring)
2364 struct drm_i915_gem_request *request;
2367 request = i915_gem_find_active_request(ring);
2369 if (request == NULL)
2372 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2374 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2376 list_for_each_entry_continue(request, &ring->request_list, list)
2377 i915_set_reset_status(dev_priv, request->ctx, false);
2380 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2381 struct intel_ring_buffer *ring)
2383 while (!list_empty(&ring->active_list)) {
2384 struct drm_i915_gem_object *obj;
2386 obj = list_first_entry(&ring->active_list,
2387 struct drm_i915_gem_object,
2390 i915_gem_object_move_to_inactive(obj);
2394 * We must free the requests after all the corresponding objects have
2395 * been moved off active lists. Which is the same order as the normal
2396 * retire_requests function does. This is important if object hold
2397 * implicit references on things like e.g. ppgtt address spaces through
2400 while (!list_empty(&ring->request_list)) {
2401 struct drm_i915_gem_request *request;
2403 request = list_first_entry(&ring->request_list,
2404 struct drm_i915_gem_request,
2407 i915_gem_free_request(request);
2410 /* These may not have been flush before the reset, do so now */
2411 kfree(ring->preallocated_lazy_request);
2412 ring->preallocated_lazy_request = NULL;
2413 ring->outstanding_lazy_seqno = 0;
2416 void i915_gem_restore_fences(struct drm_device *dev)
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2421 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2422 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2425 * Commit delayed tiling changes if we have an object still
2426 * attached to the fence, otherwise just clear the fence.
2429 i915_gem_object_update_fence(reg->obj, reg,
2430 reg->obj->tiling_mode);
2432 i915_gem_write_fence(dev, i, NULL);
2437 void i915_gem_reset(struct drm_device *dev)
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 struct intel_ring_buffer *ring;
2444 * Before we free the objects from the requests, we need to inspect
2445 * them for finding the guilty party. As the requests only borrow
2446 * their reference to the objects, the inspection must be done first.
2448 for_each_ring(ring, dev_priv, i)
2449 i915_gem_reset_ring_status(dev_priv, ring);
2451 for_each_ring(ring, dev_priv, i)
2452 i915_gem_reset_ring_cleanup(dev_priv, ring);
2454 i915_gem_context_reset(dev);
2456 i915_gem_restore_fences(dev);
2460 * This function clears the request list as sequence numbers are passed.
2463 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2467 if (list_empty(&ring->request_list))
2470 WARN_ON(i915_verify_lists(ring->dev));
2472 seqno = ring->get_seqno(ring, true);
2474 /* Move any buffers on the active list that are no longer referenced
2475 * by the ringbuffer to the flushing/inactive lists as appropriate,
2476 * before we free the context associated with the requests.
2478 while (!list_empty(&ring->active_list)) {
2479 struct drm_i915_gem_object *obj;
2481 obj = list_first_entry(&ring->active_list,
2482 struct drm_i915_gem_object,
2485 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2488 i915_gem_object_move_to_inactive(obj);
2492 while (!list_empty(&ring->request_list)) {
2493 struct drm_i915_gem_request *request;
2495 request = list_first_entry(&ring->request_list,
2496 struct drm_i915_gem_request,
2499 if (!i915_seqno_passed(seqno, request->seqno))
2502 trace_i915_gem_request_retire(ring, request->seqno);
2503 /* We know the GPU must have read the request to have
2504 * sent us the seqno + interrupt, so use the position
2505 * of tail of the request to update the last known position
2508 ring->last_retired_head = request->tail;
2510 i915_gem_free_request(request);
2513 if (unlikely(ring->trace_irq_seqno &&
2514 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2515 ring->irq_put(ring);
2516 ring->trace_irq_seqno = 0;
2519 WARN_ON(i915_verify_lists(ring->dev));
2523 i915_gem_retire_requests(struct drm_device *dev)
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 struct intel_ring_buffer *ring;
2530 for_each_ring(ring, dev_priv, i) {
2531 i915_gem_retire_requests_ring(ring);
2532 idle &= list_empty(&ring->request_list);
2536 mod_delayed_work(dev_priv->wq,
2537 &dev_priv->mm.idle_work,
2538 msecs_to_jiffies(100));
2544 i915_gem_retire_work_handler(struct work_struct *work)
2546 struct drm_i915_private *dev_priv =
2547 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2548 struct drm_device *dev = dev_priv->dev;
2551 /* Come back later if the device is busy... */
2553 if (mutex_trylock(&dev->struct_mutex)) {
2554 idle = i915_gem_retire_requests(dev);
2555 mutex_unlock(&dev->struct_mutex);
2558 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2559 round_jiffies_up_relative(HZ));
2563 i915_gem_idle_work_handler(struct work_struct *work)
2565 struct drm_i915_private *dev_priv =
2566 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2568 intel_mark_idle(dev_priv->dev);
2572 * Ensures that an object will eventually get non-busy by flushing any required
2573 * write domains, emitting any outstanding lazy request and retiring and
2574 * completed requests.
2577 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2582 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2586 i915_gem_retire_requests_ring(obj->ring);
2593 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2594 * @DRM_IOCTL_ARGS: standard ioctl arguments
2596 * Returns 0 if successful, else an error is returned with the remaining time in
2597 * the timeout parameter.
2598 * -ETIME: object is still busy after timeout
2599 * -ERESTARTSYS: signal interrupted the wait
2600 * -ENONENT: object doesn't exist
2601 * Also possible, but rare:
2602 * -EAGAIN: GPU wedged
2604 * -ENODEV: Internal IRQ fail
2605 * -E?: The add request failed
2607 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2608 * non-zero timeout parameter the wait ioctl will wait for the given number of
2609 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2610 * without holding struct_mutex the object may become re-busied before this
2611 * function completes. A similar but shorter * race condition exists in the busy
2615 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618 struct drm_i915_gem_wait *args = data;
2619 struct drm_i915_gem_object *obj;
2620 struct intel_ring_buffer *ring = NULL;
2621 struct timespec timeout_stack, *timeout = NULL;
2622 unsigned reset_counter;
2626 if (args->timeout_ns >= 0) {
2627 timeout_stack = ns_to_timespec(args->timeout_ns);
2628 timeout = &timeout_stack;
2631 ret = i915_mutex_lock_interruptible(dev);
2635 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2636 if (&obj->base == NULL) {
2637 mutex_unlock(&dev->struct_mutex);
2641 /* Need to make sure the object gets inactive eventually. */
2642 ret = i915_gem_object_flush_active(obj);
2647 seqno = obj->last_read_seqno;
2654 /* Do this after OLR check to make sure we make forward progress polling
2655 * on this IOCTL with a 0 timeout (like busy ioctl)
2657 if (!args->timeout_ns) {
2662 drm_gem_object_unreference(&obj->base);
2663 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2664 mutex_unlock(&dev->struct_mutex);
2666 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2668 args->timeout_ns = timespec_to_ns(timeout);
2672 drm_gem_object_unreference(&obj->base);
2673 mutex_unlock(&dev->struct_mutex);
2678 * i915_gem_object_sync - sync an object to a ring.
2680 * @obj: object which may be in use on another ring.
2681 * @to: ring we wish to use the object on. May be NULL.
2683 * This code is meant to abstract object synchronization with the GPU.
2684 * Calling with NULL implies synchronizing the object with the CPU
2685 * rather than a particular GPU ring.
2687 * Returns 0 if successful, else propagates up the lower layer error.
2690 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2691 struct intel_ring_buffer *to)
2693 struct intel_ring_buffer *from = obj->ring;
2697 if (from == NULL || to == from)
2700 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2701 return i915_gem_object_wait_rendering(obj, false);
2703 idx = intel_ring_sync_index(from, to);
2705 seqno = obj->last_read_seqno;
2706 if (seqno <= from->semaphore.sync_seqno[idx])
2709 ret = i915_gem_check_olr(obj->ring, seqno);
2713 trace_i915_gem_ring_sync_to(from, to, seqno);
2714 ret = to->semaphore.sync_to(to, from, seqno);
2716 /* We use last_read_seqno because sync_to()
2717 * might have just caused seqno wrap under
2720 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2725 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2727 u32 old_write_domain, old_read_domains;
2729 /* Force a pagefault for domain tracking on next user access */
2730 i915_gem_release_mmap(obj);
2732 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2735 /* Wait for any direct GTT access to complete */
2738 old_read_domains = obj->base.read_domains;
2739 old_write_domain = obj->base.write_domain;
2741 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2742 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2744 trace_i915_gem_object_change_domain(obj,
2749 int i915_vma_unbind(struct i915_vma *vma)
2751 struct drm_i915_gem_object *obj = vma->obj;
2752 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2755 if (list_empty(&vma->vma_link))
2758 if (!drm_mm_node_allocated(&vma->node)) {
2759 i915_gem_vma_destroy(vma);
2766 BUG_ON(obj->pages == NULL);
2768 ret = i915_gem_object_finish_gpu(obj);
2771 /* Continue on if we fail due to EIO, the GPU is hung so we
2772 * should be safe and we need to cleanup or else we might
2773 * cause memory corruption through use-after-free.
2776 if (i915_is_ggtt(vma->vm)) {
2777 i915_gem_object_finish_gtt(obj);
2779 /* release the fence reg _after_ flushing */
2780 ret = i915_gem_object_put_fence(obj);
2785 trace_i915_vma_unbind(vma);
2787 vma->unbind_vma(vma);
2789 i915_gem_gtt_finish_object(obj);
2791 list_del_init(&vma->mm_list);
2792 /* Avoid an unnecessary call to unbind on rebind. */
2793 if (i915_is_ggtt(vma->vm))
2794 obj->map_and_fenceable = true;
2796 drm_mm_remove_node(&vma->node);
2797 i915_gem_vma_destroy(vma);
2799 /* Since the unbound list is global, only move to that list if
2800 * no more VMAs exist. */
2801 if (list_empty(&obj->vma_list))
2802 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2804 /* And finally now the object is completely decoupled from this vma,
2805 * we can drop its hold on the backing storage and allow it to be
2806 * reaped by the shrinker.
2808 i915_gem_object_unpin_pages(obj);
2813 int i915_gpu_idle(struct drm_device *dev)
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_ring_buffer *ring;
2819 /* Flush everything onto the inactive list. */
2820 for_each_ring(ring, dev_priv, i) {
2821 ret = i915_switch_context(ring, ring->default_context);
2825 ret = intel_ring_idle(ring);
2833 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2834 struct drm_i915_gem_object *obj)
2836 struct drm_i915_private *dev_priv = dev->dev_private;
2838 int fence_pitch_shift;
2840 if (INTEL_INFO(dev)->gen >= 6) {
2841 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2842 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2844 fence_reg = FENCE_REG_965_0;
2845 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2848 fence_reg += reg * 8;
2850 /* To w/a incoherency with non-atomic 64-bit register updates,
2851 * we split the 64-bit update into two 32-bit writes. In order
2852 * for a partial fence not to be evaluated between writes, we
2853 * precede the update with write to turn off the fence register,
2854 * and only enable the fence as the last step.
2856 * For extra levels of paranoia, we make sure each step lands
2857 * before applying the next step.
2859 I915_WRITE(fence_reg, 0);
2860 POSTING_READ(fence_reg);
2863 u32 size = i915_gem_obj_ggtt_size(obj);
2866 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2868 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2869 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2870 if (obj->tiling_mode == I915_TILING_Y)
2871 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2872 val |= I965_FENCE_REG_VALID;
2874 I915_WRITE(fence_reg + 4, val >> 32);
2875 POSTING_READ(fence_reg + 4);
2877 I915_WRITE(fence_reg + 0, val);
2878 POSTING_READ(fence_reg);
2880 I915_WRITE(fence_reg + 4, 0);
2881 POSTING_READ(fence_reg + 4);
2885 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2886 struct drm_i915_gem_object *obj)
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2892 u32 size = i915_gem_obj_ggtt_size(obj);
2896 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2897 (size & -size) != size ||
2898 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2899 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2900 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2902 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2907 /* Note: pitch better be a power of two tile widths */
2908 pitch_val = obj->stride / tile_width;
2909 pitch_val = ffs(pitch_val) - 1;
2911 val = i915_gem_obj_ggtt_offset(obj);
2912 if (obj->tiling_mode == I915_TILING_Y)
2913 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2914 val |= I915_FENCE_SIZE_BITS(size);
2915 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2916 val |= I830_FENCE_REG_VALID;
2921 reg = FENCE_REG_830_0 + reg * 4;
2923 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2925 I915_WRITE(reg, val);
2929 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2930 struct drm_i915_gem_object *obj)
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2936 u32 size = i915_gem_obj_ggtt_size(obj);
2939 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2940 (size & -size) != size ||
2941 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2942 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2943 i915_gem_obj_ggtt_offset(obj), size);
2945 pitch_val = obj->stride / 128;
2946 pitch_val = ffs(pitch_val) - 1;
2948 val = i915_gem_obj_ggtt_offset(obj);
2949 if (obj->tiling_mode == I915_TILING_Y)
2950 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2951 val |= I830_FENCE_SIZE_BITS(size);
2952 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2953 val |= I830_FENCE_REG_VALID;
2957 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2958 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2961 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2963 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2966 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2967 struct drm_i915_gem_object *obj)
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2971 /* Ensure that all CPU reads are completed before installing a fence
2972 * and all writes before removing the fence.
2974 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2977 WARN(obj && (!obj->stride || !obj->tiling_mode),
2978 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2979 obj->stride, obj->tiling_mode);
2981 switch (INTEL_INFO(dev)->gen) {
2986 case 4: i965_write_fence_reg(dev, reg, obj); break;
2987 case 3: i915_write_fence_reg(dev, reg, obj); break;
2988 case 2: i830_write_fence_reg(dev, reg, obj); break;
2992 /* And similarly be paranoid that no direct access to this region
2993 * is reordered to before the fence is installed.
2995 if (i915_gem_object_needs_mb(obj))
2999 static inline int fence_number(struct drm_i915_private *dev_priv,
3000 struct drm_i915_fence_reg *fence)
3002 return fence - dev_priv->fence_regs;
3005 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3006 struct drm_i915_fence_reg *fence,
3009 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3010 int reg = fence_number(dev_priv, fence);
3012 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3015 obj->fence_reg = reg;
3017 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3019 obj->fence_reg = I915_FENCE_REG_NONE;
3021 list_del_init(&fence->lru_list);
3023 obj->fence_dirty = false;
3027 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3029 if (obj->last_fenced_seqno) {
3030 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3034 obj->last_fenced_seqno = 0;
3037 obj->fenced_gpu_access = false;
3042 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3044 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3045 struct drm_i915_fence_reg *fence;
3048 ret = i915_gem_object_wait_fence(obj);
3052 if (obj->fence_reg == I915_FENCE_REG_NONE)
3055 fence = &dev_priv->fence_regs[obj->fence_reg];
3057 if (WARN_ON(fence->pin_count))
3060 i915_gem_object_fence_lost(obj);
3061 i915_gem_object_update_fence(obj, fence, false);
3066 static struct drm_i915_fence_reg *
3067 i915_find_fence_reg(struct drm_device *dev)
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct drm_i915_fence_reg *reg, *avail;
3073 /* First try to find a free reg */
3075 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3076 reg = &dev_priv->fence_regs[i];
3080 if (!reg->pin_count)
3087 /* None available, try to steal one or wait for a user to finish */
3088 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3096 /* Wait for completion of pending flips which consume fences */
3097 if (intel_has_pending_fb_unpin(dev))
3098 return ERR_PTR(-EAGAIN);
3100 return ERR_PTR(-EDEADLK);
3104 * i915_gem_object_get_fence - set up fencing for an object
3105 * @obj: object to map through a fence reg
3107 * When mapping objects through the GTT, userspace wants to be able to write
3108 * to them without having to worry about swizzling if the object is tiled.
3109 * This function walks the fence regs looking for a free one for @obj,
3110 * stealing one if it can't find any.
3112 * It then sets up the reg based on the object's properties: address, pitch
3113 * and tiling format.
3115 * For an untiled surface, this removes any existing fence.
3118 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3120 struct drm_device *dev = obj->base.dev;
3121 struct drm_i915_private *dev_priv = dev->dev_private;
3122 bool enable = obj->tiling_mode != I915_TILING_NONE;
3123 struct drm_i915_fence_reg *reg;
3126 /* Have we updated the tiling parameters upon the object and so
3127 * will need to serialise the write to the associated fence register?
3129 if (obj->fence_dirty) {
3130 ret = i915_gem_object_wait_fence(obj);
3135 /* Just update our place in the LRU if our fence is getting reused. */
3136 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3137 reg = &dev_priv->fence_regs[obj->fence_reg];
3138 if (!obj->fence_dirty) {
3139 list_move_tail(®->lru_list,
3140 &dev_priv->mm.fence_list);
3143 } else if (enable) {
3144 reg = i915_find_fence_reg(dev);
3146 return PTR_ERR(reg);
3149 struct drm_i915_gem_object *old = reg->obj;
3151 ret = i915_gem_object_wait_fence(old);
3155 i915_gem_object_fence_lost(old);
3160 i915_gem_object_update_fence(obj, reg, enable);
3165 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3166 struct drm_mm_node *gtt_space,
3167 unsigned long cache_level)
3169 struct drm_mm_node *other;
3171 /* On non-LLC machines we have to be careful when putting differing
3172 * types of snoopable memory together to avoid the prefetcher
3173 * crossing memory domains and dying.
3178 if (!drm_mm_node_allocated(gtt_space))
3181 if (list_empty(>t_space->node_list))
3184 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3185 if (other->allocated && !other->hole_follows && other->color != cache_level)
3188 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3189 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3195 static void i915_gem_verify_gtt(struct drm_device *dev)
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 struct drm_i915_gem_object *obj;
3202 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3203 if (obj->gtt_space == NULL) {
3204 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3209 if (obj->cache_level != obj->gtt_space->color) {
3210 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3211 i915_gem_obj_ggtt_offset(obj),
3212 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3214 obj->gtt_space->color);
3219 if (!i915_gem_valid_gtt_space(dev,
3221 obj->cache_level)) {
3222 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3223 i915_gem_obj_ggtt_offset(obj),
3224 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3236 * Finds free space in the GTT aperture and binds the object there.
3238 static struct i915_vma *
3239 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3240 struct i915_address_space *vm,
3244 struct drm_device *dev = obj->base.dev;
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246 u32 size, fence_size, fence_alignment, unfenced_alignment;
3248 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3249 struct i915_vma *vma;
3252 fence_size = i915_gem_get_gtt_size(dev,
3255 fence_alignment = i915_gem_get_gtt_alignment(dev,
3257 obj->tiling_mode, true);
3258 unfenced_alignment =
3259 i915_gem_get_gtt_alignment(dev,
3261 obj->tiling_mode, false);
3264 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3266 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3267 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3268 return ERR_PTR(-EINVAL);
3271 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3273 /* If the object is bigger than the entire aperture, reject it early
3274 * before evicting everything in a vain attempt to find space.
3276 if (obj->base.size > gtt_max) {
3277 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3279 flags & PIN_MAPPABLE ? "mappable" : "total",
3281 return ERR_PTR(-E2BIG);
3284 ret = i915_gem_object_get_pages(obj);
3286 return ERR_PTR(ret);
3288 i915_gem_object_pin_pages(obj);
3290 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3295 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3297 obj->cache_level, 0, gtt_max,
3298 DRM_MM_SEARCH_DEFAULT,
3299 DRM_MM_CREATE_DEFAULT);
3301 ret = i915_gem_evict_something(dev, vm, size, alignment,
3302 obj->cache_level, flags);
3308 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3309 obj->cache_level))) {
3311 goto err_remove_node;
3314 ret = i915_gem_gtt_prepare_object(obj);
3316 goto err_remove_node;
3318 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3319 list_add_tail(&vma->mm_list, &vm->inactive_list);
3321 if (i915_is_ggtt(vm)) {
3322 bool mappable, fenceable;
3324 fenceable = (vma->node.size == fence_size &&
3325 (vma->node.start & (fence_alignment - 1)) == 0);
3327 mappable = (vma->node.start + obj->base.size <=
3328 dev_priv->gtt.mappable_end);
3330 obj->map_and_fenceable = mappable && fenceable;
3333 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3335 trace_i915_vma_bind(vma, flags);
3336 vma->bind_vma(vma, obj->cache_level,
3337 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3339 i915_gem_verify_gtt(dev);
3343 drm_mm_remove_node(&vma->node);
3345 i915_gem_vma_destroy(vma);
3348 i915_gem_object_unpin_pages(obj);
3353 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3356 /* If we don't have a page list set up, then we're not pinned
3357 * to GPU, and we can ignore the cache flush because it'll happen
3358 * again at bind time.
3360 if (obj->pages == NULL)
3364 * Stolen memory is always coherent with the GPU as it is explicitly
3365 * marked as wc by the system, or the system is cache-coherent.
3370 /* If the GPU is snooping the contents of the CPU cache,
3371 * we do not need to manually clear the CPU cache lines. However,
3372 * the caches are only snooped when the render cache is
3373 * flushed/invalidated. As we always have to emit invalidations
3374 * and flushes when moving into and out of the RENDER domain, correct
3375 * snooping behaviour occurs naturally as the result of our domain
3378 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3381 trace_i915_gem_object_clflush(obj);
3382 drm_clflush_sg(obj->pages);
3387 /** Flushes the GTT write domain for the object if it's dirty. */
3389 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3391 uint32_t old_write_domain;
3393 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3396 /* No actual flushing is required for the GTT write domain. Writes
3397 * to it immediately go to main memory as far as we know, so there's
3398 * no chipset flush. It also doesn't land in render cache.
3400 * However, we do have to enforce the order so that all writes through
3401 * the GTT land before any writes to the device, such as updates to
3406 old_write_domain = obj->base.write_domain;
3407 obj->base.write_domain = 0;
3409 trace_i915_gem_object_change_domain(obj,
3410 obj->base.read_domains,
3414 /** Flushes the CPU write domain for the object if it's dirty. */
3416 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3419 uint32_t old_write_domain;
3421 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3424 if (i915_gem_clflush_object(obj, force))
3425 i915_gem_chipset_flush(obj->base.dev);
3427 old_write_domain = obj->base.write_domain;
3428 obj->base.write_domain = 0;
3430 trace_i915_gem_object_change_domain(obj,
3431 obj->base.read_domains,
3436 * Moves a single object to the GTT read, and possibly write domain.
3438 * This function returns when the move is complete, including waiting on
3442 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3444 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3445 uint32_t old_write_domain, old_read_domains;
3448 /* Not valid to be called on unbound objects. */
3449 if (!i915_gem_obj_bound_any(obj))
3452 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3455 ret = i915_gem_object_wait_rendering(obj, !write);
3459 i915_gem_object_retire(obj);
3460 i915_gem_object_flush_cpu_write_domain(obj, false);
3462 /* Serialise direct access to this object with the barriers for
3463 * coherent writes from the GPU, by effectively invalidating the
3464 * GTT domain upon first access.
3466 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3469 old_write_domain = obj->base.write_domain;
3470 old_read_domains = obj->base.read_domains;
3472 /* It should now be out of any other write domains, and we can update
3473 * the domain values for our changes.
3475 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3476 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3478 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3479 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3483 trace_i915_gem_object_change_domain(obj,
3487 /* And bump the LRU for this access */
3488 if (i915_gem_object_is_inactive(obj)) {
3489 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3491 list_move_tail(&vma->mm_list,
3492 &dev_priv->gtt.base.inactive_list);
3499 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3500 enum i915_cache_level cache_level)
3502 struct drm_device *dev = obj->base.dev;
3503 struct i915_vma *vma, *next;
3506 if (obj->cache_level == cache_level)
3509 if (i915_gem_obj_is_pinned(obj)) {
3510 DRM_DEBUG("can not change the cache level of pinned objects\n");
3514 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3515 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3516 ret = i915_vma_unbind(vma);
3522 if (i915_gem_obj_bound_any(obj)) {
3523 ret = i915_gem_object_finish_gpu(obj);
3527 i915_gem_object_finish_gtt(obj);
3529 /* Before SandyBridge, you could not use tiling or fence
3530 * registers with snooped memory, so relinquish any fences
3531 * currently pointing to our region in the aperture.
3533 if (INTEL_INFO(dev)->gen < 6) {
3534 ret = i915_gem_object_put_fence(obj);
3539 list_for_each_entry(vma, &obj->vma_list, vma_link)
3540 if (drm_mm_node_allocated(&vma->node))
3541 vma->bind_vma(vma, cache_level,
3542 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3545 list_for_each_entry(vma, &obj->vma_list, vma_link)
3546 vma->node.color = cache_level;
3547 obj->cache_level = cache_level;
3549 if (cpu_write_needs_clflush(obj)) {
3550 u32 old_read_domains, old_write_domain;
3552 /* If we're coming from LLC cached, then we haven't
3553 * actually been tracking whether the data is in the
3554 * CPU cache or not, since we only allow one bit set
3555 * in obj->write_domain and have been skipping the clflushes.
3556 * Just set it to the CPU cache for now.
3558 i915_gem_object_retire(obj);
3559 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3561 old_read_domains = obj->base.read_domains;
3562 old_write_domain = obj->base.write_domain;
3564 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3565 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3567 trace_i915_gem_object_change_domain(obj,
3572 i915_gem_verify_gtt(dev);
3576 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3577 struct drm_file *file)
3579 struct drm_i915_gem_caching *args = data;
3580 struct drm_i915_gem_object *obj;
3583 ret = i915_mutex_lock_interruptible(dev);
3587 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3588 if (&obj->base == NULL) {
3593 switch (obj->cache_level) {
3594 case I915_CACHE_LLC:
3595 case I915_CACHE_L3_LLC:
3596 args->caching = I915_CACHING_CACHED;
3600 args->caching = I915_CACHING_DISPLAY;
3604 args->caching = I915_CACHING_NONE;
3608 drm_gem_object_unreference(&obj->base);
3610 mutex_unlock(&dev->struct_mutex);
3614 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3615 struct drm_file *file)
3617 struct drm_i915_gem_caching *args = data;
3618 struct drm_i915_gem_object *obj;
3619 enum i915_cache_level level;
3622 switch (args->caching) {
3623 case I915_CACHING_NONE:
3624 level = I915_CACHE_NONE;
3626 case I915_CACHING_CACHED:
3627 level = I915_CACHE_LLC;
3629 case I915_CACHING_DISPLAY:
3630 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3636 ret = i915_mutex_lock_interruptible(dev);
3640 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3641 if (&obj->base == NULL) {
3646 ret = i915_gem_object_set_cache_level(obj, level);
3648 drm_gem_object_unreference(&obj->base);
3650 mutex_unlock(&dev->struct_mutex);
3654 static bool is_pin_display(struct drm_i915_gem_object *obj)
3656 struct i915_vma *vma;
3658 if (list_empty(&obj->vma_list))
3661 vma = i915_gem_obj_to_ggtt(obj);
3665 /* There are 3 sources that pin objects:
3666 * 1. The display engine (scanouts, sprites, cursors);
3667 * 2. Reservations for execbuffer;
3670 * We can ignore reservations as we hold the struct_mutex and
3671 * are only called outside of the reservation path. The user
3672 * can only increment pin_count once, and so if after
3673 * subtracting the potential reference by the user, any pin_count
3674 * remains, it must be due to another use by the display engine.
3676 return vma->pin_count - !!obj->user_pin_count;
3680 * Prepare buffer for display plane (scanout, cursors, etc).
3681 * Can be called from an uninterruptible phase (modesetting) and allows
3682 * any flushes to be pipelined (for pageflips).
3685 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3687 struct intel_ring_buffer *pipelined)
3689 u32 old_read_domains, old_write_domain;
3690 bool was_pin_display;
3693 if (pipelined != obj->ring) {
3694 ret = i915_gem_object_sync(obj, pipelined);
3699 /* Mark the pin_display early so that we account for the
3700 * display coherency whilst setting up the cache domains.
3702 was_pin_display = obj->pin_display;
3703 obj->pin_display = true;
3705 /* The display engine is not coherent with the LLC cache on gen6. As
3706 * a result, we make sure that the pinning that is about to occur is
3707 * done with uncached PTEs. This is lowest common denominator for all
3710 * However for gen6+, we could do better by using the GFDT bit instead
3711 * of uncaching, which would allow us to flush all the LLC-cached data
3712 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3714 ret = i915_gem_object_set_cache_level(obj,
3715 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3717 goto err_unpin_display;
3719 /* As the user may map the buffer once pinned in the display plane
3720 * (e.g. libkms for the bootup splash), we have to ensure that we
3721 * always use map_and_fenceable for all scanout buffers.
3723 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3725 goto err_unpin_display;
3727 i915_gem_object_flush_cpu_write_domain(obj, true);
3729 old_write_domain = obj->base.write_domain;
3730 old_read_domains = obj->base.read_domains;
3732 /* It should now be out of any other write domains, and we can update
3733 * the domain values for our changes.
3735 obj->base.write_domain = 0;
3736 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3738 trace_i915_gem_object_change_domain(obj,
3745 WARN_ON(was_pin_display != is_pin_display(obj));
3746 obj->pin_display = was_pin_display;
3751 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3753 i915_gem_object_ggtt_unpin(obj);
3754 obj->pin_display = is_pin_display(obj);
3758 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3762 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3765 ret = i915_gem_object_wait_rendering(obj, false);
3769 /* Ensure that we invalidate the GPU's caches and TLBs. */
3770 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3775 * Moves a single object to the CPU read, and possibly write domain.
3777 * This function returns when the move is complete, including waiting on
3781 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3783 uint32_t old_write_domain, old_read_domains;
3786 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3789 ret = i915_gem_object_wait_rendering(obj, !write);
3793 i915_gem_object_retire(obj);
3794 i915_gem_object_flush_gtt_write_domain(obj);
3796 old_write_domain = obj->base.write_domain;
3797 old_read_domains = obj->base.read_domains;
3799 /* Flush the CPU cache if it's still invalid. */
3800 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3801 i915_gem_clflush_object(obj, false);
3803 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3806 /* It should now be out of any other write domains, and we can update
3807 * the domain values for our changes.
3809 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3811 /* If we're writing through the CPU, then the GPU read domains will
3812 * need to be invalidated at next use.
3815 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3816 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3819 trace_i915_gem_object_change_domain(obj,
3826 /* Throttle our rendering by waiting until the ring has completed our requests
3827 * emitted over 20 msec ago.
3829 * Note that if we were to use the current jiffies each time around the loop,
3830 * we wouldn't escape the function with any frames outstanding if the time to
3831 * render a frame was over 20ms.
3833 * This should get us reasonable parallelism between CPU and GPU but also
3834 * relatively low latency when blocking on a particular request to finish.
3837 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct drm_i915_file_private *file_priv = file->driver_priv;
3841 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3842 struct drm_i915_gem_request *request;
3843 struct intel_ring_buffer *ring = NULL;
3844 unsigned reset_counter;
3848 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3852 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3856 spin_lock(&file_priv->mm.lock);
3857 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3858 if (time_after_eq(request->emitted_jiffies, recent_enough))
3861 ring = request->ring;
3862 seqno = request->seqno;
3864 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3865 spin_unlock(&file_priv->mm.lock);
3870 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
3872 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3878 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3879 struct i915_address_space *vm,
3883 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3884 struct i915_vma *vma;
3887 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
3890 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
3893 vma = i915_gem_obj_to_vma(obj, vm);
3895 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3899 vma->node.start & (alignment - 1)) ||
3900 (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) {
3901 WARN(vma->pin_count,
3902 "bo is already pinned with incorrect alignment:"
3903 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3904 " obj->map_and_fenceable=%d\n",
3905 i915_gem_obj_offset(obj, vm), alignment,
3906 flags & PIN_MAPPABLE,
3907 obj->map_and_fenceable);
3908 ret = i915_vma_unbind(vma);
3916 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
3917 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
3919 return PTR_ERR(vma);
3922 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
3923 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
3926 if (flags & PIN_MAPPABLE)
3927 obj->pin_mappable |= true;
3933 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3935 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3938 BUG_ON(vma->pin_count == 0);
3939 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3941 if (--vma->pin_count == 0)
3942 obj->pin_mappable = false;
3946 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
3948 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3949 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3950 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
3952 WARN_ON(!ggtt_vma ||
3953 dev_priv->fence_regs[obj->fence_reg].pin_count >
3954 ggtt_vma->pin_count);
3955 dev_priv->fence_regs[obj->fence_reg].pin_count++;
3962 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
3964 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3965 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3966 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
3967 dev_priv->fence_regs[obj->fence_reg].pin_count--;
3972 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3973 struct drm_file *file)
3975 struct drm_i915_gem_pin *args = data;
3976 struct drm_i915_gem_object *obj;
3979 if (INTEL_INFO(dev)->gen >= 6)
3982 ret = i915_mutex_lock_interruptible(dev);
3986 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3987 if (&obj->base == NULL) {
3992 if (obj->madv != I915_MADV_WILLNEED) {
3993 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
3998 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3999 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4005 if (obj->user_pin_count == ULONG_MAX) {
4010 if (obj->user_pin_count == 0) {
4011 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4016 obj->user_pin_count++;
4017 obj->pin_filp = file;
4019 args->offset = i915_gem_obj_ggtt_offset(obj);
4021 drm_gem_object_unreference(&obj->base);
4023 mutex_unlock(&dev->struct_mutex);
4028 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4029 struct drm_file *file)
4031 struct drm_i915_gem_pin *args = data;
4032 struct drm_i915_gem_object *obj;
4035 ret = i915_mutex_lock_interruptible(dev);
4039 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4040 if (&obj->base == NULL) {
4045 if (obj->pin_filp != file) {
4046 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4051 obj->user_pin_count--;
4052 if (obj->user_pin_count == 0) {
4053 obj->pin_filp = NULL;
4054 i915_gem_object_ggtt_unpin(obj);
4058 drm_gem_object_unreference(&obj->base);
4060 mutex_unlock(&dev->struct_mutex);
4065 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4066 struct drm_file *file)
4068 struct drm_i915_gem_busy *args = data;
4069 struct drm_i915_gem_object *obj;
4072 ret = i915_mutex_lock_interruptible(dev);
4076 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4077 if (&obj->base == NULL) {
4082 /* Count all active objects as busy, even if they are currently not used
4083 * by the gpu. Users of this interface expect objects to eventually
4084 * become non-busy without any further actions, therefore emit any
4085 * necessary flushes here.
4087 ret = i915_gem_object_flush_active(obj);
4089 args->busy = obj->active;
4091 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4092 args->busy |= intel_ring_flag(obj->ring) << 16;
4095 drm_gem_object_unreference(&obj->base);
4097 mutex_unlock(&dev->struct_mutex);
4102 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4103 struct drm_file *file_priv)
4105 return i915_gem_ring_throttle(dev, file_priv);
4109 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4110 struct drm_file *file_priv)
4112 struct drm_i915_gem_madvise *args = data;
4113 struct drm_i915_gem_object *obj;
4116 switch (args->madv) {
4117 case I915_MADV_DONTNEED:
4118 case I915_MADV_WILLNEED:
4124 ret = i915_mutex_lock_interruptible(dev);
4128 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4129 if (&obj->base == NULL) {
4134 if (i915_gem_obj_is_pinned(obj)) {
4139 if (obj->madv != __I915_MADV_PURGED)
4140 obj->madv = args->madv;
4142 /* if the object is no longer attached, discard its backing storage */
4143 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4144 i915_gem_object_truncate(obj);
4146 args->retained = obj->madv != __I915_MADV_PURGED;
4149 drm_gem_object_unreference(&obj->base);
4151 mutex_unlock(&dev->struct_mutex);
4155 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4156 const struct drm_i915_gem_object_ops *ops)
4158 INIT_LIST_HEAD(&obj->global_list);
4159 INIT_LIST_HEAD(&obj->ring_list);
4160 INIT_LIST_HEAD(&obj->obj_exec_link);
4161 INIT_LIST_HEAD(&obj->vma_list);
4165 obj->fence_reg = I915_FENCE_REG_NONE;
4166 obj->madv = I915_MADV_WILLNEED;
4167 /* Avoid an unnecessary call to unbind on the first bind. */
4168 obj->map_and_fenceable = true;
4170 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4173 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4174 .get_pages = i915_gem_object_get_pages_gtt,
4175 .put_pages = i915_gem_object_put_pages_gtt,
4178 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4181 struct drm_i915_gem_object *obj;
4182 struct address_space *mapping;
4185 obj = i915_gem_object_alloc(dev);
4189 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4190 i915_gem_object_free(obj);
4194 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4195 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4196 /* 965gm cannot relocate objects above 4GiB. */
4197 mask &= ~__GFP_HIGHMEM;
4198 mask |= __GFP_DMA32;
4201 mapping = file_inode(obj->base.filp)->i_mapping;
4202 mapping_set_gfp_mask(mapping, mask);
4204 i915_gem_object_init(obj, &i915_gem_object_ops);
4206 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4207 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4210 /* On some devices, we can have the GPU use the LLC (the CPU
4211 * cache) for about a 10% performance improvement
4212 * compared to uncached. Graphics requests other than
4213 * display scanout are coherent with the CPU in
4214 * accessing this cache. This means in this mode we
4215 * don't need to clflush on the CPU side, and on the
4216 * GPU side we only need to flush internal caches to
4217 * get data visible to the CPU.
4219 * However, we maintain the display planes as UC, and so
4220 * need to rebind when first used as such.
4222 obj->cache_level = I915_CACHE_LLC;
4224 obj->cache_level = I915_CACHE_NONE;
4226 trace_i915_gem_object_create(obj);
4231 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4233 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4234 struct drm_device *dev = obj->base.dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct i915_vma *vma, *next;
4238 intel_runtime_pm_get(dev_priv);
4240 trace_i915_gem_object_destroy(obj);
4243 i915_gem_detach_phys_object(dev, obj);
4245 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4249 ret = i915_vma_unbind(vma);
4250 if (WARN_ON(ret == -ERESTARTSYS)) {
4251 bool was_interruptible;
4253 was_interruptible = dev_priv->mm.interruptible;
4254 dev_priv->mm.interruptible = false;
4256 WARN_ON(i915_vma_unbind(vma));
4258 dev_priv->mm.interruptible = was_interruptible;
4262 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4263 * before progressing. */
4265 i915_gem_object_unpin_pages(obj);
4267 if (WARN_ON(obj->pages_pin_count))
4268 obj->pages_pin_count = 0;
4269 i915_gem_object_put_pages(obj);
4270 i915_gem_object_free_mmap_offset(obj);
4271 i915_gem_object_release_stolen(obj);
4275 if (obj->base.import_attach)
4276 drm_prime_gem_destroy(&obj->base, NULL);
4278 if (obj->ops->release)
4279 obj->ops->release(obj);
4281 drm_gem_object_release(&obj->base);
4282 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4285 i915_gem_object_free(obj);
4287 intel_runtime_pm_put(dev_priv);
4290 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4291 struct i915_address_space *vm)
4293 struct i915_vma *vma;
4294 list_for_each_entry(vma, &obj->vma_list, vma_link)
4301 void i915_gem_vma_destroy(struct i915_vma *vma)
4303 WARN_ON(vma->node.allocated);
4305 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4306 if (!list_empty(&vma->exec_list))
4309 list_del(&vma->vma_link);
4315 i915_gem_stop_ringbuffers(struct drm_device *dev)
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_ring_buffer *ring;
4321 for_each_ring(ring, dev_priv, i)
4322 intel_stop_ring_buffer(ring);
4326 i915_gem_suspend(struct drm_device *dev)
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4331 mutex_lock(&dev->struct_mutex);
4332 if (dev_priv->ums.mm_suspended)
4335 ret = i915_gpu_idle(dev);
4339 i915_gem_retire_requests(dev);
4341 /* Under UMS, be paranoid and evict. */
4342 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4343 i915_gem_evict_everything(dev);
4345 i915_kernel_lost_context(dev);
4346 i915_gem_stop_ringbuffers(dev);
4348 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4349 * We need to replace this with a semaphore, or something.
4350 * And not confound ums.mm_suspended!
4352 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4354 mutex_unlock(&dev->struct_mutex);
4356 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4357 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4358 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4363 mutex_unlock(&dev->struct_mutex);
4367 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4369 struct drm_device *dev = ring->dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4372 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4375 if (!HAS_L3_DPF(dev) || !remap_info)
4378 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4383 * Note: We do not worry about the concurrent register cacheline hang
4384 * here because no other code should access these registers other than
4385 * at initialization time.
4387 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4388 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4389 intel_ring_emit(ring, reg_base + i);
4390 intel_ring_emit(ring, remap_info[i/4]);
4393 intel_ring_advance(ring);
4398 void i915_gem_init_swizzling(struct drm_device *dev)
4400 struct drm_i915_private *dev_priv = dev->dev_private;
4402 if (INTEL_INFO(dev)->gen < 5 ||
4403 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4406 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4407 DISP_TILE_SURFACE_SWIZZLING);
4412 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4414 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4415 else if (IS_GEN7(dev))
4416 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4417 else if (IS_GEN8(dev))
4418 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4424 intel_enable_blt(struct drm_device *dev)
4429 /* The blitter was dysfunctional on early prototypes */
4430 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4431 DRM_INFO("BLT not supported on this pre-production hardware;"
4432 " graphics performance will be degraded.\n");
4439 static int i915_gem_init_rings(struct drm_device *dev)
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4444 ret = intel_init_render_ring_buffer(dev);
4449 ret = intel_init_bsd_ring_buffer(dev);
4451 goto cleanup_render_ring;
4454 if (intel_enable_blt(dev)) {
4455 ret = intel_init_blt_ring_buffer(dev);
4457 goto cleanup_bsd_ring;
4460 if (HAS_VEBOX(dev)) {
4461 ret = intel_init_vebox_ring_buffer(dev);
4463 goto cleanup_blt_ring;
4466 if (HAS_BSD2(dev)) {
4467 ret = intel_init_bsd2_ring_buffer(dev);
4469 goto cleanup_vebox_ring;
4472 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4474 goto cleanup_bsd2_ring;
4479 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4481 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4483 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4485 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4486 cleanup_render_ring:
4487 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4493 i915_gem_init_hw(struct drm_device *dev)
4495 struct drm_i915_private *dev_priv = dev->dev_private;
4498 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4501 if (dev_priv->ellc_size)
4502 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4504 if (IS_HASWELL(dev))
4505 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4506 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4508 if (HAS_PCH_NOP(dev)) {
4509 if (IS_IVYBRIDGE(dev)) {
4510 u32 temp = I915_READ(GEN7_MSG_CTL);
4511 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4512 I915_WRITE(GEN7_MSG_CTL, temp);
4513 } else if (INTEL_INFO(dev)->gen >= 7) {
4514 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4515 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4516 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4520 i915_gem_init_swizzling(dev);
4522 ret = i915_gem_init_rings(dev);
4526 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4527 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4530 * XXX: Contexts should only be initialized once. Doing a switch to the
4531 * default context switch however is something we'd like to do after
4532 * reset or thaw (the latter may not actually be necessary for HW, but
4533 * goes with our code better). Context switching requires rings (for
4534 * the do_switch), but before enabling PPGTT. So don't move this.
4536 ret = i915_gem_context_enable(dev_priv);
4537 if (ret && ret != -EIO) {
4538 DRM_ERROR("Context enable failed %d\n", ret);
4539 i915_gem_cleanup_ringbuffer(dev);
4545 int i915_gem_init(struct drm_device *dev)
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4550 mutex_lock(&dev->struct_mutex);
4552 if (IS_VALLEYVIEW(dev)) {
4553 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4554 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4555 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4556 VLV_GTLC_ALLOWWAKEACK), 10))
4557 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4560 i915_gem_init_userptr(dev);
4561 i915_gem_init_global_gtt(dev);
4563 ret = i915_gem_context_init(dev);
4565 mutex_unlock(&dev->struct_mutex);
4569 ret = i915_gem_init_hw(dev);
4571 /* Allow ring initialisation to fail by marking the GPU as
4572 * wedged. But we only want to do this where the GPU is angry,
4573 * for all other failure, such as an allocation failure, bail.
4575 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4576 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4579 mutex_unlock(&dev->struct_mutex);
4581 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4582 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4583 dev_priv->dri1.allow_batchbuffer = 1;
4588 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 struct intel_ring_buffer *ring;
4594 for_each_ring(ring, dev_priv, i)
4595 intel_cleanup_ring_buffer(ring);
4599 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4600 struct drm_file *file_priv)
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4605 if (drm_core_check_feature(dev, DRIVER_MODESET))
4608 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4609 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4610 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4613 mutex_lock(&dev->struct_mutex);
4614 dev_priv->ums.mm_suspended = 0;
4616 ret = i915_gem_init_hw(dev);
4618 mutex_unlock(&dev->struct_mutex);
4622 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4624 ret = drm_irq_install(dev, dev->pdev->irq);
4626 goto cleanup_ringbuffer;
4627 mutex_unlock(&dev->struct_mutex);
4632 i915_gem_cleanup_ringbuffer(dev);
4633 dev_priv->ums.mm_suspended = 1;
4634 mutex_unlock(&dev->struct_mutex);
4640 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4641 struct drm_file *file_priv)
4643 if (drm_core_check_feature(dev, DRIVER_MODESET))
4646 mutex_lock(&dev->struct_mutex);
4647 drm_irq_uninstall(dev);
4648 mutex_unlock(&dev->struct_mutex);
4650 return i915_gem_suspend(dev);
4654 i915_gem_lastclose(struct drm_device *dev)
4658 if (drm_core_check_feature(dev, DRIVER_MODESET))
4661 ret = i915_gem_suspend(dev);
4663 DRM_ERROR("failed to idle hardware: %d\n", ret);
4667 init_ring_lists(struct intel_ring_buffer *ring)
4669 INIT_LIST_HEAD(&ring->active_list);
4670 INIT_LIST_HEAD(&ring->request_list);
4673 void i915_init_vm(struct drm_i915_private *dev_priv,
4674 struct i915_address_space *vm)
4676 if (!i915_is_ggtt(vm))
4677 drm_mm_init(&vm->mm, vm->start, vm->total);
4678 vm->dev = dev_priv->dev;
4679 INIT_LIST_HEAD(&vm->active_list);
4680 INIT_LIST_HEAD(&vm->inactive_list);
4681 INIT_LIST_HEAD(&vm->global_link);
4682 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4686 i915_gem_load(struct drm_device *dev)
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4692 kmem_cache_create("i915_gem_object",
4693 sizeof(struct drm_i915_gem_object), 0,
4697 INIT_LIST_HEAD(&dev_priv->vm_list);
4698 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4700 INIT_LIST_HEAD(&dev_priv->context_list);
4701 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4702 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4703 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4704 for (i = 0; i < I915_NUM_RINGS; i++)
4705 init_ring_lists(&dev_priv->ring[i]);
4706 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4707 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4708 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4709 i915_gem_retire_work_handler);
4710 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4711 i915_gem_idle_work_handler);
4712 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4714 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4716 I915_WRITE(MI_ARB_STATE,
4717 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4720 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4722 /* Old X drivers will take 0-2 for front, back, depth buffers */
4723 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4724 dev_priv->fence_reg_start = 3;
4726 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4727 dev_priv->num_fence_regs = 32;
4728 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4729 dev_priv->num_fence_regs = 16;
4731 dev_priv->num_fence_regs = 8;
4733 /* Initialize fence registers to zero */
4734 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4735 i915_gem_restore_fences(dev);
4737 i915_gem_detect_bit_6_swizzle(dev);
4738 init_waitqueue_head(&dev_priv->pending_flip_queue);
4740 dev_priv->mm.interruptible = true;
4742 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4743 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4744 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4745 register_shrinker(&dev_priv->mm.shrinker);
4749 * Create a physically contiguous memory object for this object
4750 * e.g. for cursor + overlay regs
4752 static int i915_gem_init_phys_object(struct drm_device *dev,
4753 int id, int size, int align)
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4756 struct drm_i915_gem_phys_object *phys_obj;
4759 if (dev_priv->mm.phys_objs[id - 1] || !size)
4762 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4768 phys_obj->handle = drm_pci_alloc(dev, size, align);
4769 if (!phys_obj->handle) {
4774 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4777 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4785 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4787 struct drm_i915_private *dev_priv = dev->dev_private;
4788 struct drm_i915_gem_phys_object *phys_obj;
4790 if (!dev_priv->mm.phys_objs[id - 1])
4793 phys_obj = dev_priv->mm.phys_objs[id - 1];
4794 if (phys_obj->cur_obj) {
4795 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4799 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4801 drm_pci_free(dev, phys_obj->handle);
4803 dev_priv->mm.phys_objs[id - 1] = NULL;
4806 void i915_gem_free_all_phys_object(struct drm_device *dev)
4810 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4811 i915_gem_free_phys_object(dev, i);
4814 void i915_gem_detach_phys_object(struct drm_device *dev,
4815 struct drm_i915_gem_object *obj)
4817 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4824 vaddr = obj->phys_obj->handle->vaddr;
4826 page_count = obj->base.size / PAGE_SIZE;
4827 for (i = 0; i < page_count; i++) {
4828 struct page *page = shmem_read_mapping_page(mapping, i);
4829 if (!IS_ERR(page)) {
4830 char *dst = kmap_atomic(page);
4831 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4834 drm_clflush_pages(&page, 1);
4836 set_page_dirty(page);
4837 mark_page_accessed(page);
4838 page_cache_release(page);
4841 i915_gem_chipset_flush(dev);
4843 obj->phys_obj->cur_obj = NULL;
4844 obj->phys_obj = NULL;
4848 i915_gem_attach_phys_object(struct drm_device *dev,
4849 struct drm_i915_gem_object *obj,
4853 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4859 if (id > I915_MAX_PHYS_OBJECT)
4862 if (obj->phys_obj) {
4863 if (obj->phys_obj->id == id)
4865 i915_gem_detach_phys_object(dev, obj);
4868 /* create a new object */
4869 if (!dev_priv->mm.phys_objs[id - 1]) {
4870 ret = i915_gem_init_phys_object(dev, id,
4871 obj->base.size, align);
4873 DRM_ERROR("failed to init phys object %d size: %zu\n",
4874 id, obj->base.size);
4879 /* bind to the object */
4880 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4881 obj->phys_obj->cur_obj = obj;
4883 page_count = obj->base.size / PAGE_SIZE;
4885 for (i = 0; i < page_count; i++) {
4889 page = shmem_read_mapping_page(mapping, i);
4891 return PTR_ERR(page);
4893 src = kmap_atomic(page);
4894 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4895 memcpy(dst, src, PAGE_SIZE);
4898 mark_page_accessed(page);
4899 page_cache_release(page);
4906 i915_gem_phys_pwrite(struct drm_device *dev,
4907 struct drm_i915_gem_object *obj,
4908 struct drm_i915_gem_pwrite *args,
4909 struct drm_file *file_priv)
4911 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4912 char __user *user_data = to_user_ptr(args->data_ptr);
4914 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4915 unsigned long unwritten;
4917 /* The physical object once assigned is fixed for the lifetime
4918 * of the obj, so we can safely drop the lock and continue
4921 mutex_unlock(&dev->struct_mutex);
4922 unwritten = copy_from_user(vaddr, user_data, args->size);
4923 mutex_lock(&dev->struct_mutex);
4928 i915_gem_chipset_flush(dev);
4932 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4934 struct drm_i915_file_private *file_priv = file->driver_priv;
4936 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4938 /* Clean up our request list when the client is going away, so that
4939 * later retire_requests won't dereference our soon-to-be-gone
4942 spin_lock(&file_priv->mm.lock);
4943 while (!list_empty(&file_priv->mm.request_list)) {
4944 struct drm_i915_gem_request *request;
4946 request = list_first_entry(&file_priv->mm.request_list,
4947 struct drm_i915_gem_request,
4949 list_del(&request->client_list);
4950 request->file_priv = NULL;
4952 spin_unlock(&file_priv->mm.lock);
4956 i915_gem_file_idle_work_handler(struct work_struct *work)
4958 struct drm_i915_file_private *file_priv =
4959 container_of(work, typeof(*file_priv), mm.idle_work.work);
4961 atomic_set(&file_priv->rps_wait_boost, false);
4964 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4966 struct drm_i915_file_private *file_priv;
4969 DRM_DEBUG_DRIVER("\n");
4971 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4975 file->driver_priv = file_priv;
4976 file_priv->dev_priv = dev->dev_private;
4977 file_priv->file = file;
4979 spin_lock_init(&file_priv->mm.lock);
4980 INIT_LIST_HEAD(&file_priv->mm.request_list);
4981 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4982 i915_gem_file_idle_work_handler);
4984 ret = i915_gem_context_open(dev, file);
4991 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4993 if (!mutex_is_locked(mutex))
4996 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4997 return mutex->owner == task;
4999 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5004 static int num_vma_bound(struct drm_i915_gem_object *obj)
5006 struct i915_vma *vma;
5009 list_for_each_entry(vma, &obj->vma_list, vma_link)
5010 if (drm_mm_node_allocated(&vma->node))
5016 static unsigned long
5017 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5019 struct drm_i915_private *dev_priv =
5020 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5021 struct drm_device *dev = dev_priv->dev;
5022 struct drm_i915_gem_object *obj;
5024 unsigned long count;
5026 if (!mutex_trylock(&dev->struct_mutex)) {
5027 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5030 if (dev_priv->mm.shrinker_no_lock_stealing)
5037 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5038 if (obj->pages_pin_count == 0)
5039 count += obj->base.size >> PAGE_SHIFT;
5041 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5042 if (!i915_gem_obj_is_pinned(obj) &&
5043 obj->pages_pin_count == num_vma_bound(obj))
5044 count += obj->base.size >> PAGE_SHIFT;
5048 mutex_unlock(&dev->struct_mutex);
5053 /* All the new VM stuff */
5054 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5055 struct i915_address_space *vm)
5057 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5058 struct i915_vma *vma;
5060 if (!dev_priv->mm.aliasing_ppgtt ||
5061 vm == &dev_priv->mm.aliasing_ppgtt->base)
5062 vm = &dev_priv->gtt.base;
5064 BUG_ON(list_empty(&o->vma_list));
5065 list_for_each_entry(vma, &o->vma_list, vma_link) {
5067 return vma->node.start;
5073 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5074 struct i915_address_space *vm)
5076 struct i915_vma *vma;
5078 list_for_each_entry(vma, &o->vma_list, vma_link)
5079 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5085 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5087 struct i915_vma *vma;
5089 list_for_each_entry(vma, &o->vma_list, vma_link)
5090 if (drm_mm_node_allocated(&vma->node))
5096 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5097 struct i915_address_space *vm)
5099 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5100 struct i915_vma *vma;
5102 if (!dev_priv->mm.aliasing_ppgtt ||
5103 vm == &dev_priv->mm.aliasing_ppgtt->base)
5104 vm = &dev_priv->gtt.base;
5106 BUG_ON(list_empty(&o->vma_list));
5108 list_for_each_entry(vma, &o->vma_list, vma_link)
5110 return vma->node.size;
5115 static unsigned long
5116 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5118 struct drm_i915_private *dev_priv =
5119 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5120 struct drm_device *dev = dev_priv->dev;
5121 unsigned long freed;
5124 if (!mutex_trylock(&dev->struct_mutex)) {
5125 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5128 if (dev_priv->mm.shrinker_no_lock_stealing)
5134 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5135 if (freed < sc->nr_to_scan)
5136 freed += __i915_gem_shrink(dev_priv,
5137 sc->nr_to_scan - freed,
5139 if (freed < sc->nr_to_scan)
5140 freed += i915_gem_shrink_all(dev_priv);
5143 mutex_unlock(&dev->struct_mutex);
5148 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5150 struct i915_vma *vma;
5152 /* This WARN has probably outlived its usefulness (callers already
5153 * WARN if they don't find the GGTT vma they expect). When removing,
5154 * remember to remove the pre-check in is_pin_display() as well */
5155 if (WARN_ON(list_empty(&obj->vma_list)))
5158 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5159 if (vma->vm != obj_to_ggtt(obj))