drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct drm_device *dev)
  91 {
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93         struct completion *x = &dev_priv->error_completion;
  94         unsigned long flags;
  95         int ret;
  96
  97         if (!atomic_read(&dev_priv->mm.wedged))
  98                 return 0;
  99
 100         /*
 101          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 102          * userspace. If it takes that long something really bad is going on and
 103          * we should simply try to bail out and fail as gracefully as possible.
 104          */
 105         ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
 106         if (ret == 0) {
 107                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 108                 return -EIO;
 109         } else if (ret < 0) {
 110                 return ret;
 111         }
 112
 113         if (atomic_read(&dev_priv->mm.wedged)) {
 114                 /* GPU is hung, bump the completion count to account for
 115                  * the token we just consumed so that we never hit zero and
 116                  * end up waiting upon a subsequent completion event that
 117                  * will never happen.
 118                  */
 119                 spin_lock_irqsave(&x->wait.lock, flags);
 120                 x->done++;
 121                 spin_unlock_irqrestore(&x->wait.lock, flags);
 122         }
 123         return 0;
 124 }
 125
 126 int i915_mutex_lock_interruptible(struct drm_device *dev)
 127 {
 128         int ret;
 129
 130         ret = i915_gem_wait_for_error(dev);
 131         if (ret)
 132                 return ret;
 133
 134         ret = mutex_lock_interruptible(&dev->struct_mutex);
 135         if (ret)
 136                 return ret;
 137
 138         WARN_ON(i915_verify_lists(dev));
 139         return 0;
 140 }
 141
 142 static inline bool
 143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 144 {
 145         return obj->gtt_space && !obj->active;
 146 }
 147
 148 int
 149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 150                     struct drm_file *file)
 151 {
 152         struct drm_i915_gem_init *args = data;
 153
 154         if (drm_core_check_feature(dev, DRIVER_MODESET))
 155                 return -ENODEV;
 156
 157         if (args->gtt_start >= args->gtt_end ||
 158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 159                 return -EINVAL;
 160
 161         /* GEM with user mode setting was never supported on ilk and later. */
 162         if (INTEL_INFO(dev)->gen >= 5)
 163                 return -ENODEV;
 164
 165         mutex_lock(&dev->struct_mutex);
 166         i915_gem_init_global_gtt(dev, args->gtt_start,
 167                                  args->gtt_end, args->gtt_end);
 168         mutex_unlock(&dev->struct_mutex);
 169
 170         return 0;
 171 }
 172
 173 int
 174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 175                             struct drm_file *file)
 176 {
 177         struct drm_i915_private *dev_priv = dev->dev_private;
 178         struct drm_i915_gem_get_aperture *args = data;
 179         struct drm_i915_gem_object *obj;
 180         size_t pinned;
 181
 182         pinned = 0;
 183         mutex_lock(&dev->struct_mutex);
 184         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
 185                 if (obj->pin_count)
 186                         pinned += obj->gtt_space->size;
 187         mutex_unlock(&dev->struct_mutex);
 188
 189         args->aper_size = dev_priv->mm.gtt_total;
 190         args->aper_available_size = args->aper_size - pinned;
 191
 192         return 0;
 193 }
 194
 195 static int
 196 i915_gem_create(struct drm_file *file,
 197                 struct drm_device *dev,
 198                 uint64_t size,
 199                 uint32_t *handle_p)
 200 {
 201         struct drm_i915_gem_object *obj;
 202         int ret;
 203         u32 handle;
 204
 205         size = roundup(size, PAGE_SIZE);
 206         if (size == 0)
 207                 return -EINVAL;
 208
 209         /* Allocate the new object */
 210         obj = i915_gem_alloc_object(dev, size);
 211         if (obj == NULL)
 212                 return -ENOMEM;
 213
 214         ret = drm_gem_handle_create(file, &obj->base, &handle);
 215         if (ret) {
 216                 drm_gem_object_release(&obj->base);
 217                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 218                 kfree(obj);
 219                 return ret;
 220         }
 221
 222         /* drop reference from allocate - handle holds it now */
 223         drm_gem_object_unreference(&obj->base);
 224         trace_i915_gem_object_create(obj);
 225
 226         *handle_p = handle;
 227         return 0;
 228 }
 229
 230 int
 231 i915_gem_dumb_create(struct drm_file *file,
 232                      struct drm_device *dev,
 233                      struct drm_mode_create_dumb *args)
 234 {
 235         /* have to work out size/pitch and return them */
 236         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 237         args->size = args->pitch * args->height;
 238         return i915_gem_create(file, dev,
 239                                args->size, &args->handle);
 240 }
 241
 242 int i915_gem_dumb_destroy(struct drm_file *file,
 243                           struct drm_device *dev,
 244                           uint32_t handle)
 245 {
 246         return drm_gem_handle_delete(file, handle);
 247 }
 248
 249 /**
 250  * Creates a new mm object and returns a handle to it.
 251  */
 252 int
 253 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 254                       struct drm_file *file)
 255 {
 256         struct drm_i915_gem_create *args = data;
 257
 258         return i915_gem_create(file, dev,
 259                                args->size, &args->handle);
 260 }
 261
 262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 263 {
 264         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 265
 266         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 267                 obj->tiling_mode != I915_TILING_NONE;
 268 }
 269
 270 static inline int
 271 __copy_to_user_swizzled(char __user *cpu_vaddr,
 272                         const char *gpu_vaddr, int gpu_offset,
 273                         int length)
 274 {
 275         int ret, cpu_offset = 0;
 276
 277         while (length > 0) {
 278                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 279                 int this_length = min(cacheline_end - gpu_offset, length);
 280                 int swizzled_gpu_offset = gpu_offset ^ 64;
 281
 282                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 283                                      gpu_vaddr + swizzled_gpu_offset,
 284                                      this_length);
 285                 if (ret)
 286                         return ret + length;
 287
 288                 cpu_offset += this_length;
 289                 gpu_offset += this_length;
 290                 length -= this_length;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static inline int
 297 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 298                           const char __user *cpu_vaddr,
 299                           int length)
 300 {
 301         int ret, cpu_offset = 0;
 302
 303         while (length > 0) {
 304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 305                 int this_length = min(cacheline_end - gpu_offset, length);
 306                 int swizzled_gpu_offset = gpu_offset ^ 64;
 307
 308                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 309                                        cpu_vaddr + cpu_offset,
 310                                        this_length);
 311                 if (ret)
 312                         return ret + length;
 313
 314                 cpu_offset += this_length;
 315                 gpu_offset += this_length;
 316                 length -= this_length;
 317         }
 318
 319         return 0;
 320 }
 321
 322 /* Per-page copy function for the shmem pread fastpath.
 323  * Flushes invalid cachelines before reading the target if
 324  * needs_clflush is set. */
 325 static int
 326 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 327                  char __user *user_data,
 328                  bool page_do_bit17_swizzling, bool needs_clflush)
 329 {
 330         char *vaddr;
 331         int ret;
 332
 333         if (unlikely(page_do_bit17_swizzling))
 334                 return -EINVAL;
 335
 336         vaddr = kmap_atomic(page);
 337         if (needs_clflush)
 338                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 339                                        page_length);
 340         ret = __copy_to_user_inatomic(user_data,
 341                                       vaddr + shmem_page_offset,
 342                                       page_length);
 343         kunmap_atomic(vaddr);
 344
 345         return ret ? -EFAULT : 0;
 346 }
 347
 348 static void
 349 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 350                              bool swizzled)
 351 {
 352         if (unlikely(swizzled)) {
 353                 unsigned long start = (unsigned long) addr;
 354                 unsigned long end = (unsigned long) addr + length;
 355
 356                 /* For swizzling simply ensure that we always flush both
 357                  * channels. Lame, but simple and it works. Swizzled
 358                  * pwrite/pread is far from a hotpath - current userspace
 359                  * doesn't use it at all. */
 360                 start = round_down(start, 128);
 361                 end = round_up(end, 128);
 362
 363                 drm_clflush_virt_range((void *)start, end - start);
 364         } else {
 365                 drm_clflush_virt_range(addr, length);
 366         }
 367
 368 }
 369
 370 /* Only difference to the fast-path function is that this can handle bit17
 371  * and uses non-atomic copy and kmap functions. */
 372 static int
 373 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 374                  char __user *user_data,
 375                  bool page_do_bit17_swizzling, bool needs_clflush)
 376 {
 377         char *vaddr;
 378         int ret;
 379
 380         vaddr = kmap(page);
 381         if (needs_clflush)
 382                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 383                                              page_length,
 384                                              page_do_bit17_swizzling);
 385
 386         if (page_do_bit17_swizzling)
 387                 ret = __copy_to_user_swizzled(user_data,
 388                                               vaddr, shmem_page_offset,
 389                                               page_length);
 390         else
 391                 ret = __copy_to_user(user_data,
 392                                      vaddr + shmem_page_offset,
 393                                      page_length);
 394         kunmap(page);
 395
 396         return ret ? - EFAULT : 0;
 397 }
 398
 399 static int
 400 i915_gem_shmem_pread(struct drm_device *dev,
 401                      struct drm_i915_gem_object *obj,
 402                      struct drm_i915_gem_pread *args,
 403                      struct drm_file *file)
 404 {
 405         char __user *user_data;
 406         ssize_t remain;
 407         loff_t offset;
 408         int shmem_page_offset, page_length, ret = 0;
 409         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 410         int prefaulted = 0;
 411         int needs_clflush = 0;
 412         struct scatterlist *sg;
 413         int i;
 414
 415         user_data = (char __user *) (uintptr_t) args->data_ptr;
 416         remain = args->size;
 417
 418         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 419
 420         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 421                 /* If we're not in the cpu read domain, set ourself into the gtt
 422                  * read domain and manually flush cachelines (if required). This
 423                  * optimizes for the case when the gpu will dirty the data
 424                  * anyway again before the next pread happens. */
 425                 if (obj->cache_level == I915_CACHE_NONE)
 426                         needs_clflush = 1;
 427                 if (obj->gtt_space) {
 428                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 429                         if (ret)
 430                                 return ret;
 431                 }
 432         }
 433
 434         ret = i915_gem_object_get_pages(obj);
 435         if (ret)
 436                 return ret;
 437
 438         i915_gem_object_pin_pages(obj);
 439
 440         offset = args->offset;
 441
 442         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 443                 struct page *page;
 444
 445                 if (i < offset >> PAGE_SHIFT)
 446                         continue;
 447
 448                 if (remain <= 0)
 449                         break;
 450
 451                 /* Operation in this page
 452                  *
 453                  * shmem_page_offset = offset within page in shmem file
 454                  * page_length = bytes to copy for this page
 455                  */
 456                 shmem_page_offset = offset_in_page(offset);
 457                 page_length = remain;
 458                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 459                         page_length = PAGE_SIZE - shmem_page_offset;
 460
 461                 page = sg_page(sg);
 462                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 463                         (page_to_phys(page) & (1 << 17)) != 0;
 464
 465                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 466                                        user_data, page_do_bit17_swizzling,
 467                                        needs_clflush);
 468                 if (ret == 0)
 469                         goto next_page;
 470
 471                 mutex_unlock(&dev->struct_mutex);
 472
 473                 if (!prefaulted) {
 474                         ret = fault_in_multipages_writeable(user_data, remain);
 475                         /* Userspace is tricking us, but we've already clobbered
 476                          * its pages with the prefault and promised to write the
 477                          * data up to the first fault. Hence ignore any errors
 478                          * and just continue. */
 479                         (void)ret;
 480                         prefaulted = 1;
 481                 }
 482
 483                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 484                                        user_data, page_do_bit17_swizzling,
 485                                        needs_clflush);
 486
 487                 mutex_lock(&dev->struct_mutex);
 488
 489 next_page:
 490                 mark_page_accessed(page);
 491
 492                 if (ret)
 493                         goto out;
 494
 495                 remain -= page_length;
 496                 user_data += page_length;
 497                 offset += page_length;
 498         }
 499
 500 out:
 501         i915_gem_object_unpin_pages(obj);
 502
 503         return ret;
 504 }
 505
 506 /**
 507  * Reads data from the object referenced by handle.
 508  *
 509  * On error, the contents of *data are undefined.
 510  */
 511 int
 512 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 513                      struct drm_file *file)
 514 {
 515         struct drm_i915_gem_pread *args = data;
 516         struct drm_i915_gem_object *obj;
 517         int ret = 0;
 518
 519         if (args->size == 0)
 520                 return 0;
 521
 522         if (!access_ok(VERIFY_WRITE,
 523                        (char __user *)(uintptr_t)args->data_ptr,
 524                        args->size))
 525                 return -EFAULT;
 526
 527         ret = i915_mutex_lock_interruptible(dev);
 528         if (ret)
 529                 return ret;
 530
 531         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 532         if (&obj->base == NULL) {
 533                 ret = -ENOENT;
 534                 goto unlock;
 535         }
 536
 537         /* Bounds check source.  */
 538         if (args->offset > obj->base.size ||
 539             args->size > obj->base.size - args->offset) {
 540                 ret = -EINVAL;
 541                 goto out;
 542         }
 543
 544         /* prime objects have no backing filp to GEM pread/pwrite
 545          * pages from.
 546          */
 547         if (!obj->base.filp) {
 548                 ret = -EINVAL;
 549                 goto out;
 550         }
 551
 552         trace_i915_gem_object_pread(obj, args->offset, args->size);
 553
 554         ret = i915_gem_shmem_pread(dev, obj, args, file);
 555
 556 out:
 557         drm_gem_object_unreference(&obj->base);
 558 unlock:
 559         mutex_unlock(&dev->struct_mutex);
 560         return ret;
 561 }
 562
 563 /* This is the fast write path which cannot handle
 564  * page faults in the source data
 565  */
 566
 567 static inline int
 568 fast_user_write(struct io_mapping *mapping,
 569                 loff_t page_base, int page_offset,
 570                 char __user *user_data,
 571                 int length)
 572 {
 573         void __iomem *vaddr_atomic;
 574         void *vaddr;
 575         unsigned long unwritten;
 576
 577         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 578         /* We can use the cpu mem copy function because this is X86. */
 579         vaddr = (void __force*)vaddr_atomic + page_offset;
 580         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 581                                                       user_data, length);
 582         io_mapping_unmap_atomic(vaddr_atomic);
 583         return unwritten;
 584 }
 585
 586 /**
 587  * This is the fast pwrite path, where we copy the data directly from the
 588  * user into the GTT, uncached.
 589  */
 590 static int
 591 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 592                          struct drm_i915_gem_object *obj,
 593                          struct drm_i915_gem_pwrite *args,
 594                          struct drm_file *file)
 595 {
 596         drm_i915_private_t *dev_priv = dev->dev_private;
 597         ssize_t remain;
 598         loff_t offset, page_base;
 599         char __user *user_data;
 600         int page_offset, page_length, ret;
 601
 602         ret = i915_gem_object_pin(obj, 0, true, true);
 603         if (ret)
 604                 goto out;
 605
 606         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 607         if (ret)
 608                 goto out_unpin;
 609
 610         ret = i915_gem_object_put_fence(obj);
 611         if (ret)
 612                 goto out_unpin;
 613
 614         user_data = (char __user *) (uintptr_t) args->data_ptr;
 615         remain = args->size;
 616
 617         offset = obj->gtt_offset + args->offset;
 618
 619         while (remain > 0) {
 620                 /* Operation in this page
 621                  *
 622                  * page_base = page offset within aperture
 623                  * page_offset = offset within page
 624                  * page_length = bytes to copy for this page
 625                  */
 626                 page_base = offset & PAGE_MASK;
 627                 page_offset = offset_in_page(offset);
 628                 page_length = remain;
 629                 if ((page_offset + remain) > PAGE_SIZE)
 630                         page_length = PAGE_SIZE - page_offset;
 631
 632                 /* If we get a fault while copying data, then (presumably) our
 633                  * source page isn't available.  Return the error and we'll
 634                  * retry in the slow path.
 635                  */
 636                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 637                                     page_offset, user_data, page_length)) {
 638                         ret = -EFAULT;
 639                         goto out_unpin;
 640                 }
 641
 642                 remain -= page_length;
 643                 user_data += page_length;
 644                 offset += page_length;
 645         }
 646
 647 out_unpin:
 648         i915_gem_object_unpin(obj);
 649 out:
 650         return ret;
 651 }
 652
 653 /* Per-page copy function for the shmem pwrite fastpath.
 654  * Flushes invalid cachelines before writing to the target if
 655  * needs_clflush_before is set and flushes out any written cachelines after
 656  * writing if needs_clflush is set. */
 657 static int
 658 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 659                   char __user *user_data,
 660                   bool page_do_bit17_swizzling,
 661                   bool needs_clflush_before,
 662                   bool needs_clflush_after)
 663 {
 664         char *vaddr;
 665         int ret;
 666
 667         if (unlikely(page_do_bit17_swizzling))
 668                 return -EINVAL;
 669
 670         vaddr = kmap_atomic(page);
 671         if (needs_clflush_before)
 672                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 673                                        page_length);
 674         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 675                                                 user_data,
 676                                                 page_length);
 677         if (needs_clflush_after)
 678                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 679                                        page_length);
 680         kunmap_atomic(vaddr);
 681
 682         return ret ? -EFAULT : 0;
 683 }
 684
 685 /* Only difference to the fast-path function is that this can handle bit17
 686  * and uses non-atomic copy and kmap functions. */
 687 static int
 688 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 689                   char __user *user_data,
 690                   bool page_do_bit17_swizzling,
 691                   bool needs_clflush_before,
 692                   bool needs_clflush_after)
 693 {
 694         char *vaddr;
 695         int ret;
 696
 697         vaddr = kmap(page);
 698         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 699                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 700                                              page_length,
 701                                              page_do_bit17_swizzling);
 702         if (page_do_bit17_swizzling)
 703                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 704                                                 user_data,
 705                                                 page_length);
 706         else
 707                 ret = __copy_from_user(vaddr + shmem_page_offset,
 708                                        user_data,
 709                                        page_length);
 710         if (needs_clflush_after)
 711                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 712                                              page_length,
 713                                              page_do_bit17_swizzling);
 714         kunmap(page);
 715
 716         return ret ? -EFAULT : 0;
 717 }
 718
 719 static int
 720 i915_gem_shmem_pwrite(struct drm_device *dev,
 721                       struct drm_i915_gem_object *obj,
 722                       struct drm_i915_gem_pwrite *args,
 723                       struct drm_file *file)
 724 {
 725         ssize_t remain;
 726         loff_t offset;
 727         char __user *user_data;
 728         int shmem_page_offset, page_length, ret = 0;
 729         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 730         int hit_slowpath = 0;
 731         int needs_clflush_after = 0;
 732         int needs_clflush_before = 0;
 733         int i;
 734         struct scatterlist *sg;
 735
 736         user_data = (char __user *) (uintptr_t) args->data_ptr;
 737         remain = args->size;
 738
 739         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 740
 741         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 742                 /* If we're not in the cpu write domain, set ourself into the gtt
 743                  * write domain and manually flush cachelines (if required). This
 744                  * optimizes for the case when the gpu will use the data
 745                  * right away and we therefore have to clflush anyway. */
 746                 if (obj->cache_level == I915_CACHE_NONE)
 747                         needs_clflush_after = 1;
 748                 if (obj->gtt_space) {
 749                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 750                         if (ret)
 751                                 return ret;
 752                 }
 753         }
 754         /* Same trick applies for invalidate partially written cachelines before
 755          * writing.  */
 756         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 757             && obj->cache_level == I915_CACHE_NONE)
 758                 needs_clflush_before = 1;
 759
 760         ret = i915_gem_object_get_pages(obj);
 761         if (ret)
 762                 return ret;
 763
 764         i915_gem_object_pin_pages(obj);
 765
 766         offset = args->offset;
 767         obj->dirty = 1;
 768
 769         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 770                 struct page *page;
 771                 int partial_cacheline_write;
 772
 773                 if (i < offset >> PAGE_SHIFT)
 774                         continue;
 775
 776                 if (remain <= 0)
 777                         break;
 778
 779                 /* Operation in this page
 780                  *
 781                  * shmem_page_offset = offset within page in shmem file
 782                  * page_length = bytes to copy for this page
 783                  */
 784                 shmem_page_offset = offset_in_page(offset);
 785
 786                 page_length = remain;
 787                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 788                         page_length = PAGE_SIZE - shmem_page_offset;
 789
 790                 /* If we don't overwrite a cacheline completely we need to be
 791                  * careful to have up-to-date data by first clflushing. Don't
 792                  * overcomplicate things and flush the entire patch. */
 793                 partial_cacheline_write = needs_clflush_before &&
 794                         ((shmem_page_offset | page_length)
 795                                 & (boot_cpu_data.x86_clflush_size - 1));
 796
 797                 page = sg_page(sg);
 798                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 799                         (page_to_phys(page) & (1 << 17)) != 0;
 800
 801                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 802                                         user_data, page_do_bit17_swizzling,
 803                                         partial_cacheline_write,
 804                                         needs_clflush_after);
 805                 if (ret == 0)
 806                         goto next_page;
 807
 808                 hit_slowpath = 1;
 809                 mutex_unlock(&dev->struct_mutex);
 810                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 811                                         user_data, page_do_bit17_swizzling,
 812                                         partial_cacheline_write,
 813                                         needs_clflush_after);
 814
 815                 mutex_lock(&dev->struct_mutex);
 816
 817 next_page:
 818                 set_page_dirty(page);
 819                 mark_page_accessed(page);
 820
 821                 if (ret)
 822                         goto out;
 823
 824                 remain -= page_length;
 825                 user_data += page_length;
 826                 offset += page_length;
 827         }
 828
 829 out:
 830         i915_gem_object_unpin_pages(obj);
 831
 832         if (hit_slowpath) {
 833                 /*
 834                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 835                  * cachelines in-line while writing and the object moved
 836                  * out of the cpu write domain while we've dropped the lock.
 837                  */
 838                 if (!needs_clflush_after &&
 839                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 840                         i915_gem_clflush_object(obj);
 841                         i915_gem_chipset_flush(dev);
 842                 }
 843         }
 844
 845         if (needs_clflush_after)
 846                 i915_gem_chipset_flush(dev);
 847
 848         return ret;
 849 }
 850
 851 /**
 852  * Writes data to the object referenced by handle.
 853  *
 854  * On error, the contents of the buffer that were to be modified are undefined.
 855  */
 856 int
 857 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 858                       struct drm_file *file)
 859 {
 860         struct drm_i915_gem_pwrite *args = data;
 861         struct drm_i915_gem_object *obj;
 862         int ret;
 863
 864         if (args->size == 0)
 865                 return 0;
 866
 867         if (!access_ok(VERIFY_READ,
 868                        (char __user *)(uintptr_t)args->data_ptr,
 869                        args->size))
 870                 return -EFAULT;
 871
 872         ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
 873                                            args->size);
 874         if (ret)
 875                 return -EFAULT;
 876
 877         ret = i915_mutex_lock_interruptible(dev);
 878         if (ret)
 879                 return ret;
 880
 881         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 882         if (&obj->base == NULL) {
 883                 ret = -ENOENT;
 884                 goto unlock;
 885         }
 886
 887         /* Bounds check destination. */
 888         if (args->offset > obj->base.size ||
 889             args->size > obj->base.size - args->offset) {
 890                 ret = -EINVAL;
 891                 goto out;
 892         }
 893
 894         /* prime objects have no backing filp to GEM pread/pwrite
 895          * pages from.
 896          */
 897         if (!obj->base.filp) {
 898                 ret = -EINVAL;
 899                 goto out;
 900         }
 901
 902         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 903
 904         ret = -EFAULT;
 905         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 906          * it would end up going through the fenced access, and we'll get
 907          * different detiling behavior between reading and writing.
 908          * pread/pwrite currently are reading and writing from the CPU
 909          * perspective, requiring manual detiling by the client.
 910          */
 911         if (obj->phys_obj) {
 912                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 913                 goto out;
 914         }
 915
 916         if (obj->cache_level == I915_CACHE_NONE &&
 917             obj->tiling_mode == I915_TILING_NONE &&
 918             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 919                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 920                 /* Note that the gtt paths might fail with non-page-backed user
 921                  * pointers (e.g. gtt mappings when moving data between
 922                  * textures). Fallback to the shmem path in that case. */
 923         }
 924
 925         if (ret == -EFAULT || ret == -ENOSPC)
 926                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 927
 928 out:
 929         drm_gem_object_unreference(&obj->base);
 930 unlock:
 931         mutex_unlock(&dev->struct_mutex);
 932         return ret;
 933 }
 934
 935 int
 936 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
 937                      bool interruptible)
 938 {
 939         if (atomic_read(&dev_priv->mm.wedged)) {
 940                 struct completion *x = &dev_priv->error_completion;
 941                 bool recovery_complete;
 942                 unsigned long flags;
 943
 944                 /* Give the error handler a chance to run. */
 945                 spin_lock_irqsave(&x->wait.lock, flags);
 946                 recovery_complete = x->done > 0;
 947                 spin_unlock_irqrestore(&x->wait.lock, flags);
 948
 949                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 950                  * -EIO unconditionally for these. */
 951                 if (!interruptible)
 952                         return -EIO;
 953
 954                 /* Recovery complete, but still wedged means reset failure. */
 955                 if (recovery_complete)
 956                         return -EIO;
 957
 958                 return -EAGAIN;
 959         }
 960
 961         return 0;
 962 }
 963
 964 /*
 965  * Compare seqno against outstanding lazy request. Emit a request if they are
 966  * equal.
 967  */
 968 static int
 969 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 970 {
 971         int ret;
 972
 973         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 974
 975         ret = 0;
 976         if (seqno == ring->outstanding_lazy_request)
 977                 ret = i915_add_request(ring, NULL, NULL);
 978
 979         return ret;
 980 }
 981
 982 /**
 983  * __wait_seqno - wait until execution of seqno has finished
 984  * @ring: the ring expected to report seqno
 985  * @seqno: duh!
 986  * @interruptible: do an interruptible wait (normally yes)
 987  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 988  *
 989  * Returns 0 if the seqno was found within the alloted time. Else returns the
 990  * errno with remaining time filled in timeout argument.
 991  */
 992 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 993                         bool interruptible, struct timespec *timeout)
 994 {
 995         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 996         struct timespec before, now, wait_time={1,0};
 997         unsigned long timeout_jiffies;
 998         long end;
 999         bool wait_forever = true;
1000         int ret;
1001
1002         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1003                 return 0;
1004
1005         trace_i915_gem_request_wait_begin(ring, seqno);
1006
1007         if (timeout != NULL) {
1008                 wait_time = *timeout;
1009                 wait_forever = false;
1010         }
1011
1012         timeout_jiffies = timespec_to_jiffies(&wait_time);
1013
1014         if (WARN_ON(!ring->irq_get(ring)))
1015                 return -ENODEV;
1016
1017         /* Record current time in case interrupted by signal, or wedged * */
1018         getrawmonotonic(&before);
1019
1020 #define EXIT_COND \
1021         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1022         atomic_read(&dev_priv->mm.wedged))
1023         do {
1024                 if (interruptible)
1025                         end = wait_event_interruptible_timeout(ring->irq_queue,
1026                                                                EXIT_COND,
1027                                                                timeout_jiffies);
1028                 else
1029                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1030                                                  timeout_jiffies);
1031
1032                 ret = i915_gem_check_wedge(dev_priv, interruptible);
1033                 if (ret)
1034                         end = ret;
1035         } while (end == 0 && wait_forever);
1036
1037         getrawmonotonic(&now);
1038
1039         ring->irq_put(ring);
1040         trace_i915_gem_request_wait_end(ring, seqno);
1041 #undef EXIT_COND
1042
1043         if (timeout) {
1044                 struct timespec sleep_time = timespec_sub(now, before);
1045                 *timeout = timespec_sub(*timeout, sleep_time);
1046         }
1047
1048         switch (end) {
1049         case -EIO:
1050         case -EAGAIN: /* Wedged */
1051         case -ERESTARTSYS: /* Signal */
1052                 return (int)end;
1053         case 0: /* Timeout */
1054                 if (timeout)
1055                         set_normalized_timespec(timeout, 0, 0);
1056                 return -ETIME;
1057         default: /* Completed */
1058                 WARN_ON(end < 0); /* We're not aware of other errors */
1059                 return 0;
1060         }
1061 }
1062
1063 /**
1064  * Waits for a sequence number to be signaled, and cleans up the
1065  * request and object lists appropriately for that event.
1066  */
1067 int
1068 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1069 {
1070         struct drm_device *dev = ring->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         bool interruptible = dev_priv->mm.interruptible;
1073         int ret;
1074
1075         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1076         BUG_ON(seqno == 0);
1077
1078         ret = i915_gem_check_wedge(dev_priv, interruptible);
1079         if (ret)
1080                 return ret;
1081
1082         ret = i915_gem_check_olr(ring, seqno);
1083         if (ret)
1084                 return ret;
1085
1086         return __wait_seqno(ring, seqno, interruptible, NULL);
1087 }
1088
1089 /**
1090  * Ensures that all rendering to the object has completed and the object is
1091  * safe to unbind from the GTT or access from the CPU.
1092  */
1093 static __must_check int
1094 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1095                                bool readonly)
1096 {
1097         struct intel_ring_buffer *ring = obj->ring;
1098         u32 seqno;
1099         int ret;
1100
1101         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1102         if (seqno == 0)
1103                 return 0;
1104
1105         ret = i915_wait_seqno(ring, seqno);
1106         if (ret)
1107                 return ret;
1108
1109         i915_gem_retire_requests_ring(ring);
1110
1111         /* Manually manage the write flush as we may have not yet
1112          * retired the buffer.
1113          */
1114         if (obj->last_write_seqno &&
1115             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1116                 obj->last_write_seqno = 0;
1117                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1118         }
1119
1120         return 0;
1121 }
1122
1123 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1124  * as the object state may change during this call.
1125  */
1126 static __must_check int
1127 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1128                                             bool readonly)
1129 {
1130         struct drm_device *dev = obj->base.dev;
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         struct intel_ring_buffer *ring = obj->ring;
1133         u32 seqno;
1134         int ret;
1135
1136         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1137         BUG_ON(!dev_priv->mm.interruptible);
1138
1139         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1140         if (seqno == 0)
1141                 return 0;
1142
1143         ret = i915_gem_check_wedge(dev_priv, true);
1144         if (ret)
1145                 return ret;
1146
1147         ret = i915_gem_check_olr(ring, seqno);
1148         if (ret)
1149                 return ret;
1150
1151         mutex_unlock(&dev->struct_mutex);
1152         ret = __wait_seqno(ring, seqno, true, NULL);
1153         mutex_lock(&dev->struct_mutex);
1154
1155         i915_gem_retire_requests_ring(ring);
1156
1157         /* Manually manage the write flush as we may have not yet
1158          * retired the buffer.
1159          */
1160         if (obj->last_write_seqno &&
1161             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1162                 obj->last_write_seqno = 0;
1163                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1164         }
1165
1166         return ret;
1167 }
1168
1169 /**
1170  * Called when user space prepares to use an object with the CPU, either
1171  * through the mmap ioctl's mapping or a GTT mapping.
1172  */
1173 int
1174 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1175                           struct drm_file *file)
1176 {
1177         struct drm_i915_gem_set_domain *args = data;
1178         struct drm_i915_gem_object *obj;
1179         uint32_t read_domains = args->read_domains;
1180         uint32_t write_domain = args->write_domain;
1181         int ret;
1182
1183         /* Only handle setting domains to types used by the CPU. */
1184         if (write_domain & I915_GEM_GPU_DOMAINS)
1185                 return -EINVAL;
1186
1187         if (read_domains & I915_GEM_GPU_DOMAINS)
1188                 return -EINVAL;
1189
1190         /* Having something in the write domain implies it's in the read
1191          * domain, and only that read domain.  Enforce that in the request.
1192          */
1193         if (write_domain != 0 && read_domains != write_domain)
1194                 return -EINVAL;
1195
1196         ret = i915_mutex_lock_interruptible(dev);
1197         if (ret)
1198                 return ret;
1199
1200         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1201         if (&obj->base == NULL) {
1202                 ret = -ENOENT;
1203                 goto unlock;
1204         }
1205
1206         /* Try to flush the object off the GPU without holding the lock.
1207          * We will repeat the flush holding the lock in the normal manner
1208          * to catch cases where we are gazumped.
1209          */
1210         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1211         if (ret)
1212                 goto unref;
1213
1214         if (read_domains & I915_GEM_DOMAIN_GTT) {
1215                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1216
1217                 /* Silently promote "you're not bound, there was nothing to do"
1218                  * to success, since the client was just asking us to
1219                  * make sure everything was done.
1220                  */
1221                 if (ret == -EINVAL)
1222                         ret = 0;
1223         } else {
1224                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1225         }
1226
1227 unref:
1228         drm_gem_object_unreference(&obj->base);
1229 unlock:
1230         mutex_unlock(&dev->struct_mutex);
1231         return ret;
1232 }
1233
1234 /**
1235  * Called when user space has done writes to this buffer
1236  */
1237 int
1238 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1239                          struct drm_file *file)
1240 {
1241         struct drm_i915_gem_sw_finish *args = data;
1242         struct drm_i915_gem_object *obj;
1243         int ret = 0;
1244
1245         ret = i915_mutex_lock_interruptible(dev);
1246         if (ret)
1247                 return ret;
1248
1249         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1250         if (&obj->base == NULL) {
1251                 ret = -ENOENT;
1252                 goto unlock;
1253         }
1254
1255         /* Pinned buffers may be scanout, so flush the cache */
1256         if (obj->pin_count)
1257                 i915_gem_object_flush_cpu_write_domain(obj);
1258
1259         drm_gem_object_unreference(&obj->base);
1260 unlock:
1261         mutex_unlock(&dev->struct_mutex);
1262         return ret;
1263 }
1264
1265 /**
1266  * Maps the contents of an object, returning the address it is mapped
1267  * into.
1268  *
1269  * While the mapping holds a reference on the contents of the object, it doesn't
1270  * imply a ref on the object itself.
1271  */
1272 int
1273 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1274                     struct drm_file *file)
1275 {
1276         struct drm_i915_gem_mmap *args = data;
1277         struct drm_gem_object *obj;
1278         unsigned long addr;
1279
1280         obj = drm_gem_object_lookup(dev, file, args->handle);
1281         if (obj == NULL)
1282                 return -ENOENT;
1283
1284         /* prime objects have no backing filp to GEM mmap
1285          * pages from.
1286          */
1287         if (!obj->filp) {
1288                 drm_gem_object_unreference_unlocked(obj);
1289                 return -EINVAL;
1290         }
1291
1292         addr = vm_mmap(obj->filp, 0, args->size,
1293                        PROT_READ | PROT_WRITE, MAP_SHARED,
1294                        args->offset);
1295         drm_gem_object_unreference_unlocked(obj);
1296         if (IS_ERR((void *)addr))
1297                 return addr;
1298
1299         args->addr_ptr = (uint64_t) addr;
1300
1301         return 0;
1302 }
1303
1304 /**
1305  * i915_gem_fault - fault a page into the GTT
1306  * vma: VMA in question
1307  * vmf: fault info
1308  *
1309  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1310  * from userspace.  The fault handler takes care of binding the object to
1311  * the GTT (if needed), allocating and programming a fence register (again,
1312  * only if needed based on whether the old reg is still valid or the object
1313  * is tiled) and inserting a new PTE into the faulting process.
1314  *
1315  * Note that the faulting process may involve evicting existing objects
1316  * from the GTT and/or fence registers to make room.  So performance may
1317  * suffer if the GTT working set is large or there are few fence registers
1318  * left.
1319  */
1320 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1321 {
1322         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1323         struct drm_device *dev = obj->base.dev;
1324         drm_i915_private_t *dev_priv = dev->dev_private;
1325         pgoff_t page_offset;
1326         unsigned long pfn;
1327         int ret = 0;
1328         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1329
1330         /* We don't use vmf->pgoff since that has the fake offset */
1331         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1332                 PAGE_SHIFT;
1333
1334         ret = i915_mutex_lock_interruptible(dev);
1335         if (ret)
1336                 goto out;
1337
1338         trace_i915_gem_object_fault(obj, page_offset, true, write);
1339
1340         /* Now bind it into the GTT if needed */
1341         ret = i915_gem_object_pin(obj, 0, true, false);
1342         if (ret)
1343                 goto unlock;
1344
1345         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1346         if (ret)
1347                 goto unpin;
1348
1349         ret = i915_gem_object_get_fence(obj);
1350         if (ret)
1351                 goto unpin;
1352
1353         obj->fault_mappable = true;
1354
1355         pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1356                 page_offset;
1357
1358         /* Finally, remap it using the new GTT offset */
1359         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1360 unpin:
1361         i915_gem_object_unpin(obj);
1362 unlock:
1363         mutex_unlock(&dev->struct_mutex);
1364 out:
1365         switch (ret) {
1366         case -EIO:
1367                 /* If this -EIO is due to a gpu hang, give the reset code a
1368                  * chance to clean up the mess. Otherwise return the proper
1369                  * SIGBUS. */
1370                 if (!atomic_read(&dev_priv->mm.wedged))
1371                         return VM_FAULT_SIGBUS;
1372         case -EAGAIN:
1373                 /* Give the error handler a chance to run and move the
1374                  * objects off the GPU active list. Next time we service the
1375                  * fault, we should be able to transition the page into the
1376                  * GTT without touching the GPU (and so avoid further
1377                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1378                  * with coherency, just lost writes.
1379                  */
1380                 set_need_resched();
1381         case 0:
1382         case -ERESTARTSYS:
1383         case -EINTR:
1384         case -EBUSY:
1385                 /*
1386                  * EBUSY is ok: this just means that another thread
1387                  * already did the job.
1388                  */
1389                 return VM_FAULT_NOPAGE;
1390         case -ENOMEM:
1391                 return VM_FAULT_OOM;
1392         case -ENOSPC:
1393                 return VM_FAULT_SIGBUS;
1394         default:
1395                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1396                 return VM_FAULT_SIGBUS;
1397         }
1398 }
1399
1400 /**
1401  * i915_gem_release_mmap - remove physical page mappings
1402  * @obj: obj in question
1403  *
1404  * Preserve the reservation of the mmapping with the DRM core code, but
1405  * relinquish ownership of the pages back to the system.
1406  *
1407  * It is vital that we remove the page mapping if we have mapped a tiled
1408  * object through the GTT and then lose the fence register due to
1409  * resource pressure. Similarly if the object has been moved out of the
1410  * aperture, than pages mapped into userspace must be revoked. Removing the
1411  * mapping will then trigger a page fault on the next user access, allowing
1412  * fixup by i915_gem_fault().
1413  */
1414 void
1415 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1416 {
1417         if (!obj->fault_mappable)
1418                 return;
1419
1420         if (obj->base.dev->dev_mapping)
1421                 unmap_mapping_range(obj->base.dev->dev_mapping,
1422                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1423                                     obj->base.size, 1);
1424
1425         obj->fault_mappable = false;
1426 }
1427
1428 static uint32_t
1429 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1430 {
1431         uint32_t gtt_size;
1432
1433         if (INTEL_INFO(dev)->gen >= 4 ||
1434             tiling_mode == I915_TILING_NONE)
1435                 return size;
1436
1437         /* Previous chips need a power-of-two fence region when tiling */
1438         if (INTEL_INFO(dev)->gen == 3)
1439                 gtt_size = 1024*1024;
1440         else
1441                 gtt_size = 512*1024;
1442
1443         while (gtt_size < size)
1444                 gtt_size <<= 1;
1445
1446         return gtt_size;
1447 }
1448
1449 /**
1450  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1451  * @obj: object to check
1452  *
1453  * Return the required GTT alignment for an object, taking into account
1454  * potential fence register mapping.
1455  */
1456 static uint32_t
1457 i915_gem_get_gtt_alignment(struct drm_device *dev,
1458                            uint32_t size,
1459                            int tiling_mode)
1460 {
1461         /*
1462          * Minimum alignment is 4k (GTT page size), but might be greater
1463          * if a fence register is needed for the object.
1464          */
1465         if (INTEL_INFO(dev)->gen >= 4 ||
1466             tiling_mode == I915_TILING_NONE)
1467                 return 4096;
1468
1469         /*
1470          * Previous chips need to be aligned to the size of the smallest
1471          * fence register that can contain the object.
1472          */
1473         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1474 }
1475
1476 /**
1477  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1478  *                                       unfenced object
1479  * @dev: the device
1480  * @size: size of the object
1481  * @tiling_mode: tiling mode of the object
1482  *
1483  * Return the required GTT alignment for an object, only taking into account
1484  * unfenced tiled surface requirements.
1485  */
1486 uint32_t
1487 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1488                                     uint32_t size,
1489                                     int tiling_mode)
1490 {
1491         /*
1492          * Minimum alignment is 4k (GTT page size) for sane hw.
1493          */
1494         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1495             tiling_mode == I915_TILING_NONE)
1496                 return 4096;
1497
1498         /* Previous hardware however needs to be aligned to a power-of-two
1499          * tile height. The simplest method for determining this is to reuse
1500          * the power-of-tile object size.
1501          */
1502         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1503 }
1504
1505 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1506 {
1507         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1508         int ret;
1509
1510         if (obj->base.map_list.map)
1511                 return 0;
1512
1513         ret = drm_gem_create_mmap_offset(&obj->base);
1514         if (ret != -ENOSPC)
1515                 return ret;
1516
1517         /* Badly fragmented mmap space? The only way we can recover
1518          * space is by destroying unwanted objects. We can't randomly release
1519          * mmap_offsets as userspace expects them to be persistent for the
1520          * lifetime of the objects. The closest we can is to release the
1521          * offsets on purgeable objects by truncating it and marking it purged,
1522          * which prevents userspace from ever using that object again.
1523          */
1524         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1525         ret = drm_gem_create_mmap_offset(&obj->base);
1526         if (ret != -ENOSPC)
1527                 return ret;
1528
1529         i915_gem_shrink_all(dev_priv);
1530         return drm_gem_create_mmap_offset(&obj->base);
1531 }
1532
1533 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1534 {
1535         if (!obj->base.map_list.map)
1536                 return;
1537
1538         drm_gem_free_mmap_offset(&obj->base);
1539 }
1540
1541 int
1542 i915_gem_mmap_gtt(struct drm_file *file,
1543                   struct drm_device *dev,
1544                   uint32_t handle,
1545                   uint64_t *offset)
1546 {
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548         struct drm_i915_gem_object *obj;
1549         int ret;
1550
1551         ret = i915_mutex_lock_interruptible(dev);
1552         if (ret)
1553                 return ret;
1554
1555         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1556         if (&obj->base == NULL) {
1557                 ret = -ENOENT;
1558                 goto unlock;
1559         }
1560
1561         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1562                 ret = -E2BIG;
1563                 goto out;
1564         }
1565
1566         if (obj->madv != I915_MADV_WILLNEED) {
1567                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1568                 ret = -EINVAL;
1569                 goto out;
1570         }
1571
1572         ret = i915_gem_object_create_mmap_offset(obj);
1573         if (ret)
1574                 goto out;
1575
1576         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1577
1578 out:
1579         drm_gem_object_unreference(&obj->base);
1580 unlock:
1581         mutex_unlock(&dev->struct_mutex);
1582         return ret;
1583 }
1584
1585 /**
1586  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1587  * @dev: DRM device
1588  * @data: GTT mapping ioctl data
1589  * @file: GEM object info
1590  *
1591  * Simply returns the fake offset to userspace so it can mmap it.
1592  * The mmap call will end up in drm_gem_mmap(), which will set things
1593  * up so we can get faults in the handler above.
1594  *
1595  * The fault handler will take care of binding the object into the GTT
1596  * (since it may have been evicted to make room for something), allocating
1597  * a fence register, and mapping the appropriate aperture address into
1598  * userspace.
1599  */
1600 int
1601 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1602                         struct drm_file *file)
1603 {
1604         struct drm_i915_gem_mmap_gtt *args = data;
1605
1606         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1607 }
1608
1609 /* Immediately discard the backing storage */
1610 static void
1611 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1612 {
1613         struct inode *inode;
1614
1615         i915_gem_object_free_mmap_offset(obj);
1616
1617         if (obj->base.filp == NULL)
1618                 return;
1619
1620         /* Our goal here is to return as much of the memory as
1621          * is possible back to the system as we are called from OOM.
1622          * To do this we must instruct the shmfs to drop all of its
1623          * backing pages, *now*.
1624          */
1625         inode = obj->base.filp->f_path.dentry->d_inode;
1626         shmem_truncate_range(inode, 0, (loff_t)-1);
1627
1628         obj->madv = __I915_MADV_PURGED;
1629 }
1630
1631 static inline int
1632 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1633 {
1634         return obj->madv == I915_MADV_DONTNEED;
1635 }
1636
1637 static void
1638 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1639 {
1640         int page_count = obj->base.size / PAGE_SIZE;
1641         struct scatterlist *sg;
1642         int ret, i;
1643
1644         BUG_ON(obj->madv == __I915_MADV_PURGED);
1645
1646         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1647         if (ret) {
1648                 /* In the event of a disaster, abandon all caches and
1649                  * hope for the best.
1650                  */
1651                 WARN_ON(ret != -EIO);
1652                 i915_gem_clflush_object(obj);
1653                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1654         }
1655
1656         if (i915_gem_object_needs_bit17_swizzle(obj))
1657                 i915_gem_object_save_bit_17_swizzle(obj);
1658
1659         if (obj->madv == I915_MADV_DONTNEED)
1660                 obj->dirty = 0;
1661
1662         for_each_sg(obj->pages->sgl, sg, page_count, i) {
1663                 struct page *page = sg_page(sg);
1664
1665                 if (obj->dirty)
1666                         set_page_dirty(page);
1667
1668                 if (obj->madv == I915_MADV_WILLNEED)
1669                         mark_page_accessed(page);
1670
1671                 page_cache_release(page);
1672         }
1673         obj->dirty = 0;
1674
1675         sg_free_table(obj->pages);
1676         kfree(obj->pages);
1677 }
1678
1679 static int
1680 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1681 {
1682         const struct drm_i915_gem_object_ops *ops = obj->ops;
1683
1684         if (obj->pages == NULL)
1685                 return 0;
1686
1687         BUG_ON(obj->gtt_space);
1688
1689         if (obj->pages_pin_count)
1690                 return -EBUSY;
1691
1692         ops->put_pages(obj);
1693         obj->pages = NULL;
1694
1695         list_del(&obj->gtt_list);
1696         if (i915_gem_object_is_purgeable(obj))
1697                 i915_gem_object_truncate(obj);
1698
1699         return 0;
1700 }
1701
1702 static long
1703 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1704 {
1705         struct drm_i915_gem_object *obj, *next;
1706         long count = 0;
1707
1708         list_for_each_entry_safe(obj, next,
1709                                  &dev_priv->mm.unbound_list,
1710                                  gtt_list) {
1711                 if (i915_gem_object_is_purgeable(obj) &&
1712                     i915_gem_object_put_pages(obj) == 0) {
1713                         count += obj->base.size >> PAGE_SHIFT;
1714                         if (count >= target)
1715                                 return count;
1716                 }
1717         }
1718
1719         list_for_each_entry_safe(obj, next,
1720                                  &dev_priv->mm.inactive_list,
1721                                  mm_list) {
1722                 if (i915_gem_object_is_purgeable(obj) &&
1723                     i915_gem_object_unbind(obj) == 0 &&
1724                     i915_gem_object_put_pages(obj) == 0) {
1725                         count += obj->base.size >> PAGE_SHIFT;
1726                         if (count >= target)
1727                                 return count;
1728                 }
1729         }
1730
1731         return count;
1732 }
1733
1734 static void
1735 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1736 {
1737         struct drm_i915_gem_object *obj, *next;
1738
1739         i915_gem_evict_everything(dev_priv->dev);
1740
1741         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1742                 i915_gem_object_put_pages(obj);
1743 }
1744
1745 static int
1746 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1747 {
1748         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1749         int page_count, i;
1750         struct address_space *mapping;
1751         struct sg_table *st;
1752         struct scatterlist *sg;
1753         struct page *page;
1754         gfp_t gfp;
1755
1756         /* Assert that the object is not currently in any GPU domain. As it
1757          * wasn't in the GTT, there shouldn't be any way it could have been in
1758          * a GPU cache
1759          */
1760         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1761         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1762
1763         st = kmalloc(sizeof(*st), GFP_KERNEL);
1764         if (st == NULL)
1765                 return -ENOMEM;
1766
1767         page_count = obj->base.size / PAGE_SIZE;
1768         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1769                 sg_free_table(st);
1770                 kfree(st);
1771                 return -ENOMEM;
1772         }
1773
1774         /* Get the list of pages out of our struct file.  They'll be pinned
1775          * at this point until we release them.
1776          *
1777          * Fail silently without starting the shrinker
1778          */
1779         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1780         gfp = mapping_gfp_mask(mapping);
1781         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1782         gfp &= ~(__GFP_IO | __GFP_WAIT);
1783         for_each_sg(st->sgl, sg, page_count, i) {
1784                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1785                 if (IS_ERR(page)) {
1786                         i915_gem_purge(dev_priv, page_count);
1787                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1788                 }
1789                 if (IS_ERR(page)) {
1790                         /* We've tried hard to allocate the memory by reaping
1791                          * our own buffer, now let the real VM do its job and
1792                          * go down in flames if truly OOM.
1793                          */
1794                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1795                         gfp |= __GFP_IO | __GFP_WAIT;
1796
1797                         i915_gem_shrink_all(dev_priv);
1798                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1799                         if (IS_ERR(page))
1800                                 goto err_pages;
1801
1802                         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1803                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1804                 }
1805
1806                 sg_set_page(sg, page, PAGE_SIZE, 0);
1807         }
1808
1809         obj->pages = st;
1810
1811         if (i915_gem_object_needs_bit17_swizzle(obj))
1812                 i915_gem_object_do_bit_17_swizzle(obj);
1813
1814         return 0;
1815
1816 err_pages:
1817         for_each_sg(st->sgl, sg, i, page_count)
1818                 page_cache_release(sg_page(sg));
1819         sg_free_table(st);
1820         kfree(st);
1821         return PTR_ERR(page);
1822 }
1823
1824 /* Ensure that the associated pages are gathered from the backing storage
1825  * and pinned into our object. i915_gem_object_get_pages() may be called
1826  * multiple times before they are released by a single call to
1827  * i915_gem_object_put_pages() - once the pages are no longer referenced
1828  * either as a result of memory pressure (reaping pages under the shrinker)
1829  * or as the object is itself released.
1830  */
1831 int
1832 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1833 {
1834         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1835         const struct drm_i915_gem_object_ops *ops = obj->ops;
1836         int ret;
1837
1838         if (obj->pages)
1839                 return 0;
1840
1841         BUG_ON(obj->pages_pin_count);
1842
1843         ret = ops->get_pages(obj);
1844         if (ret)
1845                 return ret;
1846
1847         list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1848         return 0;
1849 }
1850
1851 void
1852 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1853                                struct intel_ring_buffer *ring)
1854 {
1855         struct drm_device *dev = obj->base.dev;
1856         struct drm_i915_private *dev_priv = dev->dev_private;
1857         u32 seqno = intel_ring_get_seqno(ring);
1858
1859         BUG_ON(ring == NULL);
1860         obj->ring = ring;
1861
1862         /* Add a reference if we're newly entering the active list. */
1863         if (!obj->active) {
1864                 drm_gem_object_reference(&obj->base);
1865                 obj->active = 1;
1866         }
1867
1868         /* Move from whatever list we were on to the tail of execution. */
1869         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1870         list_move_tail(&obj->ring_list, &ring->active_list);
1871
1872         obj->last_read_seqno = seqno;
1873
1874         if (obj->fenced_gpu_access) {
1875                 obj->last_fenced_seqno = seqno;
1876
1877                 /* Bump MRU to take account of the delayed flush */
1878                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1879                         struct drm_i915_fence_reg *reg;
1880
1881                         reg = &dev_priv->fence_regs[obj->fence_reg];
1882                         list_move_tail(&reg->lru_list,
1883                                        &dev_priv->mm.fence_list);
1884                 }
1885         }
1886 }
1887
1888 static void
1889 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1890 {
1891         struct drm_device *dev = obj->base.dev;
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893
1894         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1895         BUG_ON(!obj->active);
1896
1897         if (obj->pin_count) /* are we a framebuffer? */
1898                 intel_mark_fb_idle(obj);
1899
1900         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1901
1902         list_del_init(&obj->ring_list);
1903         obj->ring = NULL;
1904
1905         obj->last_read_seqno = 0;
1906         obj->last_write_seqno = 0;
1907         obj->base.write_domain = 0;
1908
1909         obj->last_fenced_seqno = 0;
1910         obj->fenced_gpu_access = false;
1911
1912         obj->active = 0;
1913         drm_gem_object_unreference(&obj->base);
1914
1915         WARN_ON(i915_verify_lists(dev));
1916 }
1917
1918 static int
1919 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1920 {
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         struct intel_ring_buffer *ring;
1923         int ret, i, j;
1924
1925         /* The hardware uses various monotonic 32-bit counters, if we
1926          * detect that they will wraparound we need to idle the GPU
1927          * and reset those counters.
1928          */
1929         ret = 0;
1930         for_each_ring(ring, dev_priv, i) {
1931                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1932                         ret |= ring->sync_seqno[j] != 0;
1933         }
1934         if (ret == 0)
1935                 return ret;
1936
1937         ret = i915_gpu_idle(dev);
1938         if (ret)
1939                 return ret;
1940
1941         i915_gem_retire_requests(dev);
1942         for_each_ring(ring, dev_priv, i) {
1943                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1944                         ring->sync_seqno[j] = 0;
1945         }
1946
1947         return 0;
1948 }
1949
1950 int
1951 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1952 {
1953         struct drm_i915_private *dev_priv = dev->dev_private;
1954
1955         /* reserve 0 for non-seqno */
1956         if (dev_priv->next_seqno == 0) {
1957                 int ret = i915_gem_handle_seqno_wrap(dev);
1958                 if (ret)
1959                         return ret;
1960
1961                 dev_priv->next_seqno = 1;
1962         }
1963
1964         *seqno = dev_priv->next_seqno++;
1965         return 0;
1966 }
1967
1968 int
1969 i915_add_request(struct intel_ring_buffer *ring,
1970                  struct drm_file *file,
1971                  u32 *out_seqno)
1972 {
1973         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1974         struct drm_i915_gem_request *request;
1975         u32 request_ring_position;
1976         int was_empty;
1977         int ret;
1978
1979         /*
1980          * Emit any outstanding flushes - execbuf can fail to emit the flush
1981          * after having emitted the batchbuffer command. Hence we need to fix
1982          * things up similar to emitting the lazy request. The difference here
1983          * is that the flush _must_ happen before the next request, no matter
1984          * what.
1985          */
1986         ret = intel_ring_flush_all_caches(ring);
1987         if (ret)
1988                 return ret;
1989
1990         request = kmalloc(sizeof(*request), GFP_KERNEL);
1991         if (request == NULL)
1992                 return -ENOMEM;
1993
1994
1995         /* Record the position of the start of the request so that
1996          * should we detect the updated seqno part-way through the
1997          * GPU processing the request, we never over-estimate the
1998          * position of the head.
1999          */
2000         request_ring_position = intel_ring_get_tail(ring);
2001
2002         ret = ring->add_request(ring);
2003         if (ret) {
2004                 kfree(request);
2005                 return ret;
2006         }
2007
2008         request->seqno = intel_ring_get_seqno(ring);
2009         request->ring = ring;
2010         request->tail = request_ring_position;
2011         request->emitted_jiffies = jiffies;
2012         was_empty = list_empty(&ring->request_list);
2013         list_add_tail(&request->list, &ring->request_list);
2014         request->file_priv = NULL;
2015
2016         if (file) {
2017                 struct drm_i915_file_private *file_priv = file->driver_priv;
2018
2019                 spin_lock(&file_priv->mm.lock);
2020                 request->file_priv = file_priv;
2021                 list_add_tail(&request->client_list,
2022                               &file_priv->mm.request_list);
2023                 spin_unlock(&file_priv->mm.lock);
2024         }
2025
2026         trace_i915_gem_request_add(ring, request->seqno);
2027         ring->outstanding_lazy_request = 0;
2028
2029         if (!dev_priv->mm.suspended) {
2030                 if (i915_enable_hangcheck) {
2031                         mod_timer(&dev_priv->hangcheck_timer,
2032                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2033                 }
2034                 if (was_empty) {
2035                         queue_delayed_work(dev_priv->wq,
2036                                            &dev_priv->mm.retire_work,
2037                                            round_jiffies_up_relative(HZ));
2038                         intel_mark_busy(dev_priv->dev);
2039                 }
2040         }
2041
2042         if (out_seqno)
2043                 *out_seqno = request->seqno;
2044         return 0;
2045 }
2046
2047 static inline void
2048 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2049 {
2050         struct drm_i915_file_private *file_priv = request->file_priv;
2051
2052         if (!file_priv)
2053                 return;
2054
2055         spin_lock(&file_priv->mm.lock);
2056         if (request->file_priv) {
2057                 list_del(&request->client_list);
2058                 request->file_priv = NULL;
2059         }
2060         spin_unlock(&file_priv->mm.lock);
2061 }
2062
2063 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2064                                       struct intel_ring_buffer *ring)
2065 {
2066         while (!list_empty(&ring->request_list)) {
2067                 struct drm_i915_gem_request *request;
2068
2069                 request = list_first_entry(&ring->request_list,
2070                                            struct drm_i915_gem_request,
2071                                            list);
2072
2073                 list_del(&request->list);
2074                 i915_gem_request_remove_from_client(request);
2075                 kfree(request);
2076         }
2077
2078         while (!list_empty(&ring->active_list)) {
2079                 struct drm_i915_gem_object *obj;
2080
2081                 obj = list_first_entry(&ring->active_list,
2082                                        struct drm_i915_gem_object,
2083                                        ring_list);
2084
2085                 i915_gem_object_move_to_inactive(obj);
2086         }
2087 }
2088
2089 static void i915_gem_reset_fences(struct drm_device *dev)
2090 {
2091         struct drm_i915_private *dev_priv = dev->dev_private;
2092         int i;
2093
2094         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2095                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2096
2097                 i915_gem_write_fence(dev, i, NULL);
2098
2099                 if (reg->obj)
2100                         i915_gem_object_fence_lost(reg->obj);
2101
2102                 reg->pin_count = 0;
2103                 reg->obj = NULL;
2104                 INIT_LIST_HEAD(&reg->lru_list);
2105         }
2106
2107         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2108 }
2109
2110 void i915_gem_reset(struct drm_device *dev)
2111 {
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113         struct drm_i915_gem_object *obj;
2114         struct intel_ring_buffer *ring;
2115         int i;
2116
2117         for_each_ring(ring, dev_priv, i)
2118                 i915_gem_reset_ring_lists(dev_priv, ring);
2119
2120         /* Move everything out of the GPU domains to ensure we do any
2121          * necessary invalidation upon reuse.
2122          */
2123         list_for_each_entry(obj,
2124                             &dev_priv->mm.inactive_list,
2125                             mm_list)
2126         {
2127                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2128         }
2129
2130         /* The fence registers are invalidated so clear them out */
2131         i915_gem_reset_fences(dev);
2132 }
2133
2134 /**
2135  * This function clears the request list as sequence numbers are passed.
2136  */
2137 void
2138 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2139 {
2140         uint32_t seqno;
2141
2142         if (list_empty(&ring->request_list))
2143                 return;
2144
2145         WARN_ON(i915_verify_lists(ring->dev));
2146
2147         seqno = ring->get_seqno(ring, true);
2148
2149         while (!list_empty(&ring->request_list)) {
2150                 struct drm_i915_gem_request *request;
2151
2152                 request = list_first_entry(&ring->request_list,
2153                                            struct drm_i915_gem_request,
2154                                            list);
2155
2156                 if (!i915_seqno_passed(seqno, request->seqno))
2157                         break;
2158
2159                 trace_i915_gem_request_retire(ring, request->seqno);
2160                 /* We know the GPU must have read the request to have
2161                  * sent us the seqno + interrupt, so use the position
2162                  * of tail of the request to update the last known position
2163                  * of the GPU head.
2164                  */
2165                 ring->last_retired_head = request->tail;
2166
2167                 list_del(&request->list);
2168                 i915_gem_request_remove_from_client(request);
2169                 kfree(request);
2170         }
2171
2172         /* Move any buffers on the active list that are no longer referenced
2173          * by the ringbuffer to the flushing/inactive lists as appropriate.
2174          */
2175         while (!list_empty(&ring->active_list)) {
2176                 struct drm_i915_gem_object *obj;
2177
2178                 obj = list_first_entry(&ring->active_list,
2179                                       struct drm_i915_gem_object,
2180                                       ring_list);
2181
2182                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2183                         break;
2184
2185                 i915_gem_object_move_to_inactive(obj);
2186         }
2187
2188         if (unlikely(ring->trace_irq_seqno &&
2189                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2190                 ring->irq_put(ring);
2191                 ring->trace_irq_seqno = 0;
2192         }
2193
2194         WARN_ON(i915_verify_lists(ring->dev));
2195 }
2196
2197 void
2198 i915_gem_retire_requests(struct drm_device *dev)
2199 {
2200         drm_i915_private_t *dev_priv = dev->dev_private;
2201         struct intel_ring_buffer *ring;
2202         int i;
2203
2204         for_each_ring(ring, dev_priv, i)
2205                 i915_gem_retire_requests_ring(ring);
2206 }
2207
2208 static void
2209 i915_gem_retire_work_handler(struct work_struct *work)
2210 {
2211         drm_i915_private_t *dev_priv;
2212         struct drm_device *dev;
2213         struct intel_ring_buffer *ring;
2214         bool idle;
2215         int i;
2216
2217         dev_priv = container_of(work, drm_i915_private_t,
2218                                 mm.retire_work.work);
2219         dev = dev_priv->dev;
2220
2221         /* Come back later if the device is busy... */
2222         if (!mutex_trylock(&dev->struct_mutex)) {
2223                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2224                                    round_jiffies_up_relative(HZ));
2225                 return;
2226         }
2227
2228         i915_gem_retire_requests(dev);
2229
2230         /* Send a periodic flush down the ring so we don't hold onto GEM
2231          * objects indefinitely.
2232          */
2233         idle = true;
2234         for_each_ring(ring, dev_priv, i) {
2235                 if (ring->gpu_caches_dirty)
2236                         i915_add_request(ring, NULL, NULL);
2237
2238                 idle &= list_empty(&ring->request_list);
2239         }
2240
2241         if (!dev_priv->mm.suspended && !idle)
2242                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2243                                    round_jiffies_up_relative(HZ));
2244         if (idle)
2245                 intel_mark_idle(dev);
2246
2247         mutex_unlock(&dev->struct_mutex);
2248 }
2249
2250 /**
2251  * Ensures that an object will eventually get non-busy by flushing any required
2252  * write domains, emitting any outstanding lazy request and retiring and
2253  * completed requests.
2254  */
2255 static int
2256 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2257 {
2258         int ret;
2259
2260         if (obj->active) {
2261                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2262                 if (ret)
2263                         return ret;
2264
2265                 i915_gem_retire_requests_ring(obj->ring);
2266         }
2267
2268         return 0;
2269 }
2270
2271 /**
2272  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2273  * @DRM_IOCTL_ARGS: standard ioctl arguments
2274  *
2275  * Returns 0 if successful, else an error is returned with the remaining time in
2276  * the timeout parameter.
2277  *  -ETIME: object is still busy after timeout
2278  *  -ERESTARTSYS: signal interrupted the wait
2279  *  -ENONENT: object doesn't exist
2280  * Also possible, but rare:
2281  *  -EAGAIN: GPU wedged
2282  *  -ENOMEM: damn
2283  *  -ENODEV: Internal IRQ fail
2284  *  -E?: The add request failed
2285  *
2286  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2287  * non-zero timeout parameter the wait ioctl will wait for the given number of
2288  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2289  * without holding struct_mutex the object may become re-busied before this
2290  * function completes. A similar but shorter * race condition exists in the busy
2291  * ioctl
2292  */
2293 int
2294 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2295 {
2296         struct drm_i915_gem_wait *args = data;
2297         struct drm_i915_gem_object *obj;
2298         struct intel_ring_buffer *ring = NULL;
2299         struct timespec timeout_stack, *timeout = NULL;
2300         u32 seqno = 0;
2301         int ret = 0;
2302
2303         if (args->timeout_ns >= 0) {
2304                 timeout_stack = ns_to_timespec(args->timeout_ns);
2305                 timeout = &timeout_stack;
2306         }
2307
2308         ret = i915_mutex_lock_interruptible(dev);
2309         if (ret)
2310                 return ret;
2311
2312         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2313         if (&obj->base == NULL) {
2314                 mutex_unlock(&dev->struct_mutex);
2315                 return -ENOENT;
2316         }
2317
2318         /* Need to make sure the object gets inactive eventually. */
2319         ret = i915_gem_object_flush_active(obj);
2320         if (ret)
2321                 goto out;
2322
2323         if (obj->active) {
2324                 seqno = obj->last_read_seqno;
2325                 ring = obj->ring;
2326         }
2327
2328         if (seqno == 0)
2329                  goto out;
2330
2331         /* Do this after OLR check to make sure we make forward progress polling
2332          * on this IOCTL with a 0 timeout (like busy ioctl)
2333          */
2334         if (!args->timeout_ns) {
2335                 ret = -ETIME;
2336                 goto out;
2337         }
2338
2339         drm_gem_object_unreference(&obj->base);
2340         mutex_unlock(&dev->struct_mutex);
2341
2342         ret = __wait_seqno(ring, seqno, true, timeout);
2343         if (timeout) {
2344                 WARN_ON(!timespec_valid(timeout));
2345                 args->timeout_ns = timespec_to_ns(timeout);
2346         }
2347         return ret;
2348
2349 out:
2350         drm_gem_object_unreference(&obj->base);
2351         mutex_unlock(&dev->struct_mutex);
2352         return ret;
2353 }
2354
2355 /**
2356  * i915_gem_object_sync - sync an object to a ring.
2357  *
2358  * @obj: object which may be in use on another ring.
2359  * @to: ring we wish to use the object on. May be NULL.
2360  *
2361  * This code is meant to abstract object synchronization with the GPU.
2362  * Calling with NULL implies synchronizing the object with the CPU
2363  * rather than a particular GPU ring.
2364  *
2365  * Returns 0 if successful, else propagates up the lower layer error.
2366  */
2367 int
2368 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2369                      struct intel_ring_buffer *to)
2370 {
2371         struct intel_ring_buffer *from = obj->ring;
2372         u32 seqno;
2373         int ret, idx;
2374
2375         if (from == NULL || to == from)
2376                 return 0;
2377
2378         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2379                 return i915_gem_object_wait_rendering(obj, false);
2380
2381         idx = intel_ring_sync_index(from, to);
2382
2383         seqno = obj->last_read_seqno;
2384         if (seqno <= from->sync_seqno[idx])
2385                 return 0;
2386
2387         ret = i915_gem_check_olr(obj->ring, seqno);
2388         if (ret)
2389                 return ret;
2390
2391         ret = to->sync_to(to, from, seqno);
2392         if (!ret)
2393                 /* We use last_read_seqno because sync_to()
2394                  * might have just caused seqno wrap under
2395                  * the radar.
2396                  */
2397                 from->sync_seqno[idx] = obj->last_read_seqno;
2398
2399         return ret;
2400 }
2401
2402 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2403 {
2404         u32 old_write_domain, old_read_domains;
2405
2406         /* Act a barrier for all accesses through the GTT */
2407         mb();
2408
2409         /* Force a pagefault for domain tracking on next user access */
2410         i915_gem_release_mmap(obj);
2411
2412         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2413                 return;
2414
2415         old_read_domains = obj->base.read_domains;
2416         old_write_domain = obj->base.write_domain;
2417
2418         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2419         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2420
2421         trace_i915_gem_object_change_domain(obj,
2422                                             old_read_domains,
2423                                             old_write_domain);
2424 }
2425
2426 /**
2427  * Unbinds an object from the GTT aperture.
2428  */
2429 int
2430 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2431 {
2432         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2433         int ret = 0;
2434
2435         if (obj->gtt_space == NULL)
2436                 return 0;
2437
2438         if (obj->pin_count)
2439                 return -EBUSY;
2440
2441         BUG_ON(obj->pages == NULL);
2442
2443         ret = i915_gem_object_finish_gpu(obj);
2444         if (ret)
2445                 return ret;
2446         /* Continue on if we fail due to EIO, the GPU is hung so we
2447          * should be safe and we need to cleanup or else we might
2448          * cause memory corruption through use-after-free.
2449          */
2450
2451         i915_gem_object_finish_gtt(obj);
2452
2453         /* release the fence reg _after_ flushing */
2454         ret = i915_gem_object_put_fence(obj);
2455         if (ret)
2456                 return ret;
2457
2458         trace_i915_gem_object_unbind(obj);
2459
2460         if (obj->has_global_gtt_mapping)
2461                 i915_gem_gtt_unbind_object(obj);
2462         if (obj->has_aliasing_ppgtt_mapping) {
2463                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2464                 obj->has_aliasing_ppgtt_mapping = 0;
2465         }
2466         i915_gem_gtt_finish_object(obj);
2467
2468         list_del(&obj->mm_list);
2469         list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2470         /* Avoid an unnecessary call to unbind on rebind. */
2471         obj->map_and_fenceable = true;
2472
2473         drm_mm_put_block(obj->gtt_space);
2474         obj->gtt_space = NULL;
2475         obj->gtt_offset = 0;
2476
2477         return 0;
2478 }
2479
2480 int i915_gpu_idle(struct drm_device *dev)
2481 {
2482         drm_i915_private_t *dev_priv = dev->dev_private;
2483         struct intel_ring_buffer *ring;
2484         int ret, i;
2485
2486         /* Flush everything onto the inactive list. */
2487         for_each_ring(ring, dev_priv, i) {
2488                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2489                 if (ret)
2490                         return ret;
2491
2492                 ret = intel_ring_idle(ring);
2493                 if (ret)
2494                         return ret;
2495         }
2496
2497         return 0;
2498 }
2499
2500 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2501                                         struct drm_i915_gem_object *obj)
2502 {
2503         drm_i915_private_t *dev_priv = dev->dev_private;
2504         uint64_t val;
2505
2506         if (obj) {
2507                 u32 size = obj->gtt_space->size;
2508
2509                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2510                                  0xfffff000) << 32;
2511                 val |= obj->gtt_offset & 0xfffff000;
2512                 val |= (uint64_t)((obj->stride / 128) - 1) <<
2513                         SANDYBRIDGE_FENCE_PITCH_SHIFT;
2514
2515                 if (obj->tiling_mode == I915_TILING_Y)
2516                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2517                 val |= I965_FENCE_REG_VALID;
2518         } else
2519                 val = 0;
2520
2521         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2522         POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2523 }
2524
2525 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2526                                  struct drm_i915_gem_object *obj)
2527 {
2528         drm_i915_private_t *dev_priv = dev->dev_private;
2529         uint64_t val;
2530
2531         if (obj) {
2532                 u32 size = obj->gtt_space->size;
2533
2534                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2535                                  0xfffff000) << 32;
2536                 val |= obj->gtt_offset & 0xfffff000;
2537                 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2538                 if (obj->tiling_mode == I915_TILING_Y)
2539                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2540                 val |= I965_FENCE_REG_VALID;
2541         } else
2542                 val = 0;
2543
2544         I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2545         POSTING_READ(FENCE_REG_965_0 + reg * 8);
2546 }
2547
2548 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2549                                  struct drm_i915_gem_object *obj)
2550 {
2551         drm_i915_private_t *dev_priv = dev->dev_private;
2552         u32 val;
2553
2554         if (obj) {
2555                 u32 size = obj->gtt_space->size;
2556                 int pitch_val;
2557                 int tile_width;
2558
2559                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2560                      (size & -size) != size ||
2561                      (obj->gtt_offset & (size - 1)),
2562                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2563                      obj->gtt_offset, obj->map_and_fenceable, size);
2564
2565                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2566                         tile_width = 128;
2567                 else
2568                         tile_width = 512;
2569
2570                 /* Note: pitch better be a power of two tile widths */
2571                 pitch_val = obj->stride / tile_width;
2572                 pitch_val = ffs(pitch_val) - 1;
2573
2574                 val = obj->gtt_offset;
2575                 if (obj->tiling_mode == I915_TILING_Y)
2576                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2577                 val |= I915_FENCE_SIZE_BITS(size);
2578                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2579                 val |= I830_FENCE_REG_VALID;
2580         } else
2581                 val = 0;
2582
2583         if (reg < 8)
2584                 reg = FENCE_REG_830_0 + reg * 4;
2585         else
2586                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2587
2588         I915_WRITE(reg, val);
2589         POSTING_READ(reg);
2590 }
2591
2592 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2593                                 struct drm_i915_gem_object *obj)
2594 {
2595         drm_i915_private_t *dev_priv = dev->dev_private;
2596         uint32_t val;
2597
2598         if (obj) {
2599                 u32 size = obj->gtt_space->size;
2600                 uint32_t pitch_val;
2601
2602                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2603                      (size & -size) != size ||
2604                      (obj->gtt_offset & (size - 1)),
2605                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2606                      obj->gtt_offset, size);
2607
2608                 pitch_val = obj->stride / 128;
2609                 pitch_val = ffs(pitch_val) - 1;
2610
2611                 val = obj->gtt_offset;
2612                 if (obj->tiling_mode == I915_TILING_Y)
2613                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2614                 val |= I830_FENCE_SIZE_BITS(size);
2615                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2616                 val |= I830_FENCE_REG_VALID;
2617         } else
2618                 val = 0;
2619
2620         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2621         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2622 }
2623
2624 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2625                                  struct drm_i915_gem_object *obj)
2626 {
2627         switch (INTEL_INFO(dev)->gen) {
2628         case 7:
2629         case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2630         case 5:
2631         case 4: i965_write_fence_reg(dev, reg, obj); break;
2632         case 3: i915_write_fence_reg(dev, reg, obj); break;
2633         case 2: i830_write_fence_reg(dev, reg, obj); break;
2634         default: break;
2635         }
2636 }
2637
2638 static inline int fence_number(struct drm_i915_private *dev_priv,
2639                                struct drm_i915_fence_reg *fence)
2640 {
2641         return fence - dev_priv->fence_regs;
2642 }
2643
2644 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2645                                          struct drm_i915_fence_reg *fence,
2646                                          bool enable)
2647 {
2648         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2649         int reg = fence_number(dev_priv, fence);
2650
2651         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2652
2653         if (enable) {
2654                 obj->fence_reg = reg;
2655                 fence->obj = obj;
2656                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2657         } else {
2658                 obj->fence_reg = I915_FENCE_REG_NONE;
2659                 fence->obj = NULL;
2660                 list_del_init(&fence->lru_list);
2661         }
2662 }
2663
2664 static int
2665 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2666 {
2667         if (obj->last_fenced_seqno) {
2668                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2669                 if (ret)
2670                         return ret;
2671
2672                 obj->last_fenced_seqno = 0;
2673         }
2674
2675         /* Ensure that all CPU reads are completed before installing a fence
2676          * and all writes before removing the fence.
2677          */
2678         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2679                 mb();
2680
2681         obj->fenced_gpu_access = false;
2682         return 0;
2683 }
2684
2685 int
2686 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2687 {
2688         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2689         int ret;
2690
2691         ret = i915_gem_object_flush_fence(obj);
2692         if (ret)
2693                 return ret;
2694
2695         if (obj->fence_reg == I915_FENCE_REG_NONE)
2696                 return 0;
2697
2698         i915_gem_object_update_fence(obj,
2699                                      &dev_priv->fence_regs[obj->fence_reg],
2700                                      false);
2701         i915_gem_object_fence_lost(obj);
2702
2703         return 0;
2704 }
2705
2706 static struct drm_i915_fence_reg *
2707 i915_find_fence_reg(struct drm_device *dev)
2708 {
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         struct drm_i915_fence_reg *reg, *avail;
2711         int i;
2712
2713         /* First try to find a free reg */
2714         avail = NULL;
2715         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2716                 reg = &dev_priv->fence_regs[i];
2717                 if (!reg->obj)
2718                         return reg;
2719
2720                 if (!reg->pin_count)
2721                         avail = reg;
2722         }
2723
2724         if (avail == NULL)
2725                 return NULL;
2726
2727         /* None available, try to steal one or wait for a user to finish */
2728         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2729                 if (reg->pin_count)
2730                         continue;
2731
2732                 return reg;
2733         }
2734
2735         return NULL;
2736 }
2737
2738 /**
2739  * i915_gem_object_get_fence - set up fencing for an object
2740  * @obj: object to map through a fence reg
2741  *
2742  * When mapping objects through the GTT, userspace wants to be able to write
2743  * to them without having to worry about swizzling if the object is tiled.
2744  * This function walks the fence regs looking for a free one for @obj,
2745  * stealing one if it can't find any.
2746  *
2747  * It then sets up the reg based on the object's properties: address, pitch
2748  * and tiling format.
2749  *
2750  * For an untiled surface, this removes any existing fence.
2751  */
2752 int
2753 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2754 {
2755         struct drm_device *dev = obj->base.dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757         bool enable = obj->tiling_mode != I915_TILING_NONE;
2758         struct drm_i915_fence_reg *reg;
2759         int ret;
2760
2761         /* Have we updated the tiling parameters upon the object and so
2762          * will need to serialise the write to the associated fence register?
2763          */
2764         if (obj->fence_dirty) {
2765                 ret = i915_gem_object_flush_fence(obj);
2766                 if (ret)
2767                         return ret;
2768         }
2769
2770         /* Just update our place in the LRU if our fence is getting reused. */
2771         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2772                 reg = &dev_priv->fence_regs[obj->fence_reg];
2773                 if (!obj->fence_dirty) {
2774                         list_move_tail(&reg->lru_list,
2775                                        &dev_priv->mm.fence_list);
2776                         return 0;
2777                 }
2778         } else if (enable) {
2779                 reg = i915_find_fence_reg(dev);
2780                 if (reg == NULL)
2781                         return -EDEADLK;
2782
2783                 if (reg->obj) {
2784                         struct drm_i915_gem_object *old = reg->obj;
2785
2786                         ret = i915_gem_object_flush_fence(old);
2787                         if (ret)
2788                                 return ret;
2789
2790                         i915_gem_object_fence_lost(old);
2791                 }
2792         } else
2793                 return 0;
2794
2795         i915_gem_object_update_fence(obj, reg, enable);
2796         obj->fence_dirty = false;
2797
2798         return 0;
2799 }
2800
2801 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2802                                      struct drm_mm_node *gtt_space,
2803                                      unsigned long cache_level)
2804 {
2805         struct drm_mm_node *other;
2806
2807         /* On non-LLC machines we have to be careful when putting differing
2808          * types of snoopable memory together to avoid the prefetcher
2809          * crossing memory domains and dieing.
2810          */
2811         if (HAS_LLC(dev))
2812                 return true;
2813
2814         if (gtt_space == NULL)
2815                 return true;
2816
2817         if (list_empty(&gtt_space->node_list))
2818                 return true;
2819
2820         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2821         if (other->allocated && !other->hole_follows && other->color != cache_level)
2822                 return false;
2823
2824         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2825         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2826                 return false;
2827
2828         return true;
2829 }
2830
2831 static void i915_gem_verify_gtt(struct drm_device *dev)
2832 {
2833 #if WATCH_GTT
2834         struct drm_i915_private *dev_priv = dev->dev_private;
2835         struct drm_i915_gem_object *obj;
2836         int err = 0;
2837
2838         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2839                 if (obj->gtt_space == NULL) {
2840                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
2841                         err++;
2842                         continue;
2843                 }
2844
2845                 if (obj->cache_level != obj->gtt_space->color) {
2846                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2847                                obj->gtt_space->start,
2848                                obj->gtt_space->start + obj->gtt_space->size,
2849                                obj->cache_level,
2850                                obj->gtt_space->color);
2851                         err++;
2852                         continue;
2853                 }
2854
2855                 if (!i915_gem_valid_gtt_space(dev,
2856                                               obj->gtt_space,
2857                                               obj->cache_level)) {
2858                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2859                                obj->gtt_space->start,
2860                                obj->gtt_space->start + obj->gtt_space->size,
2861                                obj->cache_level);
2862                         err++;
2863                         continue;
2864                 }
2865         }
2866
2867         WARN_ON(err);
2868 #endif
2869 }
2870
2871 /**
2872  * Finds free space in the GTT aperture and binds the object there.
2873  */
2874 static int
2875 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2876                             unsigned alignment,
2877                             bool map_and_fenceable,
2878                             bool nonblocking)
2879 {
2880         struct drm_device *dev = obj->base.dev;
2881         drm_i915_private_t *dev_priv = dev->dev_private;
2882         struct drm_mm_node *free_space;
2883         u32 size, fence_size, fence_alignment, unfenced_alignment;
2884         bool mappable, fenceable;
2885         int ret;
2886
2887         if (obj->madv != I915_MADV_WILLNEED) {
2888                 DRM_ERROR("Attempting to bind a purgeable object\n");
2889                 return -EINVAL;
2890         }
2891
2892         fence_size = i915_gem_get_gtt_size(dev,
2893                                            obj->base.size,
2894                                            obj->tiling_mode);
2895         fence_alignment = i915_gem_get_gtt_alignment(dev,
2896                                                      obj->base.size,
2897                                                      obj->tiling_mode);
2898         unfenced_alignment =
2899                 i915_gem_get_unfenced_gtt_alignment(dev,
2900                                                     obj->base.size,
2901                                                     obj->tiling_mode);
2902
2903         if (alignment == 0)
2904                 alignment = map_and_fenceable ? fence_alignment :
2905                                                 unfenced_alignment;
2906         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2907                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2908                 return -EINVAL;
2909         }
2910
2911         size = map_and_fenceable ? fence_size : obj->base.size;
2912
2913         /* If the object is bigger than the entire aperture, reject it early
2914          * before evicting everything in a vain attempt to find space.
2915          */
2916         if (obj->base.size >
2917             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2918                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2919                 return -E2BIG;
2920         }
2921
2922         ret = i915_gem_object_get_pages(obj);
2923         if (ret)
2924                 return ret;
2925
2926         i915_gem_object_pin_pages(obj);
2927
2928  search_free:
2929         if (map_and_fenceable)
2930                 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2931                                                                size, alignment, obj->cache_level,
2932                                                                0, dev_priv->mm.gtt_mappable_end,
2933                                                                false);
2934         else
2935                 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2936                                                       size, alignment, obj->cache_level,
2937                                                       false);
2938
2939         if (free_space != NULL) {
2940                 if (map_and_fenceable)
2941                         free_space =
2942                                 drm_mm_get_block_range_generic(free_space,
2943                                                                size, alignment, obj->cache_level,
2944                                                                0, dev_priv->mm.gtt_mappable_end,
2945                                                                false);
2946                 else
2947                         free_space =
2948                                 drm_mm_get_block_generic(free_space,
2949                                                          size, alignment, obj->cache_level,
2950                                                          false);
2951         }
2952         if (free_space == NULL) {
2953                 ret = i915_gem_evict_something(dev, size, alignment,
2954                                                obj->cache_level,
2955                                                map_and_fenceable,
2956                                                nonblocking);
2957                 if (ret) {
2958                         i915_gem_object_unpin_pages(obj);
2959                         return ret;
2960                 }
2961
2962                 goto search_free;
2963         }
2964         if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2965                                               free_space,
2966                                               obj->cache_level))) {
2967                 i915_gem_object_unpin_pages(obj);
2968                 drm_mm_put_block(free_space);
2969                 return -EINVAL;
2970         }
2971
2972         ret = i915_gem_gtt_prepare_object(obj);
2973         if (ret) {
2974                 i915_gem_object_unpin_pages(obj);
2975                 drm_mm_put_block(free_space);
2976                 return ret;
2977         }
2978
2979         list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2980         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2981
2982         obj->gtt_space = free_space;
2983         obj->gtt_offset = free_space->start;
2984
2985         fenceable =
2986                 free_space->size == fence_size &&
2987                 (free_space->start & (fence_alignment - 1)) == 0;
2988
2989         mappable =
2990                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2991
2992         obj->map_and_fenceable = mappable && fenceable;
2993
2994         i915_gem_object_unpin_pages(obj);
2995         trace_i915_gem_object_bind(obj, map_and_fenceable);
2996         i915_gem_verify_gtt(dev);
2997         return 0;
2998 }
2999
3000 void
3001 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3002 {
3003         /* If we don't have a page list set up, then we're not pinned
3004          * to GPU, and we can ignore the cache flush because it'll happen
3005          * again at bind time.
3006          */
3007         if (obj->pages == NULL)
3008                 return;
3009
3010         /* If the GPU is snooping the contents of the CPU cache,
3011          * we do not need to manually clear the CPU cache lines.  However,
3012          * the caches are only snooped when the render cache is
3013          * flushed/invalidated.  As we always have to emit invalidations
3014          * and flushes when moving into and out of the RENDER domain, correct
3015          * snooping behaviour occurs naturally as the result of our domain
3016          * tracking.
3017          */
3018         if (obj->cache_level != I915_CACHE_NONE)
3019                 return;
3020
3021         trace_i915_gem_object_clflush(obj);
3022
3023         drm_clflush_sg(obj->pages);
3024 }
3025
3026 /** Flushes the GTT write domain for the object if it's dirty. */
3027 static void
3028 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3029 {
3030         uint32_t old_write_domain;
3031
3032         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3033                 return;
3034
3035         /* No actual flushing is required for the GTT write domain.  Writes
3036          * to it immediately go to main memory as far as we know, so there's
3037          * no chipset flush.  It also doesn't land in render cache.
3038          *
3039          * However, we do have to enforce the order so that all writes through
3040          * the GTT land before any writes to the device, such as updates to
3041          * the GATT itself.
3042          */
3043         wmb();
3044
3045         old_write_domain = obj->base.write_domain;
3046         obj->base.write_domain = 0;
3047
3048         trace_i915_gem_object_change_domain(obj,
3049                                             obj->base.read_domains,
3050                                             old_write_domain);
3051 }
3052
3053 /** Flushes the CPU write domain for the object if it's dirty. */
3054 static void
3055 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3056 {
3057         uint32_t old_write_domain;
3058
3059         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3060                 return;
3061
3062         i915_gem_clflush_object(obj);
3063         i915_gem_chipset_flush(obj->base.dev);
3064         old_write_domain = obj->base.write_domain;
3065         obj->base.write_domain = 0;
3066
3067         trace_i915_gem_object_change_domain(obj,
3068                                             obj->base.read_domains,
3069                                             old_write_domain);
3070 }
3071
3072 /**
3073  * Moves a single object to the GTT read, and possibly write domain.
3074  *
3075  * This function returns when the move is complete, including waiting on
3076  * flushes to occur.
3077  */
3078 int
3079 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3080 {
3081         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3082         uint32_t old_write_domain, old_read_domains;
3083         int ret;
3084
3085         /* Not valid to be called on unbound objects. */
3086         if (obj->gtt_space == NULL)
3087                 return -EINVAL;
3088
3089         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3090                 return 0;
3091
3092         ret = i915_gem_object_wait_rendering(obj, !write);
3093         if (ret)
3094                 return ret;
3095
3096         i915_gem_object_flush_cpu_write_domain(obj);
3097
3098         old_write_domain = obj->base.write_domain;
3099         old_read_domains = obj->base.read_domains;
3100
3101         /* It should now be out of any other write domains, and we can update
3102          * the domain values for our changes.
3103          */
3104         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3105         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3106         if (write) {
3107                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3108                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3109                 obj->dirty = 1;
3110         }
3111
3112         trace_i915_gem_object_change_domain(obj,
3113                                             old_read_domains,
3114                                             old_write_domain);
3115
3116         /* And bump the LRU for this access */
3117         if (i915_gem_object_is_inactive(obj))
3118                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3119
3120         return 0;
3121 }
3122
3123 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3124                                     enum i915_cache_level cache_level)
3125 {
3126         struct drm_device *dev = obj->base.dev;
3127         drm_i915_private_t *dev_priv = dev->dev_private;
3128         int ret;
3129
3130         if (obj->cache_level == cache_level)
3131                 return 0;
3132
3133         if (obj->pin_count) {
3134                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3135                 return -EBUSY;
3136         }
3137
3138         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3139                 ret = i915_gem_object_unbind(obj);
3140                 if (ret)
3141                         return ret;
3142         }
3143
3144         if (obj->gtt_space) {
3145                 ret = i915_gem_object_finish_gpu(obj);
3146                 if (ret)
3147                         return ret;
3148
3149                 i915_gem_object_finish_gtt(obj);
3150
3151                 /* Before SandyBridge, you could not use tiling or fence
3152                  * registers with snooped memory, so relinquish any fences
3153                  * currently pointing to our region in the aperture.
3154                  */
3155                 if (INTEL_INFO(dev)->gen < 6) {
3156                         ret = i915_gem_object_put_fence(obj);
3157                         if (ret)
3158                                 return ret;
3159                 }
3160
3161                 if (obj->has_global_gtt_mapping)
3162                         i915_gem_gtt_bind_object(obj, cache_level);
3163                 if (obj->has_aliasing_ppgtt_mapping)
3164                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3165                                                obj, cache_level);
3166
3167                 obj->gtt_space->color = cache_level;
3168         }
3169
3170         if (cache_level == I915_CACHE_NONE) {
3171                 u32 old_read_domains, old_write_domain;
3172
3173                 /* If we're coming from LLC cached, then we haven't
3174                  * actually been tracking whether the data is in the
3175                  * CPU cache or not, since we only allow one bit set
3176                  * in obj->write_domain and have been skipping the clflushes.
3177                  * Just set it to the CPU cache for now.
3178                  */
3179                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3180                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3181
3182                 old_read_domains = obj->base.read_domains;
3183                 old_write_domain = obj->base.write_domain;
3184
3185                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3186                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3187
3188                 trace_i915_gem_object_change_domain(obj,
3189                                                     old_read_domains,
3190                                                     old_write_domain);
3191         }
3192
3193         obj->cache_level = cache_level;
3194         i915_gem_verify_gtt(dev);
3195         return 0;
3196 }
3197
3198 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3199                                struct drm_file *file)
3200 {
3201         struct drm_i915_gem_caching *args = data;
3202         struct drm_i915_gem_object *obj;
3203         int ret;
3204
3205         ret = i915_mutex_lock_interruptible(dev);
3206         if (ret)
3207                 return ret;
3208
3209         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3210         if (&obj->base == NULL) {
3211                 ret = -ENOENT;
3212                 goto unlock;
3213         }
3214
3215         args->caching = obj->cache_level != I915_CACHE_NONE;
3216
3217         drm_gem_object_unreference(&obj->base);
3218 unlock:
3219         mutex_unlock(&dev->struct_mutex);
3220         return ret;
3221 }
3222
3223 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3224                                struct drm_file *file)
3225 {
3226         struct drm_i915_gem_caching *args = data;
3227         struct drm_i915_gem_object *obj;
3228         enum i915_cache_level level;
3229         int ret;
3230
3231         switch (args->caching) {
3232         case I915_CACHING_NONE:
3233                 level = I915_CACHE_NONE;
3234                 break;
3235         case I915_CACHING_CACHED:
3236                 level = I915_CACHE_LLC;
3237                 break;
3238         default:
3239                 return -EINVAL;
3240         }
3241
3242         ret = i915_mutex_lock_interruptible(dev);
3243         if (ret)
3244                 return ret;
3245
3246         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3247         if (&obj->base == NULL) {
3248                 ret = -ENOENT;
3249                 goto unlock;
3250         }
3251
3252         ret = i915_gem_object_set_cache_level(obj, level);
3253
3254         drm_gem_object_unreference(&obj->base);
3255 unlock:
3256         mutex_unlock(&dev->struct_mutex);
3257         return ret;
3258 }
3259
3260 /*
3261  * Prepare buffer for display plane (scanout, cursors, etc).
3262  * Can be called from an uninterruptible phase (modesetting) and allows
3263  * any flushes to be pipelined (for pageflips).
3264  */
3265 int
3266 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3267                                      u32 alignment,
3268                                      struct intel_ring_buffer *pipelined)
3269 {
3270         u32 old_read_domains, old_write_domain;
3271         int ret;
3272
3273         if (pipelined != obj->ring) {
3274                 ret = i915_gem_object_sync(obj, pipelined);
3275                 if (ret)
3276                         return ret;
3277         }
3278
3279         /* The display engine is not coherent with the LLC cache on gen6.  As
3280          * a result, we make sure that the pinning that is about to occur is
3281          * done with uncached PTEs. This is lowest common denominator for all
3282          * chipsets.
3283          *
3284          * However for gen6+, we could do better by using the GFDT bit instead
3285          * of uncaching, which would allow us to flush all the LLC-cached data
3286          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3287          */
3288         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3289         if (ret)
3290                 return ret;
3291
3292         /* As the user may map the buffer once pinned in the display plane
3293          * (e.g. libkms for the bootup splash), we have to ensure that we
3294          * always use map_and_fenceable for all scanout buffers.
3295          */
3296         ret = i915_gem_object_pin(obj, alignment, true, false);
3297         if (ret)
3298                 return ret;
3299
3300         i915_gem_object_flush_cpu_write_domain(obj);
3301
3302         old_write_domain = obj->base.write_domain;
3303         old_read_domains = obj->base.read_domains;
3304
3305         /* It should now be out of any other write domains, and we can update
3306          * the domain values for our changes.
3307          */
3308         obj->base.write_domain = 0;
3309         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3310
3311         trace_i915_gem_object_change_domain(obj,
3312                                             old_read_domains,
3313                                             old_write_domain);
3314
3315         return 0;
3316 }
3317
3318 int
3319 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3320 {
3321         int ret;
3322
3323         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3324                 return 0;
3325
3326         ret = i915_gem_object_wait_rendering(obj, false);
3327         if (ret)
3328                 return ret;
3329
3330         /* Ensure that we invalidate the GPU's caches and TLBs. */
3331         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3332         return 0;
3333 }
3334
3335 /**
3336  * Moves a single object to the CPU read, and possibly write domain.
3337  *
3338  * This function returns when the move is complete, including waiting on
3339  * flushes to occur.
3340  */
3341 int
3342 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3343 {
3344         uint32_t old_write_domain, old_read_domains;
3345         int ret;
3346
3347         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3348                 return 0;
3349
3350         ret = i915_gem_object_wait_rendering(obj, !write);
3351         if (ret)
3352                 return ret;
3353
3354         i915_gem_object_flush_gtt_write_domain(obj);
3355
3356         old_write_domain = obj->base.write_domain;
3357         old_read_domains = obj->base.read_domains;
3358
3359         /* Flush the CPU cache if it's still invalid. */
3360         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3361                 i915_gem_clflush_object(obj);
3362
3363                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3364         }
3365
3366         /* It should now be out of any other write domains, and we can update
3367          * the domain values for our changes.
3368          */
3369         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3370
3371         /* If we're writing through the CPU, then the GPU read domains will
3372          * need to be invalidated at next use.
3373          */
3374         if (write) {
3375                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3376                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3377         }
3378
3379         trace_i915_gem_object_change_domain(obj,
3380                                             old_read_domains,
3381                                             old_write_domain);
3382
3383         return 0;
3384 }
3385
3386 /* Throttle our rendering by waiting until the ring has completed our requests
3387  * emitted over 20 msec ago.
3388  *
3389  * Note that if we were to use the current jiffies each time around the loop,
3390  * we wouldn't escape the function with any frames outstanding if the time to
3391  * render a frame was over 20ms.
3392  *
3393  * This should get us reasonable parallelism between CPU and GPU but also
3394  * relatively low latency when blocking on a particular request to finish.
3395  */
3396 static int
3397 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3398 {
3399         struct drm_i915_private *dev_priv = dev->dev_private;
3400         struct drm_i915_file_private *file_priv = file->driver_priv;
3401         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3402         struct drm_i915_gem_request *request;
3403         struct intel_ring_buffer *ring = NULL;
3404         u32 seqno = 0;
3405         int ret;
3406
3407         if (atomic_read(&dev_priv->mm.wedged))
3408                 return -EIO;
3409
3410         spin_lock(&file_priv->mm.lock);
3411         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3412                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3413                         break;
3414
3415                 ring = request->ring;
3416                 seqno = request->seqno;
3417         }
3418         spin_unlock(&file_priv->mm.lock);
3419
3420         if (seqno == 0)
3421                 return 0;
3422
3423         ret = __wait_seqno(ring, seqno, true, NULL);
3424         if (ret == 0)
3425                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3426
3427         return ret;
3428 }
3429
3430 int
3431 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3432                     uint32_t alignment,
3433                     bool map_and_fenceable,
3434                     bool nonblocking)
3435 {
3436         int ret;
3437
3438         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3439                 return -EBUSY;
3440
3441         if (obj->gtt_space != NULL) {
3442                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3443                     (map_and_fenceable && !obj->map_and_fenceable)) {
3444                         WARN(obj->pin_count,
3445                              "bo is already pinned with incorrect alignment:"
3446                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3447                              " obj->map_and_fenceable=%d\n",
3448                              obj->gtt_offset, alignment,
3449                              map_and_fenceable,
3450                              obj->map_and_fenceable);
3451                         ret = i915_gem_object_unbind(obj);
3452                         if (ret)
3453                                 return ret;
3454                 }
3455         }
3456
3457         if (obj->gtt_space == NULL) {
3458                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3459
3460                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3461                                                   map_and_fenceable,
3462                                                   nonblocking);
3463                 if (ret)
3464                         return ret;
3465
3466                 if (!dev_priv->mm.aliasing_ppgtt)
3467                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3468         }
3469
3470         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3471                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3472
3473         obj->pin_count++;
3474         obj->pin_mappable |= map_and_fenceable;
3475
3476         return 0;
3477 }
3478
3479 void
3480 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3481 {
3482         BUG_ON(obj->pin_count == 0);
3483         BUG_ON(obj->gtt_space == NULL);
3484
3485         if (--obj->pin_count == 0)
3486                 obj->pin_mappable = false;
3487 }
3488
3489 int
3490 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3491                    struct drm_file *file)
3492 {
3493         struct drm_i915_gem_pin *args = data;
3494         struct drm_i915_gem_object *obj;
3495         int ret;
3496
3497         ret = i915_mutex_lock_interruptible(dev);
3498         if (ret)
3499                 return ret;
3500
3501         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3502         if (&obj->base == NULL) {
3503                 ret = -ENOENT;
3504                 goto unlock;
3505         }
3506
3507         if (obj->madv != I915_MADV_WILLNEED) {
3508                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3509                 ret = -EINVAL;
3510                 goto out;
3511         }
3512
3513         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3514                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3515                           args->handle);
3516                 ret = -EINVAL;
3517                 goto out;
3518         }
3519
3520         obj->user_pin_count++;
3521         obj->pin_filp = file;
3522         if (obj->user_pin_count == 1) {
3523                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3524                 if (ret)
3525                         goto out;
3526         }
3527
3528         /* XXX - flush the CPU caches for pinned objects
3529          * as the X server doesn't manage domains yet
3530          */
3531         i915_gem_object_flush_cpu_write_domain(obj);
3532         args->offset = obj->gtt_offset;
3533 out:
3534         drm_gem_object_unreference(&obj->base);
3535 unlock:
3536         mutex_unlock(&dev->struct_mutex);
3537         return ret;
3538 }
3539
3540 int
3541 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3542                      struct drm_file *file)
3543 {
3544         struct drm_i915_gem_pin *args = data;
3545         struct drm_i915_gem_object *obj;
3546         int ret;
3547
3548         ret = i915_mutex_lock_interruptible(dev);
3549         if (ret)
3550                 return ret;
3551
3552         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3553         if (&obj->base == NULL) {
3554                 ret = -ENOENT;
3555                 goto unlock;
3556         }
3557
3558         if (obj->pin_filp != file) {
3559                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3560                           args->handle);
3561                 ret = -EINVAL;
3562                 goto out;
3563         }
3564         obj->user_pin_count--;
3565         if (obj->user_pin_count == 0) {
3566                 obj->pin_filp = NULL;
3567                 i915_gem_object_unpin(obj);
3568         }
3569
3570 out:
3571         drm_gem_object_unreference(&obj->base);
3572 unlock:
3573         mutex_unlock(&dev->struct_mutex);
3574         return ret;
3575 }
3576
3577 int
3578 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3579                     struct drm_file *file)
3580 {
3581         struct drm_i915_gem_busy *args = data;
3582         struct drm_i915_gem_object *obj;
3583         int ret;
3584
3585         ret = i915_mutex_lock_interruptible(dev);
3586         if (ret)
3587                 return ret;
3588
3589         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3590         if (&obj->base == NULL) {
3591                 ret = -ENOENT;
3592                 goto unlock;
3593         }
3594
3595         /* Count all active objects as busy, even if they are currently not used
3596          * by the gpu. Users of this interface expect objects to eventually
3597          * become non-busy without any further actions, therefore emit any
3598          * necessary flushes here.
3599          */
3600         ret = i915_gem_object_flush_active(obj);
3601
3602         args->busy = obj->active;
3603         if (obj->ring) {
3604                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3605                 args->busy |= intel_ring_flag(obj->ring) << 16;
3606         }
3607
3608         drm_gem_object_unreference(&obj->base);
3609 unlock:
3610         mutex_unlock(&dev->struct_mutex);
3611         return ret;
3612 }
3613
3614 int
3615 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3616                         struct drm_file *file_priv)
3617 {
3618         return i915_gem_ring_throttle(dev, file_priv);
3619 }
3620
3621 int
3622 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3623                        struct drm_file *file_priv)
3624 {
3625         struct drm_i915_gem_madvise *args = data;
3626         struct drm_i915_gem_object *obj;
3627         int ret;
3628
3629         switch (args->madv) {
3630         case I915_MADV_DONTNEED:
3631         case I915_MADV_WILLNEED:
3632             break;
3633         default:
3634             return -EINVAL;
3635         }
3636
3637         ret = i915_mutex_lock_interruptible(dev);
3638         if (ret)
3639                 return ret;
3640
3641         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3642         if (&obj->base == NULL) {
3643                 ret = -ENOENT;
3644                 goto unlock;
3645         }
3646
3647         if (obj->pin_count) {
3648                 ret = -EINVAL;
3649                 goto out;
3650         }
3651
3652         if (obj->madv != __I915_MADV_PURGED)
3653                 obj->madv = args->madv;
3654
3655         /* if the object is no longer attached, discard its backing storage */
3656         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3657                 i915_gem_object_truncate(obj);
3658
3659         args->retained = obj->madv != __I915_MADV_PURGED;
3660
3661 out:
3662         drm_gem_object_unreference(&obj->base);
3663 unlock:
3664         mutex_unlock(&dev->struct_mutex);
3665         return ret;
3666 }
3667
3668 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3669                           const struct drm_i915_gem_object_ops *ops)
3670 {
3671         INIT_LIST_HEAD(&obj->mm_list);
3672         INIT_LIST_HEAD(&obj->gtt_list);
3673         INIT_LIST_HEAD(&obj->ring_list);
3674         INIT_LIST_HEAD(&obj->exec_list);
3675
3676         obj->ops = ops;
3677
3678         obj->fence_reg = I915_FENCE_REG_NONE;
3679         obj->madv = I915_MADV_WILLNEED;
3680         /* Avoid an unnecessary call to unbind on the first bind. */
3681         obj->map_and_fenceable = true;
3682
3683         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3684 }
3685
3686 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3687         .get_pages = i915_gem_object_get_pages_gtt,
3688         .put_pages = i915_gem_object_put_pages_gtt,
3689 };
3690
3691 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3692                                                   size_t size)
3693 {
3694         struct drm_i915_gem_object *obj;
3695         struct address_space *mapping;
3696         u32 mask;
3697
3698         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3699         if (obj == NULL)
3700                 return NULL;
3701
3702         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3703                 kfree(obj);
3704                 return NULL;
3705         }
3706
3707         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3708         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3709                 /* 965gm cannot relocate objects above 4GiB. */
3710                 mask &= ~__GFP_HIGHMEM;
3711                 mask |= __GFP_DMA32;
3712         }
3713
3714         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3715         mapping_set_gfp_mask(mapping, mask);
3716
3717         i915_gem_object_init(obj, &i915_gem_object_ops);
3718
3719         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3720         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3721
3722         if (HAS_LLC(dev)) {
3723                 /* On some devices, we can have the GPU use the LLC (the CPU
3724                  * cache) for about a 10% performance improvement
3725                  * compared to uncached.  Graphics requests other than
3726                  * display scanout are coherent with the CPU in
3727                  * accessing this cache.  This means in this mode we
3728                  * don't need to clflush on the CPU side, and on the
3729                  * GPU side we only need to flush internal caches to
3730                  * get data visible to the CPU.
3731                  *
3732                  * However, we maintain the display planes as UC, and so
3733                  * need to rebind when first used as such.
3734                  */
3735                 obj->cache_level = I915_CACHE_LLC;
3736         } else
3737                 obj->cache_level = I915_CACHE_NONE;
3738
3739         return obj;
3740 }
3741
3742 int i915_gem_init_object(struct drm_gem_object *obj)
3743 {
3744         BUG();
3745
3746         return 0;
3747 }
3748
3749 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3750 {
3751         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3752         struct drm_device *dev = obj->base.dev;
3753         drm_i915_private_t *dev_priv = dev->dev_private;
3754
3755         trace_i915_gem_object_destroy(obj);
3756
3757         if (obj->phys_obj)
3758                 i915_gem_detach_phys_object(dev, obj);
3759
3760         obj->pin_count = 0;
3761         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3762                 bool was_interruptible;
3763
3764                 was_interruptible = dev_priv->mm.interruptible;
3765                 dev_priv->mm.interruptible = false;
3766
3767                 WARN_ON(i915_gem_object_unbind(obj));
3768
3769                 dev_priv->mm.interruptible = was_interruptible;
3770         }
3771
3772         obj->pages_pin_count = 0;
3773         i915_gem_object_put_pages(obj);
3774         i915_gem_object_free_mmap_offset(obj);
3775         i915_gem_object_release_stolen(obj);
3776
3777         BUG_ON(obj->pages);
3778
3779         if (obj->base.import_attach)
3780                 drm_prime_gem_destroy(&obj->base, NULL);
3781
3782         drm_gem_object_release(&obj->base);
3783         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3784
3785         kfree(obj->bit_17);
3786         kfree(obj);
3787 }
3788
3789 int
3790 i915_gem_idle(struct drm_device *dev)
3791 {
3792         drm_i915_private_t *dev_priv = dev->dev_private;
3793         int ret;
3794
3795         mutex_lock(&dev->struct_mutex);
3796
3797         if (dev_priv->mm.suspended) {
3798                 mutex_unlock(&dev->struct_mutex);
3799                 return 0;
3800         }
3801
3802         ret = i915_gpu_idle(dev);
3803         if (ret) {
3804                 mutex_unlock(&dev->struct_mutex);
3805                 return ret;
3806         }
3807         i915_gem_retire_requests(dev);
3808
3809         /* Under UMS, be paranoid and evict. */
3810         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3811                 i915_gem_evict_everything(dev);
3812
3813         i915_gem_reset_fences(dev);
3814
3815         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3816          * We need to replace this with a semaphore, or something.
3817          * And not confound mm.suspended!
3818          */
3819         dev_priv->mm.suspended = 1;
3820         del_timer_sync(&dev_priv->hangcheck_timer);
3821
3822         i915_kernel_lost_context(dev);
3823         i915_gem_cleanup_ringbuffer(dev);
3824
3825         mutex_unlock(&dev->struct_mutex);
3826
3827         /* Cancel the retire work handler, which should be idle now. */
3828         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3829
3830         return 0;
3831 }
3832
3833 void i915_gem_l3_remap(struct drm_device *dev)
3834 {
3835         drm_i915_private_t *dev_priv = dev->dev_private;
3836         u32 misccpctl;
3837         int i;
3838
3839         if (!IS_IVYBRIDGE(dev))
3840                 return;
3841
3842         if (!dev_priv->l3_parity.remap_info)
3843                 return;
3844
3845         misccpctl = I915_READ(GEN7_MISCCPCTL);
3846         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3847         POSTING_READ(GEN7_MISCCPCTL);
3848
3849         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3850                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3851                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3852                         DRM_DEBUG("0x%x was already programmed to %x\n",
3853                                   GEN7_L3LOG_BASE + i, remap);
3854                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3855                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
3856                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3857         }
3858
3859         /* Make sure all the writes land before disabling dop clock gating */
3860         POSTING_READ(GEN7_L3LOG_BASE);
3861
3862         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3863 }
3864
3865 void i915_gem_init_swizzling(struct drm_device *dev)
3866 {
3867         drm_i915_private_t *dev_priv = dev->dev_private;
3868
3869         if (INTEL_INFO(dev)->gen < 5 ||
3870             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3871                 return;
3872
3873         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3874                                  DISP_TILE_SURFACE_SWIZZLING);
3875
3876         if (IS_GEN5(dev))
3877                 return;
3878
3879         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3880         if (IS_GEN6(dev))
3881                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3882         else
3883                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3884 }
3885
3886 static bool
3887 intel_enable_blt(struct drm_device *dev)
3888 {
3889         if (!HAS_BLT(dev))
3890                 return false;
3891
3892         /* The blitter was dysfunctional on early prototypes */
3893         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3894                 DRM_INFO("BLT not supported on this pre-production hardware;"
3895                          " graphics performance will be degraded.\n");
3896                 return false;
3897         }
3898
3899         return true;
3900 }
3901
3902 int
3903 i915_gem_init_hw(struct drm_device *dev)
3904 {
3905         drm_i915_private_t *dev_priv = dev->dev_private;
3906         int ret;
3907
3908         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3909                 return -EIO;
3910
3911         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3912                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3913
3914         i915_gem_l3_remap(dev);
3915
3916         i915_gem_init_swizzling(dev);
3917
3918         ret = intel_init_render_ring_buffer(dev);
3919         if (ret)
3920                 return ret;
3921
3922         if (HAS_BSD(dev)) {
3923                 ret = intel_init_bsd_ring_buffer(dev);
3924                 if (ret)
3925                         goto cleanup_render_ring;
3926         }
3927
3928         if (intel_enable_blt(dev)) {
3929                 ret = intel_init_blt_ring_buffer(dev);
3930                 if (ret)
3931                         goto cleanup_bsd_ring;
3932         }
3933
3934         dev_priv->next_seqno = 1;
3935
3936         /*
3937          * XXX: There was some w/a described somewhere suggesting loading
3938          * contexts before PPGTT.
3939          */
3940         i915_gem_context_init(dev);
3941         i915_gem_init_ppgtt(dev);
3942
3943         return 0;
3944
3945 cleanup_bsd_ring:
3946         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3947 cleanup_render_ring:
3948         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3949         return ret;
3950 }
3951
3952 static bool
3953 intel_enable_ppgtt(struct drm_device *dev)
3954 {
3955         if (i915_enable_ppgtt >= 0)
3956                 return i915_enable_ppgtt;
3957
3958 #ifdef CONFIG_INTEL_IOMMU
3959         /* Disable ppgtt on SNB if VT-d is on. */
3960         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3961                 return false;
3962 #endif
3963
3964         return true;
3965 }
3966
3967 int i915_gem_init(struct drm_device *dev)
3968 {
3969         struct drm_i915_private *dev_priv = dev->dev_private;
3970         unsigned long gtt_size, mappable_size;
3971         int ret;
3972
3973         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3974         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3975
3976         mutex_lock(&dev->struct_mutex);
3977         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3978                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3979                  * aperture accordingly when using aliasing ppgtt. */
3980                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3981
3982                 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3983
3984                 ret = i915_gem_init_aliasing_ppgtt(dev);
3985                 if (ret) {
3986                         mutex_unlock(&dev->struct_mutex);
3987                         return ret;
3988                 }
3989         } else {
3990                 /* Let GEM Manage all of the aperture.
3991                  *
3992                  * However, leave one page at the end still bound to the scratch
3993                  * page.  There are a number of places where the hardware
3994                  * apparently prefetches past the end of the object, and we've
3995                  * seen multiple hangs with the GPU head pointer stuck in a
3996                  * batchbuffer bound at the last page of the aperture.  One page
3997                  * should be enough to keep any prefetching inside of the
3998                  * aperture.
3999                  */
4000                 i915_gem_init_global_gtt(dev, 0, mappable_size,
4001                                          gtt_size);
4002         }
4003
4004         ret = i915_gem_init_hw(dev);
4005         mutex_unlock(&dev->struct_mutex);
4006         if (ret) {
4007                 i915_gem_cleanup_aliasing_ppgtt(dev);
4008                 return ret;
4009         }
4010
4011         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4012         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4013                 dev_priv->dri1.allow_batchbuffer = 1;
4014         return 0;
4015 }
4016
4017 void
4018 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4019 {
4020         drm_i915_private_t *dev_priv = dev->dev_private;
4021         struct intel_ring_buffer *ring;
4022         int i;
4023
4024         for_each_ring(ring, dev_priv, i)
4025                 intel_cleanup_ring_buffer(ring);
4026 }
4027
4028 int
4029 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4030                        struct drm_file *file_priv)
4031 {
4032         drm_i915_private_t *dev_priv = dev->dev_private;
4033         int ret;
4034
4035         if (drm_core_check_feature(dev, DRIVER_MODESET))
4036                 return 0;
4037
4038         if (atomic_read(&dev_priv->mm.wedged)) {
4039                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4040                 atomic_set(&dev_priv->mm.wedged, 0);
4041         }
4042
4043         mutex_lock(&dev->struct_mutex);
4044         dev_priv->mm.suspended = 0;
4045
4046         ret = i915_gem_init_hw(dev);
4047         if (ret != 0) {
4048                 mutex_unlock(&dev->struct_mutex);
4049                 return ret;
4050         }
4051
4052         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4053         mutex_unlock(&dev->struct_mutex);
4054
4055         ret = drm_irq_install(dev);
4056         if (ret)
4057                 goto cleanup_ringbuffer;
4058
4059         return 0;
4060
4061 cleanup_ringbuffer:
4062         mutex_lock(&dev->struct_mutex);
4063         i915_gem_cleanup_ringbuffer(dev);
4064         dev_priv->mm.suspended = 1;
4065         mutex_unlock(&dev->struct_mutex);
4066
4067         return ret;
4068 }
4069
4070 int
4071 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4072                        struct drm_file *file_priv)
4073 {
4074         if (drm_core_check_feature(dev, DRIVER_MODESET))
4075                 return 0;
4076
4077         drm_irq_uninstall(dev);
4078         return i915_gem_idle(dev);
4079 }
4080
4081 void
4082 i915_gem_lastclose(struct drm_device *dev)
4083 {
4084         int ret;
4085
4086         if (drm_core_check_feature(dev, DRIVER_MODESET))
4087                 return;
4088
4089         ret = i915_gem_idle(dev);
4090         if (ret)
4091                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4092 }
4093
4094 static void
4095 init_ring_lists(struct intel_ring_buffer *ring)
4096 {
4097         INIT_LIST_HEAD(&ring->active_list);
4098         INIT_LIST_HEAD(&ring->request_list);
4099 }
4100
4101 void
4102 i915_gem_load(struct drm_device *dev)
4103 {
4104         int i;
4105         drm_i915_private_t *dev_priv = dev->dev_private;
4106
4107         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4108         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4109         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4110         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4111         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4112         for (i = 0; i < I915_NUM_RINGS; i++)
4113                 init_ring_lists(&dev_priv->ring[i]);
4114         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4115                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4116         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4117                           i915_gem_retire_work_handler);
4118         init_completion(&dev_priv->error_completion);
4119
4120         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4121         if (IS_GEN3(dev)) {
4122                 I915_WRITE(MI_ARB_STATE,
4123                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4124         }
4125
4126         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4127
4128         /* Old X drivers will take 0-2 for front, back, depth buffers */
4129         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4130                 dev_priv->fence_reg_start = 3;
4131
4132         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4133                 dev_priv->num_fence_regs = 16;
4134         else
4135                 dev_priv->num_fence_regs = 8;
4136
4137         /* Initialize fence registers to zero */
4138         i915_gem_reset_fences(dev);
4139
4140         i915_gem_detect_bit_6_swizzle(dev);
4141         init_waitqueue_head(&dev_priv->pending_flip_queue);
4142
4143         dev_priv->mm.interruptible = true;
4144
4145         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4146         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4147         register_shrinker(&dev_priv->mm.inactive_shrinker);
4148 }
4149
4150 /*
4151  * Create a physically contiguous memory object for this object
4152  * e.g. for cursor + overlay regs
4153  */
4154 static int i915_gem_init_phys_object(struct drm_device *dev,
4155                                      int id, int size, int align)
4156 {
4157         drm_i915_private_t *dev_priv = dev->dev_private;
4158         struct drm_i915_gem_phys_object *phys_obj;
4159         int ret;
4160
4161         if (dev_priv->mm.phys_objs[id - 1] || !size)
4162                 return 0;
4163
4164         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4165         if (!phys_obj)
4166                 return -ENOMEM;
4167
4168         phys_obj->id = id;
4169
4170         phys_obj->handle = drm_pci_alloc(dev, size, align);
4171         if (!phys_obj->handle) {
4172                 ret = -ENOMEM;
4173                 goto kfree_obj;
4174         }
4175 #ifdef CONFIG_X86
4176         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4177 #endif
4178
4179         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4180
4181         return 0;
4182 kfree_obj:
4183         kfree(phys_obj);
4184         return ret;
4185 }
4186
4187 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4188 {
4189         drm_i915_private_t *dev_priv = dev->dev_private;
4190         struct drm_i915_gem_phys_object *phys_obj;
4191
4192         if (!dev_priv->mm.phys_objs[id - 1])
4193                 return;
4194
4195         phys_obj = dev_priv->mm.phys_objs[id - 1];
4196         if (phys_obj->cur_obj) {
4197                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4198         }
4199
4200 #ifdef CONFIG_X86
4201         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4202 #endif
4203         drm_pci_free(dev, phys_obj->handle);
4204         kfree(phys_obj);
4205         dev_priv->mm.phys_objs[id - 1] = NULL;
4206 }
4207
4208 void i915_gem_free_all_phys_object(struct drm_device *dev)
4209 {
4210         int i;
4211
4212         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4213                 i915_gem_free_phys_object(dev, i);
4214 }
4215
4216 void i915_gem_detach_phys_object(struct drm_device *dev,
4217                                  struct drm_i915_gem_object *obj)
4218 {
4219         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4220         char *vaddr;
4221         int i;
4222         int page_count;
4223
4224         if (!obj->phys_obj)
4225                 return;
4226         vaddr = obj->phys_obj->handle->vaddr;
4227
4228         page_count = obj->base.size / PAGE_SIZE;
4229         for (i = 0; i < page_count; i++) {
4230                 struct page *page = shmem_read_mapping_page(mapping, i);
4231                 if (!IS_ERR(page)) {
4232                         char *dst = kmap_atomic(page);
4233                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4234                         kunmap_atomic(dst);
4235
4236                         drm_clflush_pages(&page, 1);
4237
4238                         set_page_dirty(page);
4239                         mark_page_accessed(page);
4240                         page_cache_release(page);
4241                 }
4242         }
4243         i915_gem_chipset_flush(dev);
4244
4245         obj->phys_obj->cur_obj = NULL;
4246         obj->phys_obj = NULL;
4247 }
4248
4249 int
4250 i915_gem_attach_phys_object(struct drm_device *dev,
4251                             struct drm_i915_gem_object *obj,
4252                             int id,
4253                             int align)
4254 {
4255         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4256         drm_i915_private_t *dev_priv = dev->dev_private;
4257         int ret = 0;
4258         int page_count;
4259         int i;
4260
4261         if (id > I915_MAX_PHYS_OBJECT)
4262                 return -EINVAL;
4263
4264         if (obj->phys_obj) {
4265                 if (obj->phys_obj->id == id)
4266                         return 0;
4267                 i915_gem_detach_phys_object(dev, obj);
4268         }
4269
4270         /* create a new object */
4271         if (!dev_priv->mm.phys_objs[id - 1]) {
4272                 ret = i915_gem_init_phys_object(dev, id,
4273                                                 obj->base.size, align);
4274                 if (ret) {
4275                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4276                                   id, obj->base.size);
4277                         return ret;
4278                 }
4279         }
4280
4281         /* bind to the object */
4282         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4283         obj->phys_obj->cur_obj = obj;
4284
4285         page_count = obj->base.size / PAGE_SIZE;
4286
4287         for (i = 0; i < page_count; i++) {
4288                 struct page *page;
4289                 char *dst, *src;
4290
4291                 page = shmem_read_mapping_page(mapping, i);
4292                 if (IS_ERR(page))
4293                         return PTR_ERR(page);
4294
4295                 src = kmap_atomic(page);
4296                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4297                 memcpy(dst, src, PAGE_SIZE);
4298                 kunmap_atomic(src);
4299
4300                 mark_page_accessed(page);
4301                 page_cache_release(page);
4302         }
4303
4304         return 0;
4305 }
4306
4307 static int
4308 i915_gem_phys_pwrite(struct drm_device *dev,
4309                      struct drm_i915_gem_object *obj,
4310                      struct drm_i915_gem_pwrite *args,
4311                      struct drm_file *file_priv)
4312 {
4313         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4314         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4315
4316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4317                 unsigned long unwritten;
4318
4319                 /* The physical object once assigned is fixed for the lifetime
4320                  * of the obj, so we can safely drop the lock and continue
4321                  * to access vaddr.
4322                  */
4323                 mutex_unlock(&dev->struct_mutex);
4324                 unwritten = copy_from_user(vaddr, user_data, args->size);
4325                 mutex_lock(&dev->struct_mutex);
4326                 if (unwritten)
4327                         return -EFAULT;
4328         }
4329
4330         i915_gem_chipset_flush(dev);
4331         return 0;
4332 }
4333
4334 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4335 {
4336         struct drm_i915_file_private *file_priv = file->driver_priv;
4337
4338         /* Clean up our request list when the client is going away, so that
4339          * later retire_requests won't dereference our soon-to-be-gone
4340          * file_priv.
4341          */
4342         spin_lock(&file_priv->mm.lock);
4343         while (!list_empty(&file_priv->mm.request_list)) {
4344                 struct drm_i915_gem_request *request;
4345
4346                 request = list_first_entry(&file_priv->mm.request_list,
4347                                            struct drm_i915_gem_request,
4348                                            client_list);
4349                 list_del(&request->client_list);
4350                 request->file_priv = NULL;
4351         }
4352         spin_unlock(&file_priv->mm.lock);
4353 }
4354
4355 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4356 {
4357         if (!mutex_is_locked(mutex))
4358                 return false;
4359
4360 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4361         return mutex->owner == task;
4362 #else
4363         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4364         return false;
4365 #endif
4366 }
4367
4368 static int
4369 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4370 {
4371         struct drm_i915_private *dev_priv =
4372                 container_of(shrinker,
4373                              struct drm_i915_private,
4374                              mm.inactive_shrinker);
4375         struct drm_device *dev = dev_priv->dev;
4376         struct drm_i915_gem_object *obj;
4377         int nr_to_scan = sc->nr_to_scan;
4378         bool unlock = true;
4379         int cnt;
4380
4381         if (!mutex_trylock(&dev->struct_mutex)) {
4382                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4383                         return 0;
4384
4385                 unlock = false;
4386         }
4387
4388         if (nr_to_scan) {
4389                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4390                 if (nr_to_scan > 0)
4391                         i915_gem_shrink_all(dev_priv);
4392         }
4393
4394         cnt = 0;
4395         list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4396                 if (obj->pages_pin_count == 0)
4397                         cnt += obj->base.size >> PAGE_SHIFT;
4398         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4399                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4400                         cnt += obj->base.size >> PAGE_SHIFT;
4401
4402         if (unlock)
4403                 mutex_unlock(&dev->struct_mutex);
4404         return cnt;
4405 }