2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
45 struct i915_address_space *vm,
47 bool map_and_fenceable,
49 static int i915_gem_phys_pwrite(struct drm_device *dev,
50 struct drm_i915_gem_object *obj,
51 struct drm_i915_gem_pwrite *args,
52 struct drm_file *file);
54 static void i915_gem_write_fence(struct drm_device *dev, int reg,
55 struct drm_i915_gem_object *obj);
56 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
57 struct drm_i915_fence_reg *fence,
60 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
61 struct shrink_control *sc);
62 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
63 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
64 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
66 static bool cpu_cache_is_coherent(struct drm_device *dev,
67 enum i915_cache_level level)
69 return HAS_LLC(dev) || level != I915_CACHE_NONE;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
74 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
77 return obj->pin_display;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
83 i915_gem_release_mmap(obj);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj->fence_dirty = false;
89 obj->fence_reg = I915_FENCE_REG_NONE;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
96 spin_lock(&dev_priv->mm.object_stat_lock);
97 dev_priv->mm.object_count++;
98 dev_priv->mm.object_memory += size;
99 spin_unlock(&dev_priv->mm.object_stat_lock);
102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
105 spin_lock(&dev_priv->mm.object_stat_lock);
106 dev_priv->mm.object_count--;
107 dev_priv->mm.object_memory -= size;
108 spin_unlock(&dev_priv->mm.object_stat_lock);
112 i915_gem_wait_for_error(struct i915_gpu_error *error)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret = wait_event_interruptible_timeout(error->reset_queue,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret < 0) {
140 int i915_mutex_lock_interruptible(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
145 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
149 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 WARN_ON(i915_verify_lists(dev));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
160 return i915_gem_obj_bound_any(obj) && !obj->active;
164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_init *args = data;
170 if (drm_core_check_feature(dev, DRIVER_MODESET))
173 if (args->gtt_start >= args->gtt_end ||
174 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev)->gen >= 5)
181 mutex_lock(&dev->struct_mutex);
182 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
184 dev_priv->gtt.mappable_end = args->gtt_end;
185 mutex_unlock(&dev->struct_mutex);
191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *file)
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 struct drm_i915_gem_get_aperture *args = data;
196 struct drm_i915_gem_object *obj;
200 mutex_lock(&dev->struct_mutex);
201 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
203 pinned += i915_gem_obj_ggtt_size(obj);
204 mutex_unlock(&dev->struct_mutex);
206 args->aper_size = dev_priv->gtt.base.total;
207 args->aper_available_size = args->aper_size - pinned;
212 void *i915_gem_object_alloc(struct drm_device *dev)
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
218 void i915_gem_object_free(struct drm_i915_gem_object *obj)
220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
221 kmem_cache_free(dev_priv->slab, obj);
225 i915_gem_create(struct drm_file *file,
226 struct drm_device *dev,
230 struct drm_i915_gem_object *obj;
234 size = roundup(size, PAGE_SIZE);
238 /* Allocate the new object */
239 obj = i915_gem_alloc_object(dev, size);
243 ret = drm_gem_handle_create(file, &obj->base, &handle);
244 /* drop reference from allocate - handle holds it now */
245 drm_gem_object_unreference_unlocked(&obj->base);
254 i915_gem_dumb_create(struct drm_file *file,
255 struct drm_device *dev,
256 struct drm_mode_create_dumb *args)
258 /* have to work out size/pitch and return them */
259 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
260 args->size = args->pitch * args->height;
261 return i915_gem_create(file, dev,
262 args->size, &args->handle);
266 * Creates a new mm object and returns a handle to it.
269 i915_gem_create_ioctl(struct drm_device *dev, void *data,
270 struct drm_file *file)
272 struct drm_i915_gem_create *args = data;
274 return i915_gem_create(file, dev,
275 args->size, &args->handle);
279 __copy_to_user_swizzled(char __user *cpu_vaddr,
280 const char *gpu_vaddr, int gpu_offset,
283 int ret, cpu_offset = 0;
286 int cacheline_end = ALIGN(gpu_offset + 1, 64);
287 int this_length = min(cacheline_end - gpu_offset, length);
288 int swizzled_gpu_offset = gpu_offset ^ 64;
290 ret = __copy_to_user(cpu_vaddr + cpu_offset,
291 gpu_vaddr + swizzled_gpu_offset,
296 cpu_offset += this_length;
297 gpu_offset += this_length;
298 length -= this_length;
305 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
306 const char __user *cpu_vaddr,
309 int ret, cpu_offset = 0;
312 int cacheline_end = ALIGN(gpu_offset + 1, 64);
313 int this_length = min(cacheline_end - gpu_offset, length);
314 int swizzled_gpu_offset = gpu_offset ^ 64;
316 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
317 cpu_vaddr + cpu_offset,
322 cpu_offset += this_length;
323 gpu_offset += this_length;
324 length -= this_length;
330 /* Per-page copy function for the shmem pread fastpath.
331 * Flushes invalid cachelines before reading the target if
332 * needs_clflush is set. */
334 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
335 char __user *user_data,
336 bool page_do_bit17_swizzling, bool needs_clflush)
341 if (unlikely(page_do_bit17_swizzling))
344 vaddr = kmap_atomic(page);
346 drm_clflush_virt_range(vaddr + shmem_page_offset,
348 ret = __copy_to_user_inatomic(user_data,
349 vaddr + shmem_page_offset,
351 kunmap_atomic(vaddr);
353 return ret ? -EFAULT : 0;
357 shmem_clflush_swizzled_range(char *addr, unsigned long length,
360 if (unlikely(swizzled)) {
361 unsigned long start = (unsigned long) addr;
362 unsigned long end = (unsigned long) addr + length;
364 /* For swizzling simply ensure that we always flush both
365 * channels. Lame, but simple and it works. Swizzled
366 * pwrite/pread is far from a hotpath - current userspace
367 * doesn't use it at all. */
368 start = round_down(start, 128);
369 end = round_up(end, 128);
371 drm_clflush_virt_range((void *)start, end - start);
373 drm_clflush_virt_range(addr, length);
378 /* Only difference to the fast-path function is that this can handle bit17
379 * and uses non-atomic copy and kmap functions. */
381 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
382 char __user *user_data,
383 bool page_do_bit17_swizzling, bool needs_clflush)
390 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
392 page_do_bit17_swizzling);
394 if (page_do_bit17_swizzling)
395 ret = __copy_to_user_swizzled(user_data,
396 vaddr, shmem_page_offset,
399 ret = __copy_to_user(user_data,
400 vaddr + shmem_page_offset,
404 return ret ? - EFAULT : 0;
408 i915_gem_shmem_pread(struct drm_device *dev,
409 struct drm_i915_gem_object *obj,
410 struct drm_i915_gem_pread *args,
411 struct drm_file *file)
413 char __user *user_data;
416 int shmem_page_offset, page_length, ret = 0;
417 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
419 int needs_clflush = 0;
420 struct sg_page_iter sg_iter;
422 user_data = to_user_ptr(args->data_ptr);
425 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
427 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
428 /* If we're not in the cpu read domain, set ourself into the gtt
429 * read domain and manually flush cachelines (if required). This
430 * optimizes for the case when the gpu will dirty the data
431 * anyway again before the next pread happens. */
432 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
433 if (i915_gem_obj_bound_any(obj)) {
434 ret = i915_gem_object_set_to_gtt_domain(obj, false);
440 ret = i915_gem_object_get_pages(obj);
444 i915_gem_object_pin_pages(obj);
446 offset = args->offset;
448 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
449 offset >> PAGE_SHIFT) {
450 struct page *page = sg_page_iter_page(&sg_iter);
455 /* Operation in this page
457 * shmem_page_offset = offset within page in shmem file
458 * page_length = bytes to copy for this page
460 shmem_page_offset = offset_in_page(offset);
461 page_length = remain;
462 if ((shmem_page_offset + page_length) > PAGE_SIZE)
463 page_length = PAGE_SIZE - shmem_page_offset;
465 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
466 (page_to_phys(page) & (1 << 17)) != 0;
468 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
469 user_data, page_do_bit17_swizzling,
474 mutex_unlock(&dev->struct_mutex);
476 if (likely(!i915_prefault_disable) && !prefaulted) {
477 ret = fault_in_multipages_writeable(user_data, remain);
478 /* Userspace is tricking us, but we've already clobbered
479 * its pages with the prefault and promised to write the
480 * data up to the first fault. Hence ignore any errors
481 * and just continue. */
486 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
487 user_data, page_do_bit17_swizzling,
490 mutex_lock(&dev->struct_mutex);
493 mark_page_accessed(page);
498 remain -= page_length;
499 user_data += page_length;
500 offset += page_length;
504 i915_gem_object_unpin_pages(obj);
510 * Reads data from the object referenced by handle.
512 * On error, the contents of *data are undefined.
515 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
516 struct drm_file *file)
518 struct drm_i915_gem_pread *args = data;
519 struct drm_i915_gem_object *obj;
525 if (!access_ok(VERIFY_WRITE,
526 to_user_ptr(args->data_ptr),
530 ret = i915_mutex_lock_interruptible(dev);
534 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
535 if (&obj->base == NULL) {
540 /* Bounds check source. */
541 if (args->offset > obj->base.size ||
542 args->size > obj->base.size - args->offset) {
547 /* prime objects have no backing filp to GEM pread/pwrite
550 if (!obj->base.filp) {
555 trace_i915_gem_object_pread(obj, args->offset, args->size);
557 ret = i915_gem_shmem_pread(dev, obj, args, file);
560 drm_gem_object_unreference(&obj->base);
562 mutex_unlock(&dev->struct_mutex);
566 /* This is the fast write path which cannot handle
567 * page faults in the source data
571 fast_user_write(struct io_mapping *mapping,
572 loff_t page_base, int page_offset,
573 char __user *user_data,
576 void __iomem *vaddr_atomic;
578 unsigned long unwritten;
580 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
581 /* We can use the cpu mem copy function because this is X86. */
582 vaddr = (void __force*)vaddr_atomic + page_offset;
583 unwritten = __copy_from_user_inatomic_nocache(vaddr,
585 io_mapping_unmap_atomic(vaddr_atomic);
590 * This is the fast pwrite path, where we copy the data directly from the
591 * user into the GTT, uncached.
594 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
595 struct drm_i915_gem_object *obj,
596 struct drm_i915_gem_pwrite *args,
597 struct drm_file *file)
599 drm_i915_private_t *dev_priv = dev->dev_private;
601 loff_t offset, page_base;
602 char __user *user_data;
603 int page_offset, page_length, ret;
605 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
609 ret = i915_gem_object_set_to_gtt_domain(obj, true);
613 ret = i915_gem_object_put_fence(obj);
617 user_data = to_user_ptr(args->data_ptr);
620 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
623 /* Operation in this page
625 * page_base = page offset within aperture
626 * page_offset = offset within page
627 * page_length = bytes to copy for this page
629 page_base = offset & PAGE_MASK;
630 page_offset = offset_in_page(offset);
631 page_length = remain;
632 if ((page_offset + remain) > PAGE_SIZE)
633 page_length = PAGE_SIZE - page_offset;
635 /* If we get a fault while copying data, then (presumably) our
636 * source page isn't available. Return the error and we'll
637 * retry in the slow path.
639 if (fast_user_write(dev_priv->gtt.mappable, page_base,
640 page_offset, user_data, page_length)) {
645 remain -= page_length;
646 user_data += page_length;
647 offset += page_length;
651 i915_gem_object_unpin(obj);
656 /* Per-page copy function for the shmem pwrite fastpath.
657 * Flushes invalid cachelines before writing to the target if
658 * needs_clflush_before is set and flushes out any written cachelines after
659 * writing if needs_clflush is set. */
661 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
662 char __user *user_data,
663 bool page_do_bit17_swizzling,
664 bool needs_clflush_before,
665 bool needs_clflush_after)
670 if (unlikely(page_do_bit17_swizzling))
673 vaddr = kmap_atomic(page);
674 if (needs_clflush_before)
675 drm_clflush_virt_range(vaddr + shmem_page_offset,
677 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
680 if (needs_clflush_after)
681 drm_clflush_virt_range(vaddr + shmem_page_offset,
683 kunmap_atomic(vaddr);
685 return ret ? -EFAULT : 0;
688 /* Only difference to the fast-path function is that this can handle bit17
689 * and uses non-atomic copy and kmap functions. */
691 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
692 char __user *user_data,
693 bool page_do_bit17_swizzling,
694 bool needs_clflush_before,
695 bool needs_clflush_after)
701 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
702 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
704 page_do_bit17_swizzling);
705 if (page_do_bit17_swizzling)
706 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
710 ret = __copy_from_user(vaddr + shmem_page_offset,
713 if (needs_clflush_after)
714 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
716 page_do_bit17_swizzling);
719 return ret ? -EFAULT : 0;
723 i915_gem_shmem_pwrite(struct drm_device *dev,
724 struct drm_i915_gem_object *obj,
725 struct drm_i915_gem_pwrite *args,
726 struct drm_file *file)
730 char __user *user_data;
731 int shmem_page_offset, page_length, ret = 0;
732 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
733 int hit_slowpath = 0;
734 int needs_clflush_after = 0;
735 int needs_clflush_before = 0;
736 struct sg_page_iter sg_iter;
738 user_data = to_user_ptr(args->data_ptr);
741 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
743 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
744 /* If we're not in the cpu write domain, set ourself into the gtt
745 * write domain and manually flush cachelines (if required). This
746 * optimizes for the case when the gpu will use the data
747 * right away and we therefore have to clflush anyway. */
748 needs_clflush_after = cpu_write_needs_clflush(obj);
749 if (i915_gem_obj_bound_any(obj)) {
750 ret = i915_gem_object_set_to_gtt_domain(obj, true);
755 /* Same trick applies to invalidate partially written cachelines read
757 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
758 needs_clflush_before =
759 !cpu_cache_is_coherent(dev, obj->cache_level);
761 ret = i915_gem_object_get_pages(obj);
765 i915_gem_object_pin_pages(obj);
767 offset = args->offset;
770 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
771 offset >> PAGE_SHIFT) {
772 struct page *page = sg_page_iter_page(&sg_iter);
773 int partial_cacheline_write;
778 /* Operation in this page
780 * shmem_page_offset = offset within page in shmem file
781 * page_length = bytes to copy for this page
783 shmem_page_offset = offset_in_page(offset);
785 page_length = remain;
786 if ((shmem_page_offset + page_length) > PAGE_SIZE)
787 page_length = PAGE_SIZE - shmem_page_offset;
789 /* If we don't overwrite a cacheline completely we need to be
790 * careful to have up-to-date data by first clflushing. Don't
791 * overcomplicate things and flush the entire patch. */
792 partial_cacheline_write = needs_clflush_before &&
793 ((shmem_page_offset | page_length)
794 & (boot_cpu_data.x86_clflush_size - 1));
796 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
797 (page_to_phys(page) & (1 << 17)) != 0;
799 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
800 user_data, page_do_bit17_swizzling,
801 partial_cacheline_write,
802 needs_clflush_after);
807 mutex_unlock(&dev->struct_mutex);
808 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
809 user_data, page_do_bit17_swizzling,
810 partial_cacheline_write,
811 needs_clflush_after);
813 mutex_lock(&dev->struct_mutex);
816 set_page_dirty(page);
817 mark_page_accessed(page);
822 remain -= page_length;
823 user_data += page_length;
824 offset += page_length;
828 i915_gem_object_unpin_pages(obj);
832 * Fixup: Flush cpu caches in case we didn't flush the dirty
833 * cachelines in-line while writing and the object moved
834 * out of the cpu write domain while we've dropped the lock.
836 if (!needs_clflush_after &&
837 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 if (i915_gem_clflush_object(obj, obj->pin_display))
839 i915_gem_chipset_flush(dev);
843 if (needs_clflush_after)
844 i915_gem_chipset_flush(dev);
850 * Writes data to the object referenced by handle.
852 * On error, the contents of the buffer that were to be modified are undefined.
855 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
858 struct drm_i915_gem_pwrite *args = data;
859 struct drm_i915_gem_object *obj;
865 if (!access_ok(VERIFY_READ,
866 to_user_ptr(args->data_ptr),
870 if (likely(!i915_prefault_disable)) {
871 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
877 ret = i915_mutex_lock_interruptible(dev);
881 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
882 if (&obj->base == NULL) {
887 /* Bounds check destination. */
888 if (args->offset > obj->base.size ||
889 args->size > obj->base.size - args->offset) {
894 /* prime objects have no backing filp to GEM pread/pwrite
897 if (!obj->base.filp) {
902 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
905 /* We can only do the GTT pwrite on untiled buffers, as otherwise
906 * it would end up going through the fenced access, and we'll get
907 * different detiling behavior between reading and writing.
908 * pread/pwrite currently are reading and writing from the CPU
909 * perspective, requiring manual detiling by the client.
912 ret = i915_gem_phys_pwrite(dev, obj, args, file);
916 if (obj->tiling_mode == I915_TILING_NONE &&
917 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
918 cpu_write_needs_clflush(obj)) {
919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
925 if (ret == -EFAULT || ret == -ENOSPC)
926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
929 drm_gem_object_unreference(&obj->base);
931 mutex_unlock(&dev->struct_mutex);
936 i915_gem_check_wedge(struct i915_gpu_error *error,
939 if (i915_reset_in_progress(error)) {
940 /* Non-interruptible callers can't handle -EAGAIN, hence return
941 * -EIO unconditionally for these. */
945 /* Recovery complete, but the reset failed ... */
946 if (i915_terminally_wedged(error))
956 * Compare seqno against outstanding lazy request. Emit a request if they are
960 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
964 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
967 if (seqno == ring->outstanding_lazy_request)
968 ret = i915_add_request(ring, NULL);
974 * __wait_seqno - wait until execution of seqno has finished
975 * @ring: the ring expected to report seqno
977 * @reset_counter: reset sequence associated with the given seqno
978 * @interruptible: do an interruptible wait (normally yes)
979 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
981 * Note: It is of utmost importance that the passed in seqno and reset_counter
982 * values have been read by the caller in an smp safe manner. Where read-side
983 * locks are involved, it is sufficient to read the reset_counter before
984 * unlocking the lock that protects the seqno. For lockless tricks, the
985 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
988 * Returns 0 if the seqno was found within the alloted time. Else returns the
989 * errno with remaining time filled in timeout argument.
991 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
992 unsigned reset_counter,
993 bool interruptible, struct timespec *timeout)
995 drm_i915_private_t *dev_priv = ring->dev->dev_private;
996 struct timespec before, now, wait_time={1,0};
997 unsigned long timeout_jiffies;
999 bool wait_forever = true;
1002 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1004 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1007 trace_i915_gem_request_wait_begin(ring, seqno);
1009 if (timeout != NULL) {
1010 wait_time = *timeout;
1011 wait_forever = false;
1014 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1016 if (WARN_ON(!ring->irq_get(ring)))
1019 /* Record current time in case interrupted by signal, or wedged * */
1020 getrawmonotonic(&before);
1023 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1024 i915_reset_in_progress(&dev_priv->gpu_error) || \
1025 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1028 end = wait_event_interruptible_timeout(ring->irq_queue,
1032 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1035 /* We need to check whether any gpu reset happened in between
1036 * the caller grabbing the seqno and now ... */
1037 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1040 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1042 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1045 } while (end == 0 && wait_forever);
1047 getrawmonotonic(&now);
1049 ring->irq_put(ring);
1050 trace_i915_gem_request_wait_end(ring, seqno);
1054 struct timespec sleep_time = timespec_sub(now, before);
1055 *timeout = timespec_sub(*timeout, sleep_time);
1056 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1057 set_normalized_timespec(timeout, 0, 0);
1062 case -EAGAIN: /* Wedged */
1063 case -ERESTARTSYS: /* Signal */
1065 case 0: /* Timeout */
1067 default: /* Completed */
1068 WARN_ON(end < 0); /* We're not aware of other errors */
1074 * Waits for a sequence number to be signaled, and cleans up the
1075 * request and object lists appropriately for that event.
1078 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1080 struct drm_device *dev = ring->dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 bool interruptible = dev_priv->mm.interruptible;
1085 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1088 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1092 ret = i915_gem_check_olr(ring, seqno);
1096 return __wait_seqno(ring, seqno,
1097 atomic_read(&dev_priv->gpu_error.reset_counter),
1098 interruptible, NULL);
1102 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1103 struct intel_ring_buffer *ring)
1105 i915_gem_retire_requests_ring(ring);
1107 /* Manually manage the write flush as we may have not yet
1108 * retired the buffer.
1110 * Note that the last_write_seqno is always the earlier of
1111 * the two (read/write) seqno, so if we haved successfully waited,
1112 * we know we have passed the last write.
1114 obj->last_write_seqno = 0;
1115 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1121 * Ensures that all rendering to the object has completed and the object is
1122 * safe to unbind from the GTT or access from the CPU.
1124 static __must_check int
1125 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1128 struct intel_ring_buffer *ring = obj->ring;
1132 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1136 ret = i915_wait_seqno(ring, seqno);
1140 return i915_gem_object_wait_rendering__tail(obj, ring);
1143 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1144 * as the object state may change during this call.
1146 static __must_check int
1147 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1150 struct drm_device *dev = obj->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 struct intel_ring_buffer *ring = obj->ring;
1153 unsigned reset_counter;
1157 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1158 BUG_ON(!dev_priv->mm.interruptible);
1160 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1164 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1168 ret = i915_gem_check_olr(ring, seqno);
1172 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1173 mutex_unlock(&dev->struct_mutex);
1174 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1175 mutex_lock(&dev->struct_mutex);
1179 return i915_gem_object_wait_rendering__tail(obj, ring);
1183 * Called when user space prepares to use an object with the CPU, either
1184 * through the mmap ioctl's mapping or a GTT mapping.
1187 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *file)
1190 struct drm_i915_gem_set_domain *args = data;
1191 struct drm_i915_gem_object *obj;
1192 uint32_t read_domains = args->read_domains;
1193 uint32_t write_domain = args->write_domain;
1196 /* Only handle setting domains to types used by the CPU. */
1197 if (write_domain & I915_GEM_GPU_DOMAINS)
1200 if (read_domains & I915_GEM_GPU_DOMAINS)
1203 /* Having something in the write domain implies it's in the read
1204 * domain, and only that read domain. Enforce that in the request.
1206 if (write_domain != 0 && read_domains != write_domain)
1209 ret = i915_mutex_lock_interruptible(dev);
1213 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1214 if (&obj->base == NULL) {
1219 /* Try to flush the object off the GPU without holding the lock.
1220 * We will repeat the flush holding the lock in the normal manner
1221 * to catch cases where we are gazumped.
1223 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1227 if (read_domains & I915_GEM_DOMAIN_GTT) {
1228 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1230 /* Silently promote "you're not bound, there was nothing to do"
1231 * to success, since the client was just asking us to
1232 * make sure everything was done.
1237 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1241 drm_gem_object_unreference(&obj->base);
1243 mutex_unlock(&dev->struct_mutex);
1248 * Called when user space has done writes to this buffer
1251 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1252 struct drm_file *file)
1254 struct drm_i915_gem_sw_finish *args = data;
1255 struct drm_i915_gem_object *obj;
1258 ret = i915_mutex_lock_interruptible(dev);
1262 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1263 if (&obj->base == NULL) {
1268 /* Pinned buffers may be scanout, so flush the cache */
1269 if (obj->pin_display)
1270 i915_gem_object_flush_cpu_write_domain(obj, true);
1272 drm_gem_object_unreference(&obj->base);
1274 mutex_unlock(&dev->struct_mutex);
1279 * Maps the contents of an object, returning the address it is mapped
1282 * While the mapping holds a reference on the contents of the object, it doesn't
1283 * imply a ref on the object itself.
1286 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1287 struct drm_file *file)
1289 struct drm_i915_gem_mmap *args = data;
1290 struct drm_gem_object *obj;
1293 obj = drm_gem_object_lookup(dev, file, args->handle);
1297 /* prime objects have no backing filp to GEM mmap
1301 drm_gem_object_unreference_unlocked(obj);
1305 addr = vm_mmap(obj->filp, 0, args->size,
1306 PROT_READ | PROT_WRITE, MAP_SHARED,
1308 drm_gem_object_unreference_unlocked(obj);
1309 if (IS_ERR((void *)addr))
1312 args->addr_ptr = (uint64_t) addr;
1318 * i915_gem_fault - fault a page into the GTT
1319 * vma: VMA in question
1322 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1323 * from userspace. The fault handler takes care of binding the object to
1324 * the GTT (if needed), allocating and programming a fence register (again,
1325 * only if needed based on whether the old reg is still valid or the object
1326 * is tiled) and inserting a new PTE into the faulting process.
1328 * Note that the faulting process may involve evicting existing objects
1329 * from the GTT and/or fence registers to make room. So performance may
1330 * suffer if the GTT working set is large or there are few fence registers
1333 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1335 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1336 struct drm_device *dev = obj->base.dev;
1337 drm_i915_private_t *dev_priv = dev->dev_private;
1338 pgoff_t page_offset;
1341 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1343 /* We don't use vmf->pgoff since that has the fake offset */
1344 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1347 ret = i915_mutex_lock_interruptible(dev);
1351 trace_i915_gem_object_fault(obj, page_offset, true, write);
1353 /* Access to snoopable pages through the GTT is incoherent. */
1354 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1359 /* Now bind it into the GTT if needed */
1360 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1364 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1368 ret = i915_gem_object_get_fence(obj);
1372 obj->fault_mappable = true;
1374 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1378 /* Finally, remap it using the new GTT offset */
1379 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1381 i915_gem_object_unpin(obj);
1383 mutex_unlock(&dev->struct_mutex);
1387 /* If this -EIO is due to a gpu hang, give the reset code a
1388 * chance to clean up the mess. Otherwise return the proper
1390 if (i915_terminally_wedged(&dev_priv->gpu_error))
1391 return VM_FAULT_SIGBUS;
1393 /* Give the error handler a chance to run and move the
1394 * objects off the GPU active list. Next time we service the
1395 * fault, we should be able to transition the page into the
1396 * GTT without touching the GPU (and so avoid further
1397 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1398 * with coherency, just lost writes.
1406 * EBUSY is ok: this just means that another thread
1407 * already did the job.
1409 return VM_FAULT_NOPAGE;
1411 return VM_FAULT_OOM;
1413 return VM_FAULT_SIGBUS;
1415 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1416 return VM_FAULT_SIGBUS;
1421 * i915_gem_release_mmap - remove physical page mappings
1422 * @obj: obj in question
1424 * Preserve the reservation of the mmapping with the DRM core code, but
1425 * relinquish ownership of the pages back to the system.
1427 * It is vital that we remove the page mapping if we have mapped a tiled
1428 * object through the GTT and then lose the fence register due to
1429 * resource pressure. Similarly if the object has been moved out of the
1430 * aperture, than pages mapped into userspace must be revoked. Removing the
1431 * mapping will then trigger a page fault on the next user access, allowing
1432 * fixup by i915_gem_fault().
1435 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1437 if (!obj->fault_mappable)
1440 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1441 obj->fault_mappable = false;
1445 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1449 if (INTEL_INFO(dev)->gen >= 4 ||
1450 tiling_mode == I915_TILING_NONE)
1453 /* Previous chips need a power-of-two fence region when tiling */
1454 if (INTEL_INFO(dev)->gen == 3)
1455 gtt_size = 1024*1024;
1457 gtt_size = 512*1024;
1459 while (gtt_size < size)
1466 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1467 * @obj: object to check
1469 * Return the required GTT alignment for an object, taking into account
1470 * potential fence register mapping.
1473 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1474 int tiling_mode, bool fenced)
1477 * Minimum alignment is 4k (GTT page size), but might be greater
1478 * if a fence register is needed for the object.
1480 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1481 tiling_mode == I915_TILING_NONE)
1485 * Previous chips need to be aligned to the size of the smallest
1486 * fence register that can contain the object.
1488 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1491 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1493 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1496 if (drm_vma_node_has_offset(&obj->base.vma_node))
1499 dev_priv->mm.shrinker_no_lock_stealing = true;
1501 ret = drm_gem_create_mmap_offset(&obj->base);
1505 /* Badly fragmented mmap space? The only way we can recover
1506 * space is by destroying unwanted objects. We can't randomly release
1507 * mmap_offsets as userspace expects them to be persistent for the
1508 * lifetime of the objects. The closest we can is to release the
1509 * offsets on purgeable objects by truncating it and marking it purged,
1510 * which prevents userspace from ever using that object again.
1512 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1513 ret = drm_gem_create_mmap_offset(&obj->base);
1517 i915_gem_shrink_all(dev_priv);
1518 ret = drm_gem_create_mmap_offset(&obj->base);
1520 dev_priv->mm.shrinker_no_lock_stealing = false;
1525 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1527 drm_gem_free_mmap_offset(&obj->base);
1531 i915_gem_mmap_gtt(struct drm_file *file,
1532 struct drm_device *dev,
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 struct drm_i915_gem_object *obj;
1540 ret = i915_mutex_lock_interruptible(dev);
1544 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1545 if (&obj->base == NULL) {
1550 if (obj->base.size > dev_priv->gtt.mappable_end) {
1555 if (obj->madv != I915_MADV_WILLNEED) {
1556 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1561 ret = i915_gem_object_create_mmap_offset(obj);
1565 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1568 drm_gem_object_unreference(&obj->base);
1570 mutex_unlock(&dev->struct_mutex);
1575 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1577 * @data: GTT mapping ioctl data
1578 * @file: GEM object info
1580 * Simply returns the fake offset to userspace so it can mmap it.
1581 * The mmap call will end up in drm_gem_mmap(), which will set things
1582 * up so we can get faults in the handler above.
1584 * The fault handler will take care of binding the object into the GTT
1585 * (since it may have been evicted to make room for something), allocating
1586 * a fence register, and mapping the appropriate aperture address into
1590 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1591 struct drm_file *file)
1593 struct drm_i915_gem_mmap_gtt *args = data;
1595 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1598 /* Immediately discard the backing storage */
1600 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1602 struct inode *inode;
1604 i915_gem_object_free_mmap_offset(obj);
1606 if (obj->base.filp == NULL)
1609 /* Our goal here is to return as much of the memory as
1610 * is possible back to the system as we are called from OOM.
1611 * To do this we must instruct the shmfs to drop all of its
1612 * backing pages, *now*.
1614 inode = file_inode(obj->base.filp);
1615 shmem_truncate_range(inode, 0, (loff_t)-1);
1617 obj->madv = __I915_MADV_PURGED;
1621 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1623 return obj->madv == I915_MADV_DONTNEED;
1627 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1629 struct sg_page_iter sg_iter;
1632 BUG_ON(obj->madv == __I915_MADV_PURGED);
1634 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1636 /* In the event of a disaster, abandon all caches and
1637 * hope for the best.
1639 WARN_ON(ret != -EIO);
1640 i915_gem_clflush_object(obj, true);
1641 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1644 if (i915_gem_object_needs_bit17_swizzle(obj))
1645 i915_gem_object_save_bit_17_swizzle(obj);
1647 if (obj->madv == I915_MADV_DONTNEED)
1650 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1651 struct page *page = sg_page_iter_page(&sg_iter);
1654 set_page_dirty(page);
1656 if (obj->madv == I915_MADV_WILLNEED)
1657 mark_page_accessed(page);
1659 page_cache_release(page);
1663 sg_free_table(obj->pages);
1668 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1670 const struct drm_i915_gem_object_ops *ops = obj->ops;
1672 if (obj->pages == NULL)
1675 if (obj->pages_pin_count)
1678 BUG_ON(i915_gem_obj_bound_any(obj));
1680 /* ->put_pages might need to allocate memory for the bit17 swizzle
1681 * array, hence protect them from being reaped by removing them from gtt
1683 list_del(&obj->global_list);
1685 ops->put_pages(obj);
1688 if (i915_gem_object_is_purgeable(obj))
1689 i915_gem_object_truncate(obj);
1695 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1696 bool purgeable_only)
1698 struct list_head still_bound_list;
1699 struct drm_i915_gem_object *obj, *next;
1702 list_for_each_entry_safe(obj, next,
1703 &dev_priv->mm.unbound_list,
1705 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1706 i915_gem_object_put_pages(obj) == 0) {
1707 count += obj->base.size >> PAGE_SHIFT;
1708 if (count >= target)
1714 * As we may completely rewrite the bound list whilst unbinding
1715 * (due to retiring requests) we have to strictly process only
1716 * one element of the list at the time, and recheck the list
1717 * on every iteration.
1719 INIT_LIST_HEAD(&still_bound_list);
1720 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1721 struct i915_vma *vma, *v;
1723 obj = list_first_entry(&dev_priv->mm.bound_list,
1724 typeof(*obj), global_list);
1725 list_move_tail(&obj->global_list, &still_bound_list);
1727 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1731 * Hold a reference whilst we unbind this object, as we may
1732 * end up waiting for and retiring requests. This might
1733 * release the final reference (held by the active list)
1734 * and result in the object being freed from under us.
1735 * in this object being freed.
1737 * Note 1: Shrinking the bound list is special since only active
1738 * (and hence bound objects) can contain such limbo objects, so
1739 * we don't need special tricks for shrinking the unbound list.
1740 * The only other place where we have to be careful with active
1741 * objects suddenly disappearing due to retiring requests is the
1744 * Note 2: Even though the bound list doesn't hold a reference
1745 * to the object we can safely grab one here: The final object
1746 * unreferencing and the bound_list are both protected by the
1747 * dev->struct_mutex and so we won't ever be able to observe an
1748 * object on the bound_list with a reference count equals 0.
1750 drm_gem_object_reference(&obj->base);
1752 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1753 if (i915_vma_unbind(vma))
1756 if (i915_gem_object_put_pages(obj) == 0)
1757 count += obj->base.size >> PAGE_SHIFT;
1759 drm_gem_object_unreference(&obj->base);
1761 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1767 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1769 return __i915_gem_shrink(dev_priv, target, true);
1773 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1775 struct drm_i915_gem_object *obj, *next;
1777 i915_gem_evict_everything(dev_priv->dev);
1779 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1781 i915_gem_object_put_pages(obj);
1785 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1787 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1789 struct address_space *mapping;
1790 struct sg_table *st;
1791 struct scatterlist *sg;
1792 struct sg_page_iter sg_iter;
1794 unsigned long last_pfn = 0; /* suppress gcc warning */
1797 /* Assert that the object is not currently in any GPU domain. As it
1798 * wasn't in the GTT, there shouldn't be any way it could have been in
1801 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1802 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1804 st = kmalloc(sizeof(*st), GFP_KERNEL);
1808 page_count = obj->base.size / PAGE_SIZE;
1809 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1814 /* Get the list of pages out of our struct file. They'll be pinned
1815 * at this point until we release them.
1817 * Fail silently without starting the shrinker
1819 mapping = file_inode(obj->base.filp)->i_mapping;
1820 gfp = mapping_gfp_mask(mapping);
1821 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1822 gfp &= ~(__GFP_IO | __GFP_WAIT);
1825 for (i = 0; i < page_count; i++) {
1826 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1828 i915_gem_purge(dev_priv, page_count);
1829 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1832 /* We've tried hard to allocate the memory by reaping
1833 * our own buffer, now let the real VM do its job and
1834 * go down in flames if truly OOM.
1836 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1837 gfp |= __GFP_IO | __GFP_WAIT;
1839 i915_gem_shrink_all(dev_priv);
1840 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1844 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1845 gfp &= ~(__GFP_IO | __GFP_WAIT);
1847 #ifdef CONFIG_SWIOTLB
1848 if (swiotlb_nr_tbl()) {
1850 sg_set_page(sg, page, PAGE_SIZE, 0);
1855 if (!i || page_to_pfn(page) != last_pfn + 1) {
1859 sg_set_page(sg, page, PAGE_SIZE, 0);
1861 sg->length += PAGE_SIZE;
1863 last_pfn = page_to_pfn(page);
1865 #ifdef CONFIG_SWIOTLB
1866 if (!swiotlb_nr_tbl())
1871 if (i915_gem_object_needs_bit17_swizzle(obj))
1872 i915_gem_object_do_bit_17_swizzle(obj);
1878 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1879 page_cache_release(sg_page_iter_page(&sg_iter));
1882 return PTR_ERR(page);
1885 /* Ensure that the associated pages are gathered from the backing storage
1886 * and pinned into our object. i915_gem_object_get_pages() may be called
1887 * multiple times before they are released by a single call to
1888 * i915_gem_object_put_pages() - once the pages are no longer referenced
1889 * either as a result of memory pressure (reaping pages under the shrinker)
1890 * or as the object is itself released.
1893 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1895 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1896 const struct drm_i915_gem_object_ops *ops = obj->ops;
1902 if (obj->madv != I915_MADV_WILLNEED) {
1903 DRM_ERROR("Attempting to obtain a purgeable object\n");
1907 BUG_ON(obj->pages_pin_count);
1909 ret = ops->get_pages(obj);
1913 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1918 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *ring)
1921 struct drm_device *dev = obj->base.dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 u32 seqno = intel_ring_get_seqno(ring);
1925 BUG_ON(ring == NULL);
1926 if (obj->ring != ring && obj->last_write_seqno) {
1927 /* Keep the seqno relative to the current ring */
1928 obj->last_write_seqno = seqno;
1932 /* Add a reference if we're newly entering the active list. */
1934 drm_gem_object_reference(&obj->base);
1938 list_move_tail(&obj->ring_list, &ring->active_list);
1940 obj->last_read_seqno = seqno;
1942 if (obj->fenced_gpu_access) {
1943 obj->last_fenced_seqno = seqno;
1945 /* Bump MRU to take account of the delayed flush */
1946 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1947 struct drm_i915_fence_reg *reg;
1949 reg = &dev_priv->fence_regs[obj->fence_reg];
1950 list_move_tail(®->lru_list,
1951 &dev_priv->mm.fence_list);
1957 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1959 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1960 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1961 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1963 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1964 BUG_ON(!obj->active);
1966 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1968 list_del_init(&obj->ring_list);
1971 obj->last_read_seqno = 0;
1972 obj->last_write_seqno = 0;
1973 obj->base.write_domain = 0;
1975 obj->last_fenced_seqno = 0;
1976 obj->fenced_gpu_access = false;
1979 drm_gem_object_unreference(&obj->base);
1981 WARN_ON(i915_verify_lists(dev));
1985 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_ring_buffer *ring;
1991 /* Carefully retire all requests without writing to the rings */
1992 for_each_ring(ring, dev_priv, i) {
1993 ret = intel_ring_idle(ring);
1997 i915_gem_retire_requests(dev);
1999 /* Finally reset hw state */
2000 for_each_ring(ring, dev_priv, i) {
2001 intel_ring_init_seqno(ring, seqno);
2003 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2004 ring->sync_seqno[j] = 0;
2010 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2018 /* HWS page needs to be set less than what we
2019 * will inject to ring
2021 ret = i915_gem_init_seqno(dev, seqno - 1);
2025 /* Carefully set the last_seqno value so that wrap
2026 * detection still works
2028 dev_priv->next_seqno = seqno;
2029 dev_priv->last_seqno = seqno - 1;
2030 if (dev_priv->last_seqno == 0)
2031 dev_priv->last_seqno--;
2037 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2041 /* reserve 0 for non-seqno */
2042 if (dev_priv->next_seqno == 0) {
2043 int ret = i915_gem_init_seqno(dev, 0);
2047 dev_priv->next_seqno = 1;
2050 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2054 int __i915_add_request(struct intel_ring_buffer *ring,
2055 struct drm_file *file,
2056 struct drm_i915_gem_object *obj,
2059 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2060 struct drm_i915_gem_request *request;
2061 u32 request_ring_position, request_start;
2065 request_start = intel_ring_get_tail(ring);
2067 * Emit any outstanding flushes - execbuf can fail to emit the flush
2068 * after having emitted the batchbuffer command. Hence we need to fix
2069 * things up similar to emitting the lazy request. The difference here
2070 * is that the flush _must_ happen before the next request, no matter
2073 ret = intel_ring_flush_all_caches(ring);
2077 request = kmalloc(sizeof(*request), GFP_KERNEL);
2078 if (request == NULL)
2082 /* Record the position of the start of the request so that
2083 * should we detect the updated seqno part-way through the
2084 * GPU processing the request, we never over-estimate the
2085 * position of the head.
2087 request_ring_position = intel_ring_get_tail(ring);
2089 ret = ring->add_request(ring);
2095 request->seqno = intel_ring_get_seqno(ring);
2096 request->ring = ring;
2097 request->head = request_start;
2098 request->tail = request_ring_position;
2099 request->ctx = ring->last_context;
2100 request->batch_obj = obj;
2102 /* Whilst this request exists, batch_obj will be on the
2103 * active_list, and so will hold the active reference. Only when this
2104 * request is retired will the the batch_obj be moved onto the
2105 * inactive_list and lose its active reference. Hence we do not need
2106 * to explicitly hold another reference here.
2110 i915_gem_context_reference(request->ctx);
2112 request->emitted_jiffies = jiffies;
2113 was_empty = list_empty(&ring->request_list);
2114 list_add_tail(&request->list, &ring->request_list);
2115 request->file_priv = NULL;
2118 struct drm_i915_file_private *file_priv = file->driver_priv;
2120 spin_lock(&file_priv->mm.lock);
2121 request->file_priv = file_priv;
2122 list_add_tail(&request->client_list,
2123 &file_priv->mm.request_list);
2124 spin_unlock(&file_priv->mm.lock);
2127 trace_i915_gem_request_add(ring, request->seqno);
2128 ring->outstanding_lazy_request = 0;
2130 if (!dev_priv->ums.mm_suspended) {
2131 i915_queue_hangcheck(ring->dev);
2134 queue_delayed_work(dev_priv->wq,
2135 &dev_priv->mm.retire_work,
2136 round_jiffies_up_relative(HZ));
2137 intel_mark_busy(dev_priv->dev);
2142 *out_seqno = request->seqno;
2147 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2149 struct drm_i915_file_private *file_priv = request->file_priv;
2154 spin_lock(&file_priv->mm.lock);
2155 if (request->file_priv) {
2156 list_del(&request->client_list);
2157 request->file_priv = NULL;
2159 spin_unlock(&file_priv->mm.lock);
2162 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2163 struct i915_address_space *vm)
2165 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2166 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2172 static bool i915_head_inside_request(const u32 acthd_unmasked,
2173 const u32 request_start,
2174 const u32 request_end)
2176 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2178 if (request_start < request_end) {
2179 if (acthd >= request_start && acthd < request_end)
2181 } else if (request_start > request_end) {
2182 if (acthd >= request_start || acthd < request_end)
2189 static struct i915_address_space *
2190 request_to_vm(struct drm_i915_gem_request *request)
2192 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2193 struct i915_address_space *vm;
2195 vm = &dev_priv->gtt.base;
2200 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2201 const u32 acthd, bool *inside)
2203 /* There is a possibility that unmasked head address
2204 * pointing inside the ring, matches the batch_obj address range.
2205 * However this is extremely unlikely.
2207 if (request->batch_obj) {
2208 if (i915_head_inside_object(acthd, request->batch_obj,
2209 request_to_vm(request))) {
2215 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2223 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2224 struct drm_i915_gem_request *request,
2227 struct i915_ctx_hang_stats *hs = NULL;
2228 bool inside, guilty;
2229 unsigned long offset = 0;
2231 /* Innocent until proven guilty */
2234 if (request->batch_obj)
2235 offset = i915_gem_obj_offset(request->batch_obj,
2236 request_to_vm(request));
2238 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2239 i915_request_guilty(request, acthd, &inside)) {
2240 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2242 inside ? "inside" : "flushing",
2244 request->ctx ? request->ctx->id : 0,
2250 /* If contexts are disabled or this is the default context, use
2251 * file_priv->reset_state
2253 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2254 hs = &request->ctx->hang_stats;
2255 else if (request->file_priv)
2256 hs = &request->file_priv->hang_stats;
2262 hs->batch_pending++;
2266 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2268 list_del(&request->list);
2269 i915_gem_request_remove_from_client(request);
2272 i915_gem_context_unreference(request->ctx);
2277 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2278 struct intel_ring_buffer *ring)
2280 u32 completed_seqno;
2283 acthd = intel_ring_get_active_head(ring);
2284 completed_seqno = ring->get_seqno(ring, false);
2286 while (!list_empty(&ring->request_list)) {
2287 struct drm_i915_gem_request *request;
2289 request = list_first_entry(&ring->request_list,
2290 struct drm_i915_gem_request,
2293 if (request->seqno > completed_seqno)
2294 i915_set_reset_status(ring, request, acthd);
2296 i915_gem_free_request(request);
2299 while (!list_empty(&ring->active_list)) {
2300 struct drm_i915_gem_object *obj;
2302 obj = list_first_entry(&ring->active_list,
2303 struct drm_i915_gem_object,
2306 i915_gem_object_move_to_inactive(obj);
2310 void i915_gem_restore_fences(struct drm_device *dev)
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2315 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2316 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2319 * Commit delayed tiling changes if we have an object still
2320 * attached to the fence, otherwise just clear the fence.
2323 i915_gem_object_update_fence(reg->obj, reg,
2324 reg->obj->tiling_mode);
2326 i915_gem_write_fence(dev, i, NULL);
2331 void i915_gem_reset(struct drm_device *dev)
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_ring_buffer *ring;
2337 for_each_ring(ring, dev_priv, i)
2338 i915_gem_reset_ring_lists(dev_priv, ring);
2340 i915_gem_restore_fences(dev);
2344 * This function clears the request list as sequence numbers are passed.
2347 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2351 if (list_empty(&ring->request_list))
2354 WARN_ON(i915_verify_lists(ring->dev));
2356 seqno = ring->get_seqno(ring, true);
2358 while (!list_empty(&ring->request_list)) {
2359 struct drm_i915_gem_request *request;
2361 request = list_first_entry(&ring->request_list,
2362 struct drm_i915_gem_request,
2365 if (!i915_seqno_passed(seqno, request->seqno))
2368 trace_i915_gem_request_retire(ring, request->seqno);
2369 /* We know the GPU must have read the request to have
2370 * sent us the seqno + interrupt, so use the position
2371 * of tail of the request to update the last known position
2374 ring->last_retired_head = request->tail;
2376 i915_gem_free_request(request);
2379 /* Move any buffers on the active list that are no longer referenced
2380 * by the ringbuffer to the flushing/inactive lists as appropriate.
2382 while (!list_empty(&ring->active_list)) {
2383 struct drm_i915_gem_object *obj;
2385 obj = list_first_entry(&ring->active_list,
2386 struct drm_i915_gem_object,
2389 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2392 i915_gem_object_move_to_inactive(obj);
2395 if (unlikely(ring->trace_irq_seqno &&
2396 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2397 ring->irq_put(ring);
2398 ring->trace_irq_seqno = 0;
2401 WARN_ON(i915_verify_lists(ring->dev));
2405 i915_gem_retire_requests(struct drm_device *dev)
2407 drm_i915_private_t *dev_priv = dev->dev_private;
2408 struct intel_ring_buffer *ring;
2411 for_each_ring(ring, dev_priv, i)
2412 i915_gem_retire_requests_ring(ring);
2416 i915_gem_retire_work_handler(struct work_struct *work)
2418 drm_i915_private_t *dev_priv;
2419 struct drm_device *dev;
2420 struct intel_ring_buffer *ring;
2424 dev_priv = container_of(work, drm_i915_private_t,
2425 mm.retire_work.work);
2426 dev = dev_priv->dev;
2428 /* Come back later if the device is busy... */
2429 if (!mutex_trylock(&dev->struct_mutex)) {
2430 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2431 round_jiffies_up_relative(HZ));
2435 i915_gem_retire_requests(dev);
2437 /* Send a periodic flush down the ring so we don't hold onto GEM
2438 * objects indefinitely.
2441 for_each_ring(ring, dev_priv, i) {
2442 if (ring->gpu_caches_dirty)
2443 i915_add_request(ring, NULL);
2445 idle &= list_empty(&ring->request_list);
2448 if (!dev_priv->ums.mm_suspended && !idle)
2449 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2450 round_jiffies_up_relative(HZ));
2452 intel_mark_idle(dev);
2454 mutex_unlock(&dev->struct_mutex);
2458 * Ensures that an object will eventually get non-busy by flushing any required
2459 * write domains, emitting any outstanding lazy request and retiring and
2460 * completed requests.
2463 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2468 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2472 i915_gem_retire_requests_ring(obj->ring);
2479 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2480 * @DRM_IOCTL_ARGS: standard ioctl arguments
2482 * Returns 0 if successful, else an error is returned with the remaining time in
2483 * the timeout parameter.
2484 * -ETIME: object is still busy after timeout
2485 * -ERESTARTSYS: signal interrupted the wait
2486 * -ENONENT: object doesn't exist
2487 * Also possible, but rare:
2488 * -EAGAIN: GPU wedged
2490 * -ENODEV: Internal IRQ fail
2491 * -E?: The add request failed
2493 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2494 * non-zero timeout parameter the wait ioctl will wait for the given number of
2495 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2496 * without holding struct_mutex the object may become re-busied before this
2497 * function completes. A similar but shorter * race condition exists in the busy
2501 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2503 drm_i915_private_t *dev_priv = dev->dev_private;
2504 struct drm_i915_gem_wait *args = data;
2505 struct drm_i915_gem_object *obj;
2506 struct intel_ring_buffer *ring = NULL;
2507 struct timespec timeout_stack, *timeout = NULL;
2508 unsigned reset_counter;
2512 if (args->timeout_ns >= 0) {
2513 timeout_stack = ns_to_timespec(args->timeout_ns);
2514 timeout = &timeout_stack;
2517 ret = i915_mutex_lock_interruptible(dev);
2521 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2522 if (&obj->base == NULL) {
2523 mutex_unlock(&dev->struct_mutex);
2527 /* Need to make sure the object gets inactive eventually. */
2528 ret = i915_gem_object_flush_active(obj);
2533 seqno = obj->last_read_seqno;
2540 /* Do this after OLR check to make sure we make forward progress polling
2541 * on this IOCTL with a 0 timeout (like busy ioctl)
2543 if (!args->timeout_ns) {
2548 drm_gem_object_unreference(&obj->base);
2549 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2550 mutex_unlock(&dev->struct_mutex);
2552 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2554 args->timeout_ns = timespec_to_ns(timeout);
2558 drm_gem_object_unreference(&obj->base);
2559 mutex_unlock(&dev->struct_mutex);
2564 * i915_gem_object_sync - sync an object to a ring.
2566 * @obj: object which may be in use on another ring.
2567 * @to: ring we wish to use the object on. May be NULL.
2569 * This code is meant to abstract object synchronization with the GPU.
2570 * Calling with NULL implies synchronizing the object with the CPU
2571 * rather than a particular GPU ring.
2573 * Returns 0 if successful, else propagates up the lower layer error.
2576 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2577 struct intel_ring_buffer *to)
2579 struct intel_ring_buffer *from = obj->ring;
2583 if (from == NULL || to == from)
2586 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2587 return i915_gem_object_wait_rendering(obj, false);
2589 idx = intel_ring_sync_index(from, to);
2591 seqno = obj->last_read_seqno;
2592 if (seqno <= from->sync_seqno[idx])
2595 ret = i915_gem_check_olr(obj->ring, seqno);
2599 ret = to->sync_to(to, from, seqno);
2601 /* We use last_read_seqno because sync_to()
2602 * might have just caused seqno wrap under
2605 from->sync_seqno[idx] = obj->last_read_seqno;
2610 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2612 u32 old_write_domain, old_read_domains;
2614 /* Force a pagefault for domain tracking on next user access */
2615 i915_gem_release_mmap(obj);
2617 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2620 /* Wait for any direct GTT access to complete */
2623 old_read_domains = obj->base.read_domains;
2624 old_write_domain = obj->base.write_domain;
2626 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2627 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2629 trace_i915_gem_object_change_domain(obj,
2634 int i915_vma_unbind(struct i915_vma *vma)
2636 struct drm_i915_gem_object *obj = vma->obj;
2637 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2640 if (list_empty(&vma->vma_link))
2643 if (!drm_mm_node_allocated(&vma->node))
2649 BUG_ON(obj->pages == NULL);
2651 ret = i915_gem_object_finish_gpu(obj);
2654 /* Continue on if we fail due to EIO, the GPU is hung so we
2655 * should be safe and we need to cleanup or else we might
2656 * cause memory corruption through use-after-free.
2659 i915_gem_object_finish_gtt(obj);
2661 /* release the fence reg _after_ flushing */
2662 ret = i915_gem_object_put_fence(obj);
2666 trace_i915_vma_unbind(vma);
2668 if (obj->has_global_gtt_mapping)
2669 i915_gem_gtt_unbind_object(obj);
2670 if (obj->has_aliasing_ppgtt_mapping) {
2671 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2672 obj->has_aliasing_ppgtt_mapping = 0;
2674 i915_gem_gtt_finish_object(obj);
2675 i915_gem_object_unpin_pages(obj);
2677 list_del(&vma->mm_list);
2678 /* Avoid an unnecessary call to unbind on rebind. */
2679 if (i915_is_ggtt(vma->vm))
2680 obj->map_and_fenceable = true;
2682 drm_mm_remove_node(&vma->node);
2685 i915_gem_vma_destroy(vma);
2687 /* Since the unbound list is global, only move to that list if
2688 * no more VMAs exist.
2689 * NB: Until we have real VMAs there will only ever be one */
2690 WARN_ON(!list_empty(&obj->vma_list));
2691 if (list_empty(&obj->vma_list))
2692 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2698 * Unbinds an object from the global GTT aperture.
2701 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2703 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2704 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2706 if (!i915_gem_obj_ggtt_bound(obj))
2712 BUG_ON(obj->pages == NULL);
2714 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2717 int i915_gpu_idle(struct drm_device *dev)
2719 drm_i915_private_t *dev_priv = dev->dev_private;
2720 struct intel_ring_buffer *ring;
2723 /* Flush everything onto the inactive list. */
2724 for_each_ring(ring, dev_priv, i) {
2725 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2729 ret = intel_ring_idle(ring);
2737 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2738 struct drm_i915_gem_object *obj)
2740 drm_i915_private_t *dev_priv = dev->dev_private;
2742 int fence_pitch_shift;
2744 if (INTEL_INFO(dev)->gen >= 6) {
2745 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2746 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2748 fence_reg = FENCE_REG_965_0;
2749 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2752 fence_reg += reg * 8;
2754 /* To w/a incoherency with non-atomic 64-bit register updates,
2755 * we split the 64-bit update into two 32-bit writes. In order
2756 * for a partial fence not to be evaluated between writes, we
2757 * precede the update with write to turn off the fence register,
2758 * and only enable the fence as the last step.
2760 * For extra levels of paranoia, we make sure each step lands
2761 * before applying the next step.
2763 I915_WRITE(fence_reg, 0);
2764 POSTING_READ(fence_reg);
2767 u32 size = i915_gem_obj_ggtt_size(obj);
2770 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2772 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2773 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2774 if (obj->tiling_mode == I915_TILING_Y)
2775 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2776 val |= I965_FENCE_REG_VALID;
2778 I915_WRITE(fence_reg + 4, val >> 32);
2779 POSTING_READ(fence_reg + 4);
2781 I915_WRITE(fence_reg + 0, val);
2782 POSTING_READ(fence_reg);
2784 I915_WRITE(fence_reg + 4, 0);
2785 POSTING_READ(fence_reg + 4);
2789 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2790 struct drm_i915_gem_object *obj)
2792 drm_i915_private_t *dev_priv = dev->dev_private;
2796 u32 size = i915_gem_obj_ggtt_size(obj);
2800 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2801 (size & -size) != size ||
2802 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2803 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2804 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2806 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2811 /* Note: pitch better be a power of two tile widths */
2812 pitch_val = obj->stride / tile_width;
2813 pitch_val = ffs(pitch_val) - 1;
2815 val = i915_gem_obj_ggtt_offset(obj);
2816 if (obj->tiling_mode == I915_TILING_Y)
2817 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2818 val |= I915_FENCE_SIZE_BITS(size);
2819 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2820 val |= I830_FENCE_REG_VALID;
2825 reg = FENCE_REG_830_0 + reg * 4;
2827 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2829 I915_WRITE(reg, val);
2833 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2834 struct drm_i915_gem_object *obj)
2836 drm_i915_private_t *dev_priv = dev->dev_private;
2840 u32 size = i915_gem_obj_ggtt_size(obj);
2843 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2844 (size & -size) != size ||
2845 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2846 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2847 i915_gem_obj_ggtt_offset(obj), size);
2849 pitch_val = obj->stride / 128;
2850 pitch_val = ffs(pitch_val) - 1;
2852 val = i915_gem_obj_ggtt_offset(obj);
2853 if (obj->tiling_mode == I915_TILING_Y)
2854 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2855 val |= I830_FENCE_SIZE_BITS(size);
2856 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2857 val |= I830_FENCE_REG_VALID;
2861 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2862 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2865 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2867 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2870 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2871 struct drm_i915_gem_object *obj)
2873 struct drm_i915_private *dev_priv = dev->dev_private;
2875 /* Ensure that all CPU reads are completed before installing a fence
2876 * and all writes before removing the fence.
2878 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2881 WARN(obj && (!obj->stride || !obj->tiling_mode),
2882 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2883 obj->stride, obj->tiling_mode);
2885 switch (INTEL_INFO(dev)->gen) {
2889 case 4: i965_write_fence_reg(dev, reg, obj); break;
2890 case 3: i915_write_fence_reg(dev, reg, obj); break;
2891 case 2: i830_write_fence_reg(dev, reg, obj); break;
2895 /* And similarly be paranoid that no direct access to this region
2896 * is reordered to before the fence is installed.
2898 if (i915_gem_object_needs_mb(obj))
2902 static inline int fence_number(struct drm_i915_private *dev_priv,
2903 struct drm_i915_fence_reg *fence)
2905 return fence - dev_priv->fence_regs;
2908 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2909 struct drm_i915_fence_reg *fence,
2912 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2913 int reg = fence_number(dev_priv, fence);
2915 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2918 obj->fence_reg = reg;
2920 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2922 obj->fence_reg = I915_FENCE_REG_NONE;
2924 list_del_init(&fence->lru_list);
2926 obj->fence_dirty = false;
2930 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2932 if (obj->last_fenced_seqno) {
2933 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2937 obj->last_fenced_seqno = 0;
2940 obj->fenced_gpu_access = false;
2945 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2947 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2948 struct drm_i915_fence_reg *fence;
2951 ret = i915_gem_object_wait_fence(obj);
2955 if (obj->fence_reg == I915_FENCE_REG_NONE)
2958 fence = &dev_priv->fence_regs[obj->fence_reg];
2960 i915_gem_object_fence_lost(obj);
2961 i915_gem_object_update_fence(obj, fence, false);
2966 static struct drm_i915_fence_reg *
2967 i915_find_fence_reg(struct drm_device *dev)
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 struct drm_i915_fence_reg *reg, *avail;
2973 /* First try to find a free reg */
2975 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2976 reg = &dev_priv->fence_regs[i];
2980 if (!reg->pin_count)
2987 /* None available, try to steal one or wait for a user to finish */
2988 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2999 * i915_gem_object_get_fence - set up fencing for an object
3000 * @obj: object to map through a fence reg
3002 * When mapping objects through the GTT, userspace wants to be able to write
3003 * to them without having to worry about swizzling if the object is tiled.
3004 * This function walks the fence regs looking for a free one for @obj,
3005 * stealing one if it can't find any.
3007 * It then sets up the reg based on the object's properties: address, pitch
3008 * and tiling format.
3010 * For an untiled surface, this removes any existing fence.
3013 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3015 struct drm_device *dev = obj->base.dev;
3016 struct drm_i915_private *dev_priv = dev->dev_private;
3017 bool enable = obj->tiling_mode != I915_TILING_NONE;
3018 struct drm_i915_fence_reg *reg;
3021 /* Have we updated the tiling parameters upon the object and so
3022 * will need to serialise the write to the associated fence register?
3024 if (obj->fence_dirty) {
3025 ret = i915_gem_object_wait_fence(obj);
3030 /* Just update our place in the LRU if our fence is getting reused. */
3031 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3032 reg = &dev_priv->fence_regs[obj->fence_reg];
3033 if (!obj->fence_dirty) {
3034 list_move_tail(®->lru_list,
3035 &dev_priv->mm.fence_list);
3038 } else if (enable) {
3039 reg = i915_find_fence_reg(dev);
3044 struct drm_i915_gem_object *old = reg->obj;
3046 ret = i915_gem_object_wait_fence(old);
3050 i915_gem_object_fence_lost(old);
3055 i915_gem_object_update_fence(obj, reg, enable);
3060 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3061 struct drm_mm_node *gtt_space,
3062 unsigned long cache_level)
3064 struct drm_mm_node *other;
3066 /* On non-LLC machines we have to be careful when putting differing
3067 * types of snoopable memory together to avoid the prefetcher
3068 * crossing memory domains and dying.
3073 if (!drm_mm_node_allocated(gtt_space))
3076 if (list_empty(>t_space->node_list))
3079 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3080 if (other->allocated && !other->hole_follows && other->color != cache_level)
3083 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3084 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3090 static void i915_gem_verify_gtt(struct drm_device *dev)
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 struct drm_i915_gem_object *obj;
3097 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3098 if (obj->gtt_space == NULL) {
3099 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3104 if (obj->cache_level != obj->gtt_space->color) {
3105 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3106 i915_gem_obj_ggtt_offset(obj),
3107 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3109 obj->gtt_space->color);
3114 if (!i915_gem_valid_gtt_space(dev,
3116 obj->cache_level)) {
3117 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3118 i915_gem_obj_ggtt_offset(obj),
3119 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3131 * Finds free space in the GTT aperture and binds the object there.
3134 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3135 struct i915_address_space *vm,
3137 bool map_and_fenceable,
3140 struct drm_device *dev = obj->base.dev;
3141 drm_i915_private_t *dev_priv = dev->dev_private;
3142 u32 size, fence_size, fence_alignment, unfenced_alignment;
3144 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3145 struct i915_vma *vma;
3148 fence_size = i915_gem_get_gtt_size(dev,
3151 fence_alignment = i915_gem_get_gtt_alignment(dev,
3153 obj->tiling_mode, true);
3154 unfenced_alignment =
3155 i915_gem_get_gtt_alignment(dev,
3157 obj->tiling_mode, false);
3160 alignment = map_and_fenceable ? fence_alignment :
3162 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3163 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3167 size = map_and_fenceable ? fence_size : obj->base.size;
3169 /* If the object is bigger than the entire aperture, reject it early
3170 * before evicting everything in a vain attempt to find space.
3172 if (obj->base.size > gtt_max) {
3173 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3175 map_and_fenceable ? "mappable" : "total",
3180 ret = i915_gem_object_get_pages(obj);
3184 i915_gem_object_pin_pages(obj);
3186 BUG_ON(!i915_is_ggtt(vm));
3188 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3194 /* For now we only ever use 1 vma per object */
3195 WARN_ON(!list_is_singular(&obj->vma_list));
3198 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3200 obj->cache_level, 0, gtt_max,
3201 DRM_MM_SEARCH_DEFAULT);
3203 ret = i915_gem_evict_something(dev, vm, size, alignment,
3212 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3213 obj->cache_level))) {
3215 goto err_remove_node;
3218 ret = i915_gem_gtt_prepare_object(obj);
3220 goto err_remove_node;
3222 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3223 list_add_tail(&vma->mm_list, &vm->inactive_list);
3225 if (i915_is_ggtt(vm)) {
3226 bool mappable, fenceable;
3228 fenceable = (vma->node.size == fence_size &&
3229 (vma->node.start & (fence_alignment - 1)) == 0);
3231 mappable = (vma->node.start + obj->base.size <=
3232 dev_priv->gtt.mappable_end);
3234 obj->map_and_fenceable = mappable && fenceable;
3237 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3239 trace_i915_vma_bind(vma, map_and_fenceable);
3240 i915_gem_verify_gtt(dev);
3244 drm_mm_remove_node(&vma->node);
3246 i915_gem_vma_destroy(vma);
3248 i915_gem_object_unpin_pages(obj);
3253 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3256 /* If we don't have a page list set up, then we're not pinned
3257 * to GPU, and we can ignore the cache flush because it'll happen
3258 * again at bind time.
3260 if (obj->pages == NULL)
3264 * Stolen memory is always coherent with the GPU as it is explicitly
3265 * marked as wc by the system, or the system is cache-coherent.
3270 /* If the GPU is snooping the contents of the CPU cache,
3271 * we do not need to manually clear the CPU cache lines. However,
3272 * the caches are only snooped when the render cache is
3273 * flushed/invalidated. As we always have to emit invalidations
3274 * and flushes when moving into and out of the RENDER domain, correct
3275 * snooping behaviour occurs naturally as the result of our domain
3278 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3281 trace_i915_gem_object_clflush(obj);
3282 drm_clflush_sg(obj->pages);
3287 /** Flushes the GTT write domain for the object if it's dirty. */
3289 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3291 uint32_t old_write_domain;
3293 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3296 /* No actual flushing is required for the GTT write domain. Writes
3297 * to it immediately go to main memory as far as we know, so there's
3298 * no chipset flush. It also doesn't land in render cache.
3300 * However, we do have to enforce the order so that all writes through
3301 * the GTT land before any writes to the device, such as updates to
3306 old_write_domain = obj->base.write_domain;
3307 obj->base.write_domain = 0;
3309 trace_i915_gem_object_change_domain(obj,
3310 obj->base.read_domains,
3314 /** Flushes the CPU write domain for the object if it's dirty. */
3316 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3319 uint32_t old_write_domain;
3321 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3324 if (i915_gem_clflush_object(obj, force))
3325 i915_gem_chipset_flush(obj->base.dev);
3327 old_write_domain = obj->base.write_domain;
3328 obj->base.write_domain = 0;
3330 trace_i915_gem_object_change_domain(obj,
3331 obj->base.read_domains,
3336 * Moves a single object to the GTT read, and possibly write domain.
3338 * This function returns when the move is complete, including waiting on
3342 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3344 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3345 uint32_t old_write_domain, old_read_domains;
3348 /* Not valid to be called on unbound objects. */
3349 if (!i915_gem_obj_bound_any(obj))
3352 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3355 ret = i915_gem_object_wait_rendering(obj, !write);
3359 i915_gem_object_flush_cpu_write_domain(obj, false);
3361 /* Serialise direct access to this object with the barriers for
3362 * coherent writes from the GPU, by effectively invalidating the
3363 * GTT domain upon first access.
3365 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3368 old_write_domain = obj->base.write_domain;
3369 old_read_domains = obj->base.read_domains;
3371 /* It should now be out of any other write domains, and we can update
3372 * the domain values for our changes.
3374 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3375 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3377 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3378 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3382 trace_i915_gem_object_change_domain(obj,
3386 /* And bump the LRU for this access */
3387 if (i915_gem_object_is_inactive(obj)) {
3388 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3389 &dev_priv->gtt.base);
3391 list_move_tail(&vma->mm_list,
3392 &dev_priv->gtt.base.inactive_list);
3399 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3400 enum i915_cache_level cache_level)
3402 struct drm_device *dev = obj->base.dev;
3403 drm_i915_private_t *dev_priv = dev->dev_private;
3404 struct i915_vma *vma;
3407 if (obj->cache_level == cache_level)
3410 if (obj->pin_count) {
3411 DRM_DEBUG("can not change the cache level of pinned objects\n");
3415 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3416 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3417 ret = i915_vma_unbind(vma);
3425 if (i915_gem_obj_bound_any(obj)) {
3426 ret = i915_gem_object_finish_gpu(obj);
3430 i915_gem_object_finish_gtt(obj);
3432 /* Before SandyBridge, you could not use tiling or fence
3433 * registers with snooped memory, so relinquish any fences
3434 * currently pointing to our region in the aperture.
3436 if (INTEL_INFO(dev)->gen < 6) {
3437 ret = i915_gem_object_put_fence(obj);
3442 if (obj->has_global_gtt_mapping)
3443 i915_gem_gtt_bind_object(obj, cache_level);
3444 if (obj->has_aliasing_ppgtt_mapping)
3445 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3449 list_for_each_entry(vma, &obj->vma_list, vma_link)
3450 vma->node.color = cache_level;
3451 obj->cache_level = cache_level;
3453 if (cpu_write_needs_clflush(obj)) {
3454 u32 old_read_domains, old_write_domain;
3456 /* If we're coming from LLC cached, then we haven't
3457 * actually been tracking whether the data is in the
3458 * CPU cache or not, since we only allow one bit set
3459 * in obj->write_domain and have been skipping the clflushes.
3460 * Just set it to the CPU cache for now.
3462 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3464 old_read_domains = obj->base.read_domains;
3465 old_write_domain = obj->base.write_domain;
3467 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3468 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3470 trace_i915_gem_object_change_domain(obj,
3475 i915_gem_verify_gtt(dev);
3479 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3480 struct drm_file *file)
3482 struct drm_i915_gem_caching *args = data;
3483 struct drm_i915_gem_object *obj;
3486 ret = i915_mutex_lock_interruptible(dev);
3490 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3491 if (&obj->base == NULL) {
3496 switch (obj->cache_level) {
3497 case I915_CACHE_LLC:
3498 case I915_CACHE_L3_LLC:
3499 args->caching = I915_CACHING_CACHED;
3503 args->caching = I915_CACHING_DISPLAY;
3507 args->caching = I915_CACHING_NONE;
3511 drm_gem_object_unreference(&obj->base);
3513 mutex_unlock(&dev->struct_mutex);
3517 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3518 struct drm_file *file)
3520 struct drm_i915_gem_caching *args = data;
3521 struct drm_i915_gem_object *obj;
3522 enum i915_cache_level level;
3525 switch (args->caching) {
3526 case I915_CACHING_NONE:
3527 level = I915_CACHE_NONE;
3529 case I915_CACHING_CACHED:
3530 level = I915_CACHE_LLC;
3532 case I915_CACHING_DISPLAY:
3533 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3539 ret = i915_mutex_lock_interruptible(dev);
3543 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3544 if (&obj->base == NULL) {
3549 ret = i915_gem_object_set_cache_level(obj, level);
3551 drm_gem_object_unreference(&obj->base);
3553 mutex_unlock(&dev->struct_mutex);
3557 static bool is_pin_display(struct drm_i915_gem_object *obj)
3559 /* There are 3 sources that pin objects:
3560 * 1. The display engine (scanouts, sprites, cursors);
3561 * 2. Reservations for execbuffer;
3564 * We can ignore reservations as we hold the struct_mutex and
3565 * are only called outside of the reservation path. The user
3566 * can only increment pin_count once, and so if after
3567 * subtracting the potential reference by the user, any pin_count
3568 * remains, it must be due to another use by the display engine.
3570 return obj->pin_count - !!obj->user_pin_count;
3574 * Prepare buffer for display plane (scanout, cursors, etc).
3575 * Can be called from an uninterruptible phase (modesetting) and allows
3576 * any flushes to be pipelined (for pageflips).
3579 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3581 struct intel_ring_buffer *pipelined)
3583 u32 old_read_domains, old_write_domain;
3586 if (pipelined != obj->ring) {
3587 ret = i915_gem_object_sync(obj, pipelined);
3592 /* Mark the pin_display early so that we account for the
3593 * display coherency whilst setting up the cache domains.
3595 obj->pin_display = true;
3597 /* The display engine is not coherent with the LLC cache on gen6. As
3598 * a result, we make sure that the pinning that is about to occur is
3599 * done with uncached PTEs. This is lowest common denominator for all
3602 * However for gen6+, we could do better by using the GFDT bit instead
3603 * of uncaching, which would allow us to flush all the LLC-cached data
3604 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3606 ret = i915_gem_object_set_cache_level(obj,
3607 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3609 goto err_unpin_display;
3611 /* As the user may map the buffer once pinned in the display plane
3612 * (e.g. libkms for the bootup splash), we have to ensure that we
3613 * always use map_and_fenceable for all scanout buffers.
3615 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3617 goto err_unpin_display;
3619 i915_gem_object_flush_cpu_write_domain(obj, true);
3621 old_write_domain = obj->base.write_domain;
3622 old_read_domains = obj->base.read_domains;
3624 /* It should now be out of any other write domains, and we can update
3625 * the domain values for our changes.
3627 obj->base.write_domain = 0;
3628 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3630 trace_i915_gem_object_change_domain(obj,
3637 obj->pin_display = is_pin_display(obj);
3642 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3644 i915_gem_object_unpin(obj);
3645 obj->pin_display = is_pin_display(obj);
3649 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3653 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3656 ret = i915_gem_object_wait_rendering(obj, false);
3660 /* Ensure that we invalidate the GPU's caches and TLBs. */
3661 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3666 * Moves a single object to the CPU read, and possibly write domain.
3668 * This function returns when the move is complete, including waiting on
3672 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3674 uint32_t old_write_domain, old_read_domains;
3677 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3680 ret = i915_gem_object_wait_rendering(obj, !write);
3684 i915_gem_object_flush_gtt_write_domain(obj);
3686 old_write_domain = obj->base.write_domain;
3687 old_read_domains = obj->base.read_domains;
3689 /* Flush the CPU cache if it's still invalid. */
3690 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3691 i915_gem_clflush_object(obj, false);
3693 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3696 /* It should now be out of any other write domains, and we can update
3697 * the domain values for our changes.
3699 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3701 /* If we're writing through the CPU, then the GPU read domains will
3702 * need to be invalidated at next use.
3705 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3706 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3709 trace_i915_gem_object_change_domain(obj,
3716 /* Throttle our rendering by waiting until the ring has completed our requests
3717 * emitted over 20 msec ago.
3719 * Note that if we were to use the current jiffies each time around the loop,
3720 * we wouldn't escape the function with any frames outstanding if the time to
3721 * render a frame was over 20ms.
3723 * This should get us reasonable parallelism between CPU and GPU but also
3724 * relatively low latency when blocking on a particular request to finish.
3727 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 struct drm_i915_file_private *file_priv = file->driver_priv;
3731 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3732 struct drm_i915_gem_request *request;
3733 struct intel_ring_buffer *ring = NULL;
3734 unsigned reset_counter;
3738 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3742 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3746 spin_lock(&file_priv->mm.lock);
3747 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3748 if (time_after_eq(request->emitted_jiffies, recent_enough))
3751 ring = request->ring;
3752 seqno = request->seqno;
3754 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3755 spin_unlock(&file_priv->mm.lock);
3760 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3762 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3768 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3769 struct i915_address_space *vm,
3771 bool map_and_fenceable,
3774 struct i915_vma *vma;
3777 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3780 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3782 vma = i915_gem_obj_to_vma(obj, vm);
3786 vma->node.start & (alignment - 1)) ||
3787 (map_and_fenceable && !obj->map_and_fenceable)) {
3788 WARN(obj->pin_count,
3789 "bo is already pinned with incorrect alignment:"
3790 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3791 " obj->map_and_fenceable=%d\n",
3792 i915_gem_obj_offset(obj, vm), alignment,
3794 obj->map_and_fenceable);
3795 ret = i915_vma_unbind(vma);
3801 if (!i915_gem_obj_bound(obj, vm)) {
3802 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3804 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3810 if (!dev_priv->mm.aliasing_ppgtt)
3811 i915_gem_gtt_bind_object(obj, obj->cache_level);
3814 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3815 i915_gem_gtt_bind_object(obj, obj->cache_level);
3818 obj->pin_mappable |= map_and_fenceable;
3824 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3826 BUG_ON(obj->pin_count == 0);
3827 BUG_ON(!i915_gem_obj_bound_any(obj));
3829 if (--obj->pin_count == 0)
3830 obj->pin_mappable = false;
3834 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3835 struct drm_file *file)
3837 struct drm_i915_gem_pin *args = data;
3838 struct drm_i915_gem_object *obj;
3841 ret = i915_mutex_lock_interruptible(dev);
3845 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3846 if (&obj->base == NULL) {
3851 if (obj->madv != I915_MADV_WILLNEED) {
3852 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3857 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3858 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3864 if (obj->user_pin_count == 0) {
3865 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3870 obj->user_pin_count++;
3871 obj->pin_filp = file;
3873 args->offset = i915_gem_obj_ggtt_offset(obj);
3875 drm_gem_object_unreference(&obj->base);
3877 mutex_unlock(&dev->struct_mutex);
3882 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3883 struct drm_file *file)
3885 struct drm_i915_gem_pin *args = data;
3886 struct drm_i915_gem_object *obj;
3889 ret = i915_mutex_lock_interruptible(dev);
3893 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3894 if (&obj->base == NULL) {
3899 if (obj->pin_filp != file) {
3900 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3905 obj->user_pin_count--;
3906 if (obj->user_pin_count == 0) {
3907 obj->pin_filp = NULL;
3908 i915_gem_object_unpin(obj);
3912 drm_gem_object_unreference(&obj->base);
3914 mutex_unlock(&dev->struct_mutex);
3919 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3920 struct drm_file *file)
3922 struct drm_i915_gem_busy *args = data;
3923 struct drm_i915_gem_object *obj;
3926 ret = i915_mutex_lock_interruptible(dev);
3930 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3931 if (&obj->base == NULL) {
3936 /* Count all active objects as busy, even if they are currently not used
3937 * by the gpu. Users of this interface expect objects to eventually
3938 * become non-busy without any further actions, therefore emit any
3939 * necessary flushes here.
3941 ret = i915_gem_object_flush_active(obj);
3943 args->busy = obj->active;
3945 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3946 args->busy |= intel_ring_flag(obj->ring) << 16;
3949 drm_gem_object_unreference(&obj->base);
3951 mutex_unlock(&dev->struct_mutex);
3956 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3957 struct drm_file *file_priv)
3959 return i915_gem_ring_throttle(dev, file_priv);
3963 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3964 struct drm_file *file_priv)
3966 struct drm_i915_gem_madvise *args = data;
3967 struct drm_i915_gem_object *obj;
3970 switch (args->madv) {
3971 case I915_MADV_DONTNEED:
3972 case I915_MADV_WILLNEED:
3978 ret = i915_mutex_lock_interruptible(dev);
3982 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3983 if (&obj->base == NULL) {
3988 if (obj->pin_count) {
3993 if (obj->madv != __I915_MADV_PURGED)
3994 obj->madv = args->madv;
3996 /* if the object is no longer attached, discard its backing storage */
3997 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3998 i915_gem_object_truncate(obj);
4000 args->retained = obj->madv != __I915_MADV_PURGED;
4003 drm_gem_object_unreference(&obj->base);
4005 mutex_unlock(&dev->struct_mutex);
4009 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4010 const struct drm_i915_gem_object_ops *ops)
4012 INIT_LIST_HEAD(&obj->global_list);
4013 INIT_LIST_HEAD(&obj->ring_list);
4014 INIT_LIST_HEAD(&obj->exec_list);
4015 INIT_LIST_HEAD(&obj->obj_exec_link);
4016 INIT_LIST_HEAD(&obj->vma_list);
4020 obj->fence_reg = I915_FENCE_REG_NONE;
4021 obj->madv = I915_MADV_WILLNEED;
4022 /* Avoid an unnecessary call to unbind on the first bind. */
4023 obj->map_and_fenceable = true;
4025 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4028 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4029 .get_pages = i915_gem_object_get_pages_gtt,
4030 .put_pages = i915_gem_object_put_pages_gtt,
4033 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4036 struct drm_i915_gem_object *obj;
4037 struct address_space *mapping;
4040 obj = i915_gem_object_alloc(dev);
4044 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4045 i915_gem_object_free(obj);
4049 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4050 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4051 /* 965gm cannot relocate objects above 4GiB. */
4052 mask &= ~__GFP_HIGHMEM;
4053 mask |= __GFP_DMA32;
4056 mapping = file_inode(obj->base.filp)->i_mapping;
4057 mapping_set_gfp_mask(mapping, mask);
4059 i915_gem_object_init(obj, &i915_gem_object_ops);
4061 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4062 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4065 /* On some devices, we can have the GPU use the LLC (the CPU
4066 * cache) for about a 10% performance improvement
4067 * compared to uncached. Graphics requests other than
4068 * display scanout are coherent with the CPU in
4069 * accessing this cache. This means in this mode we
4070 * don't need to clflush on the CPU side, and on the
4071 * GPU side we only need to flush internal caches to
4072 * get data visible to the CPU.
4074 * However, we maintain the display planes as UC, and so
4075 * need to rebind when first used as such.
4077 obj->cache_level = I915_CACHE_LLC;
4079 obj->cache_level = I915_CACHE_NONE;
4081 trace_i915_gem_object_create(obj);
4086 int i915_gem_init_object(struct drm_gem_object *obj)
4093 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4095 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4096 struct drm_device *dev = obj->base.dev;
4097 drm_i915_private_t *dev_priv = dev->dev_private;
4098 struct i915_vma *vma, *next;
4100 trace_i915_gem_object_destroy(obj);
4103 i915_gem_detach_phys_object(dev, obj);
4106 /* NB: 0 or 1 elements */
4107 WARN_ON(!list_empty(&obj->vma_list) &&
4108 !list_is_singular(&obj->vma_list));
4109 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4110 int ret = i915_vma_unbind(vma);
4111 if (WARN_ON(ret == -ERESTARTSYS)) {
4112 bool was_interruptible;
4114 was_interruptible = dev_priv->mm.interruptible;
4115 dev_priv->mm.interruptible = false;
4117 WARN_ON(i915_vma_unbind(vma));
4119 dev_priv->mm.interruptible = was_interruptible;
4123 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4124 * before progressing. */
4126 i915_gem_object_unpin_pages(obj);
4128 if (WARN_ON(obj->pages_pin_count))
4129 obj->pages_pin_count = 0;
4130 i915_gem_object_put_pages(obj);
4131 i915_gem_object_free_mmap_offset(obj);
4132 i915_gem_object_release_stolen(obj);
4136 if (obj->base.import_attach)
4137 drm_prime_gem_destroy(&obj->base, NULL);
4139 drm_gem_object_release(&obj->base);
4140 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4143 i915_gem_object_free(obj);
4146 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4147 struct i915_address_space *vm)
4149 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4151 return ERR_PTR(-ENOMEM);
4153 INIT_LIST_HEAD(&vma->vma_link);
4154 INIT_LIST_HEAD(&vma->mm_list);
4155 INIT_LIST_HEAD(&vma->exec_list);
4159 /* Keep GGTT vmas first to make debug easier */
4160 if (i915_is_ggtt(vm))
4161 list_add(&vma->vma_link, &obj->vma_list);
4163 list_add_tail(&vma->vma_link, &obj->vma_list);
4168 void i915_gem_vma_destroy(struct i915_vma *vma)
4170 WARN_ON(vma->node.allocated);
4171 list_del(&vma->vma_link);
4176 i915_gem_idle(struct drm_device *dev)
4178 drm_i915_private_t *dev_priv = dev->dev_private;
4181 if (dev_priv->ums.mm_suspended) {
4182 mutex_unlock(&dev->struct_mutex);
4186 ret = i915_gpu_idle(dev);
4188 mutex_unlock(&dev->struct_mutex);
4191 i915_gem_retire_requests(dev);
4193 /* Under UMS, be paranoid and evict. */
4194 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4195 i915_gem_evict_everything(dev);
4197 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4199 i915_kernel_lost_context(dev);
4200 i915_gem_cleanup_ringbuffer(dev);
4202 /* Cancel the retire work handler, which should be idle now. */
4203 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4208 void i915_gem_l3_remap(struct drm_device *dev)
4210 drm_i915_private_t *dev_priv = dev->dev_private;
4214 if (!HAS_L3_GPU_CACHE(dev))
4217 if (!dev_priv->l3_parity.remap_info)
4220 misccpctl = I915_READ(GEN7_MISCCPCTL);
4221 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4222 POSTING_READ(GEN7_MISCCPCTL);
4224 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4225 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4226 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4227 DRM_DEBUG("0x%x was already programmed to %x\n",
4228 GEN7_L3LOG_BASE + i, remap);
4229 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4230 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4231 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4234 /* Make sure all the writes land before disabling dop clock gating */
4235 POSTING_READ(GEN7_L3LOG_BASE);
4237 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4240 void i915_gem_init_swizzling(struct drm_device *dev)
4242 drm_i915_private_t *dev_priv = dev->dev_private;
4244 if (INTEL_INFO(dev)->gen < 5 ||
4245 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4248 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4249 DISP_TILE_SURFACE_SWIZZLING);
4254 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4256 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4257 else if (IS_GEN7(dev))
4258 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4264 intel_enable_blt(struct drm_device *dev)
4269 /* The blitter was dysfunctional on early prototypes */
4270 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4271 DRM_INFO("BLT not supported on this pre-production hardware;"
4272 " graphics performance will be degraded.\n");
4279 static int i915_gem_init_rings(struct drm_device *dev)
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4284 ret = intel_init_render_ring_buffer(dev);
4289 ret = intel_init_bsd_ring_buffer(dev);
4291 goto cleanup_render_ring;
4294 if (intel_enable_blt(dev)) {
4295 ret = intel_init_blt_ring_buffer(dev);
4297 goto cleanup_bsd_ring;
4300 if (HAS_VEBOX(dev)) {
4301 ret = intel_init_vebox_ring_buffer(dev);
4303 goto cleanup_blt_ring;
4307 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4309 goto cleanup_vebox_ring;
4314 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4316 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4318 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4319 cleanup_render_ring:
4320 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4326 i915_gem_init_hw(struct drm_device *dev)
4328 drm_i915_private_t *dev_priv = dev->dev_private;
4331 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4334 if (dev_priv->ellc_size)
4335 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4337 if (HAS_PCH_NOP(dev)) {
4338 u32 temp = I915_READ(GEN7_MSG_CTL);
4339 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4340 I915_WRITE(GEN7_MSG_CTL, temp);
4343 i915_gem_l3_remap(dev);
4345 i915_gem_init_swizzling(dev);
4347 ret = i915_gem_init_rings(dev);
4352 * XXX: There was some w/a described somewhere suggesting loading
4353 * contexts before PPGTT.
4355 i915_gem_context_init(dev);
4356 if (dev_priv->mm.aliasing_ppgtt) {
4357 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4359 i915_gem_cleanup_aliasing_ppgtt(dev);
4360 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4367 int i915_gem_init(struct drm_device *dev)
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4372 mutex_lock(&dev->struct_mutex);
4374 if (IS_VALLEYVIEW(dev)) {
4375 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4376 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4377 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4378 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4381 i915_gem_init_global_gtt(dev);
4383 ret = i915_gem_init_hw(dev);
4384 mutex_unlock(&dev->struct_mutex);
4386 i915_gem_cleanup_aliasing_ppgtt(dev);
4390 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4391 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4392 dev_priv->dri1.allow_batchbuffer = 1;
4397 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4399 drm_i915_private_t *dev_priv = dev->dev_private;
4400 struct intel_ring_buffer *ring;
4403 for_each_ring(ring, dev_priv, i)
4404 intel_cleanup_ring_buffer(ring);
4408 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4409 struct drm_file *file_priv)
4411 struct drm_i915_private *dev_priv = dev->dev_private;
4414 if (drm_core_check_feature(dev, DRIVER_MODESET))
4417 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4418 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4419 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4422 mutex_lock(&dev->struct_mutex);
4423 dev_priv->ums.mm_suspended = 0;
4425 ret = i915_gem_init_hw(dev);
4427 mutex_unlock(&dev->struct_mutex);
4431 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4432 mutex_unlock(&dev->struct_mutex);
4434 ret = drm_irq_install(dev);
4436 goto cleanup_ringbuffer;
4441 mutex_lock(&dev->struct_mutex);
4442 i915_gem_cleanup_ringbuffer(dev);
4443 dev_priv->ums.mm_suspended = 1;
4444 mutex_unlock(&dev->struct_mutex);
4450 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4451 struct drm_file *file_priv)
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4456 if (drm_core_check_feature(dev, DRIVER_MODESET))
4459 drm_irq_uninstall(dev);
4461 mutex_lock(&dev->struct_mutex);
4462 ret = i915_gem_idle(dev);
4464 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4465 * We need to replace this with a semaphore, or something.
4466 * And not confound ums.mm_suspended!
4469 dev_priv->ums.mm_suspended = 1;
4470 mutex_unlock(&dev->struct_mutex);
4476 i915_gem_lastclose(struct drm_device *dev)
4480 if (drm_core_check_feature(dev, DRIVER_MODESET))
4483 mutex_lock(&dev->struct_mutex);
4484 ret = i915_gem_idle(dev);
4486 DRM_ERROR("failed to idle hardware: %d\n", ret);
4487 mutex_unlock(&dev->struct_mutex);
4491 init_ring_lists(struct intel_ring_buffer *ring)
4493 INIT_LIST_HEAD(&ring->active_list);
4494 INIT_LIST_HEAD(&ring->request_list);
4497 static void i915_init_vm(struct drm_i915_private *dev_priv,
4498 struct i915_address_space *vm)
4500 vm->dev = dev_priv->dev;
4501 INIT_LIST_HEAD(&vm->active_list);
4502 INIT_LIST_HEAD(&vm->inactive_list);
4503 INIT_LIST_HEAD(&vm->global_link);
4504 list_add(&vm->global_link, &dev_priv->vm_list);
4508 i915_gem_load(struct drm_device *dev)
4510 drm_i915_private_t *dev_priv = dev->dev_private;
4514 kmem_cache_create("i915_gem_object",
4515 sizeof(struct drm_i915_gem_object), 0,
4519 INIT_LIST_HEAD(&dev_priv->vm_list);
4520 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4522 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4523 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4524 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4525 for (i = 0; i < I915_NUM_RINGS; i++)
4526 init_ring_lists(&dev_priv->ring[i]);
4527 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4528 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4529 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4530 i915_gem_retire_work_handler);
4531 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4533 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4535 I915_WRITE(MI_ARB_STATE,
4536 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4539 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4541 /* Old X drivers will take 0-2 for front, back, depth buffers */
4542 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4543 dev_priv->fence_reg_start = 3;
4545 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4546 dev_priv->num_fence_regs = 32;
4547 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4548 dev_priv->num_fence_regs = 16;
4550 dev_priv->num_fence_regs = 8;
4552 /* Initialize fence registers to zero */
4553 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4554 i915_gem_restore_fences(dev);
4556 i915_gem_detect_bit_6_swizzle(dev);
4557 init_waitqueue_head(&dev_priv->pending_flip_queue);
4559 dev_priv->mm.interruptible = true;
4561 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4562 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4563 register_shrinker(&dev_priv->mm.inactive_shrinker);
4567 * Create a physically contiguous memory object for this object
4568 * e.g. for cursor + overlay regs
4570 static int i915_gem_init_phys_object(struct drm_device *dev,
4571 int id, int size, int align)
4573 drm_i915_private_t *dev_priv = dev->dev_private;
4574 struct drm_i915_gem_phys_object *phys_obj;
4577 if (dev_priv->mm.phys_objs[id - 1] || !size)
4580 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4586 phys_obj->handle = drm_pci_alloc(dev, size, align);
4587 if (!phys_obj->handle) {
4592 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4595 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4603 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4605 drm_i915_private_t *dev_priv = dev->dev_private;
4606 struct drm_i915_gem_phys_object *phys_obj;
4608 if (!dev_priv->mm.phys_objs[id - 1])
4611 phys_obj = dev_priv->mm.phys_objs[id - 1];
4612 if (phys_obj->cur_obj) {
4613 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4617 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4619 drm_pci_free(dev, phys_obj->handle);
4621 dev_priv->mm.phys_objs[id - 1] = NULL;
4624 void i915_gem_free_all_phys_object(struct drm_device *dev)
4628 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4629 i915_gem_free_phys_object(dev, i);
4632 void i915_gem_detach_phys_object(struct drm_device *dev,
4633 struct drm_i915_gem_object *obj)
4635 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4642 vaddr = obj->phys_obj->handle->vaddr;
4644 page_count = obj->base.size / PAGE_SIZE;
4645 for (i = 0; i < page_count; i++) {
4646 struct page *page = shmem_read_mapping_page(mapping, i);
4647 if (!IS_ERR(page)) {
4648 char *dst = kmap_atomic(page);
4649 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4652 drm_clflush_pages(&page, 1);
4654 set_page_dirty(page);
4655 mark_page_accessed(page);
4656 page_cache_release(page);
4659 i915_gem_chipset_flush(dev);
4661 obj->phys_obj->cur_obj = NULL;
4662 obj->phys_obj = NULL;
4666 i915_gem_attach_phys_object(struct drm_device *dev,
4667 struct drm_i915_gem_object *obj,
4671 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4672 drm_i915_private_t *dev_priv = dev->dev_private;
4677 if (id > I915_MAX_PHYS_OBJECT)
4680 if (obj->phys_obj) {
4681 if (obj->phys_obj->id == id)
4683 i915_gem_detach_phys_object(dev, obj);
4686 /* create a new object */
4687 if (!dev_priv->mm.phys_objs[id - 1]) {
4688 ret = i915_gem_init_phys_object(dev, id,
4689 obj->base.size, align);
4691 DRM_ERROR("failed to init phys object %d size: %zu\n",
4692 id, obj->base.size);
4697 /* bind to the object */
4698 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4699 obj->phys_obj->cur_obj = obj;
4701 page_count = obj->base.size / PAGE_SIZE;
4703 for (i = 0; i < page_count; i++) {
4707 page = shmem_read_mapping_page(mapping, i);
4709 return PTR_ERR(page);
4711 src = kmap_atomic(page);
4712 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4713 memcpy(dst, src, PAGE_SIZE);
4716 mark_page_accessed(page);
4717 page_cache_release(page);
4724 i915_gem_phys_pwrite(struct drm_device *dev,
4725 struct drm_i915_gem_object *obj,
4726 struct drm_i915_gem_pwrite *args,
4727 struct drm_file *file_priv)
4729 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4730 char __user *user_data = to_user_ptr(args->data_ptr);
4732 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4733 unsigned long unwritten;
4735 /* The physical object once assigned is fixed for the lifetime
4736 * of the obj, so we can safely drop the lock and continue
4739 mutex_unlock(&dev->struct_mutex);
4740 unwritten = copy_from_user(vaddr, user_data, args->size);
4741 mutex_lock(&dev->struct_mutex);
4746 i915_gem_chipset_flush(dev);
4750 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4752 struct drm_i915_file_private *file_priv = file->driver_priv;
4754 /* Clean up our request list when the client is going away, so that
4755 * later retire_requests won't dereference our soon-to-be-gone
4758 spin_lock(&file_priv->mm.lock);
4759 while (!list_empty(&file_priv->mm.request_list)) {
4760 struct drm_i915_gem_request *request;
4762 request = list_first_entry(&file_priv->mm.request_list,
4763 struct drm_i915_gem_request,
4765 list_del(&request->client_list);
4766 request->file_priv = NULL;
4768 spin_unlock(&file_priv->mm.lock);
4771 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4773 if (!mutex_is_locked(mutex))
4776 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4777 return mutex->owner == task;
4779 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4785 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4787 struct drm_i915_private *dev_priv =
4788 container_of(shrinker,
4789 struct drm_i915_private,
4790 mm.inactive_shrinker);
4791 struct drm_device *dev = dev_priv->dev;
4792 struct drm_i915_gem_object *obj;
4793 int nr_to_scan = sc->nr_to_scan;
4797 if (!mutex_trylock(&dev->struct_mutex)) {
4798 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4801 if (dev_priv->mm.shrinker_no_lock_stealing)
4808 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4810 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4813 i915_gem_shrink_all(dev_priv);
4817 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4818 if (obj->pages_pin_count == 0)
4819 cnt += obj->base.size >> PAGE_SHIFT;
4821 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4825 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4826 cnt += obj->base.size >> PAGE_SHIFT;
4830 mutex_unlock(&dev->struct_mutex);
4834 /* All the new VM stuff */
4835 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4836 struct i915_address_space *vm)
4838 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4839 struct i915_vma *vma;
4841 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4842 vm = &dev_priv->gtt.base;
4844 BUG_ON(list_empty(&o->vma_list));
4845 list_for_each_entry(vma, &o->vma_list, vma_link) {
4847 return vma->node.start;
4853 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4854 struct i915_address_space *vm)
4856 struct i915_vma *vma;
4858 list_for_each_entry(vma, &o->vma_list, vma_link)
4859 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4865 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4867 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4868 struct i915_address_space *vm;
4870 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4871 if (i915_gem_obj_bound(o, vm))
4877 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4878 struct i915_address_space *vm)
4880 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4881 struct i915_vma *vma;
4883 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4884 vm = &dev_priv->gtt.base;
4886 BUG_ON(list_empty(&o->vma_list));
4888 list_for_each_entry(vma, &o->vma_list, vma_link)
4890 return vma->node.size;
4895 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4896 struct i915_address_space *vm)
4898 struct i915_vma *vma;
4899 list_for_each_entry(vma, &obj->vma_list, vma_link)
4907 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4908 struct i915_address_space *vm)
4910 struct i915_vma *vma;
4912 vma = i915_gem_obj_to_vma(obj, vm);
4914 vma = i915_gem_vma_create(obj, vm);