2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct drm_device *dev)
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct completion *x = &dev_priv->error_completion;
97 if (!atomic_read(&dev_priv->mm.wedged))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret < 0) {
113 if (atomic_read(&dev_priv->mm.wedged)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x->wait.lock, flags);
121 spin_unlock_irqrestore(&x->wait.lock, flags);
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
130 ret = i915_gem_wait_for_error(dev);
134 ret = mutex_lock_interruptible(&dev->struct_mutex);
138 WARN_ON(i915_verify_lists(dev));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
145 return obj->gtt_space && !obj->active;
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file)
152 struct drm_i915_gem_init *args = data;
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev)->gen >= 5)
165 mutex_lock(&dev->struct_mutex);
166 i915_gem_init_global_gtt(dev, args->gtt_start,
167 args->gtt_end, args->gtt_end);
168 mutex_unlock(&dev->struct_mutex);
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175 struct drm_file *file)
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct drm_i915_gem_get_aperture *args = data;
179 struct drm_i915_gem_object *obj;
183 mutex_lock(&dev->struct_mutex);
184 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
186 pinned += obj->gtt_space->size;
187 mutex_unlock(&dev->struct_mutex);
189 args->aper_size = dev_priv->mm.gtt_total;
190 args->aper_available_size = args->aper_size - pinned;
195 void *i915_gem_object_alloc(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
201 void i915_gem_object_free(struct drm_i915_gem_object *obj)
203 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
204 kmem_cache_free(dev_priv->slab, obj);
208 i915_gem_create(struct drm_file *file,
209 struct drm_device *dev,
213 struct drm_i915_gem_object *obj;
217 size = roundup(size, PAGE_SIZE);
221 /* Allocate the new object */
222 obj = i915_gem_alloc_object(dev, size);
226 ret = drm_gem_handle_create(file, &obj->base, &handle);
228 drm_gem_object_release(&obj->base);
229 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
230 i915_gem_object_free(obj);
234 /* drop reference from allocate - handle holds it now */
235 drm_gem_object_unreference(&obj->base);
236 trace_i915_gem_object_create(obj);
243 i915_gem_dumb_create(struct drm_file *file,
244 struct drm_device *dev,
245 struct drm_mode_create_dumb *args)
247 /* have to work out size/pitch and return them */
248 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
249 args->size = args->pitch * args->height;
250 return i915_gem_create(file, dev,
251 args->size, &args->handle);
254 int i915_gem_dumb_destroy(struct drm_file *file,
255 struct drm_device *dev,
258 return drm_gem_handle_delete(file, handle);
262 * Creates a new mm object and returns a handle to it.
265 i915_gem_create_ioctl(struct drm_device *dev, void *data,
266 struct drm_file *file)
268 struct drm_i915_gem_create *args = data;
270 return i915_gem_create(file, dev,
271 args->size, &args->handle);
274 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
276 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
278 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
279 obj->tiling_mode != I915_TILING_NONE;
283 __copy_to_user_swizzled(char __user *cpu_vaddr,
284 const char *gpu_vaddr, int gpu_offset,
287 int ret, cpu_offset = 0;
290 int cacheline_end = ALIGN(gpu_offset + 1, 64);
291 int this_length = min(cacheline_end - gpu_offset, length);
292 int swizzled_gpu_offset = gpu_offset ^ 64;
294 ret = __copy_to_user(cpu_vaddr + cpu_offset,
295 gpu_vaddr + swizzled_gpu_offset,
300 cpu_offset += this_length;
301 gpu_offset += this_length;
302 length -= this_length;
309 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
310 const char __user *cpu_vaddr,
313 int ret, cpu_offset = 0;
316 int cacheline_end = ALIGN(gpu_offset + 1, 64);
317 int this_length = min(cacheline_end - gpu_offset, length);
318 int swizzled_gpu_offset = gpu_offset ^ 64;
320 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
321 cpu_vaddr + cpu_offset,
326 cpu_offset += this_length;
327 gpu_offset += this_length;
328 length -= this_length;
334 /* Per-page copy function for the shmem pread fastpath.
335 * Flushes invalid cachelines before reading the target if
336 * needs_clflush is set. */
338 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
339 char __user *user_data,
340 bool page_do_bit17_swizzling, bool needs_clflush)
345 if (unlikely(page_do_bit17_swizzling))
348 vaddr = kmap_atomic(page);
350 drm_clflush_virt_range(vaddr + shmem_page_offset,
352 ret = __copy_to_user_inatomic(user_data,
353 vaddr + shmem_page_offset,
355 kunmap_atomic(vaddr);
357 return ret ? -EFAULT : 0;
361 shmem_clflush_swizzled_range(char *addr, unsigned long length,
364 if (unlikely(swizzled)) {
365 unsigned long start = (unsigned long) addr;
366 unsigned long end = (unsigned long) addr + length;
368 /* For swizzling simply ensure that we always flush both
369 * channels. Lame, but simple and it works. Swizzled
370 * pwrite/pread is far from a hotpath - current userspace
371 * doesn't use it at all. */
372 start = round_down(start, 128);
373 end = round_up(end, 128);
375 drm_clflush_virt_range((void *)start, end - start);
377 drm_clflush_virt_range(addr, length);
382 /* Only difference to the fast-path function is that this can handle bit17
383 * and uses non-atomic copy and kmap functions. */
385 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
386 char __user *user_data,
387 bool page_do_bit17_swizzling, bool needs_clflush)
394 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
396 page_do_bit17_swizzling);
398 if (page_do_bit17_swizzling)
399 ret = __copy_to_user_swizzled(user_data,
400 vaddr, shmem_page_offset,
403 ret = __copy_to_user(user_data,
404 vaddr + shmem_page_offset,
408 return ret ? - EFAULT : 0;
412 i915_gem_shmem_pread(struct drm_device *dev,
413 struct drm_i915_gem_object *obj,
414 struct drm_i915_gem_pread *args,
415 struct drm_file *file)
417 char __user *user_data;
420 int shmem_page_offset, page_length, ret = 0;
421 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
423 int needs_clflush = 0;
424 struct scatterlist *sg;
427 user_data = (char __user *) (uintptr_t) args->data_ptr;
430 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
432 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
433 /* If we're not in the cpu read domain, set ourself into the gtt
434 * read domain and manually flush cachelines (if required). This
435 * optimizes for the case when the gpu will dirty the data
436 * anyway again before the next pread happens. */
437 if (obj->cache_level == I915_CACHE_NONE)
439 if (obj->gtt_space) {
440 ret = i915_gem_object_set_to_gtt_domain(obj, false);
446 ret = i915_gem_object_get_pages(obj);
450 i915_gem_object_pin_pages(obj);
452 offset = args->offset;
454 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
457 if (i < offset >> PAGE_SHIFT)
463 /* Operation in this page
465 * shmem_page_offset = offset within page in shmem file
466 * page_length = bytes to copy for this page
468 shmem_page_offset = offset_in_page(offset);
469 page_length = remain;
470 if ((shmem_page_offset + page_length) > PAGE_SIZE)
471 page_length = PAGE_SIZE - shmem_page_offset;
474 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
475 (page_to_phys(page) & (1 << 17)) != 0;
477 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
478 user_data, page_do_bit17_swizzling,
483 mutex_unlock(&dev->struct_mutex);
486 ret = fault_in_multipages_writeable(user_data, remain);
487 /* Userspace is tricking us, but we've already clobbered
488 * its pages with the prefault and promised to write the
489 * data up to the first fault. Hence ignore any errors
490 * and just continue. */
495 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
496 user_data, page_do_bit17_swizzling,
499 mutex_lock(&dev->struct_mutex);
502 mark_page_accessed(page);
507 remain -= page_length;
508 user_data += page_length;
509 offset += page_length;
513 i915_gem_object_unpin_pages(obj);
519 * Reads data from the object referenced by handle.
521 * On error, the contents of *data are undefined.
524 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
525 struct drm_file *file)
527 struct drm_i915_gem_pread *args = data;
528 struct drm_i915_gem_object *obj;
534 if (!access_ok(VERIFY_WRITE,
535 (char __user *)(uintptr_t)args->data_ptr,
539 ret = i915_mutex_lock_interruptible(dev);
543 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
544 if (&obj->base == NULL) {
549 /* Bounds check source. */
550 if (args->offset > obj->base.size ||
551 args->size > obj->base.size - args->offset) {
556 /* prime objects have no backing filp to GEM pread/pwrite
559 if (!obj->base.filp) {
564 trace_i915_gem_object_pread(obj, args->offset, args->size);
566 ret = i915_gem_shmem_pread(dev, obj, args, file);
569 drm_gem_object_unreference(&obj->base);
571 mutex_unlock(&dev->struct_mutex);
575 /* This is the fast write path which cannot handle
576 * page faults in the source data
580 fast_user_write(struct io_mapping *mapping,
581 loff_t page_base, int page_offset,
582 char __user *user_data,
585 void __iomem *vaddr_atomic;
587 unsigned long unwritten;
589 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
590 /* We can use the cpu mem copy function because this is X86. */
591 vaddr = (void __force*)vaddr_atomic + page_offset;
592 unwritten = __copy_from_user_inatomic_nocache(vaddr,
594 io_mapping_unmap_atomic(vaddr_atomic);
599 * This is the fast pwrite path, where we copy the data directly from the
600 * user into the GTT, uncached.
603 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
604 struct drm_i915_gem_object *obj,
605 struct drm_i915_gem_pwrite *args,
606 struct drm_file *file)
608 drm_i915_private_t *dev_priv = dev->dev_private;
610 loff_t offset, page_base;
611 char __user *user_data;
612 int page_offset, page_length, ret;
614 ret = i915_gem_object_pin(obj, 0, true, true);
618 ret = i915_gem_object_set_to_gtt_domain(obj, true);
622 ret = i915_gem_object_put_fence(obj);
626 user_data = (char __user *) (uintptr_t) args->data_ptr;
629 offset = obj->gtt_offset + args->offset;
632 /* Operation in this page
634 * page_base = page offset within aperture
635 * page_offset = offset within page
636 * page_length = bytes to copy for this page
638 page_base = offset & PAGE_MASK;
639 page_offset = offset_in_page(offset);
640 page_length = remain;
641 if ((page_offset + remain) > PAGE_SIZE)
642 page_length = PAGE_SIZE - page_offset;
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
648 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
649 page_offset, user_data, page_length)) {
654 remain -= page_length;
655 user_data += page_length;
656 offset += page_length;
660 i915_gem_object_unpin(obj);
665 /* Per-page copy function for the shmem pwrite fastpath.
666 * Flushes invalid cachelines before writing to the target if
667 * needs_clflush_before is set and flushes out any written cachelines after
668 * writing if needs_clflush is set. */
670 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
671 char __user *user_data,
672 bool page_do_bit17_swizzling,
673 bool needs_clflush_before,
674 bool needs_clflush_after)
679 if (unlikely(page_do_bit17_swizzling))
682 vaddr = kmap_atomic(page);
683 if (needs_clflush_before)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
686 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
689 if (needs_clflush_after)
690 drm_clflush_virt_range(vaddr + shmem_page_offset,
692 kunmap_atomic(vaddr);
694 return ret ? -EFAULT : 0;
697 /* Only difference to the fast-path function is that this can handle bit17
698 * and uses non-atomic copy and kmap functions. */
700 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
701 char __user *user_data,
702 bool page_do_bit17_swizzling,
703 bool needs_clflush_before,
704 bool needs_clflush_after)
710 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
711 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
713 page_do_bit17_swizzling);
714 if (page_do_bit17_swizzling)
715 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
719 ret = __copy_from_user(vaddr + shmem_page_offset,
722 if (needs_clflush_after)
723 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
725 page_do_bit17_swizzling);
728 return ret ? -EFAULT : 0;
732 i915_gem_shmem_pwrite(struct drm_device *dev,
733 struct drm_i915_gem_object *obj,
734 struct drm_i915_gem_pwrite *args,
735 struct drm_file *file)
739 char __user *user_data;
740 int shmem_page_offset, page_length, ret = 0;
741 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
742 int hit_slowpath = 0;
743 int needs_clflush_after = 0;
744 int needs_clflush_before = 0;
746 struct scatterlist *sg;
748 user_data = (char __user *) (uintptr_t) args->data_ptr;
751 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
753 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
754 /* If we're not in the cpu write domain, set ourself into the gtt
755 * write domain and manually flush cachelines (if required). This
756 * optimizes for the case when the gpu will use the data
757 * right away and we therefore have to clflush anyway. */
758 if (obj->cache_level == I915_CACHE_NONE)
759 needs_clflush_after = 1;
760 if (obj->gtt_space) {
761 ret = i915_gem_object_set_to_gtt_domain(obj, true);
766 /* Same trick applies for invalidate partially written cachelines before
768 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
769 && obj->cache_level == I915_CACHE_NONE)
770 needs_clflush_before = 1;
772 ret = i915_gem_object_get_pages(obj);
776 i915_gem_object_pin_pages(obj);
778 offset = args->offset;
781 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
783 int partial_cacheline_write;
785 if (i < offset >> PAGE_SHIFT)
791 /* Operation in this page
793 * shmem_page_offset = offset within page in shmem file
794 * page_length = bytes to copy for this page
796 shmem_page_offset = offset_in_page(offset);
798 page_length = remain;
799 if ((shmem_page_offset + page_length) > PAGE_SIZE)
800 page_length = PAGE_SIZE - shmem_page_offset;
802 /* If we don't overwrite a cacheline completely we need to be
803 * careful to have up-to-date data by first clflushing. Don't
804 * overcomplicate things and flush the entire patch. */
805 partial_cacheline_write = needs_clflush_before &&
806 ((shmem_page_offset | page_length)
807 & (boot_cpu_data.x86_clflush_size - 1));
810 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
811 (page_to_phys(page) & (1 << 17)) != 0;
813 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
814 user_data, page_do_bit17_swizzling,
815 partial_cacheline_write,
816 needs_clflush_after);
821 mutex_unlock(&dev->struct_mutex);
822 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
823 user_data, page_do_bit17_swizzling,
824 partial_cacheline_write,
825 needs_clflush_after);
827 mutex_lock(&dev->struct_mutex);
830 set_page_dirty(page);
831 mark_page_accessed(page);
836 remain -= page_length;
837 user_data += page_length;
838 offset += page_length;
842 i915_gem_object_unpin_pages(obj);
846 * Fixup: Flush cpu caches in case we didn't flush the dirty
847 * cachelines in-line while writing and the object moved
848 * out of the cpu write domain while we've dropped the lock.
850 if (!needs_clflush_after &&
851 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
852 i915_gem_clflush_object(obj);
853 i915_gem_chipset_flush(dev);
857 if (needs_clflush_after)
858 i915_gem_chipset_flush(dev);
864 * Writes data to the object referenced by handle.
866 * On error, the contents of the buffer that were to be modified are undefined.
869 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
870 struct drm_file *file)
872 struct drm_i915_gem_pwrite *args = data;
873 struct drm_i915_gem_object *obj;
879 if (!access_ok(VERIFY_READ,
880 (char __user *)(uintptr_t)args->data_ptr,
884 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
889 ret = i915_mutex_lock_interruptible(dev);
893 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
894 if (&obj->base == NULL) {
899 /* Bounds check destination. */
900 if (args->offset > obj->base.size ||
901 args->size > obj->base.size - args->offset) {
906 /* prime objects have no backing filp to GEM pread/pwrite
909 if (!obj->base.filp) {
914 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
917 /* We can only do the GTT pwrite on untiled buffers, as otherwise
918 * it would end up going through the fenced access, and we'll get
919 * different detiling behavior between reading and writing.
920 * pread/pwrite currently are reading and writing from the CPU
921 * perspective, requiring manual detiling by the client.
924 ret = i915_gem_phys_pwrite(dev, obj, args, file);
928 if (obj->cache_level == I915_CACHE_NONE &&
929 obj->tiling_mode == I915_TILING_NONE &&
930 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
931 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
932 /* Note that the gtt paths might fail with non-page-backed user
933 * pointers (e.g. gtt mappings when moving data between
934 * textures). Fallback to the shmem path in that case. */
937 if (ret == -EFAULT || ret == -ENOSPC)
938 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
941 drm_gem_object_unreference(&obj->base);
943 mutex_unlock(&dev->struct_mutex);
948 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
951 if (atomic_read(&dev_priv->mm.wedged)) {
952 struct completion *x = &dev_priv->error_completion;
953 bool recovery_complete;
956 /* Give the error handler a chance to run. */
957 spin_lock_irqsave(&x->wait.lock, flags);
958 recovery_complete = x->done > 0;
959 spin_unlock_irqrestore(&x->wait.lock, flags);
961 /* Non-interruptible callers can't handle -EAGAIN, hence return
962 * -EIO unconditionally for these. */
966 /* Recovery complete, but still wedged means reset failure. */
967 if (recovery_complete)
977 * Compare seqno against outstanding lazy request. Emit a request if they are
981 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
985 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
988 if (seqno == ring->outstanding_lazy_request)
989 ret = i915_add_request(ring, NULL, NULL);
995 * __wait_seqno - wait until execution of seqno has finished
996 * @ring: the ring expected to report seqno
998 * @interruptible: do an interruptible wait (normally yes)
999 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1001 * Returns 0 if the seqno was found within the alloted time. Else returns the
1002 * errno with remaining time filled in timeout argument.
1004 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1005 bool interruptible, struct timespec *timeout)
1007 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1008 struct timespec before, now, wait_time={1,0};
1009 unsigned long timeout_jiffies;
1011 bool wait_forever = true;
1014 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1017 trace_i915_gem_request_wait_begin(ring, seqno);
1019 if (timeout != NULL) {
1020 wait_time = *timeout;
1021 wait_forever = false;
1024 timeout_jiffies = timespec_to_jiffies(&wait_time);
1026 if (WARN_ON(!ring->irq_get(ring)))
1029 /* Record current time in case interrupted by signal, or wedged * */
1030 getrawmonotonic(&before);
1033 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1034 atomic_read(&dev_priv->mm.wedged))
1037 end = wait_event_interruptible_timeout(ring->irq_queue,
1041 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1044 ret = i915_gem_check_wedge(dev_priv, interruptible);
1047 } while (end == 0 && wait_forever);
1049 getrawmonotonic(&now);
1051 ring->irq_put(ring);
1052 trace_i915_gem_request_wait_end(ring, seqno);
1056 struct timespec sleep_time = timespec_sub(now, before);
1057 *timeout = timespec_sub(*timeout, sleep_time);
1062 case -EAGAIN: /* Wedged */
1063 case -ERESTARTSYS: /* Signal */
1065 case 0: /* Timeout */
1067 set_normalized_timespec(timeout, 0, 0);
1069 default: /* Completed */
1070 WARN_ON(end < 0); /* We're not aware of other errors */
1076 * Waits for a sequence number to be signaled, and cleans up the
1077 * request and object lists appropriately for that event.
1080 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1082 struct drm_device *dev = ring->dev;
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 bool interruptible = dev_priv->mm.interruptible;
1087 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1090 ret = i915_gem_check_wedge(dev_priv, interruptible);
1094 ret = i915_gem_check_olr(ring, seqno);
1098 return __wait_seqno(ring, seqno, interruptible, NULL);
1102 * Ensures that all rendering to the object has completed and the object is
1103 * safe to unbind from the GTT or access from the CPU.
1105 static __must_check int
1106 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1109 struct intel_ring_buffer *ring = obj->ring;
1113 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1117 ret = i915_wait_seqno(ring, seqno);
1121 i915_gem_retire_requests_ring(ring);
1123 /* Manually manage the write flush as we may have not yet
1124 * retired the buffer.
1126 if (obj->last_write_seqno &&
1127 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1128 obj->last_write_seqno = 0;
1129 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1135 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1136 * as the object state may change during this call.
1138 static __must_check int
1139 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1142 struct drm_device *dev = obj->base.dev;
1143 struct drm_i915_private *dev_priv = dev->dev_private;
1144 struct intel_ring_buffer *ring = obj->ring;
1148 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1149 BUG_ON(!dev_priv->mm.interruptible);
1151 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1155 ret = i915_gem_check_wedge(dev_priv, true);
1159 ret = i915_gem_check_olr(ring, seqno);
1163 mutex_unlock(&dev->struct_mutex);
1164 ret = __wait_seqno(ring, seqno, true, NULL);
1165 mutex_lock(&dev->struct_mutex);
1167 i915_gem_retire_requests_ring(ring);
1169 /* Manually manage the write flush as we may have not yet
1170 * retired the buffer.
1172 if (obj->last_write_seqno &&
1173 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1174 obj->last_write_seqno = 0;
1175 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1182 * Called when user space prepares to use an object with the CPU, either
1183 * through the mmap ioctl's mapping or a GTT mapping.
1186 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1187 struct drm_file *file)
1189 struct drm_i915_gem_set_domain *args = data;
1190 struct drm_i915_gem_object *obj;
1191 uint32_t read_domains = args->read_domains;
1192 uint32_t write_domain = args->write_domain;
1195 /* Only handle setting domains to types used by the CPU. */
1196 if (write_domain & I915_GEM_GPU_DOMAINS)
1199 if (read_domains & I915_GEM_GPU_DOMAINS)
1202 /* Having something in the write domain implies it's in the read
1203 * domain, and only that read domain. Enforce that in the request.
1205 if (write_domain != 0 && read_domains != write_domain)
1208 ret = i915_mutex_lock_interruptible(dev);
1212 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1213 if (&obj->base == NULL) {
1218 /* Try to flush the object off the GPU without holding the lock.
1219 * We will repeat the flush holding the lock in the normal manner
1220 * to catch cases where we are gazumped.
1222 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1226 if (read_domains & I915_GEM_DOMAIN_GTT) {
1227 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1229 /* Silently promote "you're not bound, there was nothing to do"
1230 * to success, since the client was just asking us to
1231 * make sure everything was done.
1236 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1240 drm_gem_object_unreference(&obj->base);
1242 mutex_unlock(&dev->struct_mutex);
1247 * Called when user space has done writes to this buffer
1250 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1251 struct drm_file *file)
1253 struct drm_i915_gem_sw_finish *args = data;
1254 struct drm_i915_gem_object *obj;
1257 ret = i915_mutex_lock_interruptible(dev);
1261 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1262 if (&obj->base == NULL) {
1267 /* Pinned buffers may be scanout, so flush the cache */
1269 i915_gem_object_flush_cpu_write_domain(obj);
1271 drm_gem_object_unreference(&obj->base);
1273 mutex_unlock(&dev->struct_mutex);
1278 * Maps the contents of an object, returning the address it is mapped
1281 * While the mapping holds a reference on the contents of the object, it doesn't
1282 * imply a ref on the object itself.
1285 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1286 struct drm_file *file)
1288 struct drm_i915_gem_mmap *args = data;
1289 struct drm_gem_object *obj;
1292 obj = drm_gem_object_lookup(dev, file, args->handle);
1296 /* prime objects have no backing filp to GEM mmap
1300 drm_gem_object_unreference_unlocked(obj);
1304 addr = vm_mmap(obj->filp, 0, args->size,
1305 PROT_READ | PROT_WRITE, MAP_SHARED,
1307 drm_gem_object_unreference_unlocked(obj);
1308 if (IS_ERR((void *)addr))
1311 args->addr_ptr = (uint64_t) addr;
1317 * i915_gem_fault - fault a page into the GTT
1318 * vma: VMA in question
1321 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1322 * from userspace. The fault handler takes care of binding the object to
1323 * the GTT (if needed), allocating and programming a fence register (again,
1324 * only if needed based on whether the old reg is still valid or the object
1325 * is tiled) and inserting a new PTE into the faulting process.
1327 * Note that the faulting process may involve evicting existing objects
1328 * from the GTT and/or fence registers to make room. So performance may
1329 * suffer if the GTT working set is large or there are few fence registers
1332 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1334 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1335 struct drm_device *dev = obj->base.dev;
1336 drm_i915_private_t *dev_priv = dev->dev_private;
1337 pgoff_t page_offset;
1340 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1342 /* We don't use vmf->pgoff since that has the fake offset */
1343 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1346 ret = i915_mutex_lock_interruptible(dev);
1350 trace_i915_gem_object_fault(obj, page_offset, true, write);
1352 /* Now bind it into the GTT if needed */
1353 ret = i915_gem_object_pin(obj, 0, true, false);
1357 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1361 ret = i915_gem_object_get_fence(obj);
1365 obj->fault_mappable = true;
1367 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1370 /* Finally, remap it using the new GTT offset */
1371 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1373 i915_gem_object_unpin(obj);
1375 mutex_unlock(&dev->struct_mutex);
1379 /* If this -EIO is due to a gpu hang, give the reset code a
1380 * chance to clean up the mess. Otherwise return the proper
1382 if (!atomic_read(&dev_priv->mm.wedged))
1383 return VM_FAULT_SIGBUS;
1385 /* Give the error handler a chance to run and move the
1386 * objects off the GPU active list. Next time we service the
1387 * fault, we should be able to transition the page into the
1388 * GTT without touching the GPU (and so avoid further
1389 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1390 * with coherency, just lost writes.
1398 * EBUSY is ok: this just means that another thread
1399 * already did the job.
1401 return VM_FAULT_NOPAGE;
1403 return VM_FAULT_OOM;
1405 return VM_FAULT_SIGBUS;
1407 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1408 return VM_FAULT_SIGBUS;
1413 * i915_gem_release_mmap - remove physical page mappings
1414 * @obj: obj in question
1416 * Preserve the reservation of the mmapping with the DRM core code, but
1417 * relinquish ownership of the pages back to the system.
1419 * It is vital that we remove the page mapping if we have mapped a tiled
1420 * object through the GTT and then lose the fence register due to
1421 * resource pressure. Similarly if the object has been moved out of the
1422 * aperture, than pages mapped into userspace must be revoked. Removing the
1423 * mapping will then trigger a page fault on the next user access, allowing
1424 * fixup by i915_gem_fault().
1427 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1429 if (!obj->fault_mappable)
1432 if (obj->base.dev->dev_mapping)
1433 unmap_mapping_range(obj->base.dev->dev_mapping,
1434 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1437 obj->fault_mappable = false;
1441 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1445 if (INTEL_INFO(dev)->gen >= 4 ||
1446 tiling_mode == I915_TILING_NONE)
1449 /* Previous chips need a power-of-two fence region when tiling */
1450 if (INTEL_INFO(dev)->gen == 3)
1451 gtt_size = 1024*1024;
1453 gtt_size = 512*1024;
1455 while (gtt_size < size)
1462 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1463 * @obj: object to check
1465 * Return the required GTT alignment for an object, taking into account
1466 * potential fence register mapping.
1469 i915_gem_get_gtt_alignment(struct drm_device *dev,
1474 * Minimum alignment is 4k (GTT page size), but might be greater
1475 * if a fence register is needed for the object.
1477 if (INTEL_INFO(dev)->gen >= 4 ||
1478 tiling_mode == I915_TILING_NONE)
1482 * Previous chips need to be aligned to the size of the smallest
1483 * fence register that can contain the object.
1485 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1489 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1492 * @size: size of the object
1493 * @tiling_mode: tiling mode of the object
1495 * Return the required GTT alignment for an object, only taking into account
1496 * unfenced tiled surface requirements.
1499 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1504 * Minimum alignment is 4k (GTT page size) for sane hw.
1506 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1507 tiling_mode == I915_TILING_NONE)
1510 /* Previous hardware however needs to be aligned to a power-of-two
1511 * tile height. The simplest method for determining this is to reuse
1512 * the power-of-tile object size.
1514 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1517 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1519 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1522 if (obj->base.map_list.map)
1525 ret = drm_gem_create_mmap_offset(&obj->base);
1529 /* Badly fragmented mmap space? The only way we can recover
1530 * space is by destroying unwanted objects. We can't randomly release
1531 * mmap_offsets as userspace expects them to be persistent for the
1532 * lifetime of the objects. The closest we can is to release the
1533 * offsets on purgeable objects by truncating it and marking it purged,
1534 * which prevents userspace from ever using that object again.
1536 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1537 ret = drm_gem_create_mmap_offset(&obj->base);
1541 i915_gem_shrink_all(dev_priv);
1542 return drm_gem_create_mmap_offset(&obj->base);
1545 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1547 if (!obj->base.map_list.map)
1550 drm_gem_free_mmap_offset(&obj->base);
1554 i915_gem_mmap_gtt(struct drm_file *file,
1555 struct drm_device *dev,
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 struct drm_i915_gem_object *obj;
1563 ret = i915_mutex_lock_interruptible(dev);
1567 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1568 if (&obj->base == NULL) {
1573 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1578 if (obj->madv != I915_MADV_WILLNEED) {
1579 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1584 ret = i915_gem_object_create_mmap_offset(obj);
1588 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1591 drm_gem_object_unreference(&obj->base);
1593 mutex_unlock(&dev->struct_mutex);
1598 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1600 * @data: GTT mapping ioctl data
1601 * @file: GEM object info
1603 * Simply returns the fake offset to userspace so it can mmap it.
1604 * The mmap call will end up in drm_gem_mmap(), which will set things
1605 * up so we can get faults in the handler above.
1607 * The fault handler will take care of binding the object into the GTT
1608 * (since it may have been evicted to make room for something), allocating
1609 * a fence register, and mapping the appropriate aperture address into
1613 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1614 struct drm_file *file)
1616 struct drm_i915_gem_mmap_gtt *args = data;
1618 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1621 /* Immediately discard the backing storage */
1623 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1625 struct inode *inode;
1627 i915_gem_object_free_mmap_offset(obj);
1629 if (obj->base.filp == NULL)
1632 /* Our goal here is to return as much of the memory as
1633 * is possible back to the system as we are called from OOM.
1634 * To do this we must instruct the shmfs to drop all of its
1635 * backing pages, *now*.
1637 inode = obj->base.filp->f_path.dentry->d_inode;
1638 shmem_truncate_range(inode, 0, (loff_t)-1);
1640 obj->madv = __I915_MADV_PURGED;
1644 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1646 return obj->madv == I915_MADV_DONTNEED;
1650 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1652 int page_count = obj->base.size / PAGE_SIZE;
1653 struct scatterlist *sg;
1656 BUG_ON(obj->madv == __I915_MADV_PURGED);
1658 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1660 /* In the event of a disaster, abandon all caches and
1661 * hope for the best.
1663 WARN_ON(ret != -EIO);
1664 i915_gem_clflush_object(obj);
1665 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1668 if (i915_gem_object_needs_bit17_swizzle(obj))
1669 i915_gem_object_save_bit_17_swizzle(obj);
1671 if (obj->madv == I915_MADV_DONTNEED)
1674 for_each_sg(obj->pages->sgl, sg, page_count, i) {
1675 struct page *page = sg_page(sg);
1678 set_page_dirty(page);
1680 if (obj->madv == I915_MADV_WILLNEED)
1681 mark_page_accessed(page);
1683 page_cache_release(page);
1687 sg_free_table(obj->pages);
1692 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1694 const struct drm_i915_gem_object_ops *ops = obj->ops;
1696 if (obj->pages == NULL)
1699 BUG_ON(obj->gtt_space);
1701 if (obj->pages_pin_count)
1704 ops->put_pages(obj);
1707 list_del(&obj->gtt_list);
1708 if (i915_gem_object_is_purgeable(obj))
1709 i915_gem_object_truncate(obj);
1715 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1717 struct drm_i915_gem_object *obj, *next;
1720 list_for_each_entry_safe(obj, next,
1721 &dev_priv->mm.unbound_list,
1723 if (i915_gem_object_is_purgeable(obj) &&
1724 i915_gem_object_put_pages(obj) == 0) {
1725 count += obj->base.size >> PAGE_SHIFT;
1726 if (count >= target)
1731 list_for_each_entry_safe(obj, next,
1732 &dev_priv->mm.inactive_list,
1734 if (i915_gem_object_is_purgeable(obj) &&
1735 i915_gem_object_unbind(obj) == 0 &&
1736 i915_gem_object_put_pages(obj) == 0) {
1737 count += obj->base.size >> PAGE_SHIFT;
1738 if (count >= target)
1747 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1749 struct drm_i915_gem_object *obj, *next;
1751 i915_gem_evict_everything(dev_priv->dev);
1753 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1754 i915_gem_object_put_pages(obj);
1758 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1760 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1762 struct address_space *mapping;
1763 struct sg_table *st;
1764 struct scatterlist *sg;
1768 /* Assert that the object is not currently in any GPU domain. As it
1769 * wasn't in the GTT, there shouldn't be any way it could have been in
1772 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1773 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1775 st = kmalloc(sizeof(*st), GFP_KERNEL);
1779 page_count = obj->base.size / PAGE_SIZE;
1780 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1786 /* Get the list of pages out of our struct file. They'll be pinned
1787 * at this point until we release them.
1789 * Fail silently without starting the shrinker
1791 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1792 gfp = mapping_gfp_mask(mapping);
1793 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1794 gfp &= ~(__GFP_IO | __GFP_WAIT);
1795 for_each_sg(st->sgl, sg, page_count, i) {
1796 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1798 i915_gem_purge(dev_priv, page_count);
1799 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1802 /* We've tried hard to allocate the memory by reaping
1803 * our own buffer, now let the real VM do its job and
1804 * go down in flames if truly OOM.
1806 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1807 gfp |= __GFP_IO | __GFP_WAIT;
1809 i915_gem_shrink_all(dev_priv);
1810 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1814 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1815 gfp &= ~(__GFP_IO | __GFP_WAIT);
1818 sg_set_page(sg, page, PAGE_SIZE, 0);
1823 if (i915_gem_object_needs_bit17_swizzle(obj))
1824 i915_gem_object_do_bit_17_swizzle(obj);
1829 for_each_sg(st->sgl, sg, i, page_count)
1830 page_cache_release(sg_page(sg));
1833 return PTR_ERR(page);
1836 /* Ensure that the associated pages are gathered from the backing storage
1837 * and pinned into our object. i915_gem_object_get_pages() may be called
1838 * multiple times before they are released by a single call to
1839 * i915_gem_object_put_pages() - once the pages are no longer referenced
1840 * either as a result of memory pressure (reaping pages under the shrinker)
1841 * or as the object is itself released.
1844 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1846 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1847 const struct drm_i915_gem_object_ops *ops = obj->ops;
1853 BUG_ON(obj->pages_pin_count);
1855 ret = ops->get_pages(obj);
1859 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1864 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1865 struct intel_ring_buffer *ring)
1867 struct drm_device *dev = obj->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 u32 seqno = intel_ring_get_seqno(ring);
1871 BUG_ON(ring == NULL);
1874 /* Add a reference if we're newly entering the active list. */
1876 drm_gem_object_reference(&obj->base);
1880 /* Move from whatever list we were on to the tail of execution. */
1881 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1882 list_move_tail(&obj->ring_list, &ring->active_list);
1884 obj->last_read_seqno = seqno;
1886 if (obj->fenced_gpu_access) {
1887 obj->last_fenced_seqno = seqno;
1889 /* Bump MRU to take account of the delayed flush */
1890 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1891 struct drm_i915_fence_reg *reg;
1893 reg = &dev_priv->fence_regs[obj->fence_reg];
1894 list_move_tail(®->lru_list,
1895 &dev_priv->mm.fence_list);
1901 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1903 struct drm_device *dev = obj->base.dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1906 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1907 BUG_ON(!obj->active);
1909 if (obj->pin_count) /* are we a framebuffer? */
1910 intel_mark_fb_idle(obj);
1912 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1914 list_del_init(&obj->ring_list);
1917 obj->last_read_seqno = 0;
1918 obj->last_write_seqno = 0;
1919 obj->base.write_domain = 0;
1921 obj->last_fenced_seqno = 0;
1922 obj->fenced_gpu_access = false;
1925 drm_gem_object_unreference(&obj->base);
1927 WARN_ON(i915_verify_lists(dev));
1931 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1934 struct intel_ring_buffer *ring;
1937 /* The hardware uses various monotonic 32-bit counters, if we
1938 * detect that they will wraparound we need to idle the GPU
1939 * and reset those counters.
1942 for_each_ring(ring, dev_priv, i) {
1943 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1944 ret |= ring->sync_seqno[j] != 0;
1949 ret = i915_gpu_idle(dev);
1953 i915_gem_retire_requests(dev);
1954 for_each_ring(ring, dev_priv, i) {
1955 ret = intel_ring_handle_seqno_wrap(ring);
1959 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1960 ring->sync_seqno[j] = 0;
1967 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1969 struct drm_i915_private *dev_priv = dev->dev_private;
1971 /* reserve 0 for non-seqno */
1972 if (dev_priv->next_seqno == 0) {
1973 int ret = i915_gem_handle_seqno_wrap(dev);
1977 dev_priv->next_seqno = 1;
1980 *seqno = dev_priv->next_seqno++;
1985 i915_add_request(struct intel_ring_buffer *ring,
1986 struct drm_file *file,
1989 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1990 struct drm_i915_gem_request *request;
1991 u32 request_ring_position;
1996 * Emit any outstanding flushes - execbuf can fail to emit the flush
1997 * after having emitted the batchbuffer command. Hence we need to fix
1998 * things up similar to emitting the lazy request. The difference here
1999 * is that the flush _must_ happen before the next request, no matter
2002 ret = intel_ring_flush_all_caches(ring);
2006 request = kmalloc(sizeof(*request), GFP_KERNEL);
2007 if (request == NULL)
2011 /* Record the position of the start of the request so that
2012 * should we detect the updated seqno part-way through the
2013 * GPU processing the request, we never over-estimate the
2014 * position of the head.
2016 request_ring_position = intel_ring_get_tail(ring);
2018 ret = ring->add_request(ring);
2024 request->seqno = intel_ring_get_seqno(ring);
2025 request->ring = ring;
2026 request->tail = request_ring_position;
2027 request->emitted_jiffies = jiffies;
2028 was_empty = list_empty(&ring->request_list);
2029 list_add_tail(&request->list, &ring->request_list);
2030 request->file_priv = NULL;
2033 struct drm_i915_file_private *file_priv = file->driver_priv;
2035 spin_lock(&file_priv->mm.lock);
2036 request->file_priv = file_priv;
2037 list_add_tail(&request->client_list,
2038 &file_priv->mm.request_list);
2039 spin_unlock(&file_priv->mm.lock);
2042 trace_i915_gem_request_add(ring, request->seqno);
2043 ring->outstanding_lazy_request = 0;
2045 if (!dev_priv->mm.suspended) {
2046 if (i915_enable_hangcheck) {
2047 mod_timer(&dev_priv->hangcheck_timer,
2048 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2051 queue_delayed_work(dev_priv->wq,
2052 &dev_priv->mm.retire_work,
2053 round_jiffies_up_relative(HZ));
2054 intel_mark_busy(dev_priv->dev);
2059 *out_seqno = request->seqno;
2064 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2066 struct drm_i915_file_private *file_priv = request->file_priv;
2071 spin_lock(&file_priv->mm.lock);
2072 if (request->file_priv) {
2073 list_del(&request->client_list);
2074 request->file_priv = NULL;
2076 spin_unlock(&file_priv->mm.lock);
2079 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2080 struct intel_ring_buffer *ring)
2082 while (!list_empty(&ring->request_list)) {
2083 struct drm_i915_gem_request *request;
2085 request = list_first_entry(&ring->request_list,
2086 struct drm_i915_gem_request,
2089 list_del(&request->list);
2090 i915_gem_request_remove_from_client(request);
2094 while (!list_empty(&ring->active_list)) {
2095 struct drm_i915_gem_object *obj;
2097 obj = list_first_entry(&ring->active_list,
2098 struct drm_i915_gem_object,
2101 i915_gem_object_move_to_inactive(obj);
2105 static void i915_gem_reset_fences(struct drm_device *dev)
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2110 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2111 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2113 i915_gem_write_fence(dev, i, NULL);
2116 i915_gem_object_fence_lost(reg->obj);
2120 INIT_LIST_HEAD(®->lru_list);
2123 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2126 void i915_gem_reset(struct drm_device *dev)
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct drm_i915_gem_object *obj;
2130 struct intel_ring_buffer *ring;
2133 for_each_ring(ring, dev_priv, i)
2134 i915_gem_reset_ring_lists(dev_priv, ring);
2136 /* Move everything out of the GPU domains to ensure we do any
2137 * necessary invalidation upon reuse.
2139 list_for_each_entry(obj,
2140 &dev_priv->mm.inactive_list,
2143 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2146 /* The fence registers are invalidated so clear them out */
2147 i915_gem_reset_fences(dev);
2151 * This function clears the request list as sequence numbers are passed.
2154 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2158 if (list_empty(&ring->request_list))
2161 WARN_ON(i915_verify_lists(ring->dev));
2163 seqno = ring->get_seqno(ring, true);
2165 while (!list_empty(&ring->request_list)) {
2166 struct drm_i915_gem_request *request;
2168 request = list_first_entry(&ring->request_list,
2169 struct drm_i915_gem_request,
2172 if (!i915_seqno_passed(seqno, request->seqno))
2175 trace_i915_gem_request_retire(ring, request->seqno);
2176 /* We know the GPU must have read the request to have
2177 * sent us the seqno + interrupt, so use the position
2178 * of tail of the request to update the last known position
2181 ring->last_retired_head = request->tail;
2183 list_del(&request->list);
2184 i915_gem_request_remove_from_client(request);
2188 /* Move any buffers on the active list that are no longer referenced
2189 * by the ringbuffer to the flushing/inactive lists as appropriate.
2191 while (!list_empty(&ring->active_list)) {
2192 struct drm_i915_gem_object *obj;
2194 obj = list_first_entry(&ring->active_list,
2195 struct drm_i915_gem_object,
2198 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2201 i915_gem_object_move_to_inactive(obj);
2204 if (unlikely(ring->trace_irq_seqno &&
2205 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2206 ring->irq_put(ring);
2207 ring->trace_irq_seqno = 0;
2210 WARN_ON(i915_verify_lists(ring->dev));
2214 i915_gem_retire_requests(struct drm_device *dev)
2216 drm_i915_private_t *dev_priv = dev->dev_private;
2217 struct intel_ring_buffer *ring;
2220 for_each_ring(ring, dev_priv, i)
2221 i915_gem_retire_requests_ring(ring);
2225 i915_gem_retire_work_handler(struct work_struct *work)
2227 drm_i915_private_t *dev_priv;
2228 struct drm_device *dev;
2229 struct intel_ring_buffer *ring;
2233 dev_priv = container_of(work, drm_i915_private_t,
2234 mm.retire_work.work);
2235 dev = dev_priv->dev;
2237 /* Come back later if the device is busy... */
2238 if (!mutex_trylock(&dev->struct_mutex)) {
2239 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2240 round_jiffies_up_relative(HZ));
2244 i915_gem_retire_requests(dev);
2246 /* Send a periodic flush down the ring so we don't hold onto GEM
2247 * objects indefinitely.
2250 for_each_ring(ring, dev_priv, i) {
2251 if (ring->gpu_caches_dirty)
2252 i915_add_request(ring, NULL, NULL);
2254 idle &= list_empty(&ring->request_list);
2257 if (!dev_priv->mm.suspended && !idle)
2258 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2259 round_jiffies_up_relative(HZ));
2261 intel_mark_idle(dev);
2263 mutex_unlock(&dev->struct_mutex);
2267 * Ensures that an object will eventually get non-busy by flushing any required
2268 * write domains, emitting any outstanding lazy request and retiring and
2269 * completed requests.
2272 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2277 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2281 i915_gem_retire_requests_ring(obj->ring);
2288 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2289 * @DRM_IOCTL_ARGS: standard ioctl arguments
2291 * Returns 0 if successful, else an error is returned with the remaining time in
2292 * the timeout parameter.
2293 * -ETIME: object is still busy after timeout
2294 * -ERESTARTSYS: signal interrupted the wait
2295 * -ENONENT: object doesn't exist
2296 * Also possible, but rare:
2297 * -EAGAIN: GPU wedged
2299 * -ENODEV: Internal IRQ fail
2300 * -E?: The add request failed
2302 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2303 * non-zero timeout parameter the wait ioctl will wait for the given number of
2304 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2305 * without holding struct_mutex the object may become re-busied before this
2306 * function completes. A similar but shorter * race condition exists in the busy
2310 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2312 struct drm_i915_gem_wait *args = data;
2313 struct drm_i915_gem_object *obj;
2314 struct intel_ring_buffer *ring = NULL;
2315 struct timespec timeout_stack, *timeout = NULL;
2319 if (args->timeout_ns >= 0) {
2320 timeout_stack = ns_to_timespec(args->timeout_ns);
2321 timeout = &timeout_stack;
2324 ret = i915_mutex_lock_interruptible(dev);
2328 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2329 if (&obj->base == NULL) {
2330 mutex_unlock(&dev->struct_mutex);
2334 /* Need to make sure the object gets inactive eventually. */
2335 ret = i915_gem_object_flush_active(obj);
2340 seqno = obj->last_read_seqno;
2347 /* Do this after OLR check to make sure we make forward progress polling
2348 * on this IOCTL with a 0 timeout (like busy ioctl)
2350 if (!args->timeout_ns) {
2355 drm_gem_object_unreference(&obj->base);
2356 mutex_unlock(&dev->struct_mutex);
2358 ret = __wait_seqno(ring, seqno, true, timeout);
2360 WARN_ON(!timespec_valid(timeout));
2361 args->timeout_ns = timespec_to_ns(timeout);
2366 drm_gem_object_unreference(&obj->base);
2367 mutex_unlock(&dev->struct_mutex);
2372 * i915_gem_object_sync - sync an object to a ring.
2374 * @obj: object which may be in use on another ring.
2375 * @to: ring we wish to use the object on. May be NULL.
2377 * This code is meant to abstract object synchronization with the GPU.
2378 * Calling with NULL implies synchronizing the object with the CPU
2379 * rather than a particular GPU ring.
2381 * Returns 0 if successful, else propagates up the lower layer error.
2384 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2385 struct intel_ring_buffer *to)
2387 struct intel_ring_buffer *from = obj->ring;
2391 if (from == NULL || to == from)
2394 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2395 return i915_gem_object_wait_rendering(obj, false);
2397 idx = intel_ring_sync_index(from, to);
2399 seqno = obj->last_read_seqno;
2400 if (seqno <= from->sync_seqno[idx])
2403 ret = i915_gem_check_olr(obj->ring, seqno);
2407 ret = to->sync_to(to, from, seqno);
2409 /* We use last_read_seqno because sync_to()
2410 * might have just caused seqno wrap under
2413 from->sync_seqno[idx] = obj->last_read_seqno;
2418 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2420 u32 old_write_domain, old_read_domains;
2422 /* Act a barrier for all accesses through the GTT */
2425 /* Force a pagefault for domain tracking on next user access */
2426 i915_gem_release_mmap(obj);
2428 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2431 old_read_domains = obj->base.read_domains;
2432 old_write_domain = obj->base.write_domain;
2434 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2435 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2437 trace_i915_gem_object_change_domain(obj,
2443 * Unbinds an object from the GTT aperture.
2446 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2448 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2451 if (obj->gtt_space == NULL)
2457 BUG_ON(obj->pages == NULL);
2459 ret = i915_gem_object_finish_gpu(obj);
2462 /* Continue on if we fail due to EIO, the GPU is hung so we
2463 * should be safe and we need to cleanup or else we might
2464 * cause memory corruption through use-after-free.
2467 i915_gem_object_finish_gtt(obj);
2469 /* release the fence reg _after_ flushing */
2470 ret = i915_gem_object_put_fence(obj);
2474 trace_i915_gem_object_unbind(obj);
2476 if (obj->has_global_gtt_mapping)
2477 i915_gem_gtt_unbind_object(obj);
2478 if (obj->has_aliasing_ppgtt_mapping) {
2479 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2480 obj->has_aliasing_ppgtt_mapping = 0;
2482 i915_gem_gtt_finish_object(obj);
2484 list_del(&obj->mm_list);
2485 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2486 /* Avoid an unnecessary call to unbind on rebind. */
2487 obj->map_and_fenceable = true;
2489 drm_mm_put_block(obj->gtt_space);
2490 obj->gtt_space = NULL;
2491 obj->gtt_offset = 0;
2496 int i915_gpu_idle(struct drm_device *dev)
2498 drm_i915_private_t *dev_priv = dev->dev_private;
2499 struct intel_ring_buffer *ring;
2502 /* Flush everything onto the inactive list. */
2503 for_each_ring(ring, dev_priv, i) {
2504 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2508 ret = intel_ring_idle(ring);
2516 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2517 struct drm_i915_gem_object *obj)
2519 drm_i915_private_t *dev_priv = dev->dev_private;
2523 u32 size = obj->gtt_space->size;
2525 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2527 val |= obj->gtt_offset & 0xfffff000;
2528 val |= (uint64_t)((obj->stride / 128) - 1) <<
2529 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2531 if (obj->tiling_mode == I915_TILING_Y)
2532 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2533 val |= I965_FENCE_REG_VALID;
2537 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2538 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2541 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2542 struct drm_i915_gem_object *obj)
2544 drm_i915_private_t *dev_priv = dev->dev_private;
2548 u32 size = obj->gtt_space->size;
2550 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2552 val |= obj->gtt_offset & 0xfffff000;
2553 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2554 if (obj->tiling_mode == I915_TILING_Y)
2555 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2556 val |= I965_FENCE_REG_VALID;
2560 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2561 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2564 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2565 struct drm_i915_gem_object *obj)
2567 drm_i915_private_t *dev_priv = dev->dev_private;
2571 u32 size = obj->gtt_space->size;
2575 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2576 (size & -size) != size ||
2577 (obj->gtt_offset & (size - 1)),
2578 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2579 obj->gtt_offset, obj->map_and_fenceable, size);
2581 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2586 /* Note: pitch better be a power of two tile widths */
2587 pitch_val = obj->stride / tile_width;
2588 pitch_val = ffs(pitch_val) - 1;
2590 val = obj->gtt_offset;
2591 if (obj->tiling_mode == I915_TILING_Y)
2592 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2593 val |= I915_FENCE_SIZE_BITS(size);
2594 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2595 val |= I830_FENCE_REG_VALID;
2600 reg = FENCE_REG_830_0 + reg * 4;
2602 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2604 I915_WRITE(reg, val);
2608 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2609 struct drm_i915_gem_object *obj)
2611 drm_i915_private_t *dev_priv = dev->dev_private;
2615 u32 size = obj->gtt_space->size;
2618 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2619 (size & -size) != size ||
2620 (obj->gtt_offset & (size - 1)),
2621 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2622 obj->gtt_offset, size);
2624 pitch_val = obj->stride / 128;
2625 pitch_val = ffs(pitch_val) - 1;
2627 val = obj->gtt_offset;
2628 if (obj->tiling_mode == I915_TILING_Y)
2629 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2630 val |= I830_FENCE_SIZE_BITS(size);
2631 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2632 val |= I830_FENCE_REG_VALID;
2636 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2637 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2640 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2641 struct drm_i915_gem_object *obj)
2643 switch (INTEL_INFO(dev)->gen) {
2645 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2647 case 4: i965_write_fence_reg(dev, reg, obj); break;
2648 case 3: i915_write_fence_reg(dev, reg, obj); break;
2649 case 2: i830_write_fence_reg(dev, reg, obj); break;
2654 static inline int fence_number(struct drm_i915_private *dev_priv,
2655 struct drm_i915_fence_reg *fence)
2657 return fence - dev_priv->fence_regs;
2660 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2661 struct drm_i915_fence_reg *fence,
2664 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2665 int reg = fence_number(dev_priv, fence);
2667 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2670 obj->fence_reg = reg;
2672 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2674 obj->fence_reg = I915_FENCE_REG_NONE;
2676 list_del_init(&fence->lru_list);
2681 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2683 if (obj->last_fenced_seqno) {
2684 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2688 obj->last_fenced_seqno = 0;
2691 /* Ensure that all CPU reads are completed before installing a fence
2692 * and all writes before removing the fence.
2694 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2697 obj->fenced_gpu_access = false;
2702 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2704 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2707 ret = i915_gem_object_flush_fence(obj);
2711 if (obj->fence_reg == I915_FENCE_REG_NONE)
2714 i915_gem_object_update_fence(obj,
2715 &dev_priv->fence_regs[obj->fence_reg],
2717 i915_gem_object_fence_lost(obj);
2722 static struct drm_i915_fence_reg *
2723 i915_find_fence_reg(struct drm_device *dev)
2725 struct drm_i915_private *dev_priv = dev->dev_private;
2726 struct drm_i915_fence_reg *reg, *avail;
2729 /* First try to find a free reg */
2731 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2732 reg = &dev_priv->fence_regs[i];
2736 if (!reg->pin_count)
2743 /* None available, try to steal one or wait for a user to finish */
2744 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2755 * i915_gem_object_get_fence - set up fencing for an object
2756 * @obj: object to map through a fence reg
2758 * When mapping objects through the GTT, userspace wants to be able to write
2759 * to them without having to worry about swizzling if the object is tiled.
2760 * This function walks the fence regs looking for a free one for @obj,
2761 * stealing one if it can't find any.
2763 * It then sets up the reg based on the object's properties: address, pitch
2764 * and tiling format.
2766 * For an untiled surface, this removes any existing fence.
2769 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2771 struct drm_device *dev = obj->base.dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 bool enable = obj->tiling_mode != I915_TILING_NONE;
2774 struct drm_i915_fence_reg *reg;
2777 /* Have we updated the tiling parameters upon the object and so
2778 * will need to serialise the write to the associated fence register?
2780 if (obj->fence_dirty) {
2781 ret = i915_gem_object_flush_fence(obj);
2786 /* Just update our place in the LRU if our fence is getting reused. */
2787 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2788 reg = &dev_priv->fence_regs[obj->fence_reg];
2789 if (!obj->fence_dirty) {
2790 list_move_tail(®->lru_list,
2791 &dev_priv->mm.fence_list);
2794 } else if (enable) {
2795 reg = i915_find_fence_reg(dev);
2800 struct drm_i915_gem_object *old = reg->obj;
2802 ret = i915_gem_object_flush_fence(old);
2806 i915_gem_object_fence_lost(old);
2811 i915_gem_object_update_fence(obj, reg, enable);
2812 obj->fence_dirty = false;
2817 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2818 struct drm_mm_node *gtt_space,
2819 unsigned long cache_level)
2821 struct drm_mm_node *other;
2823 /* On non-LLC machines we have to be careful when putting differing
2824 * types of snoopable memory together to avoid the prefetcher
2825 * crossing memory domains and dying.
2830 if (gtt_space == NULL)
2833 if (list_empty(>t_space->node_list))
2836 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2837 if (other->allocated && !other->hole_follows && other->color != cache_level)
2840 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2841 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2847 static void i915_gem_verify_gtt(struct drm_device *dev)
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 struct drm_i915_gem_object *obj;
2854 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2855 if (obj->gtt_space == NULL) {
2856 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2861 if (obj->cache_level != obj->gtt_space->color) {
2862 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2863 obj->gtt_space->start,
2864 obj->gtt_space->start + obj->gtt_space->size,
2866 obj->gtt_space->color);
2871 if (!i915_gem_valid_gtt_space(dev,
2873 obj->cache_level)) {
2874 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2875 obj->gtt_space->start,
2876 obj->gtt_space->start + obj->gtt_space->size,
2888 * Finds free space in the GTT aperture and binds the object there.
2891 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2893 bool map_and_fenceable,
2896 struct drm_device *dev = obj->base.dev;
2897 drm_i915_private_t *dev_priv = dev->dev_private;
2898 struct drm_mm_node *free_space;
2899 u32 size, fence_size, fence_alignment, unfenced_alignment;
2900 bool mappable, fenceable;
2903 if (obj->madv != I915_MADV_WILLNEED) {
2904 DRM_ERROR("Attempting to bind a purgeable object\n");
2908 fence_size = i915_gem_get_gtt_size(dev,
2911 fence_alignment = i915_gem_get_gtt_alignment(dev,
2914 unfenced_alignment =
2915 i915_gem_get_unfenced_gtt_alignment(dev,
2920 alignment = map_and_fenceable ? fence_alignment :
2922 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2923 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2927 size = map_and_fenceable ? fence_size : obj->base.size;
2929 /* If the object is bigger than the entire aperture, reject it early
2930 * before evicting everything in a vain attempt to find space.
2932 if (obj->base.size >
2933 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2934 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2938 ret = i915_gem_object_get_pages(obj);
2942 i915_gem_object_pin_pages(obj);
2945 if (map_and_fenceable)
2946 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2947 size, alignment, obj->cache_level,
2948 0, dev_priv->mm.gtt_mappable_end,
2951 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2952 size, alignment, obj->cache_level,
2955 if (free_space != NULL) {
2956 if (map_and_fenceable)
2958 drm_mm_get_block_range_generic(free_space,
2959 size, alignment, obj->cache_level,
2960 0, dev_priv->mm.gtt_mappable_end,
2964 drm_mm_get_block_generic(free_space,
2965 size, alignment, obj->cache_level,
2968 if (free_space == NULL) {
2969 ret = i915_gem_evict_something(dev, size, alignment,
2974 i915_gem_object_unpin_pages(obj);
2980 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2982 obj->cache_level))) {
2983 i915_gem_object_unpin_pages(obj);
2984 drm_mm_put_block(free_space);
2988 ret = i915_gem_gtt_prepare_object(obj);
2990 i915_gem_object_unpin_pages(obj);
2991 drm_mm_put_block(free_space);
2995 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2996 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2998 obj->gtt_space = free_space;
2999 obj->gtt_offset = free_space->start;
3002 free_space->size == fence_size &&
3003 (free_space->start & (fence_alignment - 1)) == 0;
3006 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3008 obj->map_and_fenceable = mappable && fenceable;
3010 i915_gem_object_unpin_pages(obj);
3011 trace_i915_gem_object_bind(obj, map_and_fenceable);
3012 i915_gem_verify_gtt(dev);
3017 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3019 /* If we don't have a page list set up, then we're not pinned
3020 * to GPU, and we can ignore the cache flush because it'll happen
3021 * again at bind time.
3023 if (obj->pages == NULL)
3026 /* If the GPU is snooping the contents of the CPU cache,
3027 * we do not need to manually clear the CPU cache lines. However,
3028 * the caches are only snooped when the render cache is
3029 * flushed/invalidated. As we always have to emit invalidations
3030 * and flushes when moving into and out of the RENDER domain, correct
3031 * snooping behaviour occurs naturally as the result of our domain
3034 if (obj->cache_level != I915_CACHE_NONE)
3037 trace_i915_gem_object_clflush(obj);
3039 drm_clflush_sg(obj->pages);
3042 /** Flushes the GTT write domain for the object if it's dirty. */
3044 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3046 uint32_t old_write_domain;
3048 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3051 /* No actual flushing is required for the GTT write domain. Writes
3052 * to it immediately go to main memory as far as we know, so there's
3053 * no chipset flush. It also doesn't land in render cache.
3055 * However, we do have to enforce the order so that all writes through
3056 * the GTT land before any writes to the device, such as updates to
3061 old_write_domain = obj->base.write_domain;
3062 obj->base.write_domain = 0;
3064 trace_i915_gem_object_change_domain(obj,
3065 obj->base.read_domains,
3069 /** Flushes the CPU write domain for the object if it's dirty. */
3071 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3073 uint32_t old_write_domain;
3075 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3078 i915_gem_clflush_object(obj);
3079 i915_gem_chipset_flush(obj->base.dev);
3080 old_write_domain = obj->base.write_domain;
3081 obj->base.write_domain = 0;
3083 trace_i915_gem_object_change_domain(obj,
3084 obj->base.read_domains,
3089 * Moves a single object to the GTT read, and possibly write domain.
3091 * This function returns when the move is complete, including waiting on
3095 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3097 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3098 uint32_t old_write_domain, old_read_domains;
3101 /* Not valid to be called on unbound objects. */
3102 if (obj->gtt_space == NULL)
3105 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3108 ret = i915_gem_object_wait_rendering(obj, !write);
3112 i915_gem_object_flush_cpu_write_domain(obj);
3114 old_write_domain = obj->base.write_domain;
3115 old_read_domains = obj->base.read_domains;
3117 /* It should now be out of any other write domains, and we can update
3118 * the domain values for our changes.
3120 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3121 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3123 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3124 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3128 trace_i915_gem_object_change_domain(obj,
3132 /* And bump the LRU for this access */
3133 if (i915_gem_object_is_inactive(obj))
3134 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3139 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3140 enum i915_cache_level cache_level)
3142 struct drm_device *dev = obj->base.dev;
3143 drm_i915_private_t *dev_priv = dev->dev_private;
3146 if (obj->cache_level == cache_level)
3149 if (obj->pin_count) {
3150 DRM_DEBUG("can not change the cache level of pinned objects\n");
3154 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3155 ret = i915_gem_object_unbind(obj);
3160 if (obj->gtt_space) {
3161 ret = i915_gem_object_finish_gpu(obj);
3165 i915_gem_object_finish_gtt(obj);
3167 /* Before SandyBridge, you could not use tiling or fence
3168 * registers with snooped memory, so relinquish any fences
3169 * currently pointing to our region in the aperture.
3171 if (INTEL_INFO(dev)->gen < 6) {
3172 ret = i915_gem_object_put_fence(obj);
3177 if (obj->has_global_gtt_mapping)
3178 i915_gem_gtt_bind_object(obj, cache_level);
3179 if (obj->has_aliasing_ppgtt_mapping)
3180 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3183 obj->gtt_space->color = cache_level;
3186 if (cache_level == I915_CACHE_NONE) {
3187 u32 old_read_domains, old_write_domain;
3189 /* If we're coming from LLC cached, then we haven't
3190 * actually been tracking whether the data is in the
3191 * CPU cache or not, since we only allow one bit set
3192 * in obj->write_domain and have been skipping the clflushes.
3193 * Just set it to the CPU cache for now.
3195 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3196 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3198 old_read_domains = obj->base.read_domains;
3199 old_write_domain = obj->base.write_domain;
3201 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3202 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3204 trace_i915_gem_object_change_domain(obj,
3209 obj->cache_level = cache_level;
3210 i915_gem_verify_gtt(dev);
3214 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3215 struct drm_file *file)
3217 struct drm_i915_gem_caching *args = data;
3218 struct drm_i915_gem_object *obj;
3221 ret = i915_mutex_lock_interruptible(dev);
3225 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3226 if (&obj->base == NULL) {
3231 args->caching = obj->cache_level != I915_CACHE_NONE;
3233 drm_gem_object_unreference(&obj->base);
3235 mutex_unlock(&dev->struct_mutex);
3239 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3240 struct drm_file *file)
3242 struct drm_i915_gem_caching *args = data;
3243 struct drm_i915_gem_object *obj;
3244 enum i915_cache_level level;
3247 switch (args->caching) {
3248 case I915_CACHING_NONE:
3249 level = I915_CACHE_NONE;
3251 case I915_CACHING_CACHED:
3252 level = I915_CACHE_LLC;
3258 ret = i915_mutex_lock_interruptible(dev);
3262 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3263 if (&obj->base == NULL) {
3268 ret = i915_gem_object_set_cache_level(obj, level);
3270 drm_gem_object_unreference(&obj->base);
3272 mutex_unlock(&dev->struct_mutex);
3277 * Prepare buffer for display plane (scanout, cursors, etc).
3278 * Can be called from an uninterruptible phase (modesetting) and allows
3279 * any flushes to be pipelined (for pageflips).
3282 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3284 struct intel_ring_buffer *pipelined)
3286 u32 old_read_domains, old_write_domain;
3289 if (pipelined != obj->ring) {
3290 ret = i915_gem_object_sync(obj, pipelined);
3295 /* The display engine is not coherent with the LLC cache on gen6. As
3296 * a result, we make sure that the pinning that is about to occur is
3297 * done with uncached PTEs. This is lowest common denominator for all
3300 * However for gen6+, we could do better by using the GFDT bit instead
3301 * of uncaching, which would allow us to flush all the LLC-cached data
3302 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3304 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3308 /* As the user may map the buffer once pinned in the display plane
3309 * (e.g. libkms for the bootup splash), we have to ensure that we
3310 * always use map_and_fenceable for all scanout buffers.
3312 ret = i915_gem_object_pin(obj, alignment, true, false);
3316 i915_gem_object_flush_cpu_write_domain(obj);
3318 old_write_domain = obj->base.write_domain;
3319 old_read_domains = obj->base.read_domains;
3321 /* It should now be out of any other write domains, and we can update
3322 * the domain values for our changes.
3324 obj->base.write_domain = 0;
3325 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3327 trace_i915_gem_object_change_domain(obj,
3335 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3339 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3342 ret = i915_gem_object_wait_rendering(obj, false);
3346 /* Ensure that we invalidate the GPU's caches and TLBs. */
3347 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3352 * Moves a single object to the CPU read, and possibly write domain.
3354 * This function returns when the move is complete, including waiting on
3358 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3360 uint32_t old_write_domain, old_read_domains;
3363 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3366 ret = i915_gem_object_wait_rendering(obj, !write);
3370 i915_gem_object_flush_gtt_write_domain(obj);
3372 old_write_domain = obj->base.write_domain;
3373 old_read_domains = obj->base.read_domains;
3375 /* Flush the CPU cache if it's still invalid. */
3376 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3377 i915_gem_clflush_object(obj);
3379 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3382 /* It should now be out of any other write domains, and we can update
3383 * the domain values for our changes.
3385 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3387 /* If we're writing through the CPU, then the GPU read domains will
3388 * need to be invalidated at next use.
3391 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3392 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3395 trace_i915_gem_object_change_domain(obj,
3402 /* Throttle our rendering by waiting until the ring has completed our requests
3403 * emitted over 20 msec ago.
3405 * Note that if we were to use the current jiffies each time around the loop,
3406 * we wouldn't escape the function with any frames outstanding if the time to
3407 * render a frame was over 20ms.
3409 * This should get us reasonable parallelism between CPU and GPU but also
3410 * relatively low latency when blocking on a particular request to finish.
3413 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct drm_i915_file_private *file_priv = file->driver_priv;
3417 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3418 struct drm_i915_gem_request *request;
3419 struct intel_ring_buffer *ring = NULL;
3423 if (atomic_read(&dev_priv->mm.wedged))
3426 spin_lock(&file_priv->mm.lock);
3427 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3428 if (time_after_eq(request->emitted_jiffies, recent_enough))
3431 ring = request->ring;
3432 seqno = request->seqno;
3434 spin_unlock(&file_priv->mm.lock);
3439 ret = __wait_seqno(ring, seqno, true, NULL);
3441 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3447 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3449 bool map_and_fenceable,
3454 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3457 if (obj->gtt_space != NULL) {
3458 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3459 (map_and_fenceable && !obj->map_and_fenceable)) {
3460 WARN(obj->pin_count,
3461 "bo is already pinned with incorrect alignment:"
3462 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3463 " obj->map_and_fenceable=%d\n",
3464 obj->gtt_offset, alignment,
3466 obj->map_and_fenceable);
3467 ret = i915_gem_object_unbind(obj);
3473 if (obj->gtt_space == NULL) {
3474 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3476 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3482 if (!dev_priv->mm.aliasing_ppgtt)
3483 i915_gem_gtt_bind_object(obj, obj->cache_level);
3486 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3487 i915_gem_gtt_bind_object(obj, obj->cache_level);
3490 obj->pin_mappable |= map_and_fenceable;
3496 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3498 BUG_ON(obj->pin_count == 0);
3499 BUG_ON(obj->gtt_space == NULL);
3501 if (--obj->pin_count == 0)
3502 obj->pin_mappable = false;
3506 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3507 struct drm_file *file)
3509 struct drm_i915_gem_pin *args = data;
3510 struct drm_i915_gem_object *obj;
3513 ret = i915_mutex_lock_interruptible(dev);
3517 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3518 if (&obj->base == NULL) {
3523 if (obj->madv != I915_MADV_WILLNEED) {
3524 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3529 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3530 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3536 obj->user_pin_count++;
3537 obj->pin_filp = file;
3538 if (obj->user_pin_count == 1) {
3539 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3544 /* XXX - flush the CPU caches for pinned objects
3545 * as the X server doesn't manage domains yet
3547 i915_gem_object_flush_cpu_write_domain(obj);
3548 args->offset = obj->gtt_offset;
3550 drm_gem_object_unreference(&obj->base);
3552 mutex_unlock(&dev->struct_mutex);
3557 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3558 struct drm_file *file)
3560 struct drm_i915_gem_pin *args = data;
3561 struct drm_i915_gem_object *obj;
3564 ret = i915_mutex_lock_interruptible(dev);
3568 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3569 if (&obj->base == NULL) {
3574 if (obj->pin_filp != file) {
3575 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3580 obj->user_pin_count--;
3581 if (obj->user_pin_count == 0) {
3582 obj->pin_filp = NULL;
3583 i915_gem_object_unpin(obj);
3587 drm_gem_object_unreference(&obj->base);
3589 mutex_unlock(&dev->struct_mutex);
3594 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3595 struct drm_file *file)
3597 struct drm_i915_gem_busy *args = data;
3598 struct drm_i915_gem_object *obj;
3601 ret = i915_mutex_lock_interruptible(dev);
3605 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3606 if (&obj->base == NULL) {
3611 /* Count all active objects as busy, even if they are currently not used
3612 * by the gpu. Users of this interface expect objects to eventually
3613 * become non-busy without any further actions, therefore emit any
3614 * necessary flushes here.
3616 ret = i915_gem_object_flush_active(obj);
3618 args->busy = obj->active;
3620 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3621 args->busy |= intel_ring_flag(obj->ring) << 16;
3624 drm_gem_object_unreference(&obj->base);
3626 mutex_unlock(&dev->struct_mutex);
3631 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3632 struct drm_file *file_priv)
3634 return i915_gem_ring_throttle(dev, file_priv);
3638 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3639 struct drm_file *file_priv)
3641 struct drm_i915_gem_madvise *args = data;
3642 struct drm_i915_gem_object *obj;
3645 switch (args->madv) {
3646 case I915_MADV_DONTNEED:
3647 case I915_MADV_WILLNEED:
3653 ret = i915_mutex_lock_interruptible(dev);
3657 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3658 if (&obj->base == NULL) {
3663 if (obj->pin_count) {
3668 if (obj->madv != __I915_MADV_PURGED)
3669 obj->madv = args->madv;
3671 /* if the object is no longer attached, discard its backing storage */
3672 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3673 i915_gem_object_truncate(obj);
3675 args->retained = obj->madv != __I915_MADV_PURGED;
3678 drm_gem_object_unreference(&obj->base);
3680 mutex_unlock(&dev->struct_mutex);
3684 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3685 const struct drm_i915_gem_object_ops *ops)
3687 INIT_LIST_HEAD(&obj->mm_list);
3688 INIT_LIST_HEAD(&obj->gtt_list);
3689 INIT_LIST_HEAD(&obj->ring_list);
3690 INIT_LIST_HEAD(&obj->exec_list);
3694 obj->fence_reg = I915_FENCE_REG_NONE;
3695 obj->madv = I915_MADV_WILLNEED;
3696 /* Avoid an unnecessary call to unbind on the first bind. */
3697 obj->map_and_fenceable = true;
3699 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3702 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3703 .get_pages = i915_gem_object_get_pages_gtt,
3704 .put_pages = i915_gem_object_put_pages_gtt,
3707 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3710 struct drm_i915_gem_object *obj;
3711 struct address_space *mapping;
3714 obj = i915_gem_object_alloc(dev);
3718 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3719 i915_gem_object_free(obj);
3723 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3724 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3725 /* 965gm cannot relocate objects above 4GiB. */
3726 mask &= ~__GFP_HIGHMEM;
3727 mask |= __GFP_DMA32;
3730 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3731 mapping_set_gfp_mask(mapping, mask);
3733 i915_gem_object_init(obj, &i915_gem_object_ops);
3735 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3736 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3739 /* On some devices, we can have the GPU use the LLC (the CPU
3740 * cache) for about a 10% performance improvement
3741 * compared to uncached. Graphics requests other than
3742 * display scanout are coherent with the CPU in
3743 * accessing this cache. This means in this mode we
3744 * don't need to clflush on the CPU side, and on the
3745 * GPU side we only need to flush internal caches to
3746 * get data visible to the CPU.
3748 * However, we maintain the display planes as UC, and so
3749 * need to rebind when first used as such.
3751 obj->cache_level = I915_CACHE_LLC;
3753 obj->cache_level = I915_CACHE_NONE;
3758 int i915_gem_init_object(struct drm_gem_object *obj)
3765 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3767 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3768 struct drm_device *dev = obj->base.dev;
3769 drm_i915_private_t *dev_priv = dev->dev_private;
3771 trace_i915_gem_object_destroy(obj);
3774 i915_gem_detach_phys_object(dev, obj);
3777 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3778 bool was_interruptible;
3780 was_interruptible = dev_priv->mm.interruptible;
3781 dev_priv->mm.interruptible = false;
3783 WARN_ON(i915_gem_object_unbind(obj));
3785 dev_priv->mm.interruptible = was_interruptible;
3788 obj->pages_pin_count = 0;
3789 i915_gem_object_put_pages(obj);
3790 i915_gem_object_free_mmap_offset(obj);
3791 i915_gem_object_release_stolen(obj);
3795 if (obj->base.import_attach)
3796 drm_prime_gem_destroy(&obj->base, NULL);
3798 drm_gem_object_release(&obj->base);
3799 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3802 i915_gem_object_free(obj);
3806 i915_gem_idle(struct drm_device *dev)
3808 drm_i915_private_t *dev_priv = dev->dev_private;
3811 mutex_lock(&dev->struct_mutex);
3813 if (dev_priv->mm.suspended) {
3814 mutex_unlock(&dev->struct_mutex);
3818 ret = i915_gpu_idle(dev);
3820 mutex_unlock(&dev->struct_mutex);
3823 i915_gem_retire_requests(dev);
3825 /* Under UMS, be paranoid and evict. */
3826 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3827 i915_gem_evict_everything(dev);
3829 i915_gem_reset_fences(dev);
3831 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3832 * We need to replace this with a semaphore, or something.
3833 * And not confound mm.suspended!
3835 dev_priv->mm.suspended = 1;
3836 del_timer_sync(&dev_priv->hangcheck_timer);
3838 i915_kernel_lost_context(dev);
3839 i915_gem_cleanup_ringbuffer(dev);
3841 mutex_unlock(&dev->struct_mutex);
3843 /* Cancel the retire work handler, which should be idle now. */
3844 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3849 void i915_gem_l3_remap(struct drm_device *dev)
3851 drm_i915_private_t *dev_priv = dev->dev_private;
3855 if (!IS_IVYBRIDGE(dev))
3858 if (!dev_priv->l3_parity.remap_info)
3861 misccpctl = I915_READ(GEN7_MISCCPCTL);
3862 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3863 POSTING_READ(GEN7_MISCCPCTL);
3865 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3866 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3867 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3868 DRM_DEBUG("0x%x was already programmed to %x\n",
3869 GEN7_L3LOG_BASE + i, remap);
3870 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3871 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3872 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3875 /* Make sure all the writes land before disabling dop clock gating */
3876 POSTING_READ(GEN7_L3LOG_BASE);
3878 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3881 void i915_gem_init_swizzling(struct drm_device *dev)
3883 drm_i915_private_t *dev_priv = dev->dev_private;
3885 if (INTEL_INFO(dev)->gen < 5 ||
3886 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3889 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3890 DISP_TILE_SURFACE_SWIZZLING);
3895 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3897 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3899 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3903 intel_enable_blt(struct drm_device *dev)
3908 /* The blitter was dysfunctional on early prototypes */
3909 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3910 DRM_INFO("BLT not supported on this pre-production hardware;"
3911 " graphics performance will be degraded.\n");
3919 i915_gem_init_hw(struct drm_device *dev)
3921 drm_i915_private_t *dev_priv = dev->dev_private;
3924 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3927 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3928 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3930 i915_gem_l3_remap(dev);
3932 i915_gem_init_swizzling(dev);
3934 ret = intel_init_render_ring_buffer(dev);
3939 ret = intel_init_bsd_ring_buffer(dev);
3941 goto cleanup_render_ring;
3944 if (intel_enable_blt(dev)) {
3945 ret = intel_init_blt_ring_buffer(dev);
3947 goto cleanup_bsd_ring;
3950 dev_priv->next_seqno = 1;
3953 * XXX: There was some w/a described somewhere suggesting loading
3954 * contexts before PPGTT.
3956 i915_gem_context_init(dev);
3957 i915_gem_init_ppgtt(dev);
3962 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3963 cleanup_render_ring:
3964 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3969 intel_enable_ppgtt(struct drm_device *dev)
3971 if (i915_enable_ppgtt >= 0)
3972 return i915_enable_ppgtt;
3974 #ifdef CONFIG_INTEL_IOMMU
3975 /* Disable ppgtt on SNB if VT-d is on. */
3976 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3983 int i915_gem_init(struct drm_device *dev)
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986 unsigned long gtt_size, mappable_size;
3989 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3990 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3992 mutex_lock(&dev->struct_mutex);
3993 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3994 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3995 * aperture accordingly when using aliasing ppgtt. */
3996 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3998 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4000 ret = i915_gem_init_aliasing_ppgtt(dev);
4002 mutex_unlock(&dev->struct_mutex);
4006 /* Let GEM Manage all of the aperture.
4008 * However, leave one page at the end still bound to the scratch
4009 * page. There are a number of places where the hardware
4010 * apparently prefetches past the end of the object, and we've
4011 * seen multiple hangs with the GPU head pointer stuck in a
4012 * batchbuffer bound at the last page of the aperture. One page
4013 * should be enough to keep any prefetching inside of the
4016 i915_gem_init_global_gtt(dev, 0, mappable_size,
4020 ret = i915_gem_init_hw(dev);
4021 mutex_unlock(&dev->struct_mutex);
4023 i915_gem_cleanup_aliasing_ppgtt(dev);
4027 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4028 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4029 dev_priv->dri1.allow_batchbuffer = 1;
4034 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4036 drm_i915_private_t *dev_priv = dev->dev_private;
4037 struct intel_ring_buffer *ring;
4040 for_each_ring(ring, dev_priv, i)
4041 intel_cleanup_ring_buffer(ring);
4045 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4046 struct drm_file *file_priv)
4048 drm_i915_private_t *dev_priv = dev->dev_private;
4051 if (drm_core_check_feature(dev, DRIVER_MODESET))
4054 if (atomic_read(&dev_priv->mm.wedged)) {
4055 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4056 atomic_set(&dev_priv->mm.wedged, 0);
4059 mutex_lock(&dev->struct_mutex);
4060 dev_priv->mm.suspended = 0;
4062 ret = i915_gem_init_hw(dev);
4064 mutex_unlock(&dev->struct_mutex);
4068 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4069 mutex_unlock(&dev->struct_mutex);
4071 ret = drm_irq_install(dev);
4073 goto cleanup_ringbuffer;
4078 mutex_lock(&dev->struct_mutex);
4079 i915_gem_cleanup_ringbuffer(dev);
4080 dev_priv->mm.suspended = 1;
4081 mutex_unlock(&dev->struct_mutex);
4087 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4088 struct drm_file *file_priv)
4090 if (drm_core_check_feature(dev, DRIVER_MODESET))
4093 drm_irq_uninstall(dev);
4094 return i915_gem_idle(dev);
4098 i915_gem_lastclose(struct drm_device *dev)
4102 if (drm_core_check_feature(dev, DRIVER_MODESET))
4105 ret = i915_gem_idle(dev);
4107 DRM_ERROR("failed to idle hardware: %d\n", ret);
4111 init_ring_lists(struct intel_ring_buffer *ring)
4113 INIT_LIST_HEAD(&ring->active_list);
4114 INIT_LIST_HEAD(&ring->request_list);
4118 i915_gem_load(struct drm_device *dev)
4120 drm_i915_private_t *dev_priv = dev->dev_private;
4124 kmem_cache_create("i915_gem_object",
4125 sizeof(struct drm_i915_gem_object), 0,
4129 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4130 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4131 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4132 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4133 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4134 for (i = 0; i < I915_NUM_RINGS; i++)
4135 init_ring_lists(&dev_priv->ring[i]);
4136 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4137 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4138 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4139 i915_gem_retire_work_handler);
4140 init_completion(&dev_priv->error_completion);
4142 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4144 I915_WRITE(MI_ARB_STATE,
4145 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4148 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4150 /* Old X drivers will take 0-2 for front, back, depth buffers */
4151 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4152 dev_priv->fence_reg_start = 3;
4154 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4155 dev_priv->num_fence_regs = 16;
4157 dev_priv->num_fence_regs = 8;
4159 /* Initialize fence registers to zero */
4160 i915_gem_reset_fences(dev);
4162 i915_gem_detect_bit_6_swizzle(dev);
4163 init_waitqueue_head(&dev_priv->pending_flip_queue);
4165 dev_priv->mm.interruptible = true;
4167 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4168 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4169 register_shrinker(&dev_priv->mm.inactive_shrinker);
4173 * Create a physically contiguous memory object for this object
4174 * e.g. for cursor + overlay regs
4176 static int i915_gem_init_phys_object(struct drm_device *dev,
4177 int id, int size, int align)
4179 drm_i915_private_t *dev_priv = dev->dev_private;
4180 struct drm_i915_gem_phys_object *phys_obj;
4183 if (dev_priv->mm.phys_objs[id - 1] || !size)
4186 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4192 phys_obj->handle = drm_pci_alloc(dev, size, align);
4193 if (!phys_obj->handle) {
4198 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4201 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4209 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4211 drm_i915_private_t *dev_priv = dev->dev_private;
4212 struct drm_i915_gem_phys_object *phys_obj;
4214 if (!dev_priv->mm.phys_objs[id - 1])
4217 phys_obj = dev_priv->mm.phys_objs[id - 1];
4218 if (phys_obj->cur_obj) {
4219 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4223 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4225 drm_pci_free(dev, phys_obj->handle);
4227 dev_priv->mm.phys_objs[id - 1] = NULL;
4230 void i915_gem_free_all_phys_object(struct drm_device *dev)
4234 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4235 i915_gem_free_phys_object(dev, i);
4238 void i915_gem_detach_phys_object(struct drm_device *dev,
4239 struct drm_i915_gem_object *obj)
4241 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4248 vaddr = obj->phys_obj->handle->vaddr;
4250 page_count = obj->base.size / PAGE_SIZE;
4251 for (i = 0; i < page_count; i++) {
4252 struct page *page = shmem_read_mapping_page(mapping, i);
4253 if (!IS_ERR(page)) {
4254 char *dst = kmap_atomic(page);
4255 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4258 drm_clflush_pages(&page, 1);
4260 set_page_dirty(page);
4261 mark_page_accessed(page);
4262 page_cache_release(page);
4265 i915_gem_chipset_flush(dev);
4267 obj->phys_obj->cur_obj = NULL;
4268 obj->phys_obj = NULL;
4272 i915_gem_attach_phys_object(struct drm_device *dev,
4273 struct drm_i915_gem_object *obj,
4277 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4278 drm_i915_private_t *dev_priv = dev->dev_private;
4283 if (id > I915_MAX_PHYS_OBJECT)
4286 if (obj->phys_obj) {
4287 if (obj->phys_obj->id == id)
4289 i915_gem_detach_phys_object(dev, obj);
4292 /* create a new object */
4293 if (!dev_priv->mm.phys_objs[id - 1]) {
4294 ret = i915_gem_init_phys_object(dev, id,
4295 obj->base.size, align);
4297 DRM_ERROR("failed to init phys object %d size: %zu\n",
4298 id, obj->base.size);
4303 /* bind to the object */
4304 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4305 obj->phys_obj->cur_obj = obj;
4307 page_count = obj->base.size / PAGE_SIZE;
4309 for (i = 0; i < page_count; i++) {
4313 page = shmem_read_mapping_page(mapping, i);
4315 return PTR_ERR(page);
4317 src = kmap_atomic(page);
4318 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4319 memcpy(dst, src, PAGE_SIZE);
4322 mark_page_accessed(page);
4323 page_cache_release(page);
4330 i915_gem_phys_pwrite(struct drm_device *dev,
4331 struct drm_i915_gem_object *obj,
4332 struct drm_i915_gem_pwrite *args,
4333 struct drm_file *file_priv)
4335 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4336 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4338 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4339 unsigned long unwritten;
4341 /* The physical object once assigned is fixed for the lifetime
4342 * of the obj, so we can safely drop the lock and continue
4345 mutex_unlock(&dev->struct_mutex);
4346 unwritten = copy_from_user(vaddr, user_data, args->size);
4347 mutex_lock(&dev->struct_mutex);
4352 i915_gem_chipset_flush(dev);
4356 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4358 struct drm_i915_file_private *file_priv = file->driver_priv;
4360 /* Clean up our request list when the client is going away, so that
4361 * later retire_requests won't dereference our soon-to-be-gone
4364 spin_lock(&file_priv->mm.lock);
4365 while (!list_empty(&file_priv->mm.request_list)) {
4366 struct drm_i915_gem_request *request;
4368 request = list_first_entry(&file_priv->mm.request_list,
4369 struct drm_i915_gem_request,
4371 list_del(&request->client_list);
4372 request->file_priv = NULL;
4374 spin_unlock(&file_priv->mm.lock);
4377 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4379 if (!mutex_is_locked(mutex))
4382 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4383 return mutex->owner == task;
4385 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4391 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4393 struct drm_i915_private *dev_priv =
4394 container_of(shrinker,
4395 struct drm_i915_private,
4396 mm.inactive_shrinker);
4397 struct drm_device *dev = dev_priv->dev;
4398 struct drm_i915_gem_object *obj;
4399 int nr_to_scan = sc->nr_to_scan;
4403 if (!mutex_trylock(&dev->struct_mutex)) {
4404 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4411 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4413 i915_gem_shrink_all(dev_priv);
4417 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4418 if (obj->pages_pin_count == 0)
4419 cnt += obj->base.size >> PAGE_SHIFT;
4420 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4421 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4422 cnt += obj->base.size >> PAGE_SHIFT;
4425 mutex_unlock(&dev->struct_mutex);