2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_get_aperture *args = data;
168 struct drm_i915_gem_object *obj;
172 mutex_lock(&dev->struct_mutex);
173 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
174 if (i915_gem_obj_is_pinned(obj))
175 pinned += i915_gem_obj_ggtt_size(obj);
176 mutex_unlock(&dev->struct_mutex);
178 args->aper_size = dev_priv->gtt.base.total;
179 args->aper_available_size = args->aper_size - pinned;
185 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
187 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
188 char *vaddr = obj->phys_handle->vaddr;
190 struct scatterlist *sg;
193 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
196 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
200 page = shmem_read_mapping_page(mapping, i);
202 return PTR_ERR(page);
204 src = kmap_atomic(page);
205 memcpy(vaddr, src, PAGE_SIZE);
206 drm_clflush_virt_range(vaddr, PAGE_SIZE);
209 page_cache_release(page);
213 i915_gem_chipset_flush(obj->base.dev);
215 st = kmalloc(sizeof(*st), GFP_KERNEL);
219 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
226 sg->length = obj->base.size;
228 sg_dma_address(sg) = obj->phys_handle->busaddr;
229 sg_dma_len(sg) = obj->base.size;
232 obj->has_dma_mapping = true;
237 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
241 BUG_ON(obj->madv == __I915_MADV_PURGED);
243 ret = i915_gem_object_set_to_cpu_domain(obj, true);
245 /* In the event of a disaster, abandon all caches and
248 WARN_ON(ret != -EIO);
249 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
252 if (obj->madv == I915_MADV_DONTNEED)
256 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
257 char *vaddr = obj->phys_handle->vaddr;
260 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
264 page = shmem_read_mapping_page(mapping, i);
268 dst = kmap_atomic(page);
269 drm_clflush_virt_range(vaddr, PAGE_SIZE);
270 memcpy(dst, vaddr, PAGE_SIZE);
273 set_page_dirty(page);
274 if (obj->madv == I915_MADV_WILLNEED)
275 mark_page_accessed(page);
276 page_cache_release(page);
282 sg_free_table(obj->pages);
285 obj->has_dma_mapping = false;
289 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
291 drm_pci_free(obj->base.dev, obj->phys_handle);
294 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
295 .get_pages = i915_gem_object_get_pages_phys,
296 .put_pages = i915_gem_object_put_pages_phys,
297 .release = i915_gem_object_release_phys,
301 drop_pages(struct drm_i915_gem_object *obj)
303 struct i915_vma *vma, *next;
306 drm_gem_object_reference(&obj->base);
307 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
308 if (i915_vma_unbind(vma))
311 ret = i915_gem_object_put_pages(obj);
312 drm_gem_object_unreference(&obj->base);
318 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
321 drm_dma_handle_t *phys;
324 if (obj->phys_handle) {
325 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
331 if (obj->madv != I915_MADV_WILLNEED)
334 if (obj->base.filp == NULL)
337 ret = drop_pages(obj);
341 /* create a new object */
342 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
346 obj->phys_handle = phys;
347 obj->ops = &i915_gem_phys_ops;
349 return i915_gem_object_get_pages(obj);
353 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
354 struct drm_i915_gem_pwrite *args,
355 struct drm_file *file_priv)
357 struct drm_device *dev = obj->base.dev;
358 void *vaddr = obj->phys_handle->vaddr + args->offset;
359 char __user *user_data = to_user_ptr(args->data_ptr);
362 /* We manually control the domain here and pretend that it
363 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
365 ret = i915_gem_object_wait_rendering(obj, false);
369 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
370 unsigned long unwritten;
372 /* The physical object once assigned is fixed for the lifetime
373 * of the obj, so we can safely drop the lock and continue
376 mutex_unlock(&dev->struct_mutex);
377 unwritten = copy_from_user(vaddr, user_data, args->size);
378 mutex_lock(&dev->struct_mutex);
383 drm_clflush_virt_range(vaddr, args->size);
384 i915_gem_chipset_flush(dev);
388 void *i915_gem_object_alloc(struct drm_device *dev)
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
394 void i915_gem_object_free(struct drm_i915_gem_object *obj)
396 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
397 kmem_cache_free(dev_priv->slab, obj);
401 i915_gem_create(struct drm_file *file,
402 struct drm_device *dev,
406 struct drm_i915_gem_object *obj;
410 size = roundup(size, PAGE_SIZE);
414 /* Allocate the new object */
415 obj = i915_gem_alloc_object(dev, size);
419 ret = drm_gem_handle_create(file, &obj->base, &handle);
420 /* drop reference from allocate - handle holds it now */
421 drm_gem_object_unreference_unlocked(&obj->base);
430 i915_gem_dumb_create(struct drm_file *file,
431 struct drm_device *dev,
432 struct drm_mode_create_dumb *args)
434 /* have to work out size/pitch and return them */
435 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
436 args->size = args->pitch * args->height;
437 return i915_gem_create(file, dev,
438 args->size, &args->handle);
442 * Creates a new mm object and returns a handle to it.
445 i915_gem_create_ioctl(struct drm_device *dev, void *data,
446 struct drm_file *file)
448 struct drm_i915_gem_create *args = data;
450 return i915_gem_create(file, dev,
451 args->size, &args->handle);
455 __copy_to_user_swizzled(char __user *cpu_vaddr,
456 const char *gpu_vaddr, int gpu_offset,
459 int ret, cpu_offset = 0;
462 int cacheline_end = ALIGN(gpu_offset + 1, 64);
463 int this_length = min(cacheline_end - gpu_offset, length);
464 int swizzled_gpu_offset = gpu_offset ^ 64;
466 ret = __copy_to_user(cpu_vaddr + cpu_offset,
467 gpu_vaddr + swizzled_gpu_offset,
472 cpu_offset += this_length;
473 gpu_offset += this_length;
474 length -= this_length;
481 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
482 const char __user *cpu_vaddr,
485 int ret, cpu_offset = 0;
488 int cacheline_end = ALIGN(gpu_offset + 1, 64);
489 int this_length = min(cacheline_end - gpu_offset, length);
490 int swizzled_gpu_offset = gpu_offset ^ 64;
492 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
493 cpu_vaddr + cpu_offset,
498 cpu_offset += this_length;
499 gpu_offset += this_length;
500 length -= this_length;
507 * Pins the specified object's pages and synchronizes the object with
508 * GPU accesses. Sets needs_clflush to non-zero if the caller should
509 * flush the object from the CPU cache.
511 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
521 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
522 /* If we're not in the cpu read domain, set ourself into the gtt
523 * read domain and manually flush cachelines (if required). This
524 * optimizes for the case when the gpu will dirty the data
525 * anyway again before the next pread happens. */
526 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
528 ret = i915_gem_object_wait_rendering(obj, true);
532 i915_gem_object_retire(obj);
535 ret = i915_gem_object_get_pages(obj);
539 i915_gem_object_pin_pages(obj);
544 /* Per-page copy function for the shmem pread fastpath.
545 * Flushes invalid cachelines before reading the target if
546 * needs_clflush is set. */
548 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
549 char __user *user_data,
550 bool page_do_bit17_swizzling, bool needs_clflush)
555 if (unlikely(page_do_bit17_swizzling))
558 vaddr = kmap_atomic(page);
560 drm_clflush_virt_range(vaddr + shmem_page_offset,
562 ret = __copy_to_user_inatomic(user_data,
563 vaddr + shmem_page_offset,
565 kunmap_atomic(vaddr);
567 return ret ? -EFAULT : 0;
571 shmem_clflush_swizzled_range(char *addr, unsigned long length,
574 if (unlikely(swizzled)) {
575 unsigned long start = (unsigned long) addr;
576 unsigned long end = (unsigned long) addr + length;
578 /* For swizzling simply ensure that we always flush both
579 * channels. Lame, but simple and it works. Swizzled
580 * pwrite/pread is far from a hotpath - current userspace
581 * doesn't use it at all. */
582 start = round_down(start, 128);
583 end = round_up(end, 128);
585 drm_clflush_virt_range((void *)start, end - start);
587 drm_clflush_virt_range(addr, length);
592 /* Only difference to the fast-path function is that this can handle bit17
593 * and uses non-atomic copy and kmap functions. */
595 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
596 char __user *user_data,
597 bool page_do_bit17_swizzling, bool needs_clflush)
604 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
606 page_do_bit17_swizzling);
608 if (page_do_bit17_swizzling)
609 ret = __copy_to_user_swizzled(user_data,
610 vaddr, shmem_page_offset,
613 ret = __copy_to_user(user_data,
614 vaddr + shmem_page_offset,
618 return ret ? - EFAULT : 0;
622 i915_gem_shmem_pread(struct drm_device *dev,
623 struct drm_i915_gem_object *obj,
624 struct drm_i915_gem_pread *args,
625 struct drm_file *file)
627 char __user *user_data;
630 int shmem_page_offset, page_length, ret = 0;
631 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
633 int needs_clflush = 0;
634 struct sg_page_iter sg_iter;
636 user_data = to_user_ptr(args->data_ptr);
639 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
641 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
645 offset = args->offset;
647 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
648 offset >> PAGE_SHIFT) {
649 struct page *page = sg_page_iter_page(&sg_iter);
654 /* Operation in this page
656 * shmem_page_offset = offset within page in shmem file
657 * page_length = bytes to copy for this page
659 shmem_page_offset = offset_in_page(offset);
660 page_length = remain;
661 if ((shmem_page_offset + page_length) > PAGE_SIZE)
662 page_length = PAGE_SIZE - shmem_page_offset;
664 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
665 (page_to_phys(page) & (1 << 17)) != 0;
667 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
668 user_data, page_do_bit17_swizzling,
673 mutex_unlock(&dev->struct_mutex);
675 if (likely(!i915.prefault_disable) && !prefaulted) {
676 ret = fault_in_multipages_writeable(user_data, remain);
677 /* Userspace is tricking us, but we've already clobbered
678 * its pages with the prefault and promised to write the
679 * data up to the first fault. Hence ignore any errors
680 * and just continue. */
685 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
686 user_data, page_do_bit17_swizzling,
689 mutex_lock(&dev->struct_mutex);
695 remain -= page_length;
696 user_data += page_length;
697 offset += page_length;
701 i915_gem_object_unpin_pages(obj);
707 * Reads data from the object referenced by handle.
709 * On error, the contents of *data are undefined.
712 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *file)
715 struct drm_i915_gem_pread *args = data;
716 struct drm_i915_gem_object *obj;
722 if (!access_ok(VERIFY_WRITE,
723 to_user_ptr(args->data_ptr),
727 ret = i915_mutex_lock_interruptible(dev);
731 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
732 if (&obj->base == NULL) {
737 /* Bounds check source. */
738 if (args->offset > obj->base.size ||
739 args->size > obj->base.size - args->offset) {
744 /* prime objects have no backing filp to GEM pread/pwrite
747 if (!obj->base.filp) {
752 trace_i915_gem_object_pread(obj, args->offset, args->size);
754 ret = i915_gem_shmem_pread(dev, obj, args, file);
757 drm_gem_object_unreference(&obj->base);
759 mutex_unlock(&dev->struct_mutex);
763 /* This is the fast write path which cannot handle
764 * page faults in the source data
768 fast_user_write(struct io_mapping *mapping,
769 loff_t page_base, int page_offset,
770 char __user *user_data,
773 void __iomem *vaddr_atomic;
775 unsigned long unwritten;
777 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
778 /* We can use the cpu mem copy function because this is X86. */
779 vaddr = (void __force*)vaddr_atomic + page_offset;
780 unwritten = __copy_from_user_inatomic_nocache(vaddr,
782 io_mapping_unmap_atomic(vaddr_atomic);
787 * This is the fast pwrite path, where we copy the data directly from the
788 * user into the GTT, uncached.
791 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
792 struct drm_i915_gem_object *obj,
793 struct drm_i915_gem_pwrite *args,
794 struct drm_file *file)
796 struct drm_i915_private *dev_priv = dev->dev_private;
798 loff_t offset, page_base;
799 char __user *user_data;
800 int page_offset, page_length, ret;
802 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
806 ret = i915_gem_object_set_to_gtt_domain(obj, true);
810 ret = i915_gem_object_put_fence(obj);
814 user_data = to_user_ptr(args->data_ptr);
817 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
820 /* Operation in this page
822 * page_base = page offset within aperture
823 * page_offset = offset within page
824 * page_length = bytes to copy for this page
826 page_base = offset & PAGE_MASK;
827 page_offset = offset_in_page(offset);
828 page_length = remain;
829 if ((page_offset + remain) > PAGE_SIZE)
830 page_length = PAGE_SIZE - page_offset;
832 /* If we get a fault while copying data, then (presumably) our
833 * source page isn't available. Return the error and we'll
834 * retry in the slow path.
836 if (fast_user_write(dev_priv->gtt.mappable, page_base,
837 page_offset, user_data, page_length)) {
842 remain -= page_length;
843 user_data += page_length;
844 offset += page_length;
848 i915_gem_object_ggtt_unpin(obj);
853 /* Per-page copy function for the shmem pwrite fastpath.
854 * Flushes invalid cachelines before writing to the target if
855 * needs_clflush_before is set and flushes out any written cachelines after
856 * writing if needs_clflush is set. */
858 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
859 char __user *user_data,
860 bool page_do_bit17_swizzling,
861 bool needs_clflush_before,
862 bool needs_clflush_after)
867 if (unlikely(page_do_bit17_swizzling))
870 vaddr = kmap_atomic(page);
871 if (needs_clflush_before)
872 drm_clflush_virt_range(vaddr + shmem_page_offset,
874 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
875 user_data, page_length);
876 if (needs_clflush_after)
877 drm_clflush_virt_range(vaddr + shmem_page_offset,
879 kunmap_atomic(vaddr);
881 return ret ? -EFAULT : 0;
884 /* Only difference to the fast-path function is that this can handle bit17
885 * and uses non-atomic copy and kmap functions. */
887 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
888 char __user *user_data,
889 bool page_do_bit17_swizzling,
890 bool needs_clflush_before,
891 bool needs_clflush_after)
897 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
898 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
900 page_do_bit17_swizzling);
901 if (page_do_bit17_swizzling)
902 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
906 ret = __copy_from_user(vaddr + shmem_page_offset,
909 if (needs_clflush_after)
910 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
912 page_do_bit17_swizzling);
915 return ret ? -EFAULT : 0;
919 i915_gem_shmem_pwrite(struct drm_device *dev,
920 struct drm_i915_gem_object *obj,
921 struct drm_i915_gem_pwrite *args,
922 struct drm_file *file)
926 char __user *user_data;
927 int shmem_page_offset, page_length, ret = 0;
928 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
929 int hit_slowpath = 0;
930 int needs_clflush_after = 0;
931 int needs_clflush_before = 0;
932 struct sg_page_iter sg_iter;
934 user_data = to_user_ptr(args->data_ptr);
937 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
939 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
940 /* If we're not in the cpu write domain, set ourself into the gtt
941 * write domain and manually flush cachelines (if required). This
942 * optimizes for the case when the gpu will use the data
943 * right away and we therefore have to clflush anyway. */
944 needs_clflush_after = cpu_write_needs_clflush(obj);
945 ret = i915_gem_object_wait_rendering(obj, false);
949 i915_gem_object_retire(obj);
951 /* Same trick applies to invalidate partially written cachelines read
953 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
954 needs_clflush_before =
955 !cpu_cache_is_coherent(dev, obj->cache_level);
957 ret = i915_gem_object_get_pages(obj);
961 i915_gem_object_pin_pages(obj);
963 offset = args->offset;
966 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
967 offset >> PAGE_SHIFT) {
968 struct page *page = sg_page_iter_page(&sg_iter);
969 int partial_cacheline_write;
974 /* Operation in this page
976 * shmem_page_offset = offset within page in shmem file
977 * page_length = bytes to copy for this page
979 shmem_page_offset = offset_in_page(offset);
981 page_length = remain;
982 if ((shmem_page_offset + page_length) > PAGE_SIZE)
983 page_length = PAGE_SIZE - shmem_page_offset;
985 /* If we don't overwrite a cacheline completely we need to be
986 * careful to have up-to-date data by first clflushing. Don't
987 * overcomplicate things and flush the entire patch. */
988 partial_cacheline_write = needs_clflush_before &&
989 ((shmem_page_offset | page_length)
990 & (boot_cpu_data.x86_clflush_size - 1));
992 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
993 (page_to_phys(page) & (1 << 17)) != 0;
995 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
996 user_data, page_do_bit17_swizzling,
997 partial_cacheline_write,
998 needs_clflush_after);
1003 mutex_unlock(&dev->struct_mutex);
1004 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1005 user_data, page_do_bit17_swizzling,
1006 partial_cacheline_write,
1007 needs_clflush_after);
1009 mutex_lock(&dev->struct_mutex);
1015 remain -= page_length;
1016 user_data += page_length;
1017 offset += page_length;
1021 i915_gem_object_unpin_pages(obj);
1025 * Fixup: Flush cpu caches in case we didn't flush the dirty
1026 * cachelines in-line while writing and the object moved
1027 * out of the cpu write domain while we've dropped the lock.
1029 if (!needs_clflush_after &&
1030 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1031 if (i915_gem_clflush_object(obj, obj->pin_display))
1032 i915_gem_chipset_flush(dev);
1036 if (needs_clflush_after)
1037 i915_gem_chipset_flush(dev);
1043 * Writes data to the object referenced by handle.
1045 * On error, the contents of the buffer that were to be modified are undefined.
1048 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1049 struct drm_file *file)
1051 struct drm_i915_gem_pwrite *args = data;
1052 struct drm_i915_gem_object *obj;
1055 if (args->size == 0)
1058 if (!access_ok(VERIFY_READ,
1059 to_user_ptr(args->data_ptr),
1063 if (likely(!i915.prefault_disable)) {
1064 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1070 ret = i915_mutex_lock_interruptible(dev);
1074 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1075 if (&obj->base == NULL) {
1080 /* Bounds check destination. */
1081 if (args->offset > obj->base.size ||
1082 args->size > obj->base.size - args->offset) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj->base.filp) {
1095 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj->tiling_mode == I915_TILING_NONE &&
1105 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1106 cpu_write_needs_clflush(obj)) {
1107 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret == -EFAULT || ret == -ENOSPC) {
1114 if (obj->phys_handle)
1115 ret = i915_gem_phys_pwrite(obj, args, file);
1117 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1121 drm_gem_object_unreference(&obj->base);
1123 mutex_unlock(&dev->struct_mutex);
1128 i915_gem_check_wedge(struct i915_gpu_error *error,
1131 if (i915_reset_in_progress(error)) {
1132 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133 * -EIO unconditionally for these. */
1137 /* Recovery complete, but the reset failed ... */
1138 if (i915_terminally_wedged(error))
1142 * Check if GPU Reset is in progress - we need intel_ring_begin
1143 * to work properly to reinit the hw state while the gpu is
1144 * still marked as reset-in-progress. Handle this with a flag.
1146 if (!error->reload_in_reset)
1154 * Compare seqno against outstanding lazy request. Emit a request if they are
1158 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1162 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1165 if (seqno == ring->outstanding_lazy_seqno)
1166 ret = i915_add_request(ring, NULL);
1171 static void fake_irq(unsigned long data)
1173 wake_up_process((struct task_struct *)data);
1176 static bool missed_irq(struct drm_i915_private *dev_priv,
1177 struct intel_engine_cs *ring)
1179 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1182 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1184 if (file_priv == NULL)
1187 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1191 * __i915_wait_seqno - wait until execution of seqno has finished
1192 * @ring: the ring expected to report seqno
1194 * @reset_counter: reset sequence associated with the given seqno
1195 * @interruptible: do an interruptible wait (normally yes)
1196 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1198 * Note: It is of utmost importance that the passed in seqno and reset_counter
1199 * values have been read by the caller in an smp safe manner. Where read-side
1200 * locks are involved, it is sufficient to read the reset_counter before
1201 * unlocking the lock that protects the seqno. For lockless tricks, the
1202 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1205 * Returns 0 if the seqno was found within the alloted time. Else returns the
1206 * errno with remaining time filled in timeout argument.
1208 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1209 unsigned reset_counter,
1212 struct drm_i915_file_private *file_priv)
1214 struct drm_device *dev = ring->dev;
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 const bool irq_test_in_progress =
1217 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1219 unsigned long timeout_expire;
1223 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1225 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1228 timeout_expire = timeout ?
1229 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1231 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1232 gen6_rps_boost(dev_priv);
1234 mod_delayed_work(dev_priv->wq,
1235 &file_priv->mm.idle_work,
1236 msecs_to_jiffies(100));
1239 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1242 /* Record current time in case interrupted by signal, or wedged */
1243 trace_i915_gem_request_wait_begin(ring, seqno);
1244 before = ktime_get_raw_ns();
1246 struct timer_list timer;
1248 prepare_to_wait(&ring->irq_queue, &wait,
1249 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1251 /* We need to check whether any gpu reset happened in between
1252 * the caller grabbing the seqno and now ... */
1253 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1254 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1255 * is truely gone. */
1256 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1262 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1267 if (interruptible && signal_pending(current)) {
1272 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1277 timer.function = NULL;
1278 if (timeout || missed_irq(dev_priv, ring)) {
1279 unsigned long expire;
1281 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1282 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1283 mod_timer(&timer, expire);
1288 if (timer.function) {
1289 del_singleshot_timer_sync(&timer);
1290 destroy_timer_on_stack(&timer);
1293 now = ktime_get_raw_ns();
1294 trace_i915_gem_request_wait_end(ring, seqno);
1296 if (!irq_test_in_progress)
1297 ring->irq_put(ring);
1299 finish_wait(&ring->irq_queue, &wait);
1302 s64 tres = *timeout - (now - before);
1304 *timeout = tres < 0 ? 0 : tres;
1307 * Apparently ktime isn't accurate enough and occasionally has a
1308 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1309 * things up to make the test happy. We allow up to 1 jiffy.
1311 * This is a regrssion from the timespec->ktime conversion.
1313 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1321 * Waits for a sequence number to be signaled, and cleans up the
1322 * request and object lists appropriately for that event.
1325 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1327 struct drm_device *dev = ring->dev;
1328 struct drm_i915_private *dev_priv = dev->dev_private;
1329 bool interruptible = dev_priv->mm.interruptible;
1330 unsigned reset_counter;
1333 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1336 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1340 ret = i915_gem_check_olr(ring, seqno);
1344 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1345 return __i915_wait_seqno(ring, seqno, reset_counter, interruptible,
1350 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1355 /* Manually manage the write flush as we may have not yet
1356 * retired the buffer.
1358 * Note that the last_write_seqno is always the earlier of
1359 * the two (read/write) seqno, so if we haved successfully waited,
1360 * we know we have passed the last write.
1362 obj->last_write_seqno = 0;
1368 * Ensures that all rendering to the object has completed and the object is
1369 * safe to unbind from the GTT or access from the CPU.
1371 static __must_check int
1372 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1375 struct intel_engine_cs *ring = obj->ring;
1379 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1383 ret = i915_wait_seqno(ring, seqno);
1387 return i915_gem_object_wait_rendering__tail(obj);
1390 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1391 * as the object state may change during this call.
1393 static __must_check int
1394 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1395 struct drm_i915_file_private *file_priv,
1398 struct drm_device *dev = obj->base.dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 struct intel_engine_cs *ring = obj->ring;
1401 unsigned reset_counter;
1405 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1406 BUG_ON(!dev_priv->mm.interruptible);
1408 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1412 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1416 ret = i915_gem_check_olr(ring, seqno);
1420 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1421 mutex_unlock(&dev->struct_mutex);
1422 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL,
1424 mutex_lock(&dev->struct_mutex);
1428 return i915_gem_object_wait_rendering__tail(obj);
1432 * Called when user space prepares to use an object with the CPU, either
1433 * through the mmap ioctl's mapping or a GTT mapping.
1436 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1437 struct drm_file *file)
1439 struct drm_i915_gem_set_domain *args = data;
1440 struct drm_i915_gem_object *obj;
1441 uint32_t read_domains = args->read_domains;
1442 uint32_t write_domain = args->write_domain;
1445 /* Only handle setting domains to types used by the CPU. */
1446 if (write_domain & I915_GEM_GPU_DOMAINS)
1449 if (read_domains & I915_GEM_GPU_DOMAINS)
1452 /* Having something in the write domain implies it's in the read
1453 * domain, and only that read domain. Enforce that in the request.
1455 if (write_domain != 0 && read_domains != write_domain)
1458 ret = i915_mutex_lock_interruptible(dev);
1462 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1463 if (&obj->base == NULL) {
1468 /* Try to flush the object off the GPU without holding the lock.
1469 * We will repeat the flush holding the lock in the normal manner
1470 * to catch cases where we are gazumped.
1472 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1478 if (read_domains & I915_GEM_DOMAIN_GTT) {
1479 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1481 /* Silently promote "you're not bound, there was nothing to do"
1482 * to success, since the client was just asking us to
1483 * make sure everything was done.
1488 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1492 drm_gem_object_unreference(&obj->base);
1494 mutex_unlock(&dev->struct_mutex);
1499 * Called when user space has done writes to this buffer
1502 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1503 struct drm_file *file)
1505 struct drm_i915_gem_sw_finish *args = data;
1506 struct drm_i915_gem_object *obj;
1509 ret = i915_mutex_lock_interruptible(dev);
1513 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1514 if (&obj->base == NULL) {
1519 /* Pinned buffers may be scanout, so flush the cache */
1520 if (obj->pin_display)
1521 i915_gem_object_flush_cpu_write_domain(obj, true);
1523 drm_gem_object_unreference(&obj->base);
1525 mutex_unlock(&dev->struct_mutex);
1530 * Maps the contents of an object, returning the address it is mapped
1533 * While the mapping holds a reference on the contents of the object, it doesn't
1534 * imply a ref on the object itself.
1538 * DRM driver writers who look a this function as an example for how to do GEM
1539 * mmap support, please don't implement mmap support like here. The modern way
1540 * to implement DRM mmap support is with an mmap offset ioctl (like
1541 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1542 * That way debug tooling like valgrind will understand what's going on, hiding
1543 * the mmap call in a driver private ioctl will break that. The i915 driver only
1544 * does cpu mmaps this way because we didn't know better.
1547 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1548 struct drm_file *file)
1550 struct drm_i915_gem_mmap *args = data;
1551 struct drm_gem_object *obj;
1554 obj = drm_gem_object_lookup(dev, file, args->handle);
1558 /* prime objects have no backing filp to GEM mmap
1562 drm_gem_object_unreference_unlocked(obj);
1566 addr = vm_mmap(obj->filp, 0, args->size,
1567 PROT_READ | PROT_WRITE, MAP_SHARED,
1569 drm_gem_object_unreference_unlocked(obj);
1570 if (IS_ERR((void *)addr))
1573 args->addr_ptr = (uint64_t) addr;
1579 * i915_gem_fault - fault a page into the GTT
1580 * vma: VMA in question
1583 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1584 * from userspace. The fault handler takes care of binding the object to
1585 * the GTT (if needed), allocating and programming a fence register (again,
1586 * only if needed based on whether the old reg is still valid or the object
1587 * is tiled) and inserting a new PTE into the faulting process.
1589 * Note that the faulting process may involve evicting existing objects
1590 * from the GTT and/or fence registers to make room. So performance may
1591 * suffer if the GTT working set is large or there are few fence registers
1594 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1596 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1597 struct drm_device *dev = obj->base.dev;
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 pgoff_t page_offset;
1602 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1604 intel_runtime_pm_get(dev_priv);
1606 /* We don't use vmf->pgoff since that has the fake offset */
1607 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1610 ret = i915_mutex_lock_interruptible(dev);
1614 trace_i915_gem_object_fault(obj, page_offset, true, write);
1616 /* Try to flush the object off the GPU first without holding the lock.
1617 * Upon reacquiring the lock, we will perform our sanity checks and then
1618 * repeat the flush holding the lock in the normal manner to catch cases
1619 * where we are gazumped.
1621 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1625 /* Access to snoopable pages through the GTT is incoherent. */
1626 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1631 /* Now bind it into the GTT if needed */
1632 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1636 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1640 ret = i915_gem_object_get_fence(obj);
1644 /* Finally, remap it using the new GTT offset */
1645 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1648 if (!obj->fault_mappable) {
1649 unsigned long size = min_t(unsigned long,
1650 vma->vm_end - vma->vm_start,
1654 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1655 ret = vm_insert_pfn(vma,
1656 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1662 obj->fault_mappable = true;
1664 ret = vm_insert_pfn(vma,
1665 (unsigned long)vmf->virtual_address,
1668 i915_gem_object_ggtt_unpin(obj);
1670 mutex_unlock(&dev->struct_mutex);
1675 * We eat errors when the gpu is terminally wedged to avoid
1676 * userspace unduly crashing (gl has no provisions for mmaps to
1677 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1678 * and so needs to be reported.
1680 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1681 ret = VM_FAULT_SIGBUS;
1686 * EAGAIN means the gpu is hung and we'll wait for the error
1687 * handler to reset everything when re-faulting in
1688 * i915_mutex_lock_interruptible.
1695 * EBUSY is ok: this just means that another thread
1696 * already did the job.
1698 ret = VM_FAULT_NOPAGE;
1705 ret = VM_FAULT_SIGBUS;
1708 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1709 ret = VM_FAULT_SIGBUS;
1713 intel_runtime_pm_put(dev_priv);
1718 * i915_gem_release_mmap - remove physical page mappings
1719 * @obj: obj in question
1721 * Preserve the reservation of the mmapping with the DRM core code, but
1722 * relinquish ownership of the pages back to the system.
1724 * It is vital that we remove the page mapping if we have mapped a tiled
1725 * object through the GTT and then lose the fence register due to
1726 * resource pressure. Similarly if the object has been moved out of the
1727 * aperture, than pages mapped into userspace must be revoked. Removing the
1728 * mapping will then trigger a page fault on the next user access, allowing
1729 * fixup by i915_gem_fault().
1732 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1734 if (!obj->fault_mappable)
1737 drm_vma_node_unmap(&obj->base.vma_node,
1738 obj->base.dev->anon_inode->i_mapping);
1739 obj->fault_mappable = false;
1743 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1745 struct drm_i915_gem_object *obj;
1747 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1748 i915_gem_release_mmap(obj);
1752 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1756 if (INTEL_INFO(dev)->gen >= 4 ||
1757 tiling_mode == I915_TILING_NONE)
1760 /* Previous chips need a power-of-two fence region when tiling */
1761 if (INTEL_INFO(dev)->gen == 3)
1762 gtt_size = 1024*1024;
1764 gtt_size = 512*1024;
1766 while (gtt_size < size)
1773 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1774 * @obj: object to check
1776 * Return the required GTT alignment for an object, taking into account
1777 * potential fence register mapping.
1780 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1781 int tiling_mode, bool fenced)
1784 * Minimum alignment is 4k (GTT page size), but might be greater
1785 * if a fence register is needed for the object.
1787 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1788 tiling_mode == I915_TILING_NONE)
1792 * Previous chips need to be aligned to the size of the smallest
1793 * fence register that can contain the object.
1795 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1798 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1800 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1803 if (drm_vma_node_has_offset(&obj->base.vma_node))
1806 dev_priv->mm.shrinker_no_lock_stealing = true;
1808 ret = drm_gem_create_mmap_offset(&obj->base);
1812 /* Badly fragmented mmap space? The only way we can recover
1813 * space is by destroying unwanted objects. We can't randomly release
1814 * mmap_offsets as userspace expects them to be persistent for the
1815 * lifetime of the objects. The closest we can is to release the
1816 * offsets on purgeable objects by truncating it and marking it purged,
1817 * which prevents userspace from ever using that object again.
1819 i915_gem_shrink(dev_priv,
1820 obj->base.size >> PAGE_SHIFT,
1822 I915_SHRINK_UNBOUND |
1823 I915_SHRINK_PURGEABLE);
1824 ret = drm_gem_create_mmap_offset(&obj->base);
1828 i915_gem_shrink_all(dev_priv);
1829 ret = drm_gem_create_mmap_offset(&obj->base);
1831 dev_priv->mm.shrinker_no_lock_stealing = false;
1836 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1838 drm_gem_free_mmap_offset(&obj->base);
1842 i915_gem_mmap_gtt(struct drm_file *file,
1843 struct drm_device *dev,
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct drm_i915_gem_object *obj;
1851 ret = i915_mutex_lock_interruptible(dev);
1855 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1856 if (&obj->base == NULL) {
1861 if (obj->base.size > dev_priv->gtt.mappable_end) {
1866 if (obj->madv != I915_MADV_WILLNEED) {
1867 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1872 ret = i915_gem_object_create_mmap_offset(obj);
1876 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1879 drm_gem_object_unreference(&obj->base);
1881 mutex_unlock(&dev->struct_mutex);
1886 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1888 * @data: GTT mapping ioctl data
1889 * @file: GEM object info
1891 * Simply returns the fake offset to userspace so it can mmap it.
1892 * The mmap call will end up in drm_gem_mmap(), which will set things
1893 * up so we can get faults in the handler above.
1895 * The fault handler will take care of binding the object into the GTT
1896 * (since it may have been evicted to make room for something), allocating
1897 * a fence register, and mapping the appropriate aperture address into
1901 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1902 struct drm_file *file)
1904 struct drm_i915_gem_mmap_gtt *args = data;
1906 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1910 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1912 return obj->madv == I915_MADV_DONTNEED;
1915 /* Immediately discard the backing storage */
1917 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1919 i915_gem_object_free_mmap_offset(obj);
1921 if (obj->base.filp == NULL)
1924 /* Our goal here is to return as much of the memory as
1925 * is possible back to the system as we are called from OOM.
1926 * To do this we must instruct the shmfs to drop all of its
1927 * backing pages, *now*.
1929 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1930 obj->madv = __I915_MADV_PURGED;
1933 /* Try to discard unwanted pages */
1935 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1937 struct address_space *mapping;
1939 switch (obj->madv) {
1940 case I915_MADV_DONTNEED:
1941 i915_gem_object_truncate(obj);
1942 case __I915_MADV_PURGED:
1946 if (obj->base.filp == NULL)
1949 mapping = file_inode(obj->base.filp)->i_mapping,
1950 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1954 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1956 struct sg_page_iter sg_iter;
1959 BUG_ON(obj->madv == __I915_MADV_PURGED);
1961 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1963 /* In the event of a disaster, abandon all caches and
1964 * hope for the best.
1966 WARN_ON(ret != -EIO);
1967 i915_gem_clflush_object(obj, true);
1968 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1971 if (i915_gem_object_needs_bit17_swizzle(obj))
1972 i915_gem_object_save_bit_17_swizzle(obj);
1974 if (obj->madv == I915_MADV_DONTNEED)
1977 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1978 struct page *page = sg_page_iter_page(&sg_iter);
1981 set_page_dirty(page);
1983 if (obj->madv == I915_MADV_WILLNEED)
1984 mark_page_accessed(page);
1986 page_cache_release(page);
1990 sg_free_table(obj->pages);
1995 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1997 const struct drm_i915_gem_object_ops *ops = obj->ops;
1999 if (obj->pages == NULL)
2002 if (obj->pages_pin_count)
2005 BUG_ON(i915_gem_obj_bound_any(obj));
2007 /* ->put_pages might need to allocate memory for the bit17 swizzle
2008 * array, hence protect them from being reaped by removing them from gtt
2010 list_del(&obj->global_list);
2012 ops->put_pages(obj);
2015 i915_gem_object_invalidate(obj);
2021 i915_gem_shrink(struct drm_i915_private *dev_priv,
2022 long target, unsigned flags)
2025 struct list_head *list;
2028 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2029 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2032 unsigned long count = 0;
2035 * As we may completely rewrite the (un)bound list whilst unbinding
2036 * (due to retiring requests) we have to strictly process only
2037 * one element of the list at the time, and recheck the list
2038 * on every iteration.
2040 * In particular, we must hold a reference whilst removing the
2041 * object as we may end up waiting for and/or retiring the objects.
2042 * This might release the final reference (held by the active list)
2043 * and result in the object being freed from under us. This is
2044 * similar to the precautions the eviction code must take whilst
2047 * Also note that although these lists do not hold a reference to
2048 * the object we can safely grab one here: The final object
2049 * unreferencing and the bound_list are both protected by the
2050 * dev->struct_mutex and so we won't ever be able to observe an
2051 * object on the bound_list with a reference count equals 0.
2053 for (phase = phases; phase->list; phase++) {
2054 struct list_head still_in_list;
2056 if ((flags & phase->bit) == 0)
2059 INIT_LIST_HEAD(&still_in_list);
2060 while (count < target && !list_empty(phase->list)) {
2061 struct drm_i915_gem_object *obj;
2062 struct i915_vma *vma, *v;
2064 obj = list_first_entry(phase->list,
2065 typeof(*obj), global_list);
2066 list_move_tail(&obj->global_list, &still_in_list);
2068 if (flags & I915_SHRINK_PURGEABLE &&
2069 !i915_gem_object_is_purgeable(obj))
2072 drm_gem_object_reference(&obj->base);
2074 /* For the unbound phase, this should be a no-op! */
2075 list_for_each_entry_safe(vma, v,
2076 &obj->vma_list, vma_link)
2077 if (i915_vma_unbind(vma))
2080 if (i915_gem_object_put_pages(obj) == 0)
2081 count += obj->base.size >> PAGE_SHIFT;
2083 drm_gem_object_unreference(&obj->base);
2085 list_splice(&still_in_list, phase->list);
2091 static unsigned long
2092 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2094 i915_gem_evict_everything(dev_priv->dev);
2095 return i915_gem_shrink(dev_priv, LONG_MAX,
2096 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2100 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2102 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2104 struct address_space *mapping;
2105 struct sg_table *st;
2106 struct scatterlist *sg;
2107 struct sg_page_iter sg_iter;
2109 unsigned long last_pfn = 0; /* suppress gcc warning */
2112 /* Assert that the object is not currently in any GPU domain. As it
2113 * wasn't in the GTT, there shouldn't be any way it could have been in
2116 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2117 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2119 st = kmalloc(sizeof(*st), GFP_KERNEL);
2123 page_count = obj->base.size / PAGE_SIZE;
2124 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2129 /* Get the list of pages out of our struct file. They'll be pinned
2130 * at this point until we release them.
2132 * Fail silently without starting the shrinker
2134 mapping = file_inode(obj->base.filp)->i_mapping;
2135 gfp = mapping_gfp_mask(mapping);
2136 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2137 gfp &= ~(__GFP_IO | __GFP_WAIT);
2140 for (i = 0; i < page_count; i++) {
2141 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2143 i915_gem_shrink(dev_priv,
2146 I915_SHRINK_UNBOUND |
2147 I915_SHRINK_PURGEABLE);
2148 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2151 /* We've tried hard to allocate the memory by reaping
2152 * our own buffer, now let the real VM do its job and
2153 * go down in flames if truly OOM.
2155 i915_gem_shrink_all(dev_priv);
2156 page = shmem_read_mapping_page(mapping, i);
2160 #ifdef CONFIG_SWIOTLB
2161 if (swiotlb_nr_tbl()) {
2163 sg_set_page(sg, page, PAGE_SIZE, 0);
2168 if (!i || page_to_pfn(page) != last_pfn + 1) {
2172 sg_set_page(sg, page, PAGE_SIZE, 0);
2174 sg->length += PAGE_SIZE;
2176 last_pfn = page_to_pfn(page);
2178 /* Check that the i965g/gm workaround works. */
2179 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2181 #ifdef CONFIG_SWIOTLB
2182 if (!swiotlb_nr_tbl())
2187 if (i915_gem_object_needs_bit17_swizzle(obj))
2188 i915_gem_object_do_bit_17_swizzle(obj);
2190 if (obj->tiling_mode != I915_TILING_NONE &&
2191 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2192 i915_gem_object_pin_pages(obj);
2198 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2199 page_cache_release(sg_page_iter_page(&sg_iter));
2203 /* shmemfs first checks if there is enough memory to allocate the page
2204 * and reports ENOSPC should there be insufficient, along with the usual
2205 * ENOMEM for a genuine allocation failure.
2207 * We use ENOSPC in our driver to mean that we have run out of aperture
2208 * space and so want to translate the error from shmemfs back to our
2209 * usual understanding of ENOMEM.
2211 if (PTR_ERR(page) == -ENOSPC)
2214 return PTR_ERR(page);
2217 /* Ensure that the associated pages are gathered from the backing storage
2218 * and pinned into our object. i915_gem_object_get_pages() may be called
2219 * multiple times before they are released by a single call to
2220 * i915_gem_object_put_pages() - once the pages are no longer referenced
2221 * either as a result of memory pressure (reaping pages under the shrinker)
2222 * or as the object is itself released.
2225 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2227 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2228 const struct drm_i915_gem_object_ops *ops = obj->ops;
2234 if (obj->madv != I915_MADV_WILLNEED) {
2235 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2239 BUG_ON(obj->pages_pin_count);
2241 ret = ops->get_pages(obj);
2245 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2250 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2251 struct intel_engine_cs *ring)
2253 u32 seqno = intel_ring_get_seqno(ring);
2255 BUG_ON(ring == NULL);
2256 if (obj->ring != ring && obj->last_write_seqno) {
2257 /* Keep the seqno relative to the current ring */
2258 obj->last_write_seqno = seqno;
2262 /* Add a reference if we're newly entering the active list. */
2264 drm_gem_object_reference(&obj->base);
2268 list_move_tail(&obj->ring_list, &ring->active_list);
2270 obj->last_read_seqno = seqno;
2273 void i915_vma_move_to_active(struct i915_vma *vma,
2274 struct intel_engine_cs *ring)
2276 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2277 return i915_gem_object_move_to_active(vma->obj, ring);
2281 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2283 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284 struct i915_address_space *vm;
2285 struct i915_vma *vma;
2287 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2288 BUG_ON(!obj->active);
2290 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2291 vma = i915_gem_obj_to_vma(obj, vm);
2292 if (vma && !list_empty(&vma->mm_list))
2293 list_move_tail(&vma->mm_list, &vm->inactive_list);
2296 intel_fb_obj_flush(obj, true);
2298 list_del_init(&obj->ring_list);
2301 obj->last_read_seqno = 0;
2302 obj->last_write_seqno = 0;
2303 obj->base.write_domain = 0;
2305 obj->last_fenced_seqno = 0;
2308 drm_gem_object_unreference(&obj->base);
2310 WARN_ON(i915_verify_lists(dev));
2314 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2316 struct intel_engine_cs *ring = obj->ring;
2321 if (i915_seqno_passed(ring->get_seqno(ring, true),
2322 obj->last_read_seqno))
2323 i915_gem_object_move_to_inactive(obj);
2327 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct intel_engine_cs *ring;
2333 /* Carefully retire all requests without writing to the rings */
2334 for_each_ring(ring, dev_priv, i) {
2335 ret = intel_ring_idle(ring);
2339 i915_gem_retire_requests(dev);
2341 /* Finally reset hw state */
2342 for_each_ring(ring, dev_priv, i) {
2343 intel_ring_init_seqno(ring, seqno);
2345 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2346 ring->semaphore.sync_seqno[j] = 0;
2352 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2360 /* HWS page needs to be set less than what we
2361 * will inject to ring
2363 ret = i915_gem_init_seqno(dev, seqno - 1);
2367 /* Carefully set the last_seqno value so that wrap
2368 * detection still works
2370 dev_priv->next_seqno = seqno;
2371 dev_priv->last_seqno = seqno - 1;
2372 if (dev_priv->last_seqno == 0)
2373 dev_priv->last_seqno--;
2379 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2381 struct drm_i915_private *dev_priv = dev->dev_private;
2383 /* reserve 0 for non-seqno */
2384 if (dev_priv->next_seqno == 0) {
2385 int ret = i915_gem_init_seqno(dev, 0);
2389 dev_priv->next_seqno = 1;
2392 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2396 int __i915_add_request(struct intel_engine_cs *ring,
2397 struct drm_file *file,
2398 struct drm_i915_gem_object *obj,
2401 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2402 struct drm_i915_gem_request *request;
2403 struct intel_ringbuffer *ringbuf;
2404 u32 request_ring_position, request_start;
2407 request = ring->preallocated_lazy_request;
2408 if (WARN_ON(request == NULL))
2411 if (i915.enable_execlists) {
2412 struct intel_context *ctx = request->ctx;
2413 ringbuf = ctx->engine[ring->id].ringbuf;
2415 ringbuf = ring->buffer;
2417 request_start = intel_ring_get_tail(ringbuf);
2419 * Emit any outstanding flushes - execbuf can fail to emit the flush
2420 * after having emitted the batchbuffer command. Hence we need to fix
2421 * things up similar to emitting the lazy request. The difference here
2422 * is that the flush _must_ happen before the next request, no matter
2425 if (i915.enable_execlists) {
2426 ret = logical_ring_flush_all_caches(ringbuf);
2430 ret = intel_ring_flush_all_caches(ring);
2435 /* Record the position of the start of the request so that
2436 * should we detect the updated seqno part-way through the
2437 * GPU processing the request, we never over-estimate the
2438 * position of the head.
2440 request_ring_position = intel_ring_get_tail(ringbuf);
2442 if (i915.enable_execlists) {
2443 ret = ring->emit_request(ringbuf);
2447 ret = ring->add_request(ring);
2452 request->seqno = intel_ring_get_seqno(ring);
2453 request->ring = ring;
2454 request->head = request_start;
2455 request->tail = request_ring_position;
2457 /* Whilst this request exists, batch_obj will be on the
2458 * active_list, and so will hold the active reference. Only when this
2459 * request is retired will the the batch_obj be moved onto the
2460 * inactive_list and lose its active reference. Hence we do not need
2461 * to explicitly hold another reference here.
2463 request->batch_obj = obj;
2465 if (!i915.enable_execlists) {
2466 /* Hold a reference to the current context so that we can inspect
2467 * it later in case a hangcheck error event fires.
2469 request->ctx = ring->last_context;
2471 i915_gem_context_reference(request->ctx);
2474 request->emitted_jiffies = jiffies;
2475 list_add_tail(&request->list, &ring->request_list);
2476 request->file_priv = NULL;
2479 struct drm_i915_file_private *file_priv = file->driver_priv;
2481 spin_lock(&file_priv->mm.lock);
2482 request->file_priv = file_priv;
2483 list_add_tail(&request->client_list,
2484 &file_priv->mm.request_list);
2485 spin_unlock(&file_priv->mm.lock);
2488 trace_i915_gem_request_add(ring, request->seqno);
2489 ring->outstanding_lazy_seqno = 0;
2490 ring->preallocated_lazy_request = NULL;
2492 i915_queue_hangcheck(ring->dev);
2494 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2495 queue_delayed_work(dev_priv->wq,
2496 &dev_priv->mm.retire_work,
2497 round_jiffies_up_relative(HZ));
2498 intel_mark_busy(dev_priv->dev);
2501 *out_seqno = request->seqno;
2506 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2508 struct drm_i915_file_private *file_priv = request->file_priv;
2513 spin_lock(&file_priv->mm.lock);
2514 list_del(&request->client_list);
2515 request->file_priv = NULL;
2516 spin_unlock(&file_priv->mm.lock);
2519 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2520 const struct intel_context *ctx)
2522 unsigned long elapsed;
2524 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2526 if (ctx->hang_stats.banned)
2529 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2530 if (!i915_gem_context_is_default(ctx)) {
2531 DRM_DEBUG("context hanging too fast, banning!\n");
2533 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2534 if (i915_stop_ring_allow_warn(dev_priv))
2535 DRM_ERROR("gpu hanging too fast, banning!\n");
2543 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2544 struct intel_context *ctx,
2547 struct i915_ctx_hang_stats *hs;
2552 hs = &ctx->hang_stats;
2555 hs->banned = i915_context_is_banned(dev_priv, ctx);
2557 hs->guilty_ts = get_seconds();
2559 hs->batch_pending++;
2563 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2565 struct intel_context *ctx = request->ctx;
2567 list_del(&request->list);
2568 i915_gem_request_remove_from_client(request);
2571 if (i915.enable_execlists) {
2572 struct intel_engine_cs *ring = request->ring;
2574 if (ctx != ring->default_context)
2575 intel_lr_context_unpin(ring, ctx);
2577 i915_gem_context_unreference(ctx);
2582 struct drm_i915_gem_request *
2583 i915_gem_find_active_request(struct intel_engine_cs *ring)
2585 struct drm_i915_gem_request *request;
2586 u32 completed_seqno;
2588 completed_seqno = ring->get_seqno(ring, false);
2590 list_for_each_entry(request, &ring->request_list, list) {
2591 if (i915_seqno_passed(completed_seqno, request->seqno))
2600 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2601 struct intel_engine_cs *ring)
2603 struct drm_i915_gem_request *request;
2606 request = i915_gem_find_active_request(ring);
2608 if (request == NULL)
2611 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2613 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2615 list_for_each_entry_continue(request, &ring->request_list, list)
2616 i915_set_reset_status(dev_priv, request->ctx, false);
2619 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2620 struct intel_engine_cs *ring)
2622 while (!list_empty(&ring->active_list)) {
2623 struct drm_i915_gem_object *obj;
2625 obj = list_first_entry(&ring->active_list,
2626 struct drm_i915_gem_object,
2629 i915_gem_object_move_to_inactive(obj);
2633 * Clear the execlists queue up before freeing the requests, as those
2634 * are the ones that keep the context and ringbuffer backing objects
2637 while (!list_empty(&ring->execlist_queue)) {
2638 struct intel_ctx_submit_request *submit_req;
2640 submit_req = list_first_entry(&ring->execlist_queue,
2641 struct intel_ctx_submit_request,
2643 list_del(&submit_req->execlist_link);
2644 intel_runtime_pm_put(dev_priv);
2645 i915_gem_context_unreference(submit_req->ctx);
2650 * We must free the requests after all the corresponding objects have
2651 * been moved off active lists. Which is the same order as the normal
2652 * retire_requests function does. This is important if object hold
2653 * implicit references on things like e.g. ppgtt address spaces through
2656 while (!list_empty(&ring->request_list)) {
2657 struct drm_i915_gem_request *request;
2659 request = list_first_entry(&ring->request_list,
2660 struct drm_i915_gem_request,
2663 i915_gem_free_request(request);
2666 /* These may not have been flush before the reset, do so now */
2667 kfree(ring->preallocated_lazy_request);
2668 ring->preallocated_lazy_request = NULL;
2669 ring->outstanding_lazy_seqno = 0;
2672 void i915_gem_restore_fences(struct drm_device *dev)
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2677 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2678 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2681 * Commit delayed tiling changes if we have an object still
2682 * attached to the fence, otherwise just clear the fence.
2685 i915_gem_object_update_fence(reg->obj, reg,
2686 reg->obj->tiling_mode);
2688 i915_gem_write_fence(dev, i, NULL);
2693 void i915_gem_reset(struct drm_device *dev)
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 struct intel_engine_cs *ring;
2700 * Before we free the objects from the requests, we need to inspect
2701 * them for finding the guilty party. As the requests only borrow
2702 * their reference to the objects, the inspection must be done first.
2704 for_each_ring(ring, dev_priv, i)
2705 i915_gem_reset_ring_status(dev_priv, ring);
2707 for_each_ring(ring, dev_priv, i)
2708 i915_gem_reset_ring_cleanup(dev_priv, ring);
2710 i915_gem_context_reset(dev);
2712 i915_gem_restore_fences(dev);
2716 * This function clears the request list as sequence numbers are passed.
2719 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2723 if (list_empty(&ring->request_list))
2726 WARN_ON(i915_verify_lists(ring->dev));
2728 seqno = ring->get_seqno(ring, true);
2730 /* Move any buffers on the active list that are no longer referenced
2731 * by the ringbuffer to the flushing/inactive lists as appropriate,
2732 * before we free the context associated with the requests.
2734 while (!list_empty(&ring->active_list)) {
2735 struct drm_i915_gem_object *obj;
2737 obj = list_first_entry(&ring->active_list,
2738 struct drm_i915_gem_object,
2741 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2744 i915_gem_object_move_to_inactive(obj);
2748 while (!list_empty(&ring->request_list)) {
2749 struct drm_i915_gem_request *request;
2750 struct intel_ringbuffer *ringbuf;
2752 request = list_first_entry(&ring->request_list,
2753 struct drm_i915_gem_request,
2756 if (!i915_seqno_passed(seqno, request->seqno))
2759 trace_i915_gem_request_retire(ring, request->seqno);
2761 /* This is one of the few common intersection points
2762 * between legacy ringbuffer submission and execlists:
2763 * we need to tell them apart in order to find the correct
2764 * ringbuffer to which the request belongs to.
2766 if (i915.enable_execlists) {
2767 struct intel_context *ctx = request->ctx;
2768 ringbuf = ctx->engine[ring->id].ringbuf;
2770 ringbuf = ring->buffer;
2772 /* We know the GPU must have read the request to have
2773 * sent us the seqno + interrupt, so use the position
2774 * of tail of the request to update the last known position
2777 ringbuf->last_retired_head = request->tail;
2779 i915_gem_free_request(request);
2782 if (unlikely(ring->trace_irq_seqno &&
2783 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2784 ring->irq_put(ring);
2785 ring->trace_irq_seqno = 0;
2788 WARN_ON(i915_verify_lists(ring->dev));
2792 i915_gem_retire_requests(struct drm_device *dev)
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 struct intel_engine_cs *ring;
2799 for_each_ring(ring, dev_priv, i) {
2800 i915_gem_retire_requests_ring(ring);
2801 idle &= list_empty(&ring->request_list);
2802 if (i915.enable_execlists) {
2803 unsigned long flags;
2805 spin_lock_irqsave(&ring->execlist_lock, flags);
2806 idle &= list_empty(&ring->execlist_queue);
2807 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2809 intel_execlists_retire_requests(ring);
2814 mod_delayed_work(dev_priv->wq,
2815 &dev_priv->mm.idle_work,
2816 msecs_to_jiffies(100));
2822 i915_gem_retire_work_handler(struct work_struct *work)
2824 struct drm_i915_private *dev_priv =
2825 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2826 struct drm_device *dev = dev_priv->dev;
2829 /* Come back later if the device is busy... */
2831 if (mutex_trylock(&dev->struct_mutex)) {
2832 idle = i915_gem_retire_requests(dev);
2833 mutex_unlock(&dev->struct_mutex);
2836 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2837 round_jiffies_up_relative(HZ));
2841 i915_gem_idle_work_handler(struct work_struct *work)
2843 struct drm_i915_private *dev_priv =
2844 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2846 intel_mark_idle(dev_priv->dev);
2850 * Ensures that an object will eventually get non-busy by flushing any required
2851 * write domains, emitting any outstanding lazy request and retiring and
2852 * completed requests.
2855 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2860 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2864 i915_gem_retire_requests_ring(obj->ring);
2871 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2872 * @DRM_IOCTL_ARGS: standard ioctl arguments
2874 * Returns 0 if successful, else an error is returned with the remaining time in
2875 * the timeout parameter.
2876 * -ETIME: object is still busy after timeout
2877 * -ERESTARTSYS: signal interrupted the wait
2878 * -ENONENT: object doesn't exist
2879 * Also possible, but rare:
2880 * -EAGAIN: GPU wedged
2882 * -ENODEV: Internal IRQ fail
2883 * -E?: The add request failed
2885 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2886 * non-zero timeout parameter the wait ioctl will wait for the given number of
2887 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2888 * without holding struct_mutex the object may become re-busied before this
2889 * function completes. A similar but shorter * race condition exists in the busy
2893 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 struct drm_i915_gem_wait *args = data;
2897 struct drm_i915_gem_object *obj;
2898 struct intel_engine_cs *ring = NULL;
2899 unsigned reset_counter;
2903 if (args->flags != 0)
2906 ret = i915_mutex_lock_interruptible(dev);
2910 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2911 if (&obj->base == NULL) {
2912 mutex_unlock(&dev->struct_mutex);
2916 /* Need to make sure the object gets inactive eventually. */
2917 ret = i915_gem_object_flush_active(obj);
2922 seqno = obj->last_read_seqno;
2929 /* Do this after OLR check to make sure we make forward progress polling
2930 * on this IOCTL with a timeout <=0 (like busy ioctl)
2932 if (args->timeout_ns <= 0) {
2937 drm_gem_object_unreference(&obj->base);
2938 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2939 mutex_unlock(&dev->struct_mutex);
2941 return __i915_wait_seqno(ring, seqno, reset_counter, true,
2942 &args->timeout_ns, file->driver_priv);
2945 drm_gem_object_unreference(&obj->base);
2946 mutex_unlock(&dev->struct_mutex);
2951 * i915_gem_object_sync - sync an object to a ring.
2953 * @obj: object which may be in use on another ring.
2954 * @to: ring we wish to use the object on. May be NULL.
2956 * This code is meant to abstract object synchronization with the GPU.
2957 * Calling with NULL implies synchronizing the object with the CPU
2958 * rather than a particular GPU ring.
2960 * Returns 0 if successful, else propagates up the lower layer error.
2963 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2964 struct intel_engine_cs *to)
2966 struct intel_engine_cs *from = obj->ring;
2970 if (from == NULL || to == from)
2973 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2974 return i915_gem_object_wait_rendering(obj, false);
2976 idx = intel_ring_sync_index(from, to);
2978 seqno = obj->last_read_seqno;
2979 /* Optimization: Avoid semaphore sync when we are sure we already
2980 * waited for an object with higher seqno */
2981 if (seqno <= from->semaphore.sync_seqno[idx])
2984 ret = i915_gem_check_olr(obj->ring, seqno);
2988 trace_i915_gem_ring_sync_to(from, to, seqno);
2989 ret = to->semaphore.sync_to(to, from, seqno);
2991 /* We use last_read_seqno because sync_to()
2992 * might have just caused seqno wrap under
2995 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
3000 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3002 u32 old_write_domain, old_read_domains;
3004 /* Force a pagefault for domain tracking on next user access */
3005 i915_gem_release_mmap(obj);
3007 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3010 /* Wait for any direct GTT access to complete */
3013 old_read_domains = obj->base.read_domains;
3014 old_write_domain = obj->base.write_domain;
3016 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3017 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3019 trace_i915_gem_object_change_domain(obj,
3024 int i915_vma_unbind(struct i915_vma *vma)
3026 struct drm_i915_gem_object *obj = vma->obj;
3027 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3030 if (list_empty(&vma->vma_link))
3033 if (!drm_mm_node_allocated(&vma->node)) {
3034 i915_gem_vma_destroy(vma);
3041 BUG_ON(obj->pages == NULL);
3043 ret = i915_gem_object_finish_gpu(obj);
3046 /* Continue on if we fail due to EIO, the GPU is hung so we
3047 * should be safe and we need to cleanup or else we might
3048 * cause memory corruption through use-after-free.
3051 /* Throw away the active reference before moving to the unbound list */
3052 i915_gem_object_retire(obj);
3054 if (i915_is_ggtt(vma->vm)) {
3055 i915_gem_object_finish_gtt(obj);
3057 /* release the fence reg _after_ flushing */
3058 ret = i915_gem_object_put_fence(obj);
3063 trace_i915_vma_unbind(vma);
3065 vma->unbind_vma(vma);
3067 list_del_init(&vma->mm_list);
3068 if (i915_is_ggtt(vma->vm))
3069 obj->map_and_fenceable = false;
3071 drm_mm_remove_node(&vma->node);
3072 i915_gem_vma_destroy(vma);
3074 /* Since the unbound list is global, only move to that list if
3075 * no more VMAs exist. */
3076 if (list_empty(&obj->vma_list)) {
3077 i915_gem_gtt_finish_object(obj);
3078 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3081 /* And finally now the object is completely decoupled from this vma,
3082 * we can drop its hold on the backing storage and allow it to be
3083 * reaped by the shrinker.
3085 i915_gem_object_unpin_pages(obj);
3090 int i915_gpu_idle(struct drm_device *dev)
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct intel_engine_cs *ring;
3096 /* Flush everything onto the inactive list. */
3097 for_each_ring(ring, dev_priv, i) {
3098 if (!i915.enable_execlists) {
3099 ret = i915_switch_context(ring, ring->default_context);
3104 ret = intel_ring_idle(ring);
3112 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3113 struct drm_i915_gem_object *obj)
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3117 int fence_pitch_shift;
3119 if (INTEL_INFO(dev)->gen >= 6) {
3120 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3121 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3123 fence_reg = FENCE_REG_965_0;
3124 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3127 fence_reg += reg * 8;
3129 /* To w/a incoherency with non-atomic 64-bit register updates,
3130 * we split the 64-bit update into two 32-bit writes. In order
3131 * for a partial fence not to be evaluated between writes, we
3132 * precede the update with write to turn off the fence register,
3133 * and only enable the fence as the last step.
3135 * For extra levels of paranoia, we make sure each step lands
3136 * before applying the next step.
3138 I915_WRITE(fence_reg, 0);
3139 POSTING_READ(fence_reg);
3142 u32 size = i915_gem_obj_ggtt_size(obj);
3145 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3147 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3148 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3149 if (obj->tiling_mode == I915_TILING_Y)
3150 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3151 val |= I965_FENCE_REG_VALID;
3153 I915_WRITE(fence_reg + 4, val >> 32);
3154 POSTING_READ(fence_reg + 4);
3156 I915_WRITE(fence_reg + 0, val);
3157 POSTING_READ(fence_reg);
3159 I915_WRITE(fence_reg + 4, 0);
3160 POSTING_READ(fence_reg + 4);
3164 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3165 struct drm_i915_gem_object *obj)
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3171 u32 size = i915_gem_obj_ggtt_size(obj);
3175 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3176 (size & -size) != size ||
3177 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3178 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3179 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3181 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3186 /* Note: pitch better be a power of two tile widths */
3187 pitch_val = obj->stride / tile_width;
3188 pitch_val = ffs(pitch_val) - 1;
3190 val = i915_gem_obj_ggtt_offset(obj);
3191 if (obj->tiling_mode == I915_TILING_Y)
3192 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3193 val |= I915_FENCE_SIZE_BITS(size);
3194 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3195 val |= I830_FENCE_REG_VALID;
3200 reg = FENCE_REG_830_0 + reg * 4;
3202 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3204 I915_WRITE(reg, val);
3208 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3209 struct drm_i915_gem_object *obj)
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3215 u32 size = i915_gem_obj_ggtt_size(obj);
3218 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3219 (size & -size) != size ||
3220 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3221 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3222 i915_gem_obj_ggtt_offset(obj), size);
3224 pitch_val = obj->stride / 128;
3225 pitch_val = ffs(pitch_val) - 1;
3227 val = i915_gem_obj_ggtt_offset(obj);
3228 if (obj->tiling_mode == I915_TILING_Y)
3229 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3230 val |= I830_FENCE_SIZE_BITS(size);
3231 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3232 val |= I830_FENCE_REG_VALID;
3236 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3237 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3240 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3242 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3245 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3246 struct drm_i915_gem_object *obj)
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3250 /* Ensure that all CPU reads are completed before installing a fence
3251 * and all writes before removing the fence.
3253 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3256 WARN(obj && (!obj->stride || !obj->tiling_mode),
3257 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3258 obj->stride, obj->tiling_mode);
3260 switch (INTEL_INFO(dev)->gen) {
3266 case 4: i965_write_fence_reg(dev, reg, obj); break;
3267 case 3: i915_write_fence_reg(dev, reg, obj); break;
3268 case 2: i830_write_fence_reg(dev, reg, obj); break;
3272 /* And similarly be paranoid that no direct access to this region
3273 * is reordered to before the fence is installed.
3275 if (i915_gem_object_needs_mb(obj))
3279 static inline int fence_number(struct drm_i915_private *dev_priv,
3280 struct drm_i915_fence_reg *fence)
3282 return fence - dev_priv->fence_regs;
3285 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3286 struct drm_i915_fence_reg *fence,
3289 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3290 int reg = fence_number(dev_priv, fence);
3292 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3295 obj->fence_reg = reg;
3297 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3299 obj->fence_reg = I915_FENCE_REG_NONE;
3301 list_del_init(&fence->lru_list);
3303 obj->fence_dirty = false;
3307 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3309 if (obj->last_fenced_seqno) {
3310 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3314 obj->last_fenced_seqno = 0;
3321 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3323 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3324 struct drm_i915_fence_reg *fence;
3327 ret = i915_gem_object_wait_fence(obj);
3331 if (obj->fence_reg == I915_FENCE_REG_NONE)
3334 fence = &dev_priv->fence_regs[obj->fence_reg];
3336 if (WARN_ON(fence->pin_count))
3339 i915_gem_object_fence_lost(obj);
3340 i915_gem_object_update_fence(obj, fence, false);
3345 static struct drm_i915_fence_reg *
3346 i915_find_fence_reg(struct drm_device *dev)
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 struct drm_i915_fence_reg *reg, *avail;
3352 /* First try to find a free reg */
3354 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3355 reg = &dev_priv->fence_regs[i];
3359 if (!reg->pin_count)
3366 /* None available, try to steal one or wait for a user to finish */
3367 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3375 /* Wait for completion of pending flips which consume fences */
3376 if (intel_has_pending_fb_unpin(dev))
3377 return ERR_PTR(-EAGAIN);
3379 return ERR_PTR(-EDEADLK);
3383 * i915_gem_object_get_fence - set up fencing for an object
3384 * @obj: object to map through a fence reg
3386 * When mapping objects through the GTT, userspace wants to be able to write
3387 * to them without having to worry about swizzling if the object is tiled.
3388 * This function walks the fence regs looking for a free one for @obj,
3389 * stealing one if it can't find any.
3391 * It then sets up the reg based on the object's properties: address, pitch
3392 * and tiling format.
3394 * For an untiled surface, this removes any existing fence.
3397 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3399 struct drm_device *dev = obj->base.dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 bool enable = obj->tiling_mode != I915_TILING_NONE;
3402 struct drm_i915_fence_reg *reg;
3405 /* Have we updated the tiling parameters upon the object and so
3406 * will need to serialise the write to the associated fence register?
3408 if (obj->fence_dirty) {
3409 ret = i915_gem_object_wait_fence(obj);
3414 /* Just update our place in the LRU if our fence is getting reused. */
3415 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3416 reg = &dev_priv->fence_regs[obj->fence_reg];
3417 if (!obj->fence_dirty) {
3418 list_move_tail(®->lru_list,
3419 &dev_priv->mm.fence_list);
3422 } else if (enable) {
3423 if (WARN_ON(!obj->map_and_fenceable))
3426 reg = i915_find_fence_reg(dev);
3428 return PTR_ERR(reg);
3431 struct drm_i915_gem_object *old = reg->obj;
3433 ret = i915_gem_object_wait_fence(old);
3437 i915_gem_object_fence_lost(old);
3442 i915_gem_object_update_fence(obj, reg, enable);
3447 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3448 unsigned long cache_level)
3450 struct drm_mm_node *gtt_space = &vma->node;
3451 struct drm_mm_node *other;
3454 * On some machines we have to be careful when putting differing types
3455 * of snoopable memory together to avoid the prefetcher crossing memory
3456 * domains and dying. During vm initialisation, we decide whether or not
3457 * these constraints apply and set the drm_mm.color_adjust
3460 if (vma->vm->mm.color_adjust == NULL)
3463 if (!drm_mm_node_allocated(gtt_space))
3466 if (list_empty(>t_space->node_list))
3469 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3470 if (other->allocated && !other->hole_follows && other->color != cache_level)
3473 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3474 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3481 * Finds free space in the GTT aperture and binds the object there.
3483 static struct i915_vma *
3484 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3485 struct i915_address_space *vm,
3489 struct drm_device *dev = obj->base.dev;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 u32 size, fence_size, fence_alignment, unfenced_alignment;
3492 unsigned long start =
3493 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3495 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3496 struct i915_vma *vma;
3499 fence_size = i915_gem_get_gtt_size(dev,
3502 fence_alignment = i915_gem_get_gtt_alignment(dev,
3504 obj->tiling_mode, true);
3505 unfenced_alignment =
3506 i915_gem_get_gtt_alignment(dev,
3508 obj->tiling_mode, false);
3511 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3513 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3514 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3515 return ERR_PTR(-EINVAL);
3518 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3520 /* If the object is bigger than the entire aperture, reject it early
3521 * before evicting everything in a vain attempt to find space.
3523 if (obj->base.size > end) {
3524 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3526 flags & PIN_MAPPABLE ? "mappable" : "total",
3528 return ERR_PTR(-E2BIG);
3531 ret = i915_gem_object_get_pages(obj);
3533 return ERR_PTR(ret);
3535 i915_gem_object_pin_pages(obj);
3537 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3542 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3546 DRM_MM_SEARCH_DEFAULT,
3547 DRM_MM_CREATE_DEFAULT);
3549 ret = i915_gem_evict_something(dev, vm, size, alignment,
3558 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3560 goto err_remove_node;
3563 ret = i915_gem_gtt_prepare_object(obj);
3565 goto err_remove_node;
3567 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3568 list_add_tail(&vma->mm_list, &vm->inactive_list);
3570 trace_i915_vma_bind(vma, flags);
3571 vma->bind_vma(vma, obj->cache_level,
3572 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3577 drm_mm_remove_node(&vma->node);
3579 i915_gem_vma_destroy(vma);
3582 i915_gem_object_unpin_pages(obj);
3587 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3590 /* If we don't have a page list set up, then we're not pinned
3591 * to GPU, and we can ignore the cache flush because it'll happen
3592 * again at bind time.
3594 if (obj->pages == NULL)
3598 * Stolen memory is always coherent with the GPU as it is explicitly
3599 * marked as wc by the system, or the system is cache-coherent.
3601 if (obj->stolen || obj->phys_handle)
3604 /* If the GPU is snooping the contents of the CPU cache,
3605 * we do not need to manually clear the CPU cache lines. However,
3606 * the caches are only snooped when the render cache is
3607 * flushed/invalidated. As we always have to emit invalidations
3608 * and flushes when moving into and out of the RENDER domain, correct
3609 * snooping behaviour occurs naturally as the result of our domain
3612 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3615 trace_i915_gem_object_clflush(obj);
3616 drm_clflush_sg(obj->pages);
3621 /** Flushes the GTT write domain for the object if it's dirty. */
3623 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3625 uint32_t old_write_domain;
3627 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3630 /* No actual flushing is required for the GTT write domain. Writes
3631 * to it immediately go to main memory as far as we know, so there's
3632 * no chipset flush. It also doesn't land in render cache.
3634 * However, we do have to enforce the order so that all writes through
3635 * the GTT land before any writes to the device, such as updates to
3640 old_write_domain = obj->base.write_domain;
3641 obj->base.write_domain = 0;
3643 intel_fb_obj_flush(obj, false);
3645 trace_i915_gem_object_change_domain(obj,
3646 obj->base.read_domains,
3650 /** Flushes the CPU write domain for the object if it's dirty. */
3652 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3655 uint32_t old_write_domain;
3657 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3660 if (i915_gem_clflush_object(obj, force))
3661 i915_gem_chipset_flush(obj->base.dev);
3663 old_write_domain = obj->base.write_domain;
3664 obj->base.write_domain = 0;
3666 intel_fb_obj_flush(obj, false);
3668 trace_i915_gem_object_change_domain(obj,
3669 obj->base.read_domains,
3674 * Moves a single object to the GTT read, and possibly write domain.
3676 * This function returns when the move is complete, including waiting on
3680 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3682 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3683 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3684 uint32_t old_write_domain, old_read_domains;
3687 /* Not valid to be called on unbound objects. */
3691 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3694 ret = i915_gem_object_wait_rendering(obj, !write);
3698 i915_gem_object_retire(obj);
3699 i915_gem_object_flush_cpu_write_domain(obj, false);
3701 /* Serialise direct access to this object with the barriers for
3702 * coherent writes from the GPU, by effectively invalidating the
3703 * GTT domain upon first access.
3705 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3708 old_write_domain = obj->base.write_domain;
3709 old_read_domains = obj->base.read_domains;
3711 /* It should now be out of any other write domains, and we can update
3712 * the domain values for our changes.
3714 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3715 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3717 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3718 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3723 intel_fb_obj_invalidate(obj, NULL);
3725 trace_i915_gem_object_change_domain(obj,
3729 /* And bump the LRU for this access */
3730 if (i915_gem_object_is_inactive(obj))
3731 list_move_tail(&vma->mm_list,
3732 &dev_priv->gtt.base.inactive_list);
3737 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3738 enum i915_cache_level cache_level)
3740 struct drm_device *dev = obj->base.dev;
3741 struct i915_vma *vma, *next;
3744 if (obj->cache_level == cache_level)
3747 if (i915_gem_obj_is_pinned(obj)) {
3748 DRM_DEBUG("can not change the cache level of pinned objects\n");
3752 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3753 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3754 ret = i915_vma_unbind(vma);
3760 if (i915_gem_obj_bound_any(obj)) {
3761 ret = i915_gem_object_finish_gpu(obj);
3765 i915_gem_object_finish_gtt(obj);
3767 /* Before SandyBridge, you could not use tiling or fence
3768 * registers with snooped memory, so relinquish any fences
3769 * currently pointing to our region in the aperture.
3771 if (INTEL_INFO(dev)->gen < 6) {
3772 ret = i915_gem_object_put_fence(obj);
3777 list_for_each_entry(vma, &obj->vma_list, vma_link)
3778 if (drm_mm_node_allocated(&vma->node))
3779 vma->bind_vma(vma, cache_level,
3780 vma->bound & GLOBAL_BIND);
3783 list_for_each_entry(vma, &obj->vma_list, vma_link)
3784 vma->node.color = cache_level;
3785 obj->cache_level = cache_level;
3787 if (cpu_write_needs_clflush(obj)) {
3788 u32 old_read_domains, old_write_domain;
3790 /* If we're coming from LLC cached, then we haven't
3791 * actually been tracking whether the data is in the
3792 * CPU cache or not, since we only allow one bit set
3793 * in obj->write_domain and have been skipping the clflushes.
3794 * Just set it to the CPU cache for now.
3796 i915_gem_object_retire(obj);
3797 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3799 old_read_domains = obj->base.read_domains;
3800 old_write_domain = obj->base.write_domain;
3802 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3803 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3805 trace_i915_gem_object_change_domain(obj,
3813 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3814 struct drm_file *file)
3816 struct drm_i915_gem_caching *args = data;
3817 struct drm_i915_gem_object *obj;
3820 ret = i915_mutex_lock_interruptible(dev);
3824 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3825 if (&obj->base == NULL) {
3830 switch (obj->cache_level) {
3831 case I915_CACHE_LLC:
3832 case I915_CACHE_L3_LLC:
3833 args->caching = I915_CACHING_CACHED;
3837 args->caching = I915_CACHING_DISPLAY;
3841 args->caching = I915_CACHING_NONE;
3845 drm_gem_object_unreference(&obj->base);
3847 mutex_unlock(&dev->struct_mutex);
3851 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3852 struct drm_file *file)
3854 struct drm_i915_gem_caching *args = data;
3855 struct drm_i915_gem_object *obj;
3856 enum i915_cache_level level;
3859 switch (args->caching) {
3860 case I915_CACHING_NONE:
3861 level = I915_CACHE_NONE;
3863 case I915_CACHING_CACHED:
3864 level = I915_CACHE_LLC;
3866 case I915_CACHING_DISPLAY:
3867 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3873 ret = i915_mutex_lock_interruptible(dev);
3877 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3878 if (&obj->base == NULL) {
3883 ret = i915_gem_object_set_cache_level(obj, level);
3885 drm_gem_object_unreference(&obj->base);
3887 mutex_unlock(&dev->struct_mutex);
3891 static bool is_pin_display(struct drm_i915_gem_object *obj)
3893 struct i915_vma *vma;
3895 vma = i915_gem_obj_to_ggtt(obj);
3899 /* There are 3 sources that pin objects:
3900 * 1. The display engine (scanouts, sprites, cursors);
3901 * 2. Reservations for execbuffer;
3904 * We can ignore reservations as we hold the struct_mutex and
3905 * are only called outside of the reservation path. The user
3906 * can only increment pin_count once, and so if after
3907 * subtracting the potential reference by the user, any pin_count
3908 * remains, it must be due to another use by the display engine.
3910 return vma->pin_count - !!obj->user_pin_count;
3914 * Prepare buffer for display plane (scanout, cursors, etc).
3915 * Can be called from an uninterruptible phase (modesetting) and allows
3916 * any flushes to be pipelined (for pageflips).
3919 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3921 struct intel_engine_cs *pipelined)
3923 u32 old_read_domains, old_write_domain;
3924 bool was_pin_display;
3927 if (pipelined != obj->ring) {
3928 ret = i915_gem_object_sync(obj, pipelined);
3933 /* Mark the pin_display early so that we account for the
3934 * display coherency whilst setting up the cache domains.
3936 was_pin_display = obj->pin_display;
3937 obj->pin_display = true;
3939 /* The display engine is not coherent with the LLC cache on gen6. As
3940 * a result, we make sure that the pinning that is about to occur is
3941 * done with uncached PTEs. This is lowest common denominator for all
3944 * However for gen6+, we could do better by using the GFDT bit instead
3945 * of uncaching, which would allow us to flush all the LLC-cached data
3946 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3948 ret = i915_gem_object_set_cache_level(obj,
3949 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3951 goto err_unpin_display;
3953 /* As the user may map the buffer once pinned in the display plane
3954 * (e.g. libkms for the bootup splash), we have to ensure that we
3955 * always use map_and_fenceable for all scanout buffers.
3957 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3959 goto err_unpin_display;
3961 i915_gem_object_flush_cpu_write_domain(obj, true);
3963 old_write_domain = obj->base.write_domain;
3964 old_read_domains = obj->base.read_domains;
3966 /* It should now be out of any other write domains, and we can update
3967 * the domain values for our changes.
3969 obj->base.write_domain = 0;
3970 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3972 trace_i915_gem_object_change_domain(obj,
3979 WARN_ON(was_pin_display != is_pin_display(obj));
3980 obj->pin_display = was_pin_display;
3985 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3987 i915_gem_object_ggtt_unpin(obj);
3988 obj->pin_display = is_pin_display(obj);
3992 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3996 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3999 ret = i915_gem_object_wait_rendering(obj, false);
4003 /* Ensure that we invalidate the GPU's caches and TLBs. */
4004 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4009 * Moves a single object to the CPU read, and possibly write domain.
4011 * This function returns when the move is complete, including waiting on
4015 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4017 uint32_t old_write_domain, old_read_domains;
4020 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4023 ret = i915_gem_object_wait_rendering(obj, !write);
4027 i915_gem_object_retire(obj);
4028 i915_gem_object_flush_gtt_write_domain(obj);
4030 old_write_domain = obj->base.write_domain;
4031 old_read_domains = obj->base.read_domains;
4033 /* Flush the CPU cache if it's still invalid. */
4034 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4035 i915_gem_clflush_object(obj, false);
4037 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4040 /* It should now be out of any other write domains, and we can update
4041 * the domain values for our changes.
4043 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4045 /* If we're writing through the CPU, then the GPU read domains will
4046 * need to be invalidated at next use.
4049 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4050 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4054 intel_fb_obj_invalidate(obj, NULL);
4056 trace_i915_gem_object_change_domain(obj,
4063 /* Throttle our rendering by waiting until the ring has completed our requests
4064 * emitted over 20 msec ago.
4066 * Note that if we were to use the current jiffies each time around the loop,
4067 * we wouldn't escape the function with any frames outstanding if the time to
4068 * render a frame was over 20ms.
4070 * This should get us reasonable parallelism between CPU and GPU but also
4071 * relatively low latency when blocking on a particular request to finish.
4074 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct drm_i915_file_private *file_priv = file->driver_priv;
4078 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4079 struct drm_i915_gem_request *request;
4080 struct intel_engine_cs *ring = NULL;
4081 unsigned reset_counter;
4085 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4089 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4093 spin_lock(&file_priv->mm.lock);
4094 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4095 if (time_after_eq(request->emitted_jiffies, recent_enough))
4098 ring = request->ring;
4099 seqno = request->seqno;
4101 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4102 spin_unlock(&file_priv->mm.lock);
4107 ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4109 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4115 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4117 struct drm_i915_gem_object *obj = vma->obj;
4120 vma->node.start & (alignment - 1))
4123 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4126 if (flags & PIN_OFFSET_BIAS &&
4127 vma->node.start < (flags & PIN_OFFSET_MASK))
4134 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4135 struct i915_address_space *vm,
4139 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4140 struct i915_vma *vma;
4144 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4147 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4150 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4153 vma = i915_gem_obj_to_vma(obj, vm);
4155 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4158 if (i915_vma_misplaced(vma, alignment, flags)) {
4159 WARN(vma->pin_count,
4160 "bo is already pinned with incorrect alignment:"
4161 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4162 " obj->map_and_fenceable=%d\n",
4163 i915_gem_obj_offset(obj, vm), alignment,
4164 !!(flags & PIN_MAPPABLE),
4165 obj->map_and_fenceable);
4166 ret = i915_vma_unbind(vma);
4174 bound = vma ? vma->bound : 0;
4175 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4176 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4178 return PTR_ERR(vma);
4181 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
4182 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4184 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4185 bool mappable, fenceable;
4186 u32 fence_size, fence_alignment;
4188 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4191 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4196 fenceable = (vma->node.size == fence_size &&
4197 (vma->node.start & (fence_alignment - 1)) == 0);
4199 mappable = (vma->node.start + obj->base.size <=
4200 dev_priv->gtt.mappable_end);
4202 obj->map_and_fenceable = mappable && fenceable;
4205 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4208 if (flags & PIN_MAPPABLE)
4209 obj->pin_mappable |= true;
4215 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4217 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4220 BUG_ON(vma->pin_count == 0);
4221 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4223 if (--vma->pin_count == 0)
4224 obj->pin_mappable = false;
4228 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4230 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4231 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4232 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4234 WARN_ON(!ggtt_vma ||
4235 dev_priv->fence_regs[obj->fence_reg].pin_count >
4236 ggtt_vma->pin_count);
4237 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4244 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4246 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4248 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4249 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4254 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4255 struct drm_file *file)
4257 struct drm_i915_gem_pin *args = data;
4258 struct drm_i915_gem_object *obj;
4261 if (drm_core_check_feature(dev, DRIVER_MODESET))
4264 ret = i915_mutex_lock_interruptible(dev);
4268 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4269 if (&obj->base == NULL) {
4274 if (obj->madv != I915_MADV_WILLNEED) {
4275 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4280 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4281 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4287 if (obj->user_pin_count == ULONG_MAX) {
4292 if (obj->user_pin_count == 0) {
4293 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4298 obj->user_pin_count++;
4299 obj->pin_filp = file;
4301 args->offset = i915_gem_obj_ggtt_offset(obj);
4303 drm_gem_object_unreference(&obj->base);
4305 mutex_unlock(&dev->struct_mutex);
4310 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4311 struct drm_file *file)
4313 struct drm_i915_gem_pin *args = data;
4314 struct drm_i915_gem_object *obj;
4317 if (drm_core_check_feature(dev, DRIVER_MODESET))
4320 ret = i915_mutex_lock_interruptible(dev);
4324 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4325 if (&obj->base == NULL) {
4330 if (obj->pin_filp != file) {
4331 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4336 obj->user_pin_count--;
4337 if (obj->user_pin_count == 0) {
4338 obj->pin_filp = NULL;
4339 i915_gem_object_ggtt_unpin(obj);
4343 drm_gem_object_unreference(&obj->base);
4345 mutex_unlock(&dev->struct_mutex);
4350 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4351 struct drm_file *file)
4353 struct drm_i915_gem_busy *args = data;
4354 struct drm_i915_gem_object *obj;
4357 ret = i915_mutex_lock_interruptible(dev);
4361 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4362 if (&obj->base == NULL) {
4367 /* Count all active objects as busy, even if they are currently not used
4368 * by the gpu. Users of this interface expect objects to eventually
4369 * become non-busy without any further actions, therefore emit any
4370 * necessary flushes here.
4372 ret = i915_gem_object_flush_active(obj);
4374 args->busy = obj->active;
4376 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4377 args->busy |= intel_ring_flag(obj->ring) << 16;
4380 drm_gem_object_unreference(&obj->base);
4382 mutex_unlock(&dev->struct_mutex);
4387 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4388 struct drm_file *file_priv)
4390 return i915_gem_ring_throttle(dev, file_priv);
4394 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4395 struct drm_file *file_priv)
4397 struct drm_i915_private *dev_priv = dev->dev_private;
4398 struct drm_i915_gem_madvise *args = data;
4399 struct drm_i915_gem_object *obj;
4402 switch (args->madv) {
4403 case I915_MADV_DONTNEED:
4404 case I915_MADV_WILLNEED:
4410 ret = i915_mutex_lock_interruptible(dev);
4414 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4415 if (&obj->base == NULL) {
4420 if (i915_gem_obj_is_pinned(obj)) {
4426 obj->tiling_mode != I915_TILING_NONE &&
4427 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4428 if (obj->madv == I915_MADV_WILLNEED)
4429 i915_gem_object_unpin_pages(obj);
4430 if (args->madv == I915_MADV_WILLNEED)
4431 i915_gem_object_pin_pages(obj);
4434 if (obj->madv != __I915_MADV_PURGED)
4435 obj->madv = args->madv;
4437 /* if the object is no longer attached, discard its backing storage */
4438 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4439 i915_gem_object_truncate(obj);
4441 args->retained = obj->madv != __I915_MADV_PURGED;
4444 drm_gem_object_unreference(&obj->base);
4446 mutex_unlock(&dev->struct_mutex);
4450 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4451 const struct drm_i915_gem_object_ops *ops)
4453 INIT_LIST_HEAD(&obj->global_list);
4454 INIT_LIST_HEAD(&obj->ring_list);
4455 INIT_LIST_HEAD(&obj->obj_exec_link);
4456 INIT_LIST_HEAD(&obj->vma_list);
4460 obj->fence_reg = I915_FENCE_REG_NONE;
4461 obj->madv = I915_MADV_WILLNEED;
4463 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4466 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4467 .get_pages = i915_gem_object_get_pages_gtt,
4468 .put_pages = i915_gem_object_put_pages_gtt,
4471 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4474 struct drm_i915_gem_object *obj;
4475 struct address_space *mapping;
4478 obj = i915_gem_object_alloc(dev);
4482 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4483 i915_gem_object_free(obj);
4487 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4488 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4489 /* 965gm cannot relocate objects above 4GiB. */
4490 mask &= ~__GFP_HIGHMEM;
4491 mask |= __GFP_DMA32;
4494 mapping = file_inode(obj->base.filp)->i_mapping;
4495 mapping_set_gfp_mask(mapping, mask);
4497 i915_gem_object_init(obj, &i915_gem_object_ops);
4499 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4500 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4503 /* On some devices, we can have the GPU use the LLC (the CPU
4504 * cache) for about a 10% performance improvement
4505 * compared to uncached. Graphics requests other than
4506 * display scanout are coherent with the CPU in
4507 * accessing this cache. This means in this mode we
4508 * don't need to clflush on the CPU side, and on the
4509 * GPU side we only need to flush internal caches to
4510 * get data visible to the CPU.
4512 * However, we maintain the display planes as UC, and so
4513 * need to rebind when first used as such.
4515 obj->cache_level = I915_CACHE_LLC;
4517 obj->cache_level = I915_CACHE_NONE;
4519 trace_i915_gem_object_create(obj);
4524 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4526 /* If we are the last user of the backing storage (be it shmemfs
4527 * pages or stolen etc), we know that the pages are going to be
4528 * immediately released. In this case, we can then skip copying
4529 * back the contents from the GPU.
4532 if (obj->madv != I915_MADV_WILLNEED)
4535 if (obj->base.filp == NULL)
4538 /* At first glance, this looks racy, but then again so would be
4539 * userspace racing mmap against close. However, the first external
4540 * reference to the filp can only be obtained through the
4541 * i915_gem_mmap_ioctl() which safeguards us against the user
4542 * acquiring such a reference whilst we are in the middle of
4543 * freeing the object.
4545 return atomic_long_read(&obj->base.filp->f_count) == 1;
4548 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4550 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4551 struct drm_device *dev = obj->base.dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 struct i915_vma *vma, *next;
4555 intel_runtime_pm_get(dev_priv);
4557 trace_i915_gem_object_destroy(obj);
4559 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4563 ret = i915_vma_unbind(vma);
4564 if (WARN_ON(ret == -ERESTARTSYS)) {
4565 bool was_interruptible;
4567 was_interruptible = dev_priv->mm.interruptible;
4568 dev_priv->mm.interruptible = false;
4570 WARN_ON(i915_vma_unbind(vma));
4572 dev_priv->mm.interruptible = was_interruptible;
4576 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4577 * before progressing. */
4579 i915_gem_object_unpin_pages(obj);
4581 WARN_ON(obj->frontbuffer_bits);
4583 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4584 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4585 obj->tiling_mode != I915_TILING_NONE)
4586 i915_gem_object_unpin_pages(obj);
4588 if (WARN_ON(obj->pages_pin_count))
4589 obj->pages_pin_count = 0;
4590 if (discard_backing_storage(obj))
4591 obj->madv = I915_MADV_DONTNEED;
4592 i915_gem_object_put_pages(obj);
4593 i915_gem_object_free_mmap_offset(obj);
4597 if (obj->base.import_attach)
4598 drm_prime_gem_destroy(&obj->base, NULL);
4600 if (obj->ops->release)
4601 obj->ops->release(obj);
4603 drm_gem_object_release(&obj->base);
4604 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4607 i915_gem_object_free(obj);
4609 intel_runtime_pm_put(dev_priv);
4612 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4613 struct i915_address_space *vm)
4615 struct i915_vma *vma;
4616 list_for_each_entry(vma, &obj->vma_list, vma_link)
4623 void i915_gem_vma_destroy(struct i915_vma *vma)
4625 struct i915_address_space *vm = NULL;
4626 WARN_ON(vma->node.allocated);
4628 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4629 if (!list_empty(&vma->exec_list))
4634 if (!i915_is_ggtt(vm))
4635 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4637 list_del(&vma->vma_link);
4643 i915_gem_stop_ringbuffers(struct drm_device *dev)
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct intel_engine_cs *ring;
4649 for_each_ring(ring, dev_priv, i)
4650 dev_priv->gt.stop_ring(ring);
4654 i915_gem_suspend(struct drm_device *dev)
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4659 mutex_lock(&dev->struct_mutex);
4660 ret = i915_gpu_idle(dev);
4664 i915_gem_retire_requests(dev);
4666 /* Under UMS, be paranoid and evict. */
4667 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4668 i915_gem_evict_everything(dev);
4670 i915_gem_stop_ringbuffers(dev);
4671 mutex_unlock(&dev->struct_mutex);
4673 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4674 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4675 flush_delayed_work(&dev_priv->mm.idle_work);
4680 mutex_unlock(&dev->struct_mutex);
4684 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4686 struct drm_device *dev = ring->dev;
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4689 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4692 if (!HAS_L3_DPF(dev) || !remap_info)
4695 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4700 * Note: We do not worry about the concurrent register cacheline hang
4701 * here because no other code should access these registers other than
4702 * at initialization time.
4704 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4705 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4706 intel_ring_emit(ring, reg_base + i);
4707 intel_ring_emit(ring, remap_info[i/4]);
4710 intel_ring_advance(ring);
4715 void i915_gem_init_swizzling(struct drm_device *dev)
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4719 if (INTEL_INFO(dev)->gen < 5 ||
4720 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4723 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4724 DISP_TILE_SURFACE_SWIZZLING);
4729 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4731 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4732 else if (IS_GEN7(dev))
4733 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4734 else if (IS_GEN8(dev))
4735 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4741 intel_enable_blt(struct drm_device *dev)
4746 /* The blitter was dysfunctional on early prototypes */
4747 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4748 DRM_INFO("BLT not supported on this pre-production hardware;"
4749 " graphics performance will be degraded.\n");
4756 static void init_unused_ring(struct drm_device *dev, u32 base)
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4760 I915_WRITE(RING_CTL(base), 0);
4761 I915_WRITE(RING_HEAD(base), 0);
4762 I915_WRITE(RING_TAIL(base), 0);
4763 I915_WRITE(RING_START(base), 0);
4766 static void init_unused_rings(struct drm_device *dev)
4769 init_unused_ring(dev, PRB1_BASE);
4770 init_unused_ring(dev, SRB0_BASE);
4771 init_unused_ring(dev, SRB1_BASE);
4772 init_unused_ring(dev, SRB2_BASE);
4773 init_unused_ring(dev, SRB3_BASE);
4774 } else if (IS_GEN2(dev)) {
4775 init_unused_ring(dev, SRB0_BASE);
4776 init_unused_ring(dev, SRB1_BASE);
4777 } else if (IS_GEN3(dev)) {
4778 init_unused_ring(dev, PRB1_BASE);
4779 init_unused_ring(dev, PRB2_BASE);
4783 int i915_gem_init_rings(struct drm_device *dev)
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4789 * At least 830 can leave some of the unused rings
4790 * "active" (ie. head != tail) after resume which
4791 * will prevent c3 entry. Makes sure all unused rings
4794 init_unused_rings(dev);
4796 ret = intel_init_render_ring_buffer(dev);
4801 ret = intel_init_bsd_ring_buffer(dev);
4803 goto cleanup_render_ring;
4806 if (intel_enable_blt(dev)) {
4807 ret = intel_init_blt_ring_buffer(dev);
4809 goto cleanup_bsd_ring;
4812 if (HAS_VEBOX(dev)) {
4813 ret = intel_init_vebox_ring_buffer(dev);
4815 goto cleanup_blt_ring;
4818 if (HAS_BSD2(dev)) {
4819 ret = intel_init_bsd2_ring_buffer(dev);
4821 goto cleanup_vebox_ring;
4824 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4826 goto cleanup_bsd2_ring;
4831 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4833 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4835 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4837 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4838 cleanup_render_ring:
4839 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4845 i915_gem_init_hw(struct drm_device *dev)
4847 struct drm_i915_private *dev_priv = dev->dev_private;
4850 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4853 if (dev_priv->ellc_size)
4854 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4856 if (IS_HASWELL(dev))
4857 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4858 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4860 if (HAS_PCH_NOP(dev)) {
4861 if (IS_IVYBRIDGE(dev)) {
4862 u32 temp = I915_READ(GEN7_MSG_CTL);
4863 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4864 I915_WRITE(GEN7_MSG_CTL, temp);
4865 } else if (INTEL_INFO(dev)->gen >= 7) {
4866 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4867 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4868 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4872 i915_gem_init_swizzling(dev);
4874 ret = dev_priv->gt.init_rings(dev);
4878 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4879 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4882 * XXX: Contexts should only be initialized once. Doing a switch to the
4883 * default context switch however is something we'd like to do after
4884 * reset or thaw (the latter may not actually be necessary for HW, but
4885 * goes with our code better). Context switching requires rings (for
4886 * the do_switch), but before enabling PPGTT. So don't move this.
4888 ret = i915_gem_context_enable(dev_priv);
4889 if (ret && ret != -EIO) {
4890 DRM_ERROR("Context enable failed %d\n", ret);
4891 i915_gem_cleanup_ringbuffer(dev);
4896 ret = i915_ppgtt_init_hw(dev);
4897 if (ret && ret != -EIO) {
4898 DRM_ERROR("PPGTT enable failed %d\n", ret);
4899 i915_gem_cleanup_ringbuffer(dev);
4905 int i915_gem_init(struct drm_device *dev)
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4910 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4911 i915.enable_execlists);
4913 mutex_lock(&dev->struct_mutex);
4915 if (IS_VALLEYVIEW(dev)) {
4916 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4917 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4918 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4919 VLV_GTLC_ALLOWWAKEACK), 10))
4920 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4923 if (!i915.enable_execlists) {
4924 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4925 dev_priv->gt.init_rings = i915_gem_init_rings;
4926 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4927 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4929 dev_priv->gt.do_execbuf = intel_execlists_submission;
4930 dev_priv->gt.init_rings = intel_logical_rings_init;
4931 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4932 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4935 ret = i915_gem_init_userptr(dev);
4937 mutex_unlock(&dev->struct_mutex);
4941 i915_gem_init_global_gtt(dev);
4943 ret = i915_gem_context_init(dev);
4945 mutex_unlock(&dev->struct_mutex);
4949 ret = i915_gem_init_hw(dev);
4951 /* Allow ring initialisation to fail by marking the GPU as
4952 * wedged. But we only want to do this where the GPU is angry,
4953 * for all other failure, such as an allocation failure, bail.
4955 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4956 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4959 mutex_unlock(&dev->struct_mutex);
4965 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 struct intel_engine_cs *ring;
4971 for_each_ring(ring, dev_priv, i)
4972 dev_priv->gt.cleanup_ring(ring);
4976 init_ring_lists(struct intel_engine_cs *ring)
4978 INIT_LIST_HEAD(&ring->active_list);
4979 INIT_LIST_HEAD(&ring->request_list);
4982 void i915_init_vm(struct drm_i915_private *dev_priv,
4983 struct i915_address_space *vm)
4985 if (!i915_is_ggtt(vm))
4986 drm_mm_init(&vm->mm, vm->start, vm->total);
4987 vm->dev = dev_priv->dev;
4988 INIT_LIST_HEAD(&vm->active_list);
4989 INIT_LIST_HEAD(&vm->inactive_list);
4990 INIT_LIST_HEAD(&vm->global_link);
4991 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4995 i915_gem_load(struct drm_device *dev)
4997 struct drm_i915_private *dev_priv = dev->dev_private;
5001 kmem_cache_create("i915_gem_object",
5002 sizeof(struct drm_i915_gem_object), 0,
5006 INIT_LIST_HEAD(&dev_priv->vm_list);
5007 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5009 INIT_LIST_HEAD(&dev_priv->context_list);
5010 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5011 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5012 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5013 for (i = 0; i < I915_NUM_RINGS; i++)
5014 init_ring_lists(&dev_priv->ring[i]);
5015 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5016 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5017 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5018 i915_gem_retire_work_handler);
5019 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5020 i915_gem_idle_work_handler);
5021 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5023 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5024 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5025 I915_WRITE(MI_ARB_STATE,
5026 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5029 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5031 /* Old X drivers will take 0-2 for front, back, depth buffers */
5032 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5033 dev_priv->fence_reg_start = 3;
5035 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5036 dev_priv->num_fence_regs = 32;
5037 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5038 dev_priv->num_fence_regs = 16;
5040 dev_priv->num_fence_regs = 8;
5042 /* Initialize fence registers to zero */
5043 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5044 i915_gem_restore_fences(dev);
5046 i915_gem_detect_bit_6_swizzle(dev);
5047 init_waitqueue_head(&dev_priv->pending_flip_queue);
5049 dev_priv->mm.interruptible = true;
5051 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5052 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5053 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5054 register_shrinker(&dev_priv->mm.shrinker);
5056 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5057 register_oom_notifier(&dev_priv->mm.oom_notifier);
5059 mutex_init(&dev_priv->fb_tracking.lock);
5062 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5064 struct drm_i915_file_private *file_priv = file->driver_priv;
5066 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5068 /* Clean up our request list when the client is going away, so that
5069 * later retire_requests won't dereference our soon-to-be-gone
5072 spin_lock(&file_priv->mm.lock);
5073 while (!list_empty(&file_priv->mm.request_list)) {
5074 struct drm_i915_gem_request *request;
5076 request = list_first_entry(&file_priv->mm.request_list,
5077 struct drm_i915_gem_request,
5079 list_del(&request->client_list);
5080 request->file_priv = NULL;
5082 spin_unlock(&file_priv->mm.lock);
5086 i915_gem_file_idle_work_handler(struct work_struct *work)
5088 struct drm_i915_file_private *file_priv =
5089 container_of(work, typeof(*file_priv), mm.idle_work.work);
5091 atomic_set(&file_priv->rps_wait_boost, false);
5094 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5096 struct drm_i915_file_private *file_priv;
5099 DRM_DEBUG_DRIVER("\n");
5101 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5105 file->driver_priv = file_priv;
5106 file_priv->dev_priv = dev->dev_private;
5107 file_priv->file = file;
5109 spin_lock_init(&file_priv->mm.lock);
5110 INIT_LIST_HEAD(&file_priv->mm.request_list);
5111 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5112 i915_gem_file_idle_work_handler);
5114 ret = i915_gem_context_open(dev, file);
5122 * i915_gem_track_fb - update frontbuffer tracking
5123 * old: current GEM buffer for the frontbuffer slots
5124 * new: new GEM buffer for the frontbuffer slots
5125 * frontbuffer_bits: bitmask of frontbuffer slots
5127 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5128 * from @old and setting them in @new. Both @old and @new can be NULL.
5130 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5131 struct drm_i915_gem_object *new,
5132 unsigned frontbuffer_bits)
5135 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5136 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5137 old->frontbuffer_bits &= ~frontbuffer_bits;
5141 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5142 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5143 new->frontbuffer_bits |= frontbuffer_bits;
5147 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5149 if (!mutex_is_locked(mutex))
5152 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5153 return mutex->owner == task;
5155 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5160 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5162 if (!mutex_trylock(&dev->struct_mutex)) {
5163 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5166 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5176 static int num_vma_bound(struct drm_i915_gem_object *obj)
5178 struct i915_vma *vma;
5181 list_for_each_entry(vma, &obj->vma_list, vma_link)
5182 if (drm_mm_node_allocated(&vma->node))
5188 static unsigned long
5189 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5191 struct drm_i915_private *dev_priv =
5192 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5193 struct drm_device *dev = dev_priv->dev;
5194 struct drm_i915_gem_object *obj;
5195 unsigned long count;
5198 if (!i915_gem_shrinker_lock(dev, &unlock))
5202 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5203 if (obj->pages_pin_count == 0)
5204 count += obj->base.size >> PAGE_SHIFT;
5206 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5207 if (!i915_gem_obj_is_pinned(obj) &&
5208 obj->pages_pin_count == num_vma_bound(obj))
5209 count += obj->base.size >> PAGE_SHIFT;
5213 mutex_unlock(&dev->struct_mutex);
5218 /* All the new VM stuff */
5219 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5220 struct i915_address_space *vm)
5222 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5223 struct i915_vma *vma;
5225 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5227 list_for_each_entry(vma, &o->vma_list, vma_link) {
5229 return vma->node.start;
5232 WARN(1, "%s vma for this object not found.\n",
5233 i915_is_ggtt(vm) ? "global" : "ppgtt");
5237 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5238 struct i915_address_space *vm)
5240 struct i915_vma *vma;
5242 list_for_each_entry(vma, &o->vma_list, vma_link)
5243 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5249 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5251 struct i915_vma *vma;
5253 list_for_each_entry(vma, &o->vma_list, vma_link)
5254 if (drm_mm_node_allocated(&vma->node))
5260 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5261 struct i915_address_space *vm)
5263 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5264 struct i915_vma *vma;
5266 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5268 BUG_ON(list_empty(&o->vma_list));
5270 list_for_each_entry(vma, &o->vma_list, vma_link)
5272 return vma->node.size;
5277 static unsigned long
5278 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5280 struct drm_i915_private *dev_priv =
5281 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5282 struct drm_device *dev = dev_priv->dev;
5283 unsigned long freed;
5286 if (!i915_gem_shrinker_lock(dev, &unlock))
5289 freed = i915_gem_shrink(dev_priv,
5292 I915_SHRINK_UNBOUND |
5293 I915_SHRINK_PURGEABLE);
5294 if (freed < sc->nr_to_scan)
5295 freed += i915_gem_shrink(dev_priv,
5296 sc->nr_to_scan - freed,
5298 I915_SHRINK_UNBOUND);
5300 mutex_unlock(&dev->struct_mutex);
5306 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5308 struct drm_i915_private *dev_priv =
5309 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5310 struct drm_device *dev = dev_priv->dev;
5311 struct drm_i915_gem_object *obj;
5312 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5313 unsigned long pinned, bound, unbound, freed_pages;
5314 bool was_interruptible;
5317 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5318 schedule_timeout_killable(1);
5319 if (fatal_signal_pending(current))
5323 pr_err("Unable to purge GPU memory due lock contention.\n");
5327 was_interruptible = dev_priv->mm.interruptible;
5328 dev_priv->mm.interruptible = false;
5330 freed_pages = i915_gem_shrink_all(dev_priv);
5332 dev_priv->mm.interruptible = was_interruptible;
5334 /* Because we may be allocating inside our own driver, we cannot
5335 * assert that there are no objects with pinned pages that are not
5336 * being pointed to by hardware.
5338 unbound = bound = pinned = 0;
5339 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5340 if (!obj->base.filp) /* not backed by a freeable object */
5343 if (obj->pages_pin_count)
5344 pinned += obj->base.size;
5346 unbound += obj->base.size;
5348 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5349 if (!obj->base.filp)
5352 if (obj->pages_pin_count)
5353 pinned += obj->base.size;
5355 bound += obj->base.size;
5359 mutex_unlock(&dev->struct_mutex);
5361 if (freed_pages || unbound || bound)
5362 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5363 freed_pages << PAGE_SHIFT, pinned);
5364 if (unbound || bound)
5365 pr_err("%lu and %lu bytes still available in the "
5366 "bound and unbound GPU page lists.\n",
5369 *(unsigned long *)ptr += freed_pages;
5373 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5375 struct i915_vma *vma;
5377 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5378 if (vma->vm != i915_obj_to_ggtt(obj))