2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
45 struct i915_address_space *vm,
47 bool map_and_fenceable,
49 static int i915_gem_phys_pwrite(struct drm_device *dev,
50 struct drm_i915_gem_object *obj,
51 struct drm_i915_gem_pwrite *args,
52 struct drm_file *file);
54 static void i915_gem_write_fence(struct drm_device *dev, int reg,
55 struct drm_i915_gem_object *obj);
56 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
57 struct drm_i915_fence_reg *fence,
60 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
61 struct shrink_control *sc);
62 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
63 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
64 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
66 static bool cpu_cache_is_coherent(struct drm_device *dev,
67 enum i915_cache_level level)
69 return HAS_LLC(dev) || level != I915_CACHE_NONE;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
74 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
77 return obj->pin_display;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
83 i915_gem_release_mmap(obj);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj->fence_dirty = false;
89 obj->fence_reg = I915_FENCE_REG_NONE;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
96 spin_lock(&dev_priv->mm.object_stat_lock);
97 dev_priv->mm.object_count++;
98 dev_priv->mm.object_memory += size;
99 spin_unlock(&dev_priv->mm.object_stat_lock);
102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
105 spin_lock(&dev_priv->mm.object_stat_lock);
106 dev_priv->mm.object_count--;
107 dev_priv->mm.object_memory -= size;
108 spin_unlock(&dev_priv->mm.object_stat_lock);
112 i915_gem_wait_for_error(struct i915_gpu_error *error)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret = wait_event_interruptible_timeout(error->reset_queue,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret < 0) {
140 int i915_mutex_lock_interruptible(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
145 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
149 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 WARN_ON(i915_verify_lists(dev));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
160 return i915_gem_obj_bound_any(obj) && !obj->active;
164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_init *args = data;
170 if (drm_core_check_feature(dev, DRIVER_MODESET))
173 if (args->gtt_start >= args->gtt_end ||
174 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev)->gen >= 5)
181 mutex_lock(&dev->struct_mutex);
182 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
184 dev_priv->gtt.mappable_end = args->gtt_end;
185 mutex_unlock(&dev->struct_mutex);
191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *file)
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 struct drm_i915_gem_get_aperture *args = data;
196 struct drm_i915_gem_object *obj;
200 mutex_lock(&dev->struct_mutex);
201 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
203 pinned += i915_gem_obj_ggtt_size(obj);
204 mutex_unlock(&dev->struct_mutex);
206 args->aper_size = dev_priv->gtt.base.total;
207 args->aper_available_size = args->aper_size - pinned;
212 void *i915_gem_object_alloc(struct drm_device *dev)
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
218 void i915_gem_object_free(struct drm_i915_gem_object *obj)
220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
221 kmem_cache_free(dev_priv->slab, obj);
225 i915_gem_create(struct drm_file *file,
226 struct drm_device *dev,
230 struct drm_i915_gem_object *obj;
234 size = roundup(size, PAGE_SIZE);
238 /* Allocate the new object */
239 obj = i915_gem_alloc_object(dev, size);
243 ret = drm_gem_handle_create(file, &obj->base, &handle);
244 /* drop reference from allocate - handle holds it now */
245 drm_gem_object_unreference_unlocked(&obj->base);
254 i915_gem_dumb_create(struct drm_file *file,
255 struct drm_device *dev,
256 struct drm_mode_create_dumb *args)
258 /* have to work out size/pitch and return them */
259 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
260 args->size = args->pitch * args->height;
261 return i915_gem_create(file, dev,
262 args->size, &args->handle);
266 * Creates a new mm object and returns a handle to it.
269 i915_gem_create_ioctl(struct drm_device *dev, void *data,
270 struct drm_file *file)
272 struct drm_i915_gem_create *args = data;
274 return i915_gem_create(file, dev,
275 args->size, &args->handle);
279 __copy_to_user_swizzled(char __user *cpu_vaddr,
280 const char *gpu_vaddr, int gpu_offset,
283 int ret, cpu_offset = 0;
286 int cacheline_end = ALIGN(gpu_offset + 1, 64);
287 int this_length = min(cacheline_end - gpu_offset, length);
288 int swizzled_gpu_offset = gpu_offset ^ 64;
290 ret = __copy_to_user(cpu_vaddr + cpu_offset,
291 gpu_vaddr + swizzled_gpu_offset,
296 cpu_offset += this_length;
297 gpu_offset += this_length;
298 length -= this_length;
305 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
306 const char __user *cpu_vaddr,
309 int ret, cpu_offset = 0;
312 int cacheline_end = ALIGN(gpu_offset + 1, 64);
313 int this_length = min(cacheline_end - gpu_offset, length);
314 int swizzled_gpu_offset = gpu_offset ^ 64;
316 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
317 cpu_vaddr + cpu_offset,
322 cpu_offset += this_length;
323 gpu_offset += this_length;
324 length -= this_length;
330 /* Per-page copy function for the shmem pread fastpath.
331 * Flushes invalid cachelines before reading the target if
332 * needs_clflush is set. */
334 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
335 char __user *user_data,
336 bool page_do_bit17_swizzling, bool needs_clflush)
341 if (unlikely(page_do_bit17_swizzling))
344 vaddr = kmap_atomic(page);
346 drm_clflush_virt_range(vaddr + shmem_page_offset,
348 ret = __copy_to_user_inatomic(user_data,
349 vaddr + shmem_page_offset,
351 kunmap_atomic(vaddr);
353 return ret ? -EFAULT : 0;
357 shmem_clflush_swizzled_range(char *addr, unsigned long length,
360 if (unlikely(swizzled)) {
361 unsigned long start = (unsigned long) addr;
362 unsigned long end = (unsigned long) addr + length;
364 /* For swizzling simply ensure that we always flush both
365 * channels. Lame, but simple and it works. Swizzled
366 * pwrite/pread is far from a hotpath - current userspace
367 * doesn't use it at all. */
368 start = round_down(start, 128);
369 end = round_up(end, 128);
371 drm_clflush_virt_range((void *)start, end - start);
373 drm_clflush_virt_range(addr, length);
378 /* Only difference to the fast-path function is that this can handle bit17
379 * and uses non-atomic copy and kmap functions. */
381 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
382 char __user *user_data,
383 bool page_do_bit17_swizzling, bool needs_clflush)
390 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
392 page_do_bit17_swizzling);
394 if (page_do_bit17_swizzling)
395 ret = __copy_to_user_swizzled(user_data,
396 vaddr, shmem_page_offset,
399 ret = __copy_to_user(user_data,
400 vaddr + shmem_page_offset,
404 return ret ? - EFAULT : 0;
408 i915_gem_shmem_pread(struct drm_device *dev,
409 struct drm_i915_gem_object *obj,
410 struct drm_i915_gem_pread *args,
411 struct drm_file *file)
413 char __user *user_data;
416 int shmem_page_offset, page_length, ret = 0;
417 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
419 int needs_clflush = 0;
420 struct sg_page_iter sg_iter;
422 user_data = to_user_ptr(args->data_ptr);
425 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
427 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
428 /* If we're not in the cpu read domain, set ourself into the gtt
429 * read domain and manually flush cachelines (if required). This
430 * optimizes for the case when the gpu will dirty the data
431 * anyway again before the next pread happens. */
432 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
433 if (i915_gem_obj_bound_any(obj)) {
434 ret = i915_gem_object_set_to_gtt_domain(obj, false);
440 ret = i915_gem_object_get_pages(obj);
444 i915_gem_object_pin_pages(obj);
446 offset = args->offset;
448 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
449 offset >> PAGE_SHIFT) {
450 struct page *page = sg_page_iter_page(&sg_iter);
455 /* Operation in this page
457 * shmem_page_offset = offset within page in shmem file
458 * page_length = bytes to copy for this page
460 shmem_page_offset = offset_in_page(offset);
461 page_length = remain;
462 if ((shmem_page_offset + page_length) > PAGE_SIZE)
463 page_length = PAGE_SIZE - shmem_page_offset;
465 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
466 (page_to_phys(page) & (1 << 17)) != 0;
468 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
469 user_data, page_do_bit17_swizzling,
474 mutex_unlock(&dev->struct_mutex);
476 if (likely(!i915_prefault_disable) && !prefaulted) {
477 ret = fault_in_multipages_writeable(user_data, remain);
478 /* Userspace is tricking us, but we've already clobbered
479 * its pages with the prefault and promised to write the
480 * data up to the first fault. Hence ignore any errors
481 * and just continue. */
486 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
487 user_data, page_do_bit17_swizzling,
490 mutex_lock(&dev->struct_mutex);
493 mark_page_accessed(page);
498 remain -= page_length;
499 user_data += page_length;
500 offset += page_length;
504 i915_gem_object_unpin_pages(obj);
510 * Reads data from the object referenced by handle.
512 * On error, the contents of *data are undefined.
515 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
516 struct drm_file *file)
518 struct drm_i915_gem_pread *args = data;
519 struct drm_i915_gem_object *obj;
525 if (!access_ok(VERIFY_WRITE,
526 to_user_ptr(args->data_ptr),
530 ret = i915_mutex_lock_interruptible(dev);
534 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
535 if (&obj->base == NULL) {
540 /* Bounds check source. */
541 if (args->offset > obj->base.size ||
542 args->size > obj->base.size - args->offset) {
547 /* prime objects have no backing filp to GEM pread/pwrite
550 if (!obj->base.filp) {
555 trace_i915_gem_object_pread(obj, args->offset, args->size);
557 ret = i915_gem_shmem_pread(dev, obj, args, file);
560 drm_gem_object_unreference(&obj->base);
562 mutex_unlock(&dev->struct_mutex);
566 /* This is the fast write path which cannot handle
567 * page faults in the source data
571 fast_user_write(struct io_mapping *mapping,
572 loff_t page_base, int page_offset,
573 char __user *user_data,
576 void __iomem *vaddr_atomic;
578 unsigned long unwritten;
580 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
581 /* We can use the cpu mem copy function because this is X86. */
582 vaddr = (void __force*)vaddr_atomic + page_offset;
583 unwritten = __copy_from_user_inatomic_nocache(vaddr,
585 io_mapping_unmap_atomic(vaddr_atomic);
590 * This is the fast pwrite path, where we copy the data directly from the
591 * user into the GTT, uncached.
594 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
595 struct drm_i915_gem_object *obj,
596 struct drm_i915_gem_pwrite *args,
597 struct drm_file *file)
599 drm_i915_private_t *dev_priv = dev->dev_private;
601 loff_t offset, page_base;
602 char __user *user_data;
603 int page_offset, page_length, ret;
605 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
609 ret = i915_gem_object_set_to_gtt_domain(obj, true);
613 ret = i915_gem_object_put_fence(obj);
617 user_data = to_user_ptr(args->data_ptr);
620 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
623 /* Operation in this page
625 * page_base = page offset within aperture
626 * page_offset = offset within page
627 * page_length = bytes to copy for this page
629 page_base = offset & PAGE_MASK;
630 page_offset = offset_in_page(offset);
631 page_length = remain;
632 if ((page_offset + remain) > PAGE_SIZE)
633 page_length = PAGE_SIZE - page_offset;
635 /* If we get a fault while copying data, then (presumably) our
636 * source page isn't available. Return the error and we'll
637 * retry in the slow path.
639 if (fast_user_write(dev_priv->gtt.mappable, page_base,
640 page_offset, user_data, page_length)) {
645 remain -= page_length;
646 user_data += page_length;
647 offset += page_length;
651 i915_gem_object_unpin(obj);
656 /* Per-page copy function for the shmem pwrite fastpath.
657 * Flushes invalid cachelines before writing to the target if
658 * needs_clflush_before is set and flushes out any written cachelines after
659 * writing if needs_clflush is set. */
661 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
662 char __user *user_data,
663 bool page_do_bit17_swizzling,
664 bool needs_clflush_before,
665 bool needs_clflush_after)
670 if (unlikely(page_do_bit17_swizzling))
673 vaddr = kmap_atomic(page);
674 if (needs_clflush_before)
675 drm_clflush_virt_range(vaddr + shmem_page_offset,
677 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
680 if (needs_clflush_after)
681 drm_clflush_virt_range(vaddr + shmem_page_offset,
683 kunmap_atomic(vaddr);
685 return ret ? -EFAULT : 0;
688 /* Only difference to the fast-path function is that this can handle bit17
689 * and uses non-atomic copy and kmap functions. */
691 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
692 char __user *user_data,
693 bool page_do_bit17_swizzling,
694 bool needs_clflush_before,
695 bool needs_clflush_after)
701 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
702 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
704 page_do_bit17_swizzling);
705 if (page_do_bit17_swizzling)
706 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
710 ret = __copy_from_user(vaddr + shmem_page_offset,
713 if (needs_clflush_after)
714 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
716 page_do_bit17_swizzling);
719 return ret ? -EFAULT : 0;
723 i915_gem_shmem_pwrite(struct drm_device *dev,
724 struct drm_i915_gem_object *obj,
725 struct drm_i915_gem_pwrite *args,
726 struct drm_file *file)
730 char __user *user_data;
731 int shmem_page_offset, page_length, ret = 0;
732 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
733 int hit_slowpath = 0;
734 int needs_clflush_after = 0;
735 int needs_clflush_before = 0;
736 struct sg_page_iter sg_iter;
738 user_data = to_user_ptr(args->data_ptr);
741 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
743 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
744 /* If we're not in the cpu write domain, set ourself into the gtt
745 * write domain and manually flush cachelines (if required). This
746 * optimizes for the case when the gpu will use the data
747 * right away and we therefore have to clflush anyway. */
748 needs_clflush_after = cpu_write_needs_clflush(obj);
749 if (i915_gem_obj_bound_any(obj)) {
750 ret = i915_gem_object_set_to_gtt_domain(obj, true);
755 /* Same trick applies to invalidate partially written cachelines read
757 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
758 needs_clflush_before =
759 !cpu_cache_is_coherent(dev, obj->cache_level);
761 ret = i915_gem_object_get_pages(obj);
765 i915_gem_object_pin_pages(obj);
767 offset = args->offset;
770 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
771 offset >> PAGE_SHIFT) {
772 struct page *page = sg_page_iter_page(&sg_iter);
773 int partial_cacheline_write;
778 /* Operation in this page
780 * shmem_page_offset = offset within page in shmem file
781 * page_length = bytes to copy for this page
783 shmem_page_offset = offset_in_page(offset);
785 page_length = remain;
786 if ((shmem_page_offset + page_length) > PAGE_SIZE)
787 page_length = PAGE_SIZE - shmem_page_offset;
789 /* If we don't overwrite a cacheline completely we need to be
790 * careful to have up-to-date data by first clflushing. Don't
791 * overcomplicate things and flush the entire patch. */
792 partial_cacheline_write = needs_clflush_before &&
793 ((shmem_page_offset | page_length)
794 & (boot_cpu_data.x86_clflush_size - 1));
796 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
797 (page_to_phys(page) & (1 << 17)) != 0;
799 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
800 user_data, page_do_bit17_swizzling,
801 partial_cacheline_write,
802 needs_clflush_after);
807 mutex_unlock(&dev->struct_mutex);
808 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
809 user_data, page_do_bit17_swizzling,
810 partial_cacheline_write,
811 needs_clflush_after);
813 mutex_lock(&dev->struct_mutex);
816 set_page_dirty(page);
817 mark_page_accessed(page);
822 remain -= page_length;
823 user_data += page_length;
824 offset += page_length;
828 i915_gem_object_unpin_pages(obj);
832 * Fixup: Flush cpu caches in case we didn't flush the dirty
833 * cachelines in-line while writing and the object moved
834 * out of the cpu write domain while we've dropped the lock.
836 if (!needs_clflush_after &&
837 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 if (i915_gem_clflush_object(obj, obj->pin_display))
839 i915_gem_chipset_flush(dev);
843 if (needs_clflush_after)
844 i915_gem_chipset_flush(dev);
850 * Writes data to the object referenced by handle.
852 * On error, the contents of the buffer that were to be modified are undefined.
855 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
858 struct drm_i915_gem_pwrite *args = data;
859 struct drm_i915_gem_object *obj;
865 if (!access_ok(VERIFY_READ,
866 to_user_ptr(args->data_ptr),
870 if (likely(!i915_prefault_disable)) {
871 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
877 ret = i915_mutex_lock_interruptible(dev);
881 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
882 if (&obj->base == NULL) {
887 /* Bounds check destination. */
888 if (args->offset > obj->base.size ||
889 args->size > obj->base.size - args->offset) {
894 /* prime objects have no backing filp to GEM pread/pwrite
897 if (!obj->base.filp) {
902 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
905 /* We can only do the GTT pwrite on untiled buffers, as otherwise
906 * it would end up going through the fenced access, and we'll get
907 * different detiling behavior between reading and writing.
908 * pread/pwrite currently are reading and writing from the CPU
909 * perspective, requiring manual detiling by the client.
912 ret = i915_gem_phys_pwrite(dev, obj, args, file);
916 if (obj->tiling_mode == I915_TILING_NONE &&
917 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
918 cpu_write_needs_clflush(obj)) {
919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
925 if (ret == -EFAULT || ret == -ENOSPC)
926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
929 drm_gem_object_unreference(&obj->base);
931 mutex_unlock(&dev->struct_mutex);
936 i915_gem_check_wedge(struct i915_gpu_error *error,
939 if (i915_reset_in_progress(error)) {
940 /* Non-interruptible callers can't handle -EAGAIN, hence return
941 * -EIO unconditionally for these. */
945 /* Recovery complete, but the reset failed ... */
946 if (i915_terminally_wedged(error))
956 * Compare seqno against outstanding lazy request. Emit a request if they are
960 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
964 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
967 if (seqno == ring->outstanding_lazy_request)
968 ret = i915_add_request(ring, NULL);
974 * __wait_seqno - wait until execution of seqno has finished
975 * @ring: the ring expected to report seqno
977 * @reset_counter: reset sequence associated with the given seqno
978 * @interruptible: do an interruptible wait (normally yes)
979 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
981 * Note: It is of utmost importance that the passed in seqno and reset_counter
982 * values have been read by the caller in an smp safe manner. Where read-side
983 * locks are involved, it is sufficient to read the reset_counter before
984 * unlocking the lock that protects the seqno. For lockless tricks, the
985 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
988 * Returns 0 if the seqno was found within the alloted time. Else returns the
989 * errno with remaining time filled in timeout argument.
991 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
992 unsigned reset_counter,
993 bool interruptible, struct timespec *timeout)
995 drm_i915_private_t *dev_priv = ring->dev->dev_private;
996 struct timespec before, now, wait_time={1,0};
997 unsigned long timeout_jiffies;
999 bool wait_forever = true;
1002 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1004 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1007 trace_i915_gem_request_wait_begin(ring, seqno);
1009 if (timeout != NULL) {
1010 wait_time = *timeout;
1011 wait_forever = false;
1014 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1016 if (WARN_ON(!ring->irq_get(ring)))
1019 /* Record current time in case interrupted by signal, or wedged * */
1020 getrawmonotonic(&before);
1023 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1024 i915_reset_in_progress(&dev_priv->gpu_error) || \
1025 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1028 end = wait_event_interruptible_timeout(ring->irq_queue,
1032 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1035 /* We need to check whether any gpu reset happened in between
1036 * the caller grabbing the seqno and now ... */
1037 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1040 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1042 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1045 } while (end == 0 && wait_forever);
1047 getrawmonotonic(&now);
1049 ring->irq_put(ring);
1050 trace_i915_gem_request_wait_end(ring, seqno);
1054 struct timespec sleep_time = timespec_sub(now, before);
1055 *timeout = timespec_sub(*timeout, sleep_time);
1056 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1057 set_normalized_timespec(timeout, 0, 0);
1062 case -EAGAIN: /* Wedged */
1063 case -ERESTARTSYS: /* Signal */
1065 case 0: /* Timeout */
1067 default: /* Completed */
1068 WARN_ON(end < 0); /* We're not aware of other errors */
1074 * Waits for a sequence number to be signaled, and cleans up the
1075 * request and object lists appropriately for that event.
1078 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1080 struct drm_device *dev = ring->dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 bool interruptible = dev_priv->mm.interruptible;
1085 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1088 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1092 ret = i915_gem_check_olr(ring, seqno);
1096 return __wait_seqno(ring, seqno,
1097 atomic_read(&dev_priv->gpu_error.reset_counter),
1098 interruptible, NULL);
1102 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1103 struct intel_ring_buffer *ring)
1105 i915_gem_retire_requests_ring(ring);
1107 /* Manually manage the write flush as we may have not yet
1108 * retired the buffer.
1110 * Note that the last_write_seqno is always the earlier of
1111 * the two (read/write) seqno, so if we haved successfully waited,
1112 * we know we have passed the last write.
1114 obj->last_write_seqno = 0;
1115 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1121 * Ensures that all rendering to the object has completed and the object is
1122 * safe to unbind from the GTT or access from the CPU.
1124 static __must_check int
1125 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1128 struct intel_ring_buffer *ring = obj->ring;
1132 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1136 ret = i915_wait_seqno(ring, seqno);
1140 return i915_gem_object_wait_rendering__tail(obj, ring);
1143 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1144 * as the object state may change during this call.
1146 static __must_check int
1147 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1150 struct drm_device *dev = obj->base.dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 struct intel_ring_buffer *ring = obj->ring;
1153 unsigned reset_counter;
1157 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1158 BUG_ON(!dev_priv->mm.interruptible);
1160 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1164 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1168 ret = i915_gem_check_olr(ring, seqno);
1172 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1173 mutex_unlock(&dev->struct_mutex);
1174 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1175 mutex_lock(&dev->struct_mutex);
1179 return i915_gem_object_wait_rendering__tail(obj, ring);
1183 * Called when user space prepares to use an object with the CPU, either
1184 * through the mmap ioctl's mapping or a GTT mapping.
1187 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *file)
1190 struct drm_i915_gem_set_domain *args = data;
1191 struct drm_i915_gem_object *obj;
1192 uint32_t read_domains = args->read_domains;
1193 uint32_t write_domain = args->write_domain;
1196 /* Only handle setting domains to types used by the CPU. */
1197 if (write_domain & I915_GEM_GPU_DOMAINS)
1200 if (read_domains & I915_GEM_GPU_DOMAINS)
1203 /* Having something in the write domain implies it's in the read
1204 * domain, and only that read domain. Enforce that in the request.
1206 if (write_domain != 0 && read_domains != write_domain)
1209 ret = i915_mutex_lock_interruptible(dev);
1213 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1214 if (&obj->base == NULL) {
1219 /* Try to flush the object off the GPU without holding the lock.
1220 * We will repeat the flush holding the lock in the normal manner
1221 * to catch cases where we are gazumped.
1223 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1227 if (read_domains & I915_GEM_DOMAIN_GTT) {
1228 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1230 /* Silently promote "you're not bound, there was nothing to do"
1231 * to success, since the client was just asking us to
1232 * make sure everything was done.
1237 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1241 drm_gem_object_unreference(&obj->base);
1243 mutex_unlock(&dev->struct_mutex);
1248 * Called when user space has done writes to this buffer
1251 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1252 struct drm_file *file)
1254 struct drm_i915_gem_sw_finish *args = data;
1255 struct drm_i915_gem_object *obj;
1258 ret = i915_mutex_lock_interruptible(dev);
1262 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1263 if (&obj->base == NULL) {
1268 /* Pinned buffers may be scanout, so flush the cache */
1269 if (obj->pin_display)
1270 i915_gem_object_flush_cpu_write_domain(obj, true);
1272 drm_gem_object_unreference(&obj->base);
1274 mutex_unlock(&dev->struct_mutex);
1279 * Maps the contents of an object, returning the address it is mapped
1282 * While the mapping holds a reference on the contents of the object, it doesn't
1283 * imply a ref on the object itself.
1286 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1287 struct drm_file *file)
1289 struct drm_i915_gem_mmap *args = data;
1290 struct drm_gem_object *obj;
1293 obj = drm_gem_object_lookup(dev, file, args->handle);
1297 /* prime objects have no backing filp to GEM mmap
1301 drm_gem_object_unreference_unlocked(obj);
1305 addr = vm_mmap(obj->filp, 0, args->size,
1306 PROT_READ | PROT_WRITE, MAP_SHARED,
1308 drm_gem_object_unreference_unlocked(obj);
1309 if (IS_ERR((void *)addr))
1312 args->addr_ptr = (uint64_t) addr;
1318 * i915_gem_fault - fault a page into the GTT
1319 * vma: VMA in question
1322 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1323 * from userspace. The fault handler takes care of binding the object to
1324 * the GTT (if needed), allocating and programming a fence register (again,
1325 * only if needed based on whether the old reg is still valid or the object
1326 * is tiled) and inserting a new PTE into the faulting process.
1328 * Note that the faulting process may involve evicting existing objects
1329 * from the GTT and/or fence registers to make room. So performance may
1330 * suffer if the GTT working set is large or there are few fence registers
1333 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1335 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1336 struct drm_device *dev = obj->base.dev;
1337 drm_i915_private_t *dev_priv = dev->dev_private;
1338 pgoff_t page_offset;
1341 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1343 /* We don't use vmf->pgoff since that has the fake offset */
1344 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1347 ret = i915_mutex_lock_interruptible(dev);
1351 trace_i915_gem_object_fault(obj, page_offset, true, write);
1353 /* Access to snoopable pages through the GTT is incoherent. */
1354 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1359 /* Now bind it into the GTT if needed */
1360 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1364 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1368 ret = i915_gem_object_get_fence(obj);
1372 obj->fault_mappable = true;
1374 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1378 /* Finally, remap it using the new GTT offset */
1379 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1381 i915_gem_object_unpin(obj);
1383 mutex_unlock(&dev->struct_mutex);
1387 /* If this -EIO is due to a gpu hang, give the reset code a
1388 * chance to clean up the mess. Otherwise return the proper
1390 if (i915_terminally_wedged(&dev_priv->gpu_error))
1391 return VM_FAULT_SIGBUS;
1394 * EAGAIN means the gpu is hung and we'll wait for the error
1395 * handler to reset everything when re-faulting in
1396 * i915_mutex_lock_interruptible.
1403 * EBUSY is ok: this just means that another thread
1404 * already did the job.
1406 return VM_FAULT_NOPAGE;
1408 return VM_FAULT_OOM;
1410 return VM_FAULT_SIGBUS;
1412 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1413 return VM_FAULT_SIGBUS;
1418 * i915_gem_release_mmap - remove physical page mappings
1419 * @obj: obj in question
1421 * Preserve the reservation of the mmapping with the DRM core code, but
1422 * relinquish ownership of the pages back to the system.
1424 * It is vital that we remove the page mapping if we have mapped a tiled
1425 * object through the GTT and then lose the fence register due to
1426 * resource pressure. Similarly if the object has been moved out of the
1427 * aperture, than pages mapped into userspace must be revoked. Removing the
1428 * mapping will then trigger a page fault on the next user access, allowing
1429 * fixup by i915_gem_fault().
1432 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1434 if (!obj->fault_mappable)
1437 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1438 obj->fault_mappable = false;
1442 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1446 if (INTEL_INFO(dev)->gen >= 4 ||
1447 tiling_mode == I915_TILING_NONE)
1450 /* Previous chips need a power-of-two fence region when tiling */
1451 if (INTEL_INFO(dev)->gen == 3)
1452 gtt_size = 1024*1024;
1454 gtt_size = 512*1024;
1456 while (gtt_size < size)
1463 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1464 * @obj: object to check
1466 * Return the required GTT alignment for an object, taking into account
1467 * potential fence register mapping.
1470 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1471 int tiling_mode, bool fenced)
1474 * Minimum alignment is 4k (GTT page size), but might be greater
1475 * if a fence register is needed for the object.
1477 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1478 tiling_mode == I915_TILING_NONE)
1482 * Previous chips need to be aligned to the size of the smallest
1483 * fence register that can contain the object.
1485 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1488 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1490 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1493 if (drm_vma_node_has_offset(&obj->base.vma_node))
1496 dev_priv->mm.shrinker_no_lock_stealing = true;
1498 ret = drm_gem_create_mmap_offset(&obj->base);
1502 /* Badly fragmented mmap space? The only way we can recover
1503 * space is by destroying unwanted objects. We can't randomly release
1504 * mmap_offsets as userspace expects them to be persistent for the
1505 * lifetime of the objects. The closest we can is to release the
1506 * offsets on purgeable objects by truncating it and marking it purged,
1507 * which prevents userspace from ever using that object again.
1509 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1510 ret = drm_gem_create_mmap_offset(&obj->base);
1514 i915_gem_shrink_all(dev_priv);
1515 ret = drm_gem_create_mmap_offset(&obj->base);
1517 dev_priv->mm.shrinker_no_lock_stealing = false;
1522 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1524 drm_gem_free_mmap_offset(&obj->base);
1528 i915_gem_mmap_gtt(struct drm_file *file,
1529 struct drm_device *dev,
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 struct drm_i915_gem_object *obj;
1537 ret = i915_mutex_lock_interruptible(dev);
1541 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1542 if (&obj->base == NULL) {
1547 if (obj->base.size > dev_priv->gtt.mappable_end) {
1552 if (obj->madv != I915_MADV_WILLNEED) {
1553 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1558 ret = i915_gem_object_create_mmap_offset(obj);
1562 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1565 drm_gem_object_unreference(&obj->base);
1567 mutex_unlock(&dev->struct_mutex);
1572 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1574 * @data: GTT mapping ioctl data
1575 * @file: GEM object info
1577 * Simply returns the fake offset to userspace so it can mmap it.
1578 * The mmap call will end up in drm_gem_mmap(), which will set things
1579 * up so we can get faults in the handler above.
1581 * The fault handler will take care of binding the object into the GTT
1582 * (since it may have been evicted to make room for something), allocating
1583 * a fence register, and mapping the appropriate aperture address into
1587 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1588 struct drm_file *file)
1590 struct drm_i915_gem_mmap_gtt *args = data;
1592 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1595 /* Immediately discard the backing storage */
1597 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1599 struct inode *inode;
1601 i915_gem_object_free_mmap_offset(obj);
1603 if (obj->base.filp == NULL)
1606 /* Our goal here is to return as much of the memory as
1607 * is possible back to the system as we are called from OOM.
1608 * To do this we must instruct the shmfs to drop all of its
1609 * backing pages, *now*.
1611 inode = file_inode(obj->base.filp);
1612 shmem_truncate_range(inode, 0, (loff_t)-1);
1614 obj->madv = __I915_MADV_PURGED;
1618 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1620 return obj->madv == I915_MADV_DONTNEED;
1624 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1626 struct sg_page_iter sg_iter;
1629 BUG_ON(obj->madv == __I915_MADV_PURGED);
1631 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1633 /* In the event of a disaster, abandon all caches and
1634 * hope for the best.
1636 WARN_ON(ret != -EIO);
1637 i915_gem_clflush_object(obj, true);
1638 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1641 if (i915_gem_object_needs_bit17_swizzle(obj))
1642 i915_gem_object_save_bit_17_swizzle(obj);
1644 if (obj->madv == I915_MADV_DONTNEED)
1647 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1648 struct page *page = sg_page_iter_page(&sg_iter);
1651 set_page_dirty(page);
1653 if (obj->madv == I915_MADV_WILLNEED)
1654 mark_page_accessed(page);
1656 page_cache_release(page);
1660 sg_free_table(obj->pages);
1665 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1667 const struct drm_i915_gem_object_ops *ops = obj->ops;
1669 if (obj->pages == NULL)
1672 if (obj->pages_pin_count)
1675 BUG_ON(i915_gem_obj_bound_any(obj));
1677 /* ->put_pages might need to allocate memory for the bit17 swizzle
1678 * array, hence protect them from being reaped by removing them from gtt
1680 list_del(&obj->global_list);
1682 ops->put_pages(obj);
1685 if (i915_gem_object_is_purgeable(obj))
1686 i915_gem_object_truncate(obj);
1692 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1693 bool purgeable_only)
1695 struct list_head still_bound_list;
1696 struct drm_i915_gem_object *obj, *next;
1699 list_for_each_entry_safe(obj, next,
1700 &dev_priv->mm.unbound_list,
1702 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1703 i915_gem_object_put_pages(obj) == 0) {
1704 count += obj->base.size >> PAGE_SHIFT;
1705 if (count >= target)
1711 * As we may completely rewrite the bound list whilst unbinding
1712 * (due to retiring requests) we have to strictly process only
1713 * one element of the list at the time, and recheck the list
1714 * on every iteration.
1716 INIT_LIST_HEAD(&still_bound_list);
1717 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1718 struct i915_vma *vma, *v;
1720 obj = list_first_entry(&dev_priv->mm.bound_list,
1721 typeof(*obj), global_list);
1722 list_move_tail(&obj->global_list, &still_bound_list);
1724 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1728 * Hold a reference whilst we unbind this object, as we may
1729 * end up waiting for and retiring requests. This might
1730 * release the final reference (held by the active list)
1731 * and result in the object being freed from under us.
1732 * in this object being freed.
1734 * Note 1: Shrinking the bound list is special since only active
1735 * (and hence bound objects) can contain such limbo objects, so
1736 * we don't need special tricks for shrinking the unbound list.
1737 * The only other place where we have to be careful with active
1738 * objects suddenly disappearing due to retiring requests is the
1741 * Note 2: Even though the bound list doesn't hold a reference
1742 * to the object we can safely grab one here: The final object
1743 * unreferencing and the bound_list are both protected by the
1744 * dev->struct_mutex and so we won't ever be able to observe an
1745 * object on the bound_list with a reference count equals 0.
1747 drm_gem_object_reference(&obj->base);
1749 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1750 if (i915_vma_unbind(vma))
1753 if (i915_gem_object_put_pages(obj) == 0)
1754 count += obj->base.size >> PAGE_SHIFT;
1756 drm_gem_object_unreference(&obj->base);
1758 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1764 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1766 return __i915_gem_shrink(dev_priv, target, true);
1770 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1772 struct drm_i915_gem_object *obj, *next;
1774 i915_gem_evict_everything(dev_priv->dev);
1776 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1778 i915_gem_object_put_pages(obj);
1782 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1784 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1786 struct address_space *mapping;
1787 struct sg_table *st;
1788 struct scatterlist *sg;
1789 struct sg_page_iter sg_iter;
1791 unsigned long last_pfn = 0; /* suppress gcc warning */
1794 /* Assert that the object is not currently in any GPU domain. As it
1795 * wasn't in the GTT, there shouldn't be any way it could have been in
1798 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1799 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1801 st = kmalloc(sizeof(*st), GFP_KERNEL);
1805 page_count = obj->base.size / PAGE_SIZE;
1806 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1811 /* Get the list of pages out of our struct file. They'll be pinned
1812 * at this point until we release them.
1814 * Fail silently without starting the shrinker
1816 mapping = file_inode(obj->base.filp)->i_mapping;
1817 gfp = mapping_gfp_mask(mapping);
1818 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1819 gfp &= ~(__GFP_IO | __GFP_WAIT);
1822 for (i = 0; i < page_count; i++) {
1823 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1825 i915_gem_purge(dev_priv, page_count);
1826 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1829 /* We've tried hard to allocate the memory by reaping
1830 * our own buffer, now let the real VM do its job and
1831 * go down in flames if truly OOM.
1833 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1834 gfp |= __GFP_IO | __GFP_WAIT;
1836 i915_gem_shrink_all(dev_priv);
1837 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1841 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1842 gfp &= ~(__GFP_IO | __GFP_WAIT);
1844 #ifdef CONFIG_SWIOTLB
1845 if (swiotlb_nr_tbl()) {
1847 sg_set_page(sg, page, PAGE_SIZE, 0);
1852 if (!i || page_to_pfn(page) != last_pfn + 1) {
1856 sg_set_page(sg, page, PAGE_SIZE, 0);
1858 sg->length += PAGE_SIZE;
1860 last_pfn = page_to_pfn(page);
1862 #ifdef CONFIG_SWIOTLB
1863 if (!swiotlb_nr_tbl())
1868 if (i915_gem_object_needs_bit17_swizzle(obj))
1869 i915_gem_object_do_bit_17_swizzle(obj);
1875 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1876 page_cache_release(sg_page_iter_page(&sg_iter));
1879 return PTR_ERR(page);
1882 /* Ensure that the associated pages are gathered from the backing storage
1883 * and pinned into our object. i915_gem_object_get_pages() may be called
1884 * multiple times before they are released by a single call to
1885 * i915_gem_object_put_pages() - once the pages are no longer referenced
1886 * either as a result of memory pressure (reaping pages under the shrinker)
1887 * or as the object is itself released.
1890 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1892 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1893 const struct drm_i915_gem_object_ops *ops = obj->ops;
1899 if (obj->madv != I915_MADV_WILLNEED) {
1900 DRM_ERROR("Attempting to obtain a purgeable object\n");
1904 BUG_ON(obj->pages_pin_count);
1906 ret = ops->get_pages(obj);
1910 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1915 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1916 struct intel_ring_buffer *ring)
1918 struct drm_device *dev = obj->base.dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920 u32 seqno = intel_ring_get_seqno(ring);
1922 BUG_ON(ring == NULL);
1923 if (obj->ring != ring && obj->last_write_seqno) {
1924 /* Keep the seqno relative to the current ring */
1925 obj->last_write_seqno = seqno;
1929 /* Add a reference if we're newly entering the active list. */
1931 drm_gem_object_reference(&obj->base);
1935 list_move_tail(&obj->ring_list, &ring->active_list);
1937 obj->last_read_seqno = seqno;
1939 if (obj->fenced_gpu_access) {
1940 obj->last_fenced_seqno = seqno;
1942 /* Bump MRU to take account of the delayed flush */
1943 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1944 struct drm_i915_fence_reg *reg;
1946 reg = &dev_priv->fence_regs[obj->fence_reg];
1947 list_move_tail(®->lru_list,
1948 &dev_priv->mm.fence_list);
1954 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1956 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1957 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1958 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1960 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1961 BUG_ON(!obj->active);
1963 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1965 list_del_init(&obj->ring_list);
1968 obj->last_read_seqno = 0;
1969 obj->last_write_seqno = 0;
1970 obj->base.write_domain = 0;
1972 obj->last_fenced_seqno = 0;
1973 obj->fenced_gpu_access = false;
1976 drm_gem_object_unreference(&obj->base);
1978 WARN_ON(i915_verify_lists(dev));
1982 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985 struct intel_ring_buffer *ring;
1988 /* Carefully retire all requests without writing to the rings */
1989 for_each_ring(ring, dev_priv, i) {
1990 ret = intel_ring_idle(ring);
1994 i915_gem_retire_requests(dev);
1996 /* Finally reset hw state */
1997 for_each_ring(ring, dev_priv, i) {
1998 intel_ring_init_seqno(ring, seqno);
2000 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2001 ring->sync_seqno[j] = 0;
2007 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2015 /* HWS page needs to be set less than what we
2016 * will inject to ring
2018 ret = i915_gem_init_seqno(dev, seqno - 1);
2022 /* Carefully set the last_seqno value so that wrap
2023 * detection still works
2025 dev_priv->next_seqno = seqno;
2026 dev_priv->last_seqno = seqno - 1;
2027 if (dev_priv->last_seqno == 0)
2028 dev_priv->last_seqno--;
2034 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2038 /* reserve 0 for non-seqno */
2039 if (dev_priv->next_seqno == 0) {
2040 int ret = i915_gem_init_seqno(dev, 0);
2044 dev_priv->next_seqno = 1;
2047 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2051 int __i915_add_request(struct intel_ring_buffer *ring,
2052 struct drm_file *file,
2053 struct drm_i915_gem_object *obj,
2056 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2057 struct drm_i915_gem_request *request;
2058 u32 request_ring_position, request_start;
2062 request_start = intel_ring_get_tail(ring);
2064 * Emit any outstanding flushes - execbuf can fail to emit the flush
2065 * after having emitted the batchbuffer command. Hence we need to fix
2066 * things up similar to emitting the lazy request. The difference here
2067 * is that the flush _must_ happen before the next request, no matter
2070 ret = intel_ring_flush_all_caches(ring);
2074 request = kmalloc(sizeof(*request), GFP_KERNEL);
2075 if (request == NULL)
2079 /* Record the position of the start of the request so that
2080 * should we detect the updated seqno part-way through the
2081 * GPU processing the request, we never over-estimate the
2082 * position of the head.
2084 request_ring_position = intel_ring_get_tail(ring);
2086 ret = ring->add_request(ring);
2092 request->seqno = intel_ring_get_seqno(ring);
2093 request->ring = ring;
2094 request->head = request_start;
2095 request->tail = request_ring_position;
2096 request->ctx = ring->last_context;
2097 request->batch_obj = obj;
2099 /* Whilst this request exists, batch_obj will be on the
2100 * active_list, and so will hold the active reference. Only when this
2101 * request is retired will the the batch_obj be moved onto the
2102 * inactive_list and lose its active reference. Hence we do not need
2103 * to explicitly hold another reference here.
2107 i915_gem_context_reference(request->ctx);
2109 request->emitted_jiffies = jiffies;
2110 was_empty = list_empty(&ring->request_list);
2111 list_add_tail(&request->list, &ring->request_list);
2112 request->file_priv = NULL;
2115 struct drm_i915_file_private *file_priv = file->driver_priv;
2117 spin_lock(&file_priv->mm.lock);
2118 request->file_priv = file_priv;
2119 list_add_tail(&request->client_list,
2120 &file_priv->mm.request_list);
2121 spin_unlock(&file_priv->mm.lock);
2124 trace_i915_gem_request_add(ring, request->seqno);
2125 ring->outstanding_lazy_request = 0;
2127 if (!dev_priv->ums.mm_suspended) {
2128 i915_queue_hangcheck(ring->dev);
2131 queue_delayed_work(dev_priv->wq,
2132 &dev_priv->mm.retire_work,
2133 round_jiffies_up_relative(HZ));
2134 intel_mark_busy(dev_priv->dev);
2139 *out_seqno = request->seqno;
2144 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2146 struct drm_i915_file_private *file_priv = request->file_priv;
2151 spin_lock(&file_priv->mm.lock);
2152 if (request->file_priv) {
2153 list_del(&request->client_list);
2154 request->file_priv = NULL;
2156 spin_unlock(&file_priv->mm.lock);
2159 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2160 struct i915_address_space *vm)
2162 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2163 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2169 static bool i915_head_inside_request(const u32 acthd_unmasked,
2170 const u32 request_start,
2171 const u32 request_end)
2173 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2175 if (request_start < request_end) {
2176 if (acthd >= request_start && acthd < request_end)
2178 } else if (request_start > request_end) {
2179 if (acthd >= request_start || acthd < request_end)
2186 static struct i915_address_space *
2187 request_to_vm(struct drm_i915_gem_request *request)
2189 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2190 struct i915_address_space *vm;
2192 vm = &dev_priv->gtt.base;
2197 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2198 const u32 acthd, bool *inside)
2200 /* There is a possibility that unmasked head address
2201 * pointing inside the ring, matches the batch_obj address range.
2202 * However this is extremely unlikely.
2204 if (request->batch_obj) {
2205 if (i915_head_inside_object(acthd, request->batch_obj,
2206 request_to_vm(request))) {
2212 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2220 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2221 struct drm_i915_gem_request *request,
2224 struct i915_ctx_hang_stats *hs = NULL;
2225 bool inside, guilty;
2226 unsigned long offset = 0;
2228 /* Innocent until proven guilty */
2231 if (request->batch_obj)
2232 offset = i915_gem_obj_offset(request->batch_obj,
2233 request_to_vm(request));
2235 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2236 i915_request_guilty(request, acthd, &inside)) {
2237 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2239 inside ? "inside" : "flushing",
2241 request->ctx ? request->ctx->id : 0,
2247 /* If contexts are disabled or this is the default context, use
2248 * file_priv->reset_state
2250 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2251 hs = &request->ctx->hang_stats;
2252 else if (request->file_priv)
2253 hs = &request->file_priv->hang_stats;
2259 hs->batch_pending++;
2263 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2265 list_del(&request->list);
2266 i915_gem_request_remove_from_client(request);
2269 i915_gem_context_unreference(request->ctx);
2274 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2275 struct intel_ring_buffer *ring)
2277 u32 completed_seqno;
2280 acthd = intel_ring_get_active_head(ring);
2281 completed_seqno = ring->get_seqno(ring, false);
2283 while (!list_empty(&ring->request_list)) {
2284 struct drm_i915_gem_request *request;
2286 request = list_first_entry(&ring->request_list,
2287 struct drm_i915_gem_request,
2290 if (request->seqno > completed_seqno)
2291 i915_set_reset_status(ring, request, acthd);
2293 i915_gem_free_request(request);
2296 while (!list_empty(&ring->active_list)) {
2297 struct drm_i915_gem_object *obj;
2299 obj = list_first_entry(&ring->active_list,
2300 struct drm_i915_gem_object,
2303 i915_gem_object_move_to_inactive(obj);
2307 void i915_gem_restore_fences(struct drm_device *dev)
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2312 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2313 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2316 * Commit delayed tiling changes if we have an object still
2317 * attached to the fence, otherwise just clear the fence.
2320 i915_gem_object_update_fence(reg->obj, reg,
2321 reg->obj->tiling_mode);
2323 i915_gem_write_fence(dev, i, NULL);
2328 void i915_gem_reset(struct drm_device *dev)
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct intel_ring_buffer *ring;
2334 for_each_ring(ring, dev_priv, i)
2335 i915_gem_reset_ring_lists(dev_priv, ring);
2337 i915_gem_restore_fences(dev);
2341 * This function clears the request list as sequence numbers are passed.
2344 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2348 if (list_empty(&ring->request_list))
2351 WARN_ON(i915_verify_lists(ring->dev));
2353 seqno = ring->get_seqno(ring, true);
2355 while (!list_empty(&ring->request_list)) {
2356 struct drm_i915_gem_request *request;
2358 request = list_first_entry(&ring->request_list,
2359 struct drm_i915_gem_request,
2362 if (!i915_seqno_passed(seqno, request->seqno))
2365 trace_i915_gem_request_retire(ring, request->seqno);
2366 /* We know the GPU must have read the request to have
2367 * sent us the seqno + interrupt, so use the position
2368 * of tail of the request to update the last known position
2371 ring->last_retired_head = request->tail;
2373 i915_gem_free_request(request);
2376 /* Move any buffers on the active list that are no longer referenced
2377 * by the ringbuffer to the flushing/inactive lists as appropriate.
2379 while (!list_empty(&ring->active_list)) {
2380 struct drm_i915_gem_object *obj;
2382 obj = list_first_entry(&ring->active_list,
2383 struct drm_i915_gem_object,
2386 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2389 i915_gem_object_move_to_inactive(obj);
2392 if (unlikely(ring->trace_irq_seqno &&
2393 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2394 ring->irq_put(ring);
2395 ring->trace_irq_seqno = 0;
2398 WARN_ON(i915_verify_lists(ring->dev));
2402 i915_gem_retire_requests(struct drm_device *dev)
2404 drm_i915_private_t *dev_priv = dev->dev_private;
2405 struct intel_ring_buffer *ring;
2408 for_each_ring(ring, dev_priv, i)
2409 i915_gem_retire_requests_ring(ring);
2413 i915_gem_retire_work_handler(struct work_struct *work)
2415 drm_i915_private_t *dev_priv;
2416 struct drm_device *dev;
2417 struct intel_ring_buffer *ring;
2421 dev_priv = container_of(work, drm_i915_private_t,
2422 mm.retire_work.work);
2423 dev = dev_priv->dev;
2425 /* Come back later if the device is busy... */
2426 if (!mutex_trylock(&dev->struct_mutex)) {
2427 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2428 round_jiffies_up_relative(HZ));
2432 i915_gem_retire_requests(dev);
2434 /* Send a periodic flush down the ring so we don't hold onto GEM
2435 * objects indefinitely.
2438 for_each_ring(ring, dev_priv, i) {
2439 if (ring->gpu_caches_dirty)
2440 i915_add_request(ring, NULL);
2442 idle &= list_empty(&ring->request_list);
2445 if (!dev_priv->ums.mm_suspended && !idle)
2446 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2447 round_jiffies_up_relative(HZ));
2449 intel_mark_idle(dev);
2451 mutex_unlock(&dev->struct_mutex);
2455 * Ensures that an object will eventually get non-busy by flushing any required
2456 * write domains, emitting any outstanding lazy request and retiring and
2457 * completed requests.
2460 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2465 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2469 i915_gem_retire_requests_ring(obj->ring);
2476 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2477 * @DRM_IOCTL_ARGS: standard ioctl arguments
2479 * Returns 0 if successful, else an error is returned with the remaining time in
2480 * the timeout parameter.
2481 * -ETIME: object is still busy after timeout
2482 * -ERESTARTSYS: signal interrupted the wait
2483 * -ENONENT: object doesn't exist
2484 * Also possible, but rare:
2485 * -EAGAIN: GPU wedged
2487 * -ENODEV: Internal IRQ fail
2488 * -E?: The add request failed
2490 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2491 * non-zero timeout parameter the wait ioctl will wait for the given number of
2492 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2493 * without holding struct_mutex the object may become re-busied before this
2494 * function completes. A similar but shorter * race condition exists in the busy
2498 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2500 drm_i915_private_t *dev_priv = dev->dev_private;
2501 struct drm_i915_gem_wait *args = data;
2502 struct drm_i915_gem_object *obj;
2503 struct intel_ring_buffer *ring = NULL;
2504 struct timespec timeout_stack, *timeout = NULL;
2505 unsigned reset_counter;
2509 if (args->timeout_ns >= 0) {
2510 timeout_stack = ns_to_timespec(args->timeout_ns);
2511 timeout = &timeout_stack;
2514 ret = i915_mutex_lock_interruptible(dev);
2518 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2519 if (&obj->base == NULL) {
2520 mutex_unlock(&dev->struct_mutex);
2524 /* Need to make sure the object gets inactive eventually. */
2525 ret = i915_gem_object_flush_active(obj);
2530 seqno = obj->last_read_seqno;
2537 /* Do this after OLR check to make sure we make forward progress polling
2538 * on this IOCTL with a 0 timeout (like busy ioctl)
2540 if (!args->timeout_ns) {
2545 drm_gem_object_unreference(&obj->base);
2546 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2547 mutex_unlock(&dev->struct_mutex);
2549 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2551 args->timeout_ns = timespec_to_ns(timeout);
2555 drm_gem_object_unreference(&obj->base);
2556 mutex_unlock(&dev->struct_mutex);
2561 * i915_gem_object_sync - sync an object to a ring.
2563 * @obj: object which may be in use on another ring.
2564 * @to: ring we wish to use the object on. May be NULL.
2566 * This code is meant to abstract object synchronization with the GPU.
2567 * Calling with NULL implies synchronizing the object with the CPU
2568 * rather than a particular GPU ring.
2570 * Returns 0 if successful, else propagates up the lower layer error.
2573 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2574 struct intel_ring_buffer *to)
2576 struct intel_ring_buffer *from = obj->ring;
2580 if (from == NULL || to == from)
2583 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2584 return i915_gem_object_wait_rendering(obj, false);
2586 idx = intel_ring_sync_index(from, to);
2588 seqno = obj->last_read_seqno;
2589 if (seqno <= from->sync_seqno[idx])
2592 ret = i915_gem_check_olr(obj->ring, seqno);
2596 ret = to->sync_to(to, from, seqno);
2598 /* We use last_read_seqno because sync_to()
2599 * might have just caused seqno wrap under
2602 from->sync_seqno[idx] = obj->last_read_seqno;
2607 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2609 u32 old_write_domain, old_read_domains;
2611 /* Force a pagefault for domain tracking on next user access */
2612 i915_gem_release_mmap(obj);
2614 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2617 /* Wait for any direct GTT access to complete */
2620 old_read_domains = obj->base.read_domains;
2621 old_write_domain = obj->base.write_domain;
2623 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2624 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2626 trace_i915_gem_object_change_domain(obj,
2631 int i915_vma_unbind(struct i915_vma *vma)
2633 struct drm_i915_gem_object *obj = vma->obj;
2634 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2637 if (list_empty(&vma->vma_link))
2640 if (!drm_mm_node_allocated(&vma->node))
2646 BUG_ON(obj->pages == NULL);
2648 ret = i915_gem_object_finish_gpu(obj);
2651 /* Continue on if we fail due to EIO, the GPU is hung so we
2652 * should be safe and we need to cleanup or else we might
2653 * cause memory corruption through use-after-free.
2656 i915_gem_object_finish_gtt(obj);
2658 /* release the fence reg _after_ flushing */
2659 ret = i915_gem_object_put_fence(obj);
2663 trace_i915_vma_unbind(vma);
2665 if (obj->has_global_gtt_mapping)
2666 i915_gem_gtt_unbind_object(obj);
2667 if (obj->has_aliasing_ppgtt_mapping) {
2668 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2669 obj->has_aliasing_ppgtt_mapping = 0;
2671 i915_gem_gtt_finish_object(obj);
2672 i915_gem_object_unpin_pages(obj);
2674 list_del(&vma->mm_list);
2675 /* Avoid an unnecessary call to unbind on rebind. */
2676 if (i915_is_ggtt(vma->vm))
2677 obj->map_and_fenceable = true;
2679 drm_mm_remove_node(&vma->node);
2682 i915_gem_vma_destroy(vma);
2684 /* Since the unbound list is global, only move to that list if
2685 * no more VMAs exist.
2686 * NB: Until we have real VMAs there will only ever be one */
2687 WARN_ON(!list_empty(&obj->vma_list));
2688 if (list_empty(&obj->vma_list))
2689 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2695 * Unbinds an object from the global GTT aperture.
2698 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2700 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2701 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2703 if (!i915_gem_obj_ggtt_bound(obj))
2709 BUG_ON(obj->pages == NULL);
2711 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2714 int i915_gpu_idle(struct drm_device *dev)
2716 drm_i915_private_t *dev_priv = dev->dev_private;
2717 struct intel_ring_buffer *ring;
2720 /* Flush everything onto the inactive list. */
2721 for_each_ring(ring, dev_priv, i) {
2722 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2726 ret = intel_ring_idle(ring);
2734 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2735 struct drm_i915_gem_object *obj)
2737 drm_i915_private_t *dev_priv = dev->dev_private;
2739 int fence_pitch_shift;
2741 if (INTEL_INFO(dev)->gen >= 6) {
2742 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2743 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2745 fence_reg = FENCE_REG_965_0;
2746 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2749 fence_reg += reg * 8;
2751 /* To w/a incoherency with non-atomic 64-bit register updates,
2752 * we split the 64-bit update into two 32-bit writes. In order
2753 * for a partial fence not to be evaluated between writes, we
2754 * precede the update with write to turn off the fence register,
2755 * and only enable the fence as the last step.
2757 * For extra levels of paranoia, we make sure each step lands
2758 * before applying the next step.
2760 I915_WRITE(fence_reg, 0);
2761 POSTING_READ(fence_reg);
2764 u32 size = i915_gem_obj_ggtt_size(obj);
2767 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2769 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2770 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2771 if (obj->tiling_mode == I915_TILING_Y)
2772 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2773 val |= I965_FENCE_REG_VALID;
2775 I915_WRITE(fence_reg + 4, val >> 32);
2776 POSTING_READ(fence_reg + 4);
2778 I915_WRITE(fence_reg + 0, val);
2779 POSTING_READ(fence_reg);
2781 I915_WRITE(fence_reg + 4, 0);
2782 POSTING_READ(fence_reg + 4);
2786 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2787 struct drm_i915_gem_object *obj)
2789 drm_i915_private_t *dev_priv = dev->dev_private;
2793 u32 size = i915_gem_obj_ggtt_size(obj);
2797 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2798 (size & -size) != size ||
2799 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2800 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2801 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2803 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2808 /* Note: pitch better be a power of two tile widths */
2809 pitch_val = obj->stride / tile_width;
2810 pitch_val = ffs(pitch_val) - 1;
2812 val = i915_gem_obj_ggtt_offset(obj);
2813 if (obj->tiling_mode == I915_TILING_Y)
2814 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2815 val |= I915_FENCE_SIZE_BITS(size);
2816 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2817 val |= I830_FENCE_REG_VALID;
2822 reg = FENCE_REG_830_0 + reg * 4;
2824 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2826 I915_WRITE(reg, val);
2830 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2831 struct drm_i915_gem_object *obj)
2833 drm_i915_private_t *dev_priv = dev->dev_private;
2837 u32 size = i915_gem_obj_ggtt_size(obj);
2840 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2841 (size & -size) != size ||
2842 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2843 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2844 i915_gem_obj_ggtt_offset(obj), size);
2846 pitch_val = obj->stride / 128;
2847 pitch_val = ffs(pitch_val) - 1;
2849 val = i915_gem_obj_ggtt_offset(obj);
2850 if (obj->tiling_mode == I915_TILING_Y)
2851 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2852 val |= I830_FENCE_SIZE_BITS(size);
2853 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2854 val |= I830_FENCE_REG_VALID;
2858 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2859 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2862 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2864 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2867 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2868 struct drm_i915_gem_object *obj)
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2872 /* Ensure that all CPU reads are completed before installing a fence
2873 * and all writes before removing the fence.
2875 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2878 WARN(obj && (!obj->stride || !obj->tiling_mode),
2879 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2880 obj->stride, obj->tiling_mode);
2882 switch (INTEL_INFO(dev)->gen) {
2886 case 4: i965_write_fence_reg(dev, reg, obj); break;
2887 case 3: i915_write_fence_reg(dev, reg, obj); break;
2888 case 2: i830_write_fence_reg(dev, reg, obj); break;
2892 /* And similarly be paranoid that no direct access to this region
2893 * is reordered to before the fence is installed.
2895 if (i915_gem_object_needs_mb(obj))
2899 static inline int fence_number(struct drm_i915_private *dev_priv,
2900 struct drm_i915_fence_reg *fence)
2902 return fence - dev_priv->fence_regs;
2905 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2906 struct drm_i915_fence_reg *fence,
2909 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2910 int reg = fence_number(dev_priv, fence);
2912 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2915 obj->fence_reg = reg;
2917 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2919 obj->fence_reg = I915_FENCE_REG_NONE;
2921 list_del_init(&fence->lru_list);
2923 obj->fence_dirty = false;
2927 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2929 if (obj->last_fenced_seqno) {
2930 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2934 obj->last_fenced_seqno = 0;
2937 obj->fenced_gpu_access = false;
2942 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2944 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2945 struct drm_i915_fence_reg *fence;
2948 ret = i915_gem_object_wait_fence(obj);
2952 if (obj->fence_reg == I915_FENCE_REG_NONE)
2955 fence = &dev_priv->fence_regs[obj->fence_reg];
2957 i915_gem_object_fence_lost(obj);
2958 i915_gem_object_update_fence(obj, fence, false);
2963 static struct drm_i915_fence_reg *
2964 i915_find_fence_reg(struct drm_device *dev)
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967 struct drm_i915_fence_reg *reg, *avail;
2970 /* First try to find a free reg */
2972 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2973 reg = &dev_priv->fence_regs[i];
2977 if (!reg->pin_count)
2984 /* None available, try to steal one or wait for a user to finish */
2985 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2996 * i915_gem_object_get_fence - set up fencing for an object
2997 * @obj: object to map through a fence reg
2999 * When mapping objects through the GTT, userspace wants to be able to write
3000 * to them without having to worry about swizzling if the object is tiled.
3001 * This function walks the fence regs looking for a free one for @obj,
3002 * stealing one if it can't find any.
3004 * It then sets up the reg based on the object's properties: address, pitch
3005 * and tiling format.
3007 * For an untiled surface, this removes any existing fence.
3010 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3012 struct drm_device *dev = obj->base.dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 bool enable = obj->tiling_mode != I915_TILING_NONE;
3015 struct drm_i915_fence_reg *reg;
3018 /* Have we updated the tiling parameters upon the object and so
3019 * will need to serialise the write to the associated fence register?
3021 if (obj->fence_dirty) {
3022 ret = i915_gem_object_wait_fence(obj);
3027 /* Just update our place in the LRU if our fence is getting reused. */
3028 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3029 reg = &dev_priv->fence_regs[obj->fence_reg];
3030 if (!obj->fence_dirty) {
3031 list_move_tail(®->lru_list,
3032 &dev_priv->mm.fence_list);
3035 } else if (enable) {
3036 reg = i915_find_fence_reg(dev);
3041 struct drm_i915_gem_object *old = reg->obj;
3043 ret = i915_gem_object_wait_fence(old);
3047 i915_gem_object_fence_lost(old);
3052 i915_gem_object_update_fence(obj, reg, enable);
3057 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3058 struct drm_mm_node *gtt_space,
3059 unsigned long cache_level)
3061 struct drm_mm_node *other;
3063 /* On non-LLC machines we have to be careful when putting differing
3064 * types of snoopable memory together to avoid the prefetcher
3065 * crossing memory domains and dying.
3070 if (!drm_mm_node_allocated(gtt_space))
3073 if (list_empty(>t_space->node_list))
3076 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3077 if (other->allocated && !other->hole_follows && other->color != cache_level)
3080 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3081 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3087 static void i915_gem_verify_gtt(struct drm_device *dev)
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 struct drm_i915_gem_object *obj;
3094 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3095 if (obj->gtt_space == NULL) {
3096 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3101 if (obj->cache_level != obj->gtt_space->color) {
3102 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3103 i915_gem_obj_ggtt_offset(obj),
3104 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3106 obj->gtt_space->color);
3111 if (!i915_gem_valid_gtt_space(dev,
3113 obj->cache_level)) {
3114 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3115 i915_gem_obj_ggtt_offset(obj),
3116 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3128 * Finds free space in the GTT aperture and binds the object there.
3131 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3132 struct i915_address_space *vm,
3134 bool map_and_fenceable,
3137 struct drm_device *dev = obj->base.dev;
3138 drm_i915_private_t *dev_priv = dev->dev_private;
3139 u32 size, fence_size, fence_alignment, unfenced_alignment;
3141 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3142 struct i915_vma *vma;
3145 fence_size = i915_gem_get_gtt_size(dev,
3148 fence_alignment = i915_gem_get_gtt_alignment(dev,
3150 obj->tiling_mode, true);
3151 unfenced_alignment =
3152 i915_gem_get_gtt_alignment(dev,
3154 obj->tiling_mode, false);
3157 alignment = map_and_fenceable ? fence_alignment :
3159 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3160 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3164 size = map_and_fenceable ? fence_size : obj->base.size;
3166 /* If the object is bigger than the entire aperture, reject it early
3167 * before evicting everything in a vain attempt to find space.
3169 if (obj->base.size > gtt_max) {
3170 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3172 map_and_fenceable ? "mappable" : "total",
3177 ret = i915_gem_object_get_pages(obj);
3181 i915_gem_object_pin_pages(obj);
3183 BUG_ON(!i915_is_ggtt(vm));
3185 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3191 /* For now we only ever use 1 vma per object */
3192 WARN_ON(!list_is_singular(&obj->vma_list));
3195 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3197 obj->cache_level, 0, gtt_max,
3198 DRM_MM_SEARCH_DEFAULT);
3200 ret = i915_gem_evict_something(dev, vm, size, alignment,
3209 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3210 obj->cache_level))) {
3212 goto err_remove_node;
3215 ret = i915_gem_gtt_prepare_object(obj);
3217 goto err_remove_node;
3219 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3220 list_add_tail(&vma->mm_list, &vm->inactive_list);
3222 if (i915_is_ggtt(vm)) {
3223 bool mappable, fenceable;
3225 fenceable = (vma->node.size == fence_size &&
3226 (vma->node.start & (fence_alignment - 1)) == 0);
3228 mappable = (vma->node.start + obj->base.size <=
3229 dev_priv->gtt.mappable_end);
3231 obj->map_and_fenceable = mappable && fenceable;
3234 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3236 trace_i915_vma_bind(vma, map_and_fenceable);
3237 i915_gem_verify_gtt(dev);
3241 drm_mm_remove_node(&vma->node);
3243 i915_gem_vma_destroy(vma);
3245 i915_gem_object_unpin_pages(obj);
3250 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3253 /* If we don't have a page list set up, then we're not pinned
3254 * to GPU, and we can ignore the cache flush because it'll happen
3255 * again at bind time.
3257 if (obj->pages == NULL)
3261 * Stolen memory is always coherent with the GPU as it is explicitly
3262 * marked as wc by the system, or the system is cache-coherent.
3267 /* If the GPU is snooping the contents of the CPU cache,
3268 * we do not need to manually clear the CPU cache lines. However,
3269 * the caches are only snooped when the render cache is
3270 * flushed/invalidated. As we always have to emit invalidations
3271 * and flushes when moving into and out of the RENDER domain, correct
3272 * snooping behaviour occurs naturally as the result of our domain
3275 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3278 trace_i915_gem_object_clflush(obj);
3279 drm_clflush_sg(obj->pages);
3284 /** Flushes the GTT write domain for the object if it's dirty. */
3286 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3288 uint32_t old_write_domain;
3290 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3293 /* No actual flushing is required for the GTT write domain. Writes
3294 * to it immediately go to main memory as far as we know, so there's
3295 * no chipset flush. It also doesn't land in render cache.
3297 * However, we do have to enforce the order so that all writes through
3298 * the GTT land before any writes to the device, such as updates to
3303 old_write_domain = obj->base.write_domain;
3304 obj->base.write_domain = 0;
3306 trace_i915_gem_object_change_domain(obj,
3307 obj->base.read_domains,
3311 /** Flushes the CPU write domain for the object if it's dirty. */
3313 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3316 uint32_t old_write_domain;
3318 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3321 if (i915_gem_clflush_object(obj, force))
3322 i915_gem_chipset_flush(obj->base.dev);
3324 old_write_domain = obj->base.write_domain;
3325 obj->base.write_domain = 0;
3327 trace_i915_gem_object_change_domain(obj,
3328 obj->base.read_domains,
3333 * Moves a single object to the GTT read, and possibly write domain.
3335 * This function returns when the move is complete, including waiting on
3339 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3341 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3342 uint32_t old_write_domain, old_read_domains;
3345 /* Not valid to be called on unbound objects. */
3346 if (!i915_gem_obj_bound_any(obj))
3349 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3352 ret = i915_gem_object_wait_rendering(obj, !write);
3356 i915_gem_object_flush_cpu_write_domain(obj, false);
3358 /* Serialise direct access to this object with the barriers for
3359 * coherent writes from the GPU, by effectively invalidating the
3360 * GTT domain upon first access.
3362 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3365 old_write_domain = obj->base.write_domain;
3366 old_read_domains = obj->base.read_domains;
3368 /* It should now be out of any other write domains, and we can update
3369 * the domain values for our changes.
3371 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3372 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3374 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3375 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3379 trace_i915_gem_object_change_domain(obj,
3383 /* And bump the LRU for this access */
3384 if (i915_gem_object_is_inactive(obj)) {
3385 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3386 &dev_priv->gtt.base);
3388 list_move_tail(&vma->mm_list,
3389 &dev_priv->gtt.base.inactive_list);
3396 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3397 enum i915_cache_level cache_level)
3399 struct drm_device *dev = obj->base.dev;
3400 drm_i915_private_t *dev_priv = dev->dev_private;
3401 struct i915_vma *vma;
3404 if (obj->cache_level == cache_level)
3407 if (obj->pin_count) {
3408 DRM_DEBUG("can not change the cache level of pinned objects\n");
3412 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3413 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3414 ret = i915_vma_unbind(vma);
3422 if (i915_gem_obj_bound_any(obj)) {
3423 ret = i915_gem_object_finish_gpu(obj);
3427 i915_gem_object_finish_gtt(obj);
3429 /* Before SandyBridge, you could not use tiling or fence
3430 * registers with snooped memory, so relinquish any fences
3431 * currently pointing to our region in the aperture.
3433 if (INTEL_INFO(dev)->gen < 6) {
3434 ret = i915_gem_object_put_fence(obj);
3439 if (obj->has_global_gtt_mapping)
3440 i915_gem_gtt_bind_object(obj, cache_level);
3441 if (obj->has_aliasing_ppgtt_mapping)
3442 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3446 list_for_each_entry(vma, &obj->vma_list, vma_link)
3447 vma->node.color = cache_level;
3448 obj->cache_level = cache_level;
3450 if (cpu_write_needs_clflush(obj)) {
3451 u32 old_read_domains, old_write_domain;
3453 /* If we're coming from LLC cached, then we haven't
3454 * actually been tracking whether the data is in the
3455 * CPU cache or not, since we only allow one bit set
3456 * in obj->write_domain and have been skipping the clflushes.
3457 * Just set it to the CPU cache for now.
3459 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3461 old_read_domains = obj->base.read_domains;
3462 old_write_domain = obj->base.write_domain;
3464 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3465 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3467 trace_i915_gem_object_change_domain(obj,
3472 i915_gem_verify_gtt(dev);
3476 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3477 struct drm_file *file)
3479 struct drm_i915_gem_caching *args = data;
3480 struct drm_i915_gem_object *obj;
3483 ret = i915_mutex_lock_interruptible(dev);
3487 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3488 if (&obj->base == NULL) {
3493 switch (obj->cache_level) {
3494 case I915_CACHE_LLC:
3495 case I915_CACHE_L3_LLC:
3496 args->caching = I915_CACHING_CACHED;
3500 args->caching = I915_CACHING_DISPLAY;
3504 args->caching = I915_CACHING_NONE;
3508 drm_gem_object_unreference(&obj->base);
3510 mutex_unlock(&dev->struct_mutex);
3514 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3515 struct drm_file *file)
3517 struct drm_i915_gem_caching *args = data;
3518 struct drm_i915_gem_object *obj;
3519 enum i915_cache_level level;
3522 switch (args->caching) {
3523 case I915_CACHING_NONE:
3524 level = I915_CACHE_NONE;
3526 case I915_CACHING_CACHED:
3527 level = I915_CACHE_LLC;
3529 case I915_CACHING_DISPLAY:
3530 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3536 ret = i915_mutex_lock_interruptible(dev);
3540 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3541 if (&obj->base == NULL) {
3546 ret = i915_gem_object_set_cache_level(obj, level);
3548 drm_gem_object_unreference(&obj->base);
3550 mutex_unlock(&dev->struct_mutex);
3554 static bool is_pin_display(struct drm_i915_gem_object *obj)
3556 /* There are 3 sources that pin objects:
3557 * 1. The display engine (scanouts, sprites, cursors);
3558 * 2. Reservations for execbuffer;
3561 * We can ignore reservations as we hold the struct_mutex and
3562 * are only called outside of the reservation path. The user
3563 * can only increment pin_count once, and so if after
3564 * subtracting the potential reference by the user, any pin_count
3565 * remains, it must be due to another use by the display engine.
3567 return obj->pin_count - !!obj->user_pin_count;
3571 * Prepare buffer for display plane (scanout, cursors, etc).
3572 * Can be called from an uninterruptible phase (modesetting) and allows
3573 * any flushes to be pipelined (for pageflips).
3576 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3578 struct intel_ring_buffer *pipelined)
3580 u32 old_read_domains, old_write_domain;
3583 if (pipelined != obj->ring) {
3584 ret = i915_gem_object_sync(obj, pipelined);
3589 /* Mark the pin_display early so that we account for the
3590 * display coherency whilst setting up the cache domains.
3592 obj->pin_display = true;
3594 /* The display engine is not coherent with the LLC cache on gen6. As
3595 * a result, we make sure that the pinning that is about to occur is
3596 * done with uncached PTEs. This is lowest common denominator for all
3599 * However for gen6+, we could do better by using the GFDT bit instead
3600 * of uncaching, which would allow us to flush all the LLC-cached data
3601 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3603 ret = i915_gem_object_set_cache_level(obj,
3604 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3606 goto err_unpin_display;
3608 /* As the user may map the buffer once pinned in the display plane
3609 * (e.g. libkms for the bootup splash), we have to ensure that we
3610 * always use map_and_fenceable for all scanout buffers.
3612 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3614 goto err_unpin_display;
3616 i915_gem_object_flush_cpu_write_domain(obj, true);
3618 old_write_domain = obj->base.write_domain;
3619 old_read_domains = obj->base.read_domains;
3621 /* It should now be out of any other write domains, and we can update
3622 * the domain values for our changes.
3624 obj->base.write_domain = 0;
3625 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3627 trace_i915_gem_object_change_domain(obj,
3634 obj->pin_display = is_pin_display(obj);
3639 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3641 i915_gem_object_unpin(obj);
3642 obj->pin_display = is_pin_display(obj);
3646 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3650 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3653 ret = i915_gem_object_wait_rendering(obj, false);
3657 /* Ensure that we invalidate the GPU's caches and TLBs. */
3658 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3663 * Moves a single object to the CPU read, and possibly write domain.
3665 * This function returns when the move is complete, including waiting on
3669 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3671 uint32_t old_write_domain, old_read_domains;
3674 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3677 ret = i915_gem_object_wait_rendering(obj, !write);
3681 i915_gem_object_flush_gtt_write_domain(obj);
3683 old_write_domain = obj->base.write_domain;
3684 old_read_domains = obj->base.read_domains;
3686 /* Flush the CPU cache if it's still invalid. */
3687 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3688 i915_gem_clflush_object(obj, false);
3690 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3693 /* It should now be out of any other write domains, and we can update
3694 * the domain values for our changes.
3696 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3698 /* If we're writing through the CPU, then the GPU read domains will
3699 * need to be invalidated at next use.
3702 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3703 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3706 trace_i915_gem_object_change_domain(obj,
3713 /* Throttle our rendering by waiting until the ring has completed our requests
3714 * emitted over 20 msec ago.
3716 * Note that if we were to use the current jiffies each time around the loop,
3717 * we wouldn't escape the function with any frames outstanding if the time to
3718 * render a frame was over 20ms.
3720 * This should get us reasonable parallelism between CPU and GPU but also
3721 * relatively low latency when blocking on a particular request to finish.
3724 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct drm_i915_file_private *file_priv = file->driver_priv;
3728 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3729 struct drm_i915_gem_request *request;
3730 struct intel_ring_buffer *ring = NULL;
3731 unsigned reset_counter;
3735 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3739 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3743 spin_lock(&file_priv->mm.lock);
3744 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3745 if (time_after_eq(request->emitted_jiffies, recent_enough))
3748 ring = request->ring;
3749 seqno = request->seqno;
3751 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3752 spin_unlock(&file_priv->mm.lock);
3757 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3759 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3765 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3766 struct i915_address_space *vm,
3768 bool map_and_fenceable,
3771 struct i915_vma *vma;
3774 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3777 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3779 vma = i915_gem_obj_to_vma(obj, vm);
3783 vma->node.start & (alignment - 1)) ||
3784 (map_and_fenceable && !obj->map_and_fenceable)) {
3785 WARN(obj->pin_count,
3786 "bo is already pinned with incorrect alignment:"
3787 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3788 " obj->map_and_fenceable=%d\n",
3789 i915_gem_obj_offset(obj, vm), alignment,
3791 obj->map_and_fenceable);
3792 ret = i915_vma_unbind(vma);
3798 if (!i915_gem_obj_bound(obj, vm)) {
3799 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3801 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3807 if (!dev_priv->mm.aliasing_ppgtt)
3808 i915_gem_gtt_bind_object(obj, obj->cache_level);
3811 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3812 i915_gem_gtt_bind_object(obj, obj->cache_level);
3815 obj->pin_mappable |= map_and_fenceable;
3821 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3823 BUG_ON(obj->pin_count == 0);
3824 BUG_ON(!i915_gem_obj_bound_any(obj));
3826 if (--obj->pin_count == 0)
3827 obj->pin_mappable = false;
3831 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3832 struct drm_file *file)
3834 struct drm_i915_gem_pin *args = data;
3835 struct drm_i915_gem_object *obj;
3838 ret = i915_mutex_lock_interruptible(dev);
3842 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3843 if (&obj->base == NULL) {
3848 if (obj->madv != I915_MADV_WILLNEED) {
3849 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3854 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3855 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3861 if (obj->user_pin_count == 0) {
3862 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3867 obj->user_pin_count++;
3868 obj->pin_filp = file;
3870 args->offset = i915_gem_obj_ggtt_offset(obj);
3872 drm_gem_object_unreference(&obj->base);
3874 mutex_unlock(&dev->struct_mutex);
3879 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3880 struct drm_file *file)
3882 struct drm_i915_gem_pin *args = data;
3883 struct drm_i915_gem_object *obj;
3886 ret = i915_mutex_lock_interruptible(dev);
3890 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3891 if (&obj->base == NULL) {
3896 if (obj->pin_filp != file) {
3897 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3902 obj->user_pin_count--;
3903 if (obj->user_pin_count == 0) {
3904 obj->pin_filp = NULL;
3905 i915_gem_object_unpin(obj);
3909 drm_gem_object_unreference(&obj->base);
3911 mutex_unlock(&dev->struct_mutex);
3916 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3917 struct drm_file *file)
3919 struct drm_i915_gem_busy *args = data;
3920 struct drm_i915_gem_object *obj;
3923 ret = i915_mutex_lock_interruptible(dev);
3927 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3928 if (&obj->base == NULL) {
3933 /* Count all active objects as busy, even if they are currently not used
3934 * by the gpu. Users of this interface expect objects to eventually
3935 * become non-busy without any further actions, therefore emit any
3936 * necessary flushes here.
3938 ret = i915_gem_object_flush_active(obj);
3940 args->busy = obj->active;
3942 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3943 args->busy |= intel_ring_flag(obj->ring) << 16;
3946 drm_gem_object_unreference(&obj->base);
3948 mutex_unlock(&dev->struct_mutex);
3953 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3954 struct drm_file *file_priv)
3956 return i915_gem_ring_throttle(dev, file_priv);
3960 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3961 struct drm_file *file_priv)
3963 struct drm_i915_gem_madvise *args = data;
3964 struct drm_i915_gem_object *obj;
3967 switch (args->madv) {
3968 case I915_MADV_DONTNEED:
3969 case I915_MADV_WILLNEED:
3975 ret = i915_mutex_lock_interruptible(dev);
3979 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3980 if (&obj->base == NULL) {
3985 if (obj->pin_count) {
3990 if (obj->madv != __I915_MADV_PURGED)
3991 obj->madv = args->madv;
3993 /* if the object is no longer attached, discard its backing storage */
3994 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3995 i915_gem_object_truncate(obj);
3997 args->retained = obj->madv != __I915_MADV_PURGED;
4000 drm_gem_object_unreference(&obj->base);
4002 mutex_unlock(&dev->struct_mutex);
4006 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4007 const struct drm_i915_gem_object_ops *ops)
4009 INIT_LIST_HEAD(&obj->global_list);
4010 INIT_LIST_HEAD(&obj->ring_list);
4011 INIT_LIST_HEAD(&obj->exec_list);
4012 INIT_LIST_HEAD(&obj->obj_exec_link);
4013 INIT_LIST_HEAD(&obj->vma_list);
4017 obj->fence_reg = I915_FENCE_REG_NONE;
4018 obj->madv = I915_MADV_WILLNEED;
4019 /* Avoid an unnecessary call to unbind on the first bind. */
4020 obj->map_and_fenceable = true;
4022 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4025 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4026 .get_pages = i915_gem_object_get_pages_gtt,
4027 .put_pages = i915_gem_object_put_pages_gtt,
4030 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4033 struct drm_i915_gem_object *obj;
4034 struct address_space *mapping;
4037 obj = i915_gem_object_alloc(dev);
4041 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4042 i915_gem_object_free(obj);
4046 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4047 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4048 /* 965gm cannot relocate objects above 4GiB. */
4049 mask &= ~__GFP_HIGHMEM;
4050 mask |= __GFP_DMA32;
4053 mapping = file_inode(obj->base.filp)->i_mapping;
4054 mapping_set_gfp_mask(mapping, mask);
4056 i915_gem_object_init(obj, &i915_gem_object_ops);
4058 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4059 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4062 /* On some devices, we can have the GPU use the LLC (the CPU
4063 * cache) for about a 10% performance improvement
4064 * compared to uncached. Graphics requests other than
4065 * display scanout are coherent with the CPU in
4066 * accessing this cache. This means in this mode we
4067 * don't need to clflush on the CPU side, and on the
4068 * GPU side we only need to flush internal caches to
4069 * get data visible to the CPU.
4071 * However, we maintain the display planes as UC, and so
4072 * need to rebind when first used as such.
4074 obj->cache_level = I915_CACHE_LLC;
4076 obj->cache_level = I915_CACHE_NONE;
4078 trace_i915_gem_object_create(obj);
4083 int i915_gem_init_object(struct drm_gem_object *obj)
4090 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4092 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4093 struct drm_device *dev = obj->base.dev;
4094 drm_i915_private_t *dev_priv = dev->dev_private;
4095 struct i915_vma *vma, *next;
4097 trace_i915_gem_object_destroy(obj);
4100 i915_gem_detach_phys_object(dev, obj);
4103 /* NB: 0 or 1 elements */
4104 WARN_ON(!list_empty(&obj->vma_list) &&
4105 !list_is_singular(&obj->vma_list));
4106 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4107 int ret = i915_vma_unbind(vma);
4108 if (WARN_ON(ret == -ERESTARTSYS)) {
4109 bool was_interruptible;
4111 was_interruptible = dev_priv->mm.interruptible;
4112 dev_priv->mm.interruptible = false;
4114 WARN_ON(i915_vma_unbind(vma));
4116 dev_priv->mm.interruptible = was_interruptible;
4120 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4121 * before progressing. */
4123 i915_gem_object_unpin_pages(obj);
4125 if (WARN_ON(obj->pages_pin_count))
4126 obj->pages_pin_count = 0;
4127 i915_gem_object_put_pages(obj);
4128 i915_gem_object_free_mmap_offset(obj);
4129 i915_gem_object_release_stolen(obj);
4133 if (obj->base.import_attach)
4134 drm_prime_gem_destroy(&obj->base, NULL);
4136 drm_gem_object_release(&obj->base);
4137 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4140 i915_gem_object_free(obj);
4143 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4144 struct i915_address_space *vm)
4146 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4148 return ERR_PTR(-ENOMEM);
4150 INIT_LIST_HEAD(&vma->vma_link);
4151 INIT_LIST_HEAD(&vma->mm_list);
4152 INIT_LIST_HEAD(&vma->exec_list);
4156 /* Keep GGTT vmas first to make debug easier */
4157 if (i915_is_ggtt(vm))
4158 list_add(&vma->vma_link, &obj->vma_list);
4160 list_add_tail(&vma->vma_link, &obj->vma_list);
4165 void i915_gem_vma_destroy(struct i915_vma *vma)
4167 WARN_ON(vma->node.allocated);
4168 list_del(&vma->vma_link);
4173 i915_gem_idle(struct drm_device *dev)
4175 drm_i915_private_t *dev_priv = dev->dev_private;
4178 if (dev_priv->ums.mm_suspended) {
4179 mutex_unlock(&dev->struct_mutex);
4183 ret = i915_gpu_idle(dev);
4185 mutex_unlock(&dev->struct_mutex);
4188 i915_gem_retire_requests(dev);
4190 /* Under UMS, be paranoid and evict. */
4191 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4192 i915_gem_evict_everything(dev);
4194 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4196 i915_kernel_lost_context(dev);
4197 i915_gem_cleanup_ringbuffer(dev);
4199 /* Cancel the retire work handler, which should be idle now. */
4200 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4205 void i915_gem_l3_remap(struct drm_device *dev)
4207 drm_i915_private_t *dev_priv = dev->dev_private;
4211 if (!HAS_L3_GPU_CACHE(dev))
4214 if (!dev_priv->l3_parity.remap_info)
4217 misccpctl = I915_READ(GEN7_MISCCPCTL);
4218 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4219 POSTING_READ(GEN7_MISCCPCTL);
4221 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4222 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4223 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4224 DRM_DEBUG("0x%x was already programmed to %x\n",
4225 GEN7_L3LOG_BASE + i, remap);
4226 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4227 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4228 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4231 /* Make sure all the writes land before disabling dop clock gating */
4232 POSTING_READ(GEN7_L3LOG_BASE);
4234 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4237 void i915_gem_init_swizzling(struct drm_device *dev)
4239 drm_i915_private_t *dev_priv = dev->dev_private;
4241 if (INTEL_INFO(dev)->gen < 5 ||
4242 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4245 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4246 DISP_TILE_SURFACE_SWIZZLING);
4251 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4253 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4254 else if (IS_GEN7(dev))
4255 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4261 intel_enable_blt(struct drm_device *dev)
4266 /* The blitter was dysfunctional on early prototypes */
4267 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4268 DRM_INFO("BLT not supported on this pre-production hardware;"
4269 " graphics performance will be degraded.\n");
4276 static int i915_gem_init_rings(struct drm_device *dev)
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4281 ret = intel_init_render_ring_buffer(dev);
4286 ret = intel_init_bsd_ring_buffer(dev);
4288 goto cleanup_render_ring;
4291 if (intel_enable_blt(dev)) {
4292 ret = intel_init_blt_ring_buffer(dev);
4294 goto cleanup_bsd_ring;
4297 if (HAS_VEBOX(dev)) {
4298 ret = intel_init_vebox_ring_buffer(dev);
4300 goto cleanup_blt_ring;
4304 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4306 goto cleanup_vebox_ring;
4311 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4313 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4315 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4316 cleanup_render_ring:
4317 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4323 i915_gem_init_hw(struct drm_device *dev)
4325 drm_i915_private_t *dev_priv = dev->dev_private;
4328 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4331 if (dev_priv->ellc_size)
4332 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4334 if (HAS_PCH_NOP(dev)) {
4335 u32 temp = I915_READ(GEN7_MSG_CTL);
4336 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4337 I915_WRITE(GEN7_MSG_CTL, temp);
4340 i915_gem_l3_remap(dev);
4342 i915_gem_init_swizzling(dev);
4344 ret = i915_gem_init_rings(dev);
4349 * XXX: There was some w/a described somewhere suggesting loading
4350 * contexts before PPGTT.
4352 i915_gem_context_init(dev);
4353 if (dev_priv->mm.aliasing_ppgtt) {
4354 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4356 i915_gem_cleanup_aliasing_ppgtt(dev);
4357 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4364 int i915_gem_init(struct drm_device *dev)
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4369 mutex_lock(&dev->struct_mutex);
4371 if (IS_VALLEYVIEW(dev)) {
4372 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4373 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4374 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4375 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4378 i915_gem_init_global_gtt(dev);
4380 ret = i915_gem_init_hw(dev);
4381 mutex_unlock(&dev->struct_mutex);
4383 i915_gem_cleanup_aliasing_ppgtt(dev);
4387 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4388 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4389 dev_priv->dri1.allow_batchbuffer = 1;
4394 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4396 drm_i915_private_t *dev_priv = dev->dev_private;
4397 struct intel_ring_buffer *ring;
4400 for_each_ring(ring, dev_priv, i)
4401 intel_cleanup_ring_buffer(ring);
4405 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4406 struct drm_file *file_priv)
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4411 if (drm_core_check_feature(dev, DRIVER_MODESET))
4414 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4415 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4416 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4419 mutex_lock(&dev->struct_mutex);
4420 dev_priv->ums.mm_suspended = 0;
4422 ret = i915_gem_init_hw(dev);
4424 mutex_unlock(&dev->struct_mutex);
4428 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4429 mutex_unlock(&dev->struct_mutex);
4431 ret = drm_irq_install(dev);
4433 goto cleanup_ringbuffer;
4438 mutex_lock(&dev->struct_mutex);
4439 i915_gem_cleanup_ringbuffer(dev);
4440 dev_priv->ums.mm_suspended = 1;
4441 mutex_unlock(&dev->struct_mutex);
4447 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4448 struct drm_file *file_priv)
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4453 if (drm_core_check_feature(dev, DRIVER_MODESET))
4456 drm_irq_uninstall(dev);
4458 mutex_lock(&dev->struct_mutex);
4459 ret = i915_gem_idle(dev);
4461 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4462 * We need to replace this with a semaphore, or something.
4463 * And not confound ums.mm_suspended!
4466 dev_priv->ums.mm_suspended = 1;
4467 mutex_unlock(&dev->struct_mutex);
4473 i915_gem_lastclose(struct drm_device *dev)
4477 if (drm_core_check_feature(dev, DRIVER_MODESET))
4480 mutex_lock(&dev->struct_mutex);
4481 ret = i915_gem_idle(dev);
4483 DRM_ERROR("failed to idle hardware: %d\n", ret);
4484 mutex_unlock(&dev->struct_mutex);
4488 init_ring_lists(struct intel_ring_buffer *ring)
4490 INIT_LIST_HEAD(&ring->active_list);
4491 INIT_LIST_HEAD(&ring->request_list);
4494 static void i915_init_vm(struct drm_i915_private *dev_priv,
4495 struct i915_address_space *vm)
4497 vm->dev = dev_priv->dev;
4498 INIT_LIST_HEAD(&vm->active_list);
4499 INIT_LIST_HEAD(&vm->inactive_list);
4500 INIT_LIST_HEAD(&vm->global_link);
4501 list_add(&vm->global_link, &dev_priv->vm_list);
4505 i915_gem_load(struct drm_device *dev)
4507 drm_i915_private_t *dev_priv = dev->dev_private;
4511 kmem_cache_create("i915_gem_object",
4512 sizeof(struct drm_i915_gem_object), 0,
4516 INIT_LIST_HEAD(&dev_priv->vm_list);
4517 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4519 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4520 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4521 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4522 for (i = 0; i < I915_NUM_RINGS; i++)
4523 init_ring_lists(&dev_priv->ring[i]);
4524 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4525 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4526 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4527 i915_gem_retire_work_handler);
4528 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4530 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4532 I915_WRITE(MI_ARB_STATE,
4533 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4536 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4538 /* Old X drivers will take 0-2 for front, back, depth buffers */
4539 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4540 dev_priv->fence_reg_start = 3;
4542 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4543 dev_priv->num_fence_regs = 32;
4544 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4545 dev_priv->num_fence_regs = 16;
4547 dev_priv->num_fence_regs = 8;
4549 /* Initialize fence registers to zero */
4550 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4551 i915_gem_restore_fences(dev);
4553 i915_gem_detect_bit_6_swizzle(dev);
4554 init_waitqueue_head(&dev_priv->pending_flip_queue);
4556 dev_priv->mm.interruptible = true;
4558 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4559 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4560 register_shrinker(&dev_priv->mm.inactive_shrinker);
4564 * Create a physically contiguous memory object for this object
4565 * e.g. for cursor + overlay regs
4567 static int i915_gem_init_phys_object(struct drm_device *dev,
4568 int id, int size, int align)
4570 drm_i915_private_t *dev_priv = dev->dev_private;
4571 struct drm_i915_gem_phys_object *phys_obj;
4574 if (dev_priv->mm.phys_objs[id - 1] || !size)
4577 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4583 phys_obj->handle = drm_pci_alloc(dev, size, align);
4584 if (!phys_obj->handle) {
4589 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4592 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4600 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4602 drm_i915_private_t *dev_priv = dev->dev_private;
4603 struct drm_i915_gem_phys_object *phys_obj;
4605 if (!dev_priv->mm.phys_objs[id - 1])
4608 phys_obj = dev_priv->mm.phys_objs[id - 1];
4609 if (phys_obj->cur_obj) {
4610 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4614 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4616 drm_pci_free(dev, phys_obj->handle);
4618 dev_priv->mm.phys_objs[id - 1] = NULL;
4621 void i915_gem_free_all_phys_object(struct drm_device *dev)
4625 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4626 i915_gem_free_phys_object(dev, i);
4629 void i915_gem_detach_phys_object(struct drm_device *dev,
4630 struct drm_i915_gem_object *obj)
4632 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4639 vaddr = obj->phys_obj->handle->vaddr;
4641 page_count = obj->base.size / PAGE_SIZE;
4642 for (i = 0; i < page_count; i++) {
4643 struct page *page = shmem_read_mapping_page(mapping, i);
4644 if (!IS_ERR(page)) {
4645 char *dst = kmap_atomic(page);
4646 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4649 drm_clflush_pages(&page, 1);
4651 set_page_dirty(page);
4652 mark_page_accessed(page);
4653 page_cache_release(page);
4656 i915_gem_chipset_flush(dev);
4658 obj->phys_obj->cur_obj = NULL;
4659 obj->phys_obj = NULL;
4663 i915_gem_attach_phys_object(struct drm_device *dev,
4664 struct drm_i915_gem_object *obj,
4668 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4669 drm_i915_private_t *dev_priv = dev->dev_private;
4674 if (id > I915_MAX_PHYS_OBJECT)
4677 if (obj->phys_obj) {
4678 if (obj->phys_obj->id == id)
4680 i915_gem_detach_phys_object(dev, obj);
4683 /* create a new object */
4684 if (!dev_priv->mm.phys_objs[id - 1]) {
4685 ret = i915_gem_init_phys_object(dev, id,
4686 obj->base.size, align);
4688 DRM_ERROR("failed to init phys object %d size: %zu\n",
4689 id, obj->base.size);
4694 /* bind to the object */
4695 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4696 obj->phys_obj->cur_obj = obj;
4698 page_count = obj->base.size / PAGE_SIZE;
4700 for (i = 0; i < page_count; i++) {
4704 page = shmem_read_mapping_page(mapping, i);
4706 return PTR_ERR(page);
4708 src = kmap_atomic(page);
4709 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4710 memcpy(dst, src, PAGE_SIZE);
4713 mark_page_accessed(page);
4714 page_cache_release(page);
4721 i915_gem_phys_pwrite(struct drm_device *dev,
4722 struct drm_i915_gem_object *obj,
4723 struct drm_i915_gem_pwrite *args,
4724 struct drm_file *file_priv)
4726 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4727 char __user *user_data = to_user_ptr(args->data_ptr);
4729 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4730 unsigned long unwritten;
4732 /* The physical object once assigned is fixed for the lifetime
4733 * of the obj, so we can safely drop the lock and continue
4736 mutex_unlock(&dev->struct_mutex);
4737 unwritten = copy_from_user(vaddr, user_data, args->size);
4738 mutex_lock(&dev->struct_mutex);
4743 i915_gem_chipset_flush(dev);
4747 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4749 struct drm_i915_file_private *file_priv = file->driver_priv;
4751 /* Clean up our request list when the client is going away, so that
4752 * later retire_requests won't dereference our soon-to-be-gone
4755 spin_lock(&file_priv->mm.lock);
4756 while (!list_empty(&file_priv->mm.request_list)) {
4757 struct drm_i915_gem_request *request;
4759 request = list_first_entry(&file_priv->mm.request_list,
4760 struct drm_i915_gem_request,
4762 list_del(&request->client_list);
4763 request->file_priv = NULL;
4765 spin_unlock(&file_priv->mm.lock);
4768 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4770 if (!mutex_is_locked(mutex))
4773 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4774 return mutex->owner == task;
4776 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4782 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4784 struct drm_i915_private *dev_priv =
4785 container_of(shrinker,
4786 struct drm_i915_private,
4787 mm.inactive_shrinker);
4788 struct drm_device *dev = dev_priv->dev;
4789 struct drm_i915_gem_object *obj;
4790 int nr_to_scan = sc->nr_to_scan;
4794 if (!mutex_trylock(&dev->struct_mutex)) {
4795 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4798 if (dev_priv->mm.shrinker_no_lock_stealing)
4805 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4807 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4810 i915_gem_shrink_all(dev_priv);
4814 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4815 if (obj->pages_pin_count == 0)
4816 cnt += obj->base.size >> PAGE_SHIFT;
4818 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4822 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4823 cnt += obj->base.size >> PAGE_SHIFT;
4827 mutex_unlock(&dev->struct_mutex);
4831 /* All the new VM stuff */
4832 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4833 struct i915_address_space *vm)
4835 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4836 struct i915_vma *vma;
4838 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4839 vm = &dev_priv->gtt.base;
4841 BUG_ON(list_empty(&o->vma_list));
4842 list_for_each_entry(vma, &o->vma_list, vma_link) {
4844 return vma->node.start;
4850 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4851 struct i915_address_space *vm)
4853 struct i915_vma *vma;
4855 list_for_each_entry(vma, &o->vma_list, vma_link)
4856 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4862 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4864 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4865 struct i915_address_space *vm;
4867 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4868 if (i915_gem_obj_bound(o, vm))
4874 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4875 struct i915_address_space *vm)
4877 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4878 struct i915_vma *vma;
4880 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4881 vm = &dev_priv->gtt.base;
4883 BUG_ON(list_empty(&o->vma_list));
4885 list_for_each_entry(vma, &o->vma_list, vma_link)
4887 return vma->node.size;
4892 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4893 struct i915_address_space *vm)
4895 struct i915_vma *vma;
4896 list_for_each_entry(vma, &obj->vma_list, vma_link)
4904 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4905 struct i915_address_space *vm)
4907 struct i915_vma *vma;
4909 vma = i915_gem_obj_to_vma(obj, vm);
4911 vma = i915_gem_vma_create(obj, vm);