2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
52 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
56 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = i915_gem_alloc_object(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 drm_gem_object_handle_unreference_unlocked(obj);
136 args->handle = handle;
142 fast_shmem_read(struct page **pages,
143 loff_t page_base, int page_offset,
150 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
154 kunmap_atomic(vaddr, KM_USER0);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164 drm_i915_private_t *dev_priv = obj->dev->dev_private;
165 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
167 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
168 obj_priv->tiling_mode != I915_TILING_NONE;
172 slow_shmem_copy(struct page *dst_page,
174 struct page *src_page,
178 char *dst_vaddr, *src_vaddr;
180 dst_vaddr = kmap(dst_page);
181 src_vaddr = kmap(src_page);
183 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
190 slow_shmem_bit17_copy(struct page *gpu_page,
192 struct page *cpu_page,
197 char *gpu_vaddr, *cpu_vaddr;
199 /* Use the unswizzled path if this page isn't affected. */
200 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
202 return slow_shmem_copy(cpu_page, cpu_offset,
203 gpu_page, gpu_offset, length);
205 return slow_shmem_copy(gpu_page, gpu_offset,
206 cpu_page, cpu_offset, length);
209 gpu_vaddr = kmap(gpu_page);
210 cpu_vaddr = kmap(cpu_page);
212 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
213 * XORing with the other bits (A9 for Y, A9 and A10 for X)
216 int cacheline_end = ALIGN(gpu_offset + 1, 64);
217 int this_length = min(cacheline_end - gpu_offset, length);
218 int swizzled_gpu_offset = gpu_offset ^ 64;
221 memcpy(cpu_vaddr + cpu_offset,
222 gpu_vaddr + swizzled_gpu_offset,
225 memcpy(gpu_vaddr + swizzled_gpu_offset,
226 cpu_vaddr + cpu_offset,
229 cpu_offset += this_length;
230 gpu_offset += this_length;
231 length -= this_length;
239 * This is the fast shmem pread path, which attempts to copy_from_user directly
240 * from the backing pages of the object to the user's address space. On a
241 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
244 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
245 struct drm_i915_gem_pread *args,
246 struct drm_file *file_priv)
248 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
250 loff_t offset, page_base;
251 char __user *user_data;
252 int page_offset, page_length;
255 user_data = (char __user *) (uintptr_t) args->data_ptr;
258 mutex_lock(&dev->struct_mutex);
260 ret = i915_gem_object_get_pages(obj, 0);
264 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
269 obj_priv = to_intel_bo(obj);
270 offset = args->offset;
273 /* Operation in this page
275 * page_base = page offset within aperture
276 * page_offset = offset within page
277 * page_length = bytes to copy for this page
279 page_base = (offset & ~(PAGE_SIZE-1));
280 page_offset = offset & (PAGE_SIZE-1);
281 page_length = remain;
282 if ((page_offset + remain) > PAGE_SIZE)
283 page_length = PAGE_SIZE - page_offset;
285 ret = fast_shmem_read(obj_priv->pages,
286 page_base, page_offset,
287 user_data, page_length);
291 remain -= page_length;
292 user_data += page_length;
293 offset += page_length;
297 i915_gem_object_put_pages(obj);
299 mutex_unlock(&dev->struct_mutex);
305 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
309 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
311 /* If we've insufficient memory to map in the pages, attempt
312 * to make some space by throwing out some old buffers.
314 if (ret == -ENOMEM) {
315 struct drm_device *dev = obj->dev;
317 ret = i915_gem_evict_something(dev, obj->size);
321 ret = i915_gem_object_get_pages(obj, 0);
328 * This is the fallback shmem pread path, which allocates temporary storage
329 * in kernel space to copy_to_user into outside of the struct_mutex, so we
330 * can copy out of the object's backing pages while holding the struct mutex
331 * and not take page faults.
334 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
335 struct drm_i915_gem_pread *args,
336 struct drm_file *file_priv)
338 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
339 struct mm_struct *mm = current->mm;
340 struct page **user_pages;
342 loff_t offset, pinned_pages, i;
343 loff_t first_data_page, last_data_page, num_pages;
344 int shmem_page_index, shmem_page_offset;
345 int data_page_index, data_page_offset;
348 uint64_t data_ptr = args->data_ptr;
349 int do_bit17_swizzling;
353 /* Pin the user pages containing the data. We can't fault while
354 * holding the struct mutex, yet we want to hold it while
355 * dereferencing the user data.
357 first_data_page = data_ptr / PAGE_SIZE;
358 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
359 num_pages = last_data_page - first_data_page + 1;
361 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
362 if (user_pages == NULL)
365 down_read(&mm->mmap_sem);
366 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
367 num_pages, 1, 0, user_pages, NULL);
368 up_read(&mm->mmap_sem);
369 if (pinned_pages < num_pages) {
371 goto fail_put_user_pages;
374 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
376 mutex_lock(&dev->struct_mutex);
378 ret = i915_gem_object_get_pages_or_evict(obj);
382 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
387 obj_priv = to_intel_bo(obj);
388 offset = args->offset;
391 /* Operation in this page
393 * shmem_page_index = page number within shmem file
394 * shmem_page_offset = offset within page in shmem file
395 * data_page_index = page number in get_user_pages return
396 * data_page_offset = offset with data_page_index page.
397 * page_length = bytes to copy for this page
399 shmem_page_index = offset / PAGE_SIZE;
400 shmem_page_offset = offset & ~PAGE_MASK;
401 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
402 data_page_offset = data_ptr & ~PAGE_MASK;
404 page_length = remain;
405 if ((shmem_page_offset + page_length) > PAGE_SIZE)
406 page_length = PAGE_SIZE - shmem_page_offset;
407 if ((data_page_offset + page_length) > PAGE_SIZE)
408 page_length = PAGE_SIZE - data_page_offset;
410 if (do_bit17_swizzling) {
411 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
413 user_pages[data_page_index],
418 slow_shmem_copy(user_pages[data_page_index],
420 obj_priv->pages[shmem_page_index],
425 remain -= page_length;
426 data_ptr += page_length;
427 offset += page_length;
431 i915_gem_object_put_pages(obj);
433 mutex_unlock(&dev->struct_mutex);
435 for (i = 0; i < pinned_pages; i++) {
436 SetPageDirty(user_pages[i]);
437 page_cache_release(user_pages[i]);
439 drm_free_large(user_pages);
445 * Reads data from the object referenced by handle.
447 * On error, the contents of *data are undefined.
450 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
451 struct drm_file *file_priv)
453 struct drm_i915_gem_pread *args = data;
454 struct drm_gem_object *obj;
455 struct drm_i915_gem_object *obj_priv;
458 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
461 obj_priv = to_intel_bo(obj);
463 /* Bounds check source.
465 * XXX: This could use review for overflow issues...
467 if (args->offset > obj->size || args->size > obj->size ||
468 args->offset + args->size > obj->size) {
469 drm_gem_object_unreference_unlocked(obj);
473 if (i915_gem_object_needs_bit17_swizzle(obj)) {
474 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
476 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
478 ret = i915_gem_shmem_pread_slow(dev, obj, args,
482 drm_gem_object_unreference_unlocked(obj);
487 /* This is the fast write path which cannot handle
488 * page faults in the source data
492 fast_user_write(struct io_mapping *mapping,
493 loff_t page_base, int page_offset,
494 char __user *user_data,
498 unsigned long unwritten;
500 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
501 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
503 io_mapping_unmap_atomic(vaddr_atomic);
509 /* Here's the write path which can sleep for
514 slow_kernel_write(struct io_mapping *mapping,
515 loff_t gtt_base, int gtt_offset,
516 struct page *user_page, int user_offset,
519 char __iomem *dst_vaddr;
522 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
523 src_vaddr = kmap(user_page);
525 memcpy_toio(dst_vaddr + gtt_offset,
526 src_vaddr + user_offset,
530 io_mapping_unmap(dst_vaddr);
534 fast_shmem_write(struct page **pages,
535 loff_t page_base, int page_offset,
540 unsigned long unwritten;
542 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
545 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
546 kunmap_atomic(vaddr, KM_USER0);
554 * This is the fast pwrite path, where we copy the data directly from the
555 * user into the GTT, uncached.
558 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
559 struct drm_i915_gem_pwrite *args,
560 struct drm_file *file_priv)
562 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
563 drm_i915_private_t *dev_priv = dev->dev_private;
565 loff_t offset, page_base;
566 char __user *user_data;
567 int page_offset, page_length;
570 user_data = (char __user *) (uintptr_t) args->data_ptr;
572 if (!access_ok(VERIFY_READ, user_data, remain))
576 mutex_lock(&dev->struct_mutex);
577 ret = i915_gem_object_pin(obj, 0);
579 mutex_unlock(&dev->struct_mutex);
582 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
586 obj_priv = to_intel_bo(obj);
587 offset = obj_priv->gtt_offset + args->offset;
590 /* Operation in this page
592 * page_base = page offset within aperture
593 * page_offset = offset within page
594 * page_length = bytes to copy for this page
596 page_base = (offset & ~(PAGE_SIZE-1));
597 page_offset = offset & (PAGE_SIZE-1);
598 page_length = remain;
599 if ((page_offset + remain) > PAGE_SIZE)
600 page_length = PAGE_SIZE - page_offset;
602 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
603 page_offset, user_data, page_length);
605 /* If we get a fault while copying data, then (presumably) our
606 * source page isn't available. Return the error and we'll
607 * retry in the slow path.
612 remain -= page_length;
613 user_data += page_length;
614 offset += page_length;
618 i915_gem_object_unpin(obj);
619 mutex_unlock(&dev->struct_mutex);
625 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
626 * the memory and maps it using kmap_atomic for copying.
628 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
629 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
632 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
633 struct drm_i915_gem_pwrite *args,
634 struct drm_file *file_priv)
636 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
637 drm_i915_private_t *dev_priv = dev->dev_private;
639 loff_t gtt_page_base, offset;
640 loff_t first_data_page, last_data_page, num_pages;
641 loff_t pinned_pages, i;
642 struct page **user_pages;
643 struct mm_struct *mm = current->mm;
644 int gtt_page_offset, data_page_offset, data_page_index, page_length;
646 uint64_t data_ptr = args->data_ptr;
650 /* Pin the user pages containing the data. We can't fault while
651 * holding the struct mutex, and all of the pwrite implementations
652 * want to hold it while dereferencing the user data.
654 first_data_page = data_ptr / PAGE_SIZE;
655 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
656 num_pages = last_data_page - first_data_page + 1;
658 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
659 if (user_pages == NULL)
662 down_read(&mm->mmap_sem);
663 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
664 num_pages, 0, 0, user_pages, NULL);
665 up_read(&mm->mmap_sem);
666 if (pinned_pages < num_pages) {
668 goto out_unpin_pages;
671 mutex_lock(&dev->struct_mutex);
672 ret = i915_gem_object_pin(obj, 0);
676 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
678 goto out_unpin_object;
680 obj_priv = to_intel_bo(obj);
681 offset = obj_priv->gtt_offset + args->offset;
684 /* Operation in this page
686 * gtt_page_base = page offset within aperture
687 * gtt_page_offset = offset within page in aperture
688 * data_page_index = page number in get_user_pages return
689 * data_page_offset = offset with data_page_index page.
690 * page_length = bytes to copy for this page
692 gtt_page_base = offset & PAGE_MASK;
693 gtt_page_offset = offset & ~PAGE_MASK;
694 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
695 data_page_offset = data_ptr & ~PAGE_MASK;
697 page_length = remain;
698 if ((gtt_page_offset + page_length) > PAGE_SIZE)
699 page_length = PAGE_SIZE - gtt_page_offset;
700 if ((data_page_offset + page_length) > PAGE_SIZE)
701 page_length = PAGE_SIZE - data_page_offset;
703 slow_kernel_write(dev_priv->mm.gtt_mapping,
704 gtt_page_base, gtt_page_offset,
705 user_pages[data_page_index],
709 remain -= page_length;
710 offset += page_length;
711 data_ptr += page_length;
715 i915_gem_object_unpin(obj);
717 mutex_unlock(&dev->struct_mutex);
719 for (i = 0; i < pinned_pages; i++)
720 page_cache_release(user_pages[i]);
721 drm_free_large(user_pages);
727 * This is the fast shmem pwrite path, which attempts to directly
728 * copy_from_user into the kmapped pages backing the object.
731 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
732 struct drm_i915_gem_pwrite *args,
733 struct drm_file *file_priv)
735 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
737 loff_t offset, page_base;
738 char __user *user_data;
739 int page_offset, page_length;
742 user_data = (char __user *) (uintptr_t) args->data_ptr;
745 mutex_lock(&dev->struct_mutex);
747 ret = i915_gem_object_get_pages(obj, 0);
751 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
755 obj_priv = to_intel_bo(obj);
756 offset = args->offset;
760 /* Operation in this page
762 * page_base = page offset within aperture
763 * page_offset = offset within page
764 * page_length = bytes to copy for this page
766 page_base = (offset & ~(PAGE_SIZE-1));
767 page_offset = offset & (PAGE_SIZE-1);
768 page_length = remain;
769 if ((page_offset + remain) > PAGE_SIZE)
770 page_length = PAGE_SIZE - page_offset;
772 ret = fast_shmem_write(obj_priv->pages,
773 page_base, page_offset,
774 user_data, page_length);
778 remain -= page_length;
779 user_data += page_length;
780 offset += page_length;
784 i915_gem_object_put_pages(obj);
786 mutex_unlock(&dev->struct_mutex);
792 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
793 * the memory and maps it using kmap_atomic for copying.
795 * This avoids taking mmap_sem for faulting on the user's address while the
796 * struct_mutex is held.
799 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
800 struct drm_i915_gem_pwrite *args,
801 struct drm_file *file_priv)
803 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
804 struct mm_struct *mm = current->mm;
805 struct page **user_pages;
807 loff_t offset, pinned_pages, i;
808 loff_t first_data_page, last_data_page, num_pages;
809 int shmem_page_index, shmem_page_offset;
810 int data_page_index, data_page_offset;
813 uint64_t data_ptr = args->data_ptr;
814 int do_bit17_swizzling;
818 /* Pin the user pages containing the data. We can't fault while
819 * holding the struct mutex, and all of the pwrite implementations
820 * want to hold it while dereferencing the user data.
822 first_data_page = data_ptr / PAGE_SIZE;
823 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
824 num_pages = last_data_page - first_data_page + 1;
826 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
827 if (user_pages == NULL)
830 down_read(&mm->mmap_sem);
831 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
832 num_pages, 0, 0, user_pages, NULL);
833 up_read(&mm->mmap_sem);
834 if (pinned_pages < num_pages) {
836 goto fail_put_user_pages;
839 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
841 mutex_lock(&dev->struct_mutex);
843 ret = i915_gem_object_get_pages_or_evict(obj);
847 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
851 obj_priv = to_intel_bo(obj);
852 offset = args->offset;
856 /* Operation in this page
858 * shmem_page_index = page number within shmem file
859 * shmem_page_offset = offset within page in shmem file
860 * data_page_index = page number in get_user_pages return
861 * data_page_offset = offset with data_page_index page.
862 * page_length = bytes to copy for this page
864 shmem_page_index = offset / PAGE_SIZE;
865 shmem_page_offset = offset & ~PAGE_MASK;
866 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
867 data_page_offset = data_ptr & ~PAGE_MASK;
869 page_length = remain;
870 if ((shmem_page_offset + page_length) > PAGE_SIZE)
871 page_length = PAGE_SIZE - shmem_page_offset;
872 if ((data_page_offset + page_length) > PAGE_SIZE)
873 page_length = PAGE_SIZE - data_page_offset;
875 if (do_bit17_swizzling) {
876 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
878 user_pages[data_page_index],
883 slow_shmem_copy(obj_priv->pages[shmem_page_index],
885 user_pages[data_page_index],
890 remain -= page_length;
891 data_ptr += page_length;
892 offset += page_length;
896 i915_gem_object_put_pages(obj);
898 mutex_unlock(&dev->struct_mutex);
900 for (i = 0; i < pinned_pages; i++)
901 page_cache_release(user_pages[i]);
902 drm_free_large(user_pages);
908 * Writes data to the object referenced by handle.
910 * On error, the contents of the buffer that were to be modified are undefined.
913 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
914 struct drm_file *file_priv)
916 struct drm_i915_gem_pwrite *args = data;
917 struct drm_gem_object *obj;
918 struct drm_i915_gem_object *obj_priv;
921 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
924 obj_priv = to_intel_bo(obj);
926 /* Bounds check destination.
928 * XXX: This could use review for overflow issues...
930 if (args->offset > obj->size || args->size > obj->size ||
931 args->offset + args->size > obj->size) {
932 drm_gem_object_unreference_unlocked(obj);
936 /* We can only do the GTT pwrite on untiled buffers, as otherwise
937 * it would end up going through the fenced access, and we'll get
938 * different detiling behavior between reading and writing.
939 * pread/pwrite currently are reading and writing from the CPU
940 * perspective, requiring manual detiling by the client.
942 if (obj_priv->phys_obj)
943 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
944 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
945 dev->gtt_total != 0 &&
946 obj->write_domain != I915_GEM_DOMAIN_CPU) {
947 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
948 if (ret == -EFAULT) {
949 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
952 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
953 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
955 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
956 if (ret == -EFAULT) {
957 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
964 DRM_INFO("pwrite failed %d\n", ret);
967 drm_gem_object_unreference_unlocked(obj);
973 * Called when user space prepares to use an object with the CPU, either
974 * through the mmap ioctl's mapping or a GTT mapping.
977 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
978 struct drm_file *file_priv)
980 struct drm_i915_private *dev_priv = dev->dev_private;
981 struct drm_i915_gem_set_domain *args = data;
982 struct drm_gem_object *obj;
983 struct drm_i915_gem_object *obj_priv;
984 uint32_t read_domains = args->read_domains;
985 uint32_t write_domain = args->write_domain;
988 if (!(dev->driver->driver_features & DRIVER_GEM))
991 /* Only handle setting domains to types used by the CPU. */
992 if (write_domain & I915_GEM_GPU_DOMAINS)
995 if (read_domains & I915_GEM_GPU_DOMAINS)
998 /* Having something in the write domain implies it's in the read
999 * domain, and only that read domain. Enforce that in the request.
1001 if (write_domain != 0 && read_domains != write_domain)
1004 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1007 obj_priv = to_intel_bo(obj);
1009 mutex_lock(&dev->struct_mutex);
1011 intel_mark_busy(dev, obj);
1014 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1015 obj, obj->size, read_domains, write_domain);
1017 if (read_domains & I915_GEM_DOMAIN_GTT) {
1018 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1020 /* Update the LRU on the fence for the CPU access that's
1023 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1024 struct drm_i915_fence_reg *reg =
1025 &dev_priv->fence_regs[obj_priv->fence_reg];
1026 list_move_tail(®->lru_list,
1027 &dev_priv->mm.fence_list);
1030 /* Silently promote "you're not bound, there was nothing to do"
1031 * to success, since the client was just asking us to
1032 * make sure everything was done.
1037 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1040 drm_gem_object_unreference(obj);
1041 mutex_unlock(&dev->struct_mutex);
1046 * Called when user space has done writes to this buffer
1049 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1050 struct drm_file *file_priv)
1052 struct drm_i915_gem_sw_finish *args = data;
1053 struct drm_gem_object *obj;
1054 struct drm_i915_gem_object *obj_priv;
1057 if (!(dev->driver->driver_features & DRIVER_GEM))
1060 mutex_lock(&dev->struct_mutex);
1061 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1063 mutex_unlock(&dev->struct_mutex);
1068 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1069 __func__, args->handle, obj, obj->size);
1071 obj_priv = to_intel_bo(obj);
1073 /* Pinned buffers may be scanout, so flush the cache */
1074 if (obj_priv->pin_count)
1075 i915_gem_object_flush_cpu_write_domain(obj);
1077 drm_gem_object_unreference(obj);
1078 mutex_unlock(&dev->struct_mutex);
1083 * Maps the contents of an object, returning the address it is mapped
1086 * While the mapping holds a reference on the contents of the object, it doesn't
1087 * imply a ref on the object itself.
1090 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv)
1093 struct drm_i915_gem_mmap *args = data;
1094 struct drm_gem_object *obj;
1098 if (!(dev->driver->driver_features & DRIVER_GEM))
1101 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1105 offset = args->offset;
1107 down_write(¤t->mm->mmap_sem);
1108 addr = do_mmap(obj->filp, 0, args->size,
1109 PROT_READ | PROT_WRITE, MAP_SHARED,
1111 up_write(¤t->mm->mmap_sem);
1112 drm_gem_object_unreference_unlocked(obj);
1113 if (IS_ERR((void *)addr))
1116 args->addr_ptr = (uint64_t) addr;
1122 * i915_gem_fault - fault a page into the GTT
1123 * vma: VMA in question
1126 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1127 * from userspace. The fault handler takes care of binding the object to
1128 * the GTT (if needed), allocating and programming a fence register (again,
1129 * only if needed based on whether the old reg is still valid or the object
1130 * is tiled) and inserting a new PTE into the faulting process.
1132 * Note that the faulting process may involve evicting existing objects
1133 * from the GTT and/or fence registers to make room. So performance may
1134 * suffer if the GTT working set is large or there are few fence registers
1137 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1139 struct drm_gem_object *obj = vma->vm_private_data;
1140 struct drm_device *dev = obj->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1143 pgoff_t page_offset;
1146 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1148 /* We don't use vmf->pgoff since that has the fake offset */
1149 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1152 /* Now bind it into the GTT if needed */
1153 mutex_lock(&dev->struct_mutex);
1154 if (!obj_priv->gtt_space) {
1155 ret = i915_gem_object_bind_to_gtt(obj, 0);
1159 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1161 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1166 /* Need a new fence register? */
1167 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1168 ret = i915_gem_object_get_fence_reg(obj);
1173 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1176 /* Finally, remap it using the new GTT offset */
1177 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1179 mutex_unlock(&dev->struct_mutex);
1184 return VM_FAULT_NOPAGE;
1187 return VM_FAULT_OOM;
1189 return VM_FAULT_SIGBUS;
1194 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1195 * @obj: obj in question
1197 * GEM memory mapping works by handing back to userspace a fake mmap offset
1198 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1199 * up the object based on the offset and sets up the various memory mapping
1202 * This routine allocates and attaches a fake offset for @obj.
1205 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1207 struct drm_device *dev = obj->dev;
1208 struct drm_gem_mm *mm = dev->mm_private;
1209 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1210 struct drm_map_list *list;
1211 struct drm_local_map *map;
1214 /* Set the object up for mmap'ing */
1215 list = &obj->map_list;
1216 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1221 map->type = _DRM_GEM;
1222 map->size = obj->size;
1225 /* Get a DRM GEM mmap offset allocated... */
1226 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1227 obj->size / PAGE_SIZE, 0, 0);
1228 if (!list->file_offset_node) {
1229 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1234 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1235 obj->size / PAGE_SIZE, 0);
1236 if (!list->file_offset_node) {
1241 list->hash.key = list->file_offset_node->start;
1242 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1243 DRM_ERROR("failed to add to map hash\n");
1248 /* By now we should be all set, any drm_mmap request on the offset
1249 * below will get to our mmap & fault handler */
1250 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1255 drm_mm_put_block(list->file_offset_node);
1263 * i915_gem_release_mmap - remove physical page mappings
1264 * @obj: obj in question
1266 * Preserve the reservation of the mmapping with the DRM core code, but
1267 * relinquish ownership of the pages back to the system.
1269 * It is vital that we remove the page mapping if we have mapped a tiled
1270 * object through the GTT and then lose the fence register due to
1271 * resource pressure. Similarly if the object has been moved out of the
1272 * aperture, than pages mapped into userspace must be revoked. Removing the
1273 * mapping will then trigger a page fault on the next user access, allowing
1274 * fixup by i915_gem_fault().
1277 i915_gem_release_mmap(struct drm_gem_object *obj)
1279 struct drm_device *dev = obj->dev;
1280 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1282 if (dev->dev_mapping)
1283 unmap_mapping_range(dev->dev_mapping,
1284 obj_priv->mmap_offset, obj->size, 1);
1288 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1290 struct drm_device *dev = obj->dev;
1291 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1292 struct drm_gem_mm *mm = dev->mm_private;
1293 struct drm_map_list *list;
1295 list = &obj->map_list;
1296 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1298 if (list->file_offset_node) {
1299 drm_mm_put_block(list->file_offset_node);
1300 list->file_offset_node = NULL;
1308 obj_priv->mmap_offset = 0;
1312 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1313 * @obj: object to check
1315 * Return the required GTT alignment for an object, taking into account
1316 * potential fence register mapping if needed.
1319 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1321 struct drm_device *dev = obj->dev;
1322 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1326 * Minimum alignment is 4k (GTT page size), but might be greater
1327 * if a fence register is needed for the object.
1329 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1333 * Previous chips need to be aligned to the size of the smallest
1334 * fence register that can contain the object.
1341 for (i = start; i < obj->size; i <<= 1)
1348 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1350 * @data: GTT mapping ioctl data
1351 * @file_priv: GEM object info
1353 * Simply returns the fake offset to userspace so it can mmap it.
1354 * The mmap call will end up in drm_gem_mmap(), which will set things
1355 * up so we can get faults in the handler above.
1357 * The fault handler will take care of binding the object into the GTT
1358 * (since it may have been evicted to make room for something), allocating
1359 * a fence register, and mapping the appropriate aperture address into
1363 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1364 struct drm_file *file_priv)
1366 struct drm_i915_gem_mmap_gtt *args = data;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 struct drm_gem_object *obj;
1369 struct drm_i915_gem_object *obj_priv;
1372 if (!(dev->driver->driver_features & DRIVER_GEM))
1375 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1379 mutex_lock(&dev->struct_mutex);
1381 obj_priv = to_intel_bo(obj);
1383 if (obj_priv->madv != I915_MADV_WILLNEED) {
1384 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1385 drm_gem_object_unreference(obj);
1386 mutex_unlock(&dev->struct_mutex);
1391 if (!obj_priv->mmap_offset) {
1392 ret = i915_gem_create_mmap_offset(obj);
1394 drm_gem_object_unreference(obj);
1395 mutex_unlock(&dev->struct_mutex);
1400 args->offset = obj_priv->mmap_offset;
1403 * Pull it into the GTT so that we have a page list (makes the
1404 * initial fault faster and any subsequent flushing possible).
1406 if (!obj_priv->agp_mem) {
1407 ret = i915_gem_object_bind_to_gtt(obj, 0);
1409 drm_gem_object_unreference(obj);
1410 mutex_unlock(&dev->struct_mutex);
1413 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1416 drm_gem_object_unreference(obj);
1417 mutex_unlock(&dev->struct_mutex);
1423 i915_gem_object_put_pages(struct drm_gem_object *obj)
1425 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1426 int page_count = obj->size / PAGE_SIZE;
1429 BUG_ON(obj_priv->pages_refcount == 0);
1430 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1432 if (--obj_priv->pages_refcount != 0)
1435 if (obj_priv->tiling_mode != I915_TILING_NONE)
1436 i915_gem_object_save_bit_17_swizzle(obj);
1438 if (obj_priv->madv == I915_MADV_DONTNEED)
1439 obj_priv->dirty = 0;
1441 for (i = 0; i < page_count; i++) {
1442 if (obj_priv->dirty)
1443 set_page_dirty(obj_priv->pages[i]);
1445 if (obj_priv->madv == I915_MADV_WILLNEED)
1446 mark_page_accessed(obj_priv->pages[i]);
1448 page_cache_release(obj_priv->pages[i]);
1450 obj_priv->dirty = 0;
1452 drm_free_large(obj_priv->pages);
1453 obj_priv->pages = NULL;
1457 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1458 struct intel_ring_buffer *ring)
1460 struct drm_device *dev = obj->dev;
1461 drm_i915_private_t *dev_priv = dev->dev_private;
1462 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1463 BUG_ON(ring == NULL);
1464 obj_priv->ring = ring;
1466 /* Add a reference if we're newly entering the active list. */
1467 if (!obj_priv->active) {
1468 drm_gem_object_reference(obj);
1469 obj_priv->active = 1;
1471 /* Move from whatever list we were on to the tail of execution. */
1472 spin_lock(&dev_priv->mm.active_list_lock);
1473 list_move_tail(&obj_priv->list, &ring->active_list);
1474 spin_unlock(&dev_priv->mm.active_list_lock);
1475 obj_priv->last_rendering_seqno = seqno;
1479 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1481 struct drm_device *dev = obj->dev;
1482 drm_i915_private_t *dev_priv = dev->dev_private;
1483 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1485 BUG_ON(!obj_priv->active);
1486 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1487 obj_priv->last_rendering_seqno = 0;
1490 /* Immediately discard the backing storage */
1492 i915_gem_object_truncate(struct drm_gem_object *obj)
1494 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1495 struct inode *inode;
1497 inode = obj->filp->f_path.dentry->d_inode;
1498 if (inode->i_op->truncate)
1499 inode->i_op->truncate (inode);
1501 obj_priv->madv = __I915_MADV_PURGED;
1505 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1507 return obj_priv->madv == I915_MADV_DONTNEED;
1511 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1517 i915_verify_inactive(dev, __FILE__, __LINE__);
1518 if (obj_priv->pin_count != 0)
1519 list_del_init(&obj_priv->list);
1521 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1523 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1525 obj_priv->last_rendering_seqno = 0;
1526 obj_priv->ring = NULL;
1527 if (obj_priv->active) {
1528 obj_priv->active = 0;
1529 drm_gem_object_unreference(obj);
1531 i915_verify_inactive(dev, __FILE__, __LINE__);
1535 i915_gem_process_flushing_list(struct drm_device *dev,
1536 uint32_t flush_domains, uint32_t seqno,
1537 struct intel_ring_buffer *ring)
1539 drm_i915_private_t *dev_priv = dev->dev_private;
1540 struct drm_i915_gem_object *obj_priv, *next;
1542 list_for_each_entry_safe(obj_priv, next,
1543 &dev_priv->mm.gpu_write_list,
1545 struct drm_gem_object *obj = &obj_priv->base;
1547 if ((obj->write_domain & flush_domains) ==
1548 obj->write_domain &&
1549 obj_priv->ring->ring_flag == ring->ring_flag) {
1550 uint32_t old_write_domain = obj->write_domain;
1552 obj->write_domain = 0;
1553 list_del_init(&obj_priv->gpu_write_list);
1554 i915_gem_object_move_to_active(obj, seqno, ring);
1556 /* update the fence lru list */
1557 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1558 struct drm_i915_fence_reg *reg =
1559 &dev_priv->fence_regs[obj_priv->fence_reg];
1560 list_move_tail(®->lru_list,
1561 &dev_priv->mm.fence_list);
1564 trace_i915_gem_object_change_domain(obj,
1572 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1573 uint32_t flush_domains, struct intel_ring_buffer *ring)
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 struct drm_i915_file_private *i915_file_priv = NULL;
1577 struct drm_i915_gem_request *request;
1581 if (file_priv != NULL)
1582 i915_file_priv = file_priv->driver_priv;
1584 request = kzalloc(sizeof(*request), GFP_KERNEL);
1585 if (request == NULL)
1588 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1590 request->seqno = seqno;
1591 request->ring = ring;
1592 request->emitted_jiffies = jiffies;
1593 was_empty = list_empty(&ring->request_list);
1594 list_add_tail(&request->list, &ring->request_list);
1596 if (i915_file_priv) {
1597 list_add_tail(&request->client_list,
1598 &i915_file_priv->mm.request_list);
1600 INIT_LIST_HEAD(&request->client_list);
1603 /* Associate any objects on the flushing list matching the write
1604 * domain we're flushing with our flush.
1606 if (flush_domains != 0)
1607 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1609 if (!dev_priv->mm.suspended) {
1610 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1612 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1618 * Command execution barrier
1620 * Ensures that all commands in the ring are finished
1621 * before signalling the CPU
1624 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1626 uint32_t flush_domains = 0;
1628 /* The sampler always gets flushed on i965 (sigh) */
1630 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1632 ring->flush(dev, ring,
1633 I915_GEM_DOMAIN_COMMAND, flush_domains);
1634 return flush_domains;
1638 * Moves buffers associated only with the given active seqno from the active
1639 * to inactive list, potentially freeing them.
1642 i915_gem_retire_request(struct drm_device *dev,
1643 struct drm_i915_gem_request *request)
1645 drm_i915_private_t *dev_priv = dev->dev_private;
1647 trace_i915_gem_request_retire(dev, request->seqno);
1649 /* Move any buffers on the active list that are no longer referenced
1650 * by the ringbuffer to the flushing/inactive lists as appropriate.
1652 spin_lock(&dev_priv->mm.active_list_lock);
1653 while (!list_empty(&request->ring->active_list)) {
1654 struct drm_gem_object *obj;
1655 struct drm_i915_gem_object *obj_priv;
1657 obj_priv = list_first_entry(&request->ring->active_list,
1658 struct drm_i915_gem_object,
1660 obj = &obj_priv->base;
1662 /* If the seqno being retired doesn't match the oldest in the
1663 * list, then the oldest in the list must still be newer than
1666 if (obj_priv->last_rendering_seqno != request->seqno)
1670 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1671 __func__, request->seqno, obj);
1674 if (obj->write_domain != 0)
1675 i915_gem_object_move_to_flushing(obj);
1677 /* Take a reference on the object so it won't be
1678 * freed while the spinlock is held. The list
1679 * protection for this spinlock is safe when breaking
1680 * the lock like this since the next thing we do
1681 * is just get the head of the list again.
1683 drm_gem_object_reference(obj);
1684 i915_gem_object_move_to_inactive(obj);
1685 spin_unlock(&dev_priv->mm.active_list_lock);
1686 drm_gem_object_unreference(obj);
1687 spin_lock(&dev_priv->mm.active_list_lock);
1691 spin_unlock(&dev_priv->mm.active_list_lock);
1695 * Returns true if seq1 is later than seq2.
1698 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1700 return (int32_t)(seq1 - seq2) >= 0;
1704 i915_get_gem_seqno(struct drm_device *dev,
1705 struct intel_ring_buffer *ring)
1707 return ring->get_gem_seqno(dev, ring);
1711 * This function clears the request list as sequence numbers are passed.
1714 i915_gem_retire_requests_ring(struct drm_device *dev,
1715 struct intel_ring_buffer *ring)
1717 drm_i915_private_t *dev_priv = dev->dev_private;
1720 if (!ring->status_page.page_addr
1721 || list_empty(&ring->request_list))
1724 seqno = i915_get_gem_seqno(dev, ring);
1726 while (!list_empty(&ring->request_list)) {
1727 struct drm_i915_gem_request *request;
1728 uint32_t retiring_seqno;
1730 request = list_first_entry(&ring->request_list,
1731 struct drm_i915_gem_request,
1733 retiring_seqno = request->seqno;
1735 if (i915_seqno_passed(seqno, retiring_seqno) ||
1736 atomic_read(&dev_priv->mm.wedged)) {
1737 i915_gem_retire_request(dev, request);
1739 list_del(&request->list);
1740 list_del(&request->client_list);
1746 if (unlikely (dev_priv->trace_irq_seqno &&
1747 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1749 ring->user_irq_put(dev, ring);
1750 dev_priv->trace_irq_seqno = 0;
1755 i915_gem_retire_requests(struct drm_device *dev)
1757 drm_i915_private_t *dev_priv = dev->dev_private;
1759 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1760 struct drm_i915_gem_object *obj_priv, *tmp;
1762 /* We must be careful that during unbind() we do not
1763 * accidentally infinitely recurse into retire requests.
1765 * retire -> free -> unbind -> wait -> retire_ring
1767 list_for_each_entry_safe(obj_priv, tmp,
1768 &dev_priv->mm.deferred_free_list,
1770 i915_gem_free_object_tail(&obj_priv->base);
1773 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1775 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1779 i915_gem_retire_work_handler(struct work_struct *work)
1781 drm_i915_private_t *dev_priv;
1782 struct drm_device *dev;
1784 dev_priv = container_of(work, drm_i915_private_t,
1785 mm.retire_work.work);
1786 dev = dev_priv->dev;
1788 mutex_lock(&dev->struct_mutex);
1789 i915_gem_retire_requests(dev);
1791 if (!dev_priv->mm.suspended &&
1792 (!list_empty(&dev_priv->render_ring.request_list) ||
1794 !list_empty(&dev_priv->bsd_ring.request_list))))
1795 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1796 mutex_unlock(&dev->struct_mutex);
1800 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1801 int interruptible, struct intel_ring_buffer *ring)
1803 drm_i915_private_t *dev_priv = dev->dev_private;
1809 if (atomic_read(&dev_priv->mm.wedged))
1812 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1813 if (HAS_PCH_SPLIT(dev))
1814 ier = I915_READ(DEIER) | I915_READ(GTIER);
1816 ier = I915_READ(IER);
1818 DRM_ERROR("something (likely vbetool) disabled "
1819 "interrupts, re-enabling\n");
1820 i915_driver_irq_preinstall(dev);
1821 i915_driver_irq_postinstall(dev);
1824 trace_i915_gem_request_wait_begin(dev, seqno);
1826 ring->waiting_gem_seqno = seqno;
1827 ring->user_irq_get(dev, ring);
1829 ret = wait_event_interruptible(ring->irq_queue,
1831 ring->get_gem_seqno(dev, ring), seqno)
1832 || atomic_read(&dev_priv->mm.wedged));
1834 wait_event(ring->irq_queue,
1836 ring->get_gem_seqno(dev, ring), seqno)
1837 || atomic_read(&dev_priv->mm.wedged));
1839 ring->user_irq_put(dev, ring);
1840 ring->waiting_gem_seqno = 0;
1842 trace_i915_gem_request_wait_end(dev, seqno);
1844 if (atomic_read(&dev_priv->mm.wedged))
1847 if (ret && ret != -ERESTARTSYS)
1848 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1849 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1851 /* Directly dispatch request retiring. While we have the work queue
1852 * to handle this, the waiter on a request often wants an associated
1853 * buffer to have made it to the inactive list, and we would need
1854 * a separate wait queue to handle that.
1857 i915_gem_retire_requests_ring(dev, ring);
1863 * Waits for a sequence number to be signaled, and cleans up the
1864 * request and object lists appropriately for that event.
1867 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1868 struct intel_ring_buffer *ring)
1870 return i915_do_wait_request(dev, seqno, 1, ring);
1874 i915_gem_flush(struct drm_device *dev,
1875 uint32_t invalidate_domains,
1876 uint32_t flush_domains)
1878 drm_i915_private_t *dev_priv = dev->dev_private;
1879 if (flush_domains & I915_GEM_DOMAIN_CPU)
1880 drm_agp_chipset_flush(dev);
1881 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1886 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1892 i915_gem_flush_ring(struct drm_device *dev,
1893 uint32_t invalidate_domains,
1894 uint32_t flush_domains,
1895 struct intel_ring_buffer *ring)
1897 if (flush_domains & I915_GEM_DOMAIN_CPU)
1898 drm_agp_chipset_flush(dev);
1899 ring->flush(dev, ring,
1905 * Ensures that all rendering to the object has completed and the object is
1906 * safe to unbind from the GTT or access from the CPU.
1909 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1911 struct drm_device *dev = obj->dev;
1912 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1915 /* This function only exists to support waiting for existing rendering,
1916 * not for emitting required flushes.
1918 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1920 /* If there is rendering queued on the buffer being evicted, wait for
1923 if (obj_priv->active) {
1925 DRM_INFO("%s: object %p wait for seqno %08x\n",
1926 __func__, obj, obj_priv->last_rendering_seqno);
1928 ret = i915_wait_request(dev,
1929 obj_priv->last_rendering_seqno, obj_priv->ring);
1938 * Unbinds an object from the GTT aperture.
1941 i915_gem_object_unbind(struct drm_gem_object *obj)
1943 struct drm_device *dev = obj->dev;
1944 drm_i915_private_t *dev_priv = dev->dev_private;
1945 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1949 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1950 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1952 if (obj_priv->gtt_space == NULL)
1955 if (obj_priv->pin_count != 0) {
1956 DRM_ERROR("Attempting to unbind pinned buffer\n");
1960 /* blow away mappings if mapped through GTT */
1961 i915_gem_release_mmap(obj);
1963 /* Move the object to the CPU domain to ensure that
1964 * any possible CPU writes while it's not in the GTT
1965 * are flushed when we go to remap it. This will
1966 * also ensure that all pending GPU writes are finished
1969 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1970 if (ret == -ERESTARTSYS)
1972 /* Continue on if we fail due to EIO, the GPU is hung so we
1973 * should be safe and we need to cleanup or else we might
1974 * cause memory corruption through use-after-free.
1977 BUG_ON(obj_priv->active);
1979 /* release the fence reg _after_ flushing */
1980 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1981 i915_gem_clear_fence_reg(obj);
1983 if (obj_priv->agp_mem != NULL) {
1984 drm_unbind_agp(obj_priv->agp_mem);
1985 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1986 obj_priv->agp_mem = NULL;
1989 i915_gem_object_put_pages(obj);
1990 BUG_ON(obj_priv->pages_refcount);
1992 if (obj_priv->gtt_space) {
1993 atomic_dec(&dev->gtt_count);
1994 atomic_sub(obj->size, &dev->gtt_memory);
1996 drm_mm_put_block(obj_priv->gtt_space);
1997 obj_priv->gtt_space = NULL;
2000 /* Remove ourselves from the LRU list if present. */
2001 spin_lock(&dev_priv->mm.active_list_lock);
2002 if (!list_empty(&obj_priv->list))
2003 list_del_init(&obj_priv->list);
2004 spin_unlock(&dev_priv->mm.active_list_lock);
2006 if (i915_gem_object_is_purgeable(obj_priv))
2007 i915_gem_object_truncate(obj);
2009 trace_i915_gem_object_unbind(obj);
2014 static struct drm_gem_object *
2015 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2017 drm_i915_private_t *dev_priv = dev->dev_private;
2018 struct drm_i915_gem_object *obj_priv;
2019 struct drm_gem_object *best = NULL;
2020 struct drm_gem_object *first = NULL;
2022 /* Try to find the smallest clean object */
2023 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2024 struct drm_gem_object *obj = &obj_priv->base;
2025 if (obj->size >= min_size) {
2026 if ((!obj_priv->dirty ||
2027 i915_gem_object_is_purgeable(obj_priv)) &&
2028 (!best || obj->size < best->size)) {
2030 if (best->size == min_size)
2038 return best ? best : first;
2042 i915_gpu_idle(struct drm_device *dev)
2044 drm_i915_private_t *dev_priv = dev->dev_private;
2046 uint32_t seqno1, seqno2;
2049 spin_lock(&dev_priv->mm.active_list_lock);
2050 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2051 list_empty(&dev_priv->render_ring.active_list) &&
2053 list_empty(&dev_priv->bsd_ring.active_list)));
2054 spin_unlock(&dev_priv->mm.active_list_lock);
2059 /* Flush everything onto the inactive list. */
2060 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2061 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2062 &dev_priv->render_ring);
2065 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2068 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2069 &dev_priv->bsd_ring);
2073 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2083 i915_gem_evict_everything(struct drm_device *dev)
2085 drm_i915_private_t *dev_priv = dev->dev_private;
2089 spin_lock(&dev_priv->mm.active_list_lock);
2090 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2091 list_empty(&dev_priv->mm.flushing_list) &&
2092 list_empty(&dev_priv->render_ring.active_list) &&
2094 || list_empty(&dev_priv->bsd_ring.active_list)));
2095 spin_unlock(&dev_priv->mm.active_list_lock);
2100 /* Flush everything (on to the inactive lists) and evict */
2101 ret = i915_gpu_idle(dev);
2105 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2107 ret = i915_gem_evict_from_inactive_list(dev);
2111 spin_lock(&dev_priv->mm.active_list_lock);
2112 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2113 list_empty(&dev_priv->mm.flushing_list) &&
2114 list_empty(&dev_priv->render_ring.active_list) &&
2116 || list_empty(&dev_priv->bsd_ring.active_list)));
2117 spin_unlock(&dev_priv->mm.active_list_lock);
2118 BUG_ON(!lists_empty);
2124 i915_gem_evict_something(struct drm_device *dev, int min_size)
2126 drm_i915_private_t *dev_priv = dev->dev_private;
2127 struct drm_gem_object *obj;
2130 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
2131 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
2133 i915_gem_retire_requests(dev);
2135 /* If there's an inactive buffer available now, grab it
2138 obj = i915_gem_find_inactive_object(dev, min_size);
2140 struct drm_i915_gem_object *obj_priv;
2143 DRM_INFO("%s: evicting %p\n", __func__, obj);
2145 obj_priv = to_intel_bo(obj);
2146 BUG_ON(obj_priv->pin_count != 0);
2147 BUG_ON(obj_priv->active);
2149 /* Wait on the rendering and unbind the buffer. */
2150 return i915_gem_object_unbind(obj);
2153 /* If we didn't get anything, but the ring is still processing
2154 * things, wait for the next to finish and hopefully leave us
2155 * a buffer to evict.
2157 if (!list_empty(&render_ring->request_list)) {
2158 struct drm_i915_gem_request *request;
2160 request = list_first_entry(&render_ring->request_list,
2161 struct drm_i915_gem_request,
2164 ret = i915_wait_request(dev,
2165 request->seqno, request->ring);
2172 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2173 struct drm_i915_gem_request *request;
2175 request = list_first_entry(&bsd_ring->request_list,
2176 struct drm_i915_gem_request,
2179 ret = i915_wait_request(dev,
2180 request->seqno, request->ring);
2187 /* If we didn't have anything on the request list but there
2188 * are buffers awaiting a flush, emit one and try again.
2189 * When we wait on it, those buffers waiting for that flush
2190 * will get moved to inactive.
2192 if (!list_empty(&dev_priv->mm.flushing_list)) {
2193 struct drm_i915_gem_object *obj_priv;
2195 /* Find an object that we can immediately reuse */
2196 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2197 obj = &obj_priv->base;
2198 if (obj->size >= min_size)
2207 i915_gem_flush_ring(dev,
2211 seqno = i915_add_request(dev, NULL,
2220 /* If we didn't do any of the above, there's no single buffer
2221 * large enough to swap out for the new one, so just evict
2222 * everything and start again. (This should be rare.)
2224 if (!list_empty (&dev_priv->mm.inactive_list))
2225 return i915_gem_evict_from_inactive_list(dev);
2227 return i915_gem_evict_everything(dev);
2232 i915_gem_object_get_pages(struct drm_gem_object *obj,
2235 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2237 struct address_space *mapping;
2238 struct inode *inode;
2241 BUG_ON(obj_priv->pages_refcount
2242 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2244 if (obj_priv->pages_refcount++ != 0)
2247 /* Get the list of pages out of our struct file. They'll be pinned
2248 * at this point until we release them.
2250 page_count = obj->size / PAGE_SIZE;
2251 BUG_ON(obj_priv->pages != NULL);
2252 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2253 if (obj_priv->pages == NULL) {
2254 obj_priv->pages_refcount--;
2258 inode = obj->filp->f_path.dentry->d_inode;
2259 mapping = inode->i_mapping;
2260 for (i = 0; i < page_count; i++) {
2261 page = read_cache_page_gfp(mapping, i,
2269 obj_priv->pages[i] = page;
2272 if (obj_priv->tiling_mode != I915_TILING_NONE)
2273 i915_gem_object_do_bit_17_swizzle(obj);
2279 page_cache_release(obj_priv->pages[i]);
2281 drm_free_large(obj_priv->pages);
2282 obj_priv->pages = NULL;
2283 obj_priv->pages_refcount--;
2284 return PTR_ERR(page);
2287 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2289 struct drm_gem_object *obj = reg->obj;
2290 struct drm_device *dev = obj->dev;
2291 drm_i915_private_t *dev_priv = dev->dev_private;
2292 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2293 int regnum = obj_priv->fence_reg;
2296 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2298 val |= obj_priv->gtt_offset & 0xfffff000;
2299 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2300 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2302 if (obj_priv->tiling_mode == I915_TILING_Y)
2303 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2304 val |= I965_FENCE_REG_VALID;
2306 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2309 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2311 struct drm_gem_object *obj = reg->obj;
2312 struct drm_device *dev = obj->dev;
2313 drm_i915_private_t *dev_priv = dev->dev_private;
2314 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2315 int regnum = obj_priv->fence_reg;
2318 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2320 val |= obj_priv->gtt_offset & 0xfffff000;
2321 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2322 if (obj_priv->tiling_mode == I915_TILING_Y)
2323 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2324 val |= I965_FENCE_REG_VALID;
2326 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2329 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2331 struct drm_gem_object *obj = reg->obj;
2332 struct drm_device *dev = obj->dev;
2333 drm_i915_private_t *dev_priv = dev->dev_private;
2334 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2335 int regnum = obj_priv->fence_reg;
2337 uint32_t fence_reg, val;
2340 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2341 (obj_priv->gtt_offset & (obj->size - 1))) {
2342 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2343 __func__, obj_priv->gtt_offset, obj->size);
2347 if (obj_priv->tiling_mode == I915_TILING_Y &&
2348 HAS_128_BYTE_Y_TILING(dev))
2353 /* Note: pitch better be a power of two tile widths */
2354 pitch_val = obj_priv->stride / tile_width;
2355 pitch_val = ffs(pitch_val) - 1;
2357 if (obj_priv->tiling_mode == I915_TILING_Y &&
2358 HAS_128_BYTE_Y_TILING(dev))
2359 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2361 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2363 val = obj_priv->gtt_offset;
2364 if (obj_priv->tiling_mode == I915_TILING_Y)
2365 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2366 val |= I915_FENCE_SIZE_BITS(obj->size);
2367 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2368 val |= I830_FENCE_REG_VALID;
2371 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2373 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2374 I915_WRITE(fence_reg, val);
2377 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2379 struct drm_gem_object *obj = reg->obj;
2380 struct drm_device *dev = obj->dev;
2381 drm_i915_private_t *dev_priv = dev->dev_private;
2382 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2383 int regnum = obj_priv->fence_reg;
2386 uint32_t fence_size_bits;
2388 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2389 (obj_priv->gtt_offset & (obj->size - 1))) {
2390 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2391 __func__, obj_priv->gtt_offset);
2395 pitch_val = obj_priv->stride / 128;
2396 pitch_val = ffs(pitch_val) - 1;
2397 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2399 val = obj_priv->gtt_offset;
2400 if (obj_priv->tiling_mode == I915_TILING_Y)
2401 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2402 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2403 WARN_ON(fence_size_bits & ~0x00000f00);
2404 val |= fence_size_bits;
2405 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2406 val |= I830_FENCE_REG_VALID;
2408 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2411 static int i915_find_fence_reg(struct drm_device *dev)
2413 struct drm_i915_fence_reg *reg = NULL;
2414 struct drm_i915_gem_object *obj_priv = NULL;
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2416 struct drm_gem_object *obj = NULL;
2419 /* First try to find a free reg */
2421 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2422 reg = &dev_priv->fence_regs[i];
2426 obj_priv = to_intel_bo(reg->obj);
2427 if (!obj_priv->pin_count)
2434 /* None available, try to steal one or wait for a user to finish */
2435 i = I915_FENCE_REG_NONE;
2436 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2439 obj_priv = to_intel_bo(obj);
2441 if (obj_priv->pin_count)
2445 i = obj_priv->fence_reg;
2449 BUG_ON(i == I915_FENCE_REG_NONE);
2451 /* We only have a reference on obj from the active list. put_fence_reg
2452 * might drop that one, causing a use-after-free in it. So hold a
2453 * private reference to obj like the other callers of put_fence_reg
2454 * (set_tiling ioctl) do. */
2455 drm_gem_object_reference(obj);
2456 ret = i915_gem_object_put_fence_reg(obj);
2457 drm_gem_object_unreference(obj);
2465 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2466 * @obj: object to map through a fence reg
2468 * When mapping objects through the GTT, userspace wants to be able to write
2469 * to them without having to worry about swizzling if the object is tiled.
2471 * This function walks the fence regs looking for a free one for @obj,
2472 * stealing one if it can't find any.
2474 * It then sets up the reg based on the object's properties: address, pitch
2475 * and tiling format.
2478 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2480 struct drm_device *dev = obj->dev;
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2483 struct drm_i915_fence_reg *reg = NULL;
2486 /* Just update our place in the LRU if our fence is getting used. */
2487 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2488 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2489 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2493 switch (obj_priv->tiling_mode) {
2494 case I915_TILING_NONE:
2495 WARN(1, "allocating a fence for non-tiled object?\n");
2498 if (!obj_priv->stride)
2500 WARN((obj_priv->stride & (512 - 1)),
2501 "object 0x%08x is X tiled but has non-512B pitch\n",
2502 obj_priv->gtt_offset);
2505 if (!obj_priv->stride)
2507 WARN((obj_priv->stride & (128 - 1)),
2508 "object 0x%08x is Y tiled but has non-128B pitch\n",
2509 obj_priv->gtt_offset);
2513 ret = i915_find_fence_reg(dev);
2517 obj_priv->fence_reg = ret;
2518 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2519 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2524 sandybridge_write_fence_reg(reg);
2525 else if (IS_I965G(dev))
2526 i965_write_fence_reg(reg);
2527 else if (IS_I9XX(dev))
2528 i915_write_fence_reg(reg);
2530 i830_write_fence_reg(reg);
2532 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2533 obj_priv->tiling_mode);
2539 * i915_gem_clear_fence_reg - clear out fence register info
2540 * @obj: object to clear
2542 * Zeroes out the fence register itself and clears out the associated
2543 * data structures in dev_priv and obj_priv.
2546 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2548 struct drm_device *dev = obj->dev;
2549 drm_i915_private_t *dev_priv = dev->dev_private;
2550 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2551 struct drm_i915_fence_reg *reg =
2552 &dev_priv->fence_regs[obj_priv->fence_reg];
2555 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2556 (obj_priv->fence_reg * 8), 0);
2557 } else if (IS_I965G(dev)) {
2558 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2562 if (obj_priv->fence_reg < 8)
2563 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2565 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2568 I915_WRITE(fence_reg, 0);
2572 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2573 list_del_init(®->lru_list);
2577 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2578 * to the buffer to finish, and then resets the fence register.
2579 * @obj: tiled object holding a fence register.
2581 * Zeroes out the fence register itself and clears out the associated
2582 * data structures in dev_priv and obj_priv.
2585 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2587 struct drm_device *dev = obj->dev;
2588 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2590 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2593 /* If we've changed tiling, GTT-mappings of the object
2594 * need to re-fault to ensure that the correct fence register
2595 * setup is in place.
2597 i915_gem_release_mmap(obj);
2599 /* On the i915, GPU access to tiled buffers is via a fence,
2600 * therefore we must wait for any outstanding access to complete
2601 * before clearing the fence.
2603 if (!IS_I965G(dev)) {
2606 ret = i915_gem_object_flush_gpu_write_domain(obj);
2610 ret = i915_gem_object_wait_rendering(obj);
2615 i915_gem_object_flush_gtt_write_domain(obj);
2616 i915_gem_clear_fence_reg (obj);
2622 * Finds free space in the GTT aperture and binds the object there.
2625 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2627 struct drm_device *dev = obj->dev;
2628 drm_i915_private_t *dev_priv = dev->dev_private;
2629 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2630 struct drm_mm_node *free_space;
2631 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2634 if (obj_priv->madv != I915_MADV_WILLNEED) {
2635 DRM_ERROR("Attempting to bind a purgeable object\n");
2640 alignment = i915_gem_get_gtt_alignment(obj);
2641 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2642 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2646 /* If the object is bigger than the entire aperture, reject it early
2647 * before evicting everything in a vain attempt to find space.
2649 if (obj->size > dev->gtt_total) {
2650 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2655 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2656 obj->size, alignment, 0);
2657 if (free_space != NULL) {
2658 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2660 if (obj_priv->gtt_space != NULL)
2661 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2663 if (obj_priv->gtt_space == NULL) {
2664 /* If the gtt is empty and we're still having trouble
2665 * fitting our object in, we're out of memory.
2668 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2670 ret = i915_gem_evict_something(dev, obj->size);
2678 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2679 obj->size, obj_priv->gtt_offset);
2681 ret = i915_gem_object_get_pages(obj, gfpmask);
2683 drm_mm_put_block(obj_priv->gtt_space);
2684 obj_priv->gtt_space = NULL;
2686 if (ret == -ENOMEM) {
2687 /* first try to clear up some space from the GTT */
2688 ret = i915_gem_evict_something(dev, obj->size);
2690 /* now try to shrink everyone else */
2705 /* Create an AGP memory structure pointing at our pages, and bind it
2708 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2710 obj->size >> PAGE_SHIFT,
2711 obj_priv->gtt_offset,
2712 obj_priv->agp_type);
2713 if (obj_priv->agp_mem == NULL) {
2714 i915_gem_object_put_pages(obj);
2715 drm_mm_put_block(obj_priv->gtt_space);
2716 obj_priv->gtt_space = NULL;
2718 ret = i915_gem_evict_something(dev, obj->size);
2724 atomic_inc(&dev->gtt_count);
2725 atomic_add(obj->size, &dev->gtt_memory);
2727 /* Assert that the object is not currently in any GPU domain. As it
2728 * wasn't in the GTT, there shouldn't be any way it could have been in
2731 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2732 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2734 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2740 i915_gem_clflush_object(struct drm_gem_object *obj)
2742 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2744 /* If we don't have a page list set up, then we're not pinned
2745 * to GPU, and we can ignore the cache flush because it'll happen
2746 * again at bind time.
2748 if (obj_priv->pages == NULL)
2751 trace_i915_gem_object_clflush(obj);
2753 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2756 /** Flushes any GPU write domain for the object if it's dirty. */
2758 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2760 struct drm_device *dev = obj->dev;
2761 uint32_t old_write_domain;
2762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2764 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2767 /* Queue the GPU write cache flushing we need. */
2768 old_write_domain = obj->write_domain;
2769 i915_gem_flush(dev, 0, obj->write_domain);
2770 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2773 trace_i915_gem_object_change_domain(obj,
2779 /** Flushes the GTT write domain for the object if it's dirty. */
2781 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2783 uint32_t old_write_domain;
2785 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2788 /* No actual flushing is required for the GTT write domain. Writes
2789 * to it immediately go to main memory as far as we know, so there's
2790 * no chipset flush. It also doesn't land in render cache.
2792 old_write_domain = obj->write_domain;
2793 obj->write_domain = 0;
2795 trace_i915_gem_object_change_domain(obj,
2800 /** Flushes the CPU write domain for the object if it's dirty. */
2802 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2804 struct drm_device *dev = obj->dev;
2805 uint32_t old_write_domain;
2807 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2810 i915_gem_clflush_object(obj);
2811 drm_agp_chipset_flush(dev);
2812 old_write_domain = obj->write_domain;
2813 obj->write_domain = 0;
2815 trace_i915_gem_object_change_domain(obj,
2821 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2825 switch (obj->write_domain) {
2826 case I915_GEM_DOMAIN_GTT:
2827 i915_gem_object_flush_gtt_write_domain(obj);
2829 case I915_GEM_DOMAIN_CPU:
2830 i915_gem_object_flush_cpu_write_domain(obj);
2833 ret = i915_gem_object_flush_gpu_write_domain(obj);
2841 * Moves a single object to the GTT read, and possibly write domain.
2843 * This function returns when the move is complete, including waiting on
2847 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2849 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2850 uint32_t old_write_domain, old_read_domains;
2853 /* Not valid to be called on unbound objects. */
2854 if (obj_priv->gtt_space == NULL)
2857 ret = i915_gem_object_flush_gpu_write_domain(obj);
2861 /* Wait on any GPU rendering and flushing to occur. */
2862 ret = i915_gem_object_wait_rendering(obj);
2866 old_write_domain = obj->write_domain;
2867 old_read_domains = obj->read_domains;
2869 /* If we're writing through the GTT domain, then CPU and GPU caches
2870 * will need to be invalidated at next use.
2873 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2875 i915_gem_object_flush_cpu_write_domain(obj);
2877 /* It should now be out of any other write domains, and we can update
2878 * the domain values for our changes.
2880 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2881 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2883 obj->write_domain = I915_GEM_DOMAIN_GTT;
2884 obj_priv->dirty = 1;
2887 trace_i915_gem_object_change_domain(obj,
2895 * Prepare buffer for display plane. Use uninterruptible for possible flush
2896 * wait, as in modesetting process we're not supposed to be interrupted.
2899 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2901 struct drm_device *dev = obj->dev;
2902 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2903 uint32_t old_write_domain, old_read_domains;
2906 /* Not valid to be called on unbound objects. */
2907 if (obj_priv->gtt_space == NULL)
2910 ret = i915_gem_object_flush_gpu_write_domain(obj);
2914 /* Wait on any GPU rendering and flushing to occur. */
2915 if (obj_priv->active) {
2917 DRM_INFO("%s: object %p wait for seqno %08x\n",
2918 __func__, obj, obj_priv->last_rendering_seqno);
2920 ret = i915_do_wait_request(dev,
2921 obj_priv->last_rendering_seqno,
2928 i915_gem_object_flush_cpu_write_domain(obj);
2930 old_write_domain = obj->write_domain;
2931 old_read_domains = obj->read_domains;
2933 /* It should now be out of any other write domains, and we can update
2934 * the domain values for our changes.
2936 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2937 obj->read_domains = I915_GEM_DOMAIN_GTT;
2938 obj->write_domain = I915_GEM_DOMAIN_GTT;
2939 obj_priv->dirty = 1;
2941 trace_i915_gem_object_change_domain(obj,
2949 * Moves a single object to the CPU read, and possibly write domain.
2951 * This function returns when the move is complete, including waiting on
2955 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2957 uint32_t old_write_domain, old_read_domains;
2960 ret = i915_gem_object_flush_gpu_write_domain(obj);
2964 /* Wait on any GPU rendering and flushing to occur. */
2965 ret = i915_gem_object_wait_rendering(obj);
2969 i915_gem_object_flush_gtt_write_domain(obj);
2971 /* If we have a partially-valid cache of the object in the CPU,
2972 * finish invalidating it and free the per-page flags.
2974 i915_gem_object_set_to_full_cpu_read_domain(obj);
2976 old_write_domain = obj->write_domain;
2977 old_read_domains = obj->read_domains;
2979 /* Flush the CPU cache if it's still invalid. */
2980 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2981 i915_gem_clflush_object(obj);
2983 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2986 /* It should now be out of any other write domains, and we can update
2987 * the domain values for our changes.
2989 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2991 /* If we're writing through the CPU, then the GPU read domains will
2992 * need to be invalidated at next use.
2995 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2996 obj->write_domain = I915_GEM_DOMAIN_CPU;
2999 trace_i915_gem_object_change_domain(obj,
3007 * Set the next domain for the specified object. This
3008 * may not actually perform the necessary flushing/invaliding though,
3009 * as that may want to be batched with other set_domain operations
3011 * This is (we hope) the only really tricky part of gem. The goal
3012 * is fairly simple -- track which caches hold bits of the object
3013 * and make sure they remain coherent. A few concrete examples may
3014 * help to explain how it works. For shorthand, we use the notation
3015 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3016 * a pair of read and write domain masks.
3018 * Case 1: the batch buffer
3024 * 5. Unmapped from GTT
3027 * Let's take these a step at a time
3030 * Pages allocated from the kernel may still have
3031 * cache contents, so we set them to (CPU, CPU) always.
3032 * 2. Written by CPU (using pwrite)
3033 * The pwrite function calls set_domain (CPU, CPU) and
3034 * this function does nothing (as nothing changes)
3036 * This function asserts that the object is not
3037 * currently in any GPU-based read or write domains
3039 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3040 * As write_domain is zero, this function adds in the
3041 * current read domains (CPU+COMMAND, 0).
3042 * flush_domains is set to CPU.
3043 * invalidate_domains is set to COMMAND
3044 * clflush is run to get data out of the CPU caches
3045 * then i915_dev_set_domain calls i915_gem_flush to
3046 * emit an MI_FLUSH and drm_agp_chipset_flush
3047 * 5. Unmapped from GTT
3048 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3049 * flush_domains and invalidate_domains end up both zero
3050 * so no flushing/invalidating happens
3054 * Case 2: The shared render buffer
3058 * 3. Read/written by GPU
3059 * 4. set_domain to (CPU,CPU)
3060 * 5. Read/written by CPU
3061 * 6. Read/written by GPU
3064 * Same as last example, (CPU, CPU)
3066 * Nothing changes (assertions find that it is not in the GPU)
3067 * 3. Read/written by GPU
3068 * execbuffer calls set_domain (RENDER, RENDER)
3069 * flush_domains gets CPU
3070 * invalidate_domains gets GPU
3072 * MI_FLUSH and drm_agp_chipset_flush
3073 * 4. set_domain (CPU, CPU)
3074 * flush_domains gets GPU
3075 * invalidate_domains gets CPU
3076 * wait_rendering (obj) to make sure all drawing is complete.
3077 * This will include an MI_FLUSH to get the data from GPU
3079 * clflush (obj) to invalidate the CPU cache
3080 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3081 * 5. Read/written by CPU
3082 * cache lines are loaded and dirtied
3083 * 6. Read written by GPU
3084 * Same as last GPU access
3086 * Case 3: The constant buffer
3091 * 4. Updated (written) by CPU again
3100 * flush_domains = CPU
3101 * invalidate_domains = RENDER
3104 * drm_agp_chipset_flush
3105 * 4. Updated (written) by CPU again
3107 * flush_domains = 0 (no previous write domain)
3108 * invalidate_domains = 0 (no new read domains)
3111 * flush_domains = CPU
3112 * invalidate_domains = RENDER
3115 * drm_agp_chipset_flush
3118 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3120 struct drm_device *dev = obj->dev;
3121 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3122 uint32_t invalidate_domains = 0;
3123 uint32_t flush_domains = 0;
3124 uint32_t old_read_domains;
3126 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3127 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3129 intel_mark_busy(dev, obj);
3132 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3134 obj->read_domains, obj->pending_read_domains,
3135 obj->write_domain, obj->pending_write_domain);
3138 * If the object isn't moving to a new write domain,
3139 * let the object stay in multiple read domains
3141 if (obj->pending_write_domain == 0)
3142 obj->pending_read_domains |= obj->read_domains;
3144 obj_priv->dirty = 1;
3147 * Flush the current write domain if
3148 * the new read domains don't match. Invalidate
3149 * any read domains which differ from the old
3152 if (obj->write_domain &&
3153 obj->write_domain != obj->pending_read_domains) {
3154 flush_domains |= obj->write_domain;
3155 invalidate_domains |=
3156 obj->pending_read_domains & ~obj->write_domain;
3159 * Invalidate any read caches which may have
3160 * stale data. That is, any new read domains.
3162 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3163 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3165 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3166 __func__, flush_domains, invalidate_domains);
3168 i915_gem_clflush_object(obj);
3171 old_read_domains = obj->read_domains;
3173 /* The actual obj->write_domain will be updated with
3174 * pending_write_domain after we emit the accumulated flush for all
3175 * of our domain changes in execbuffers (which clears objects'
3176 * write_domains). So if we have a current write domain that we
3177 * aren't changing, set pending_write_domain to that.
3179 if (flush_domains == 0 && obj->pending_write_domain == 0)
3180 obj->pending_write_domain = obj->write_domain;
3181 obj->read_domains = obj->pending_read_domains;
3183 dev->invalidate_domains |= invalidate_domains;
3184 dev->flush_domains |= flush_domains;
3186 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3188 obj->read_domains, obj->write_domain,
3189 dev->invalidate_domains, dev->flush_domains);
3192 trace_i915_gem_object_change_domain(obj,
3198 * Moves the object from a partially CPU read to a full one.
3200 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3201 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3204 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3206 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3208 if (!obj_priv->page_cpu_valid)
3211 /* If we're partially in the CPU read domain, finish moving it in.
3213 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3216 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3217 if (obj_priv->page_cpu_valid[i])
3219 drm_clflush_pages(obj_priv->pages + i, 1);
3223 /* Free the page_cpu_valid mappings which are now stale, whether
3224 * or not we've got I915_GEM_DOMAIN_CPU.
3226 kfree(obj_priv->page_cpu_valid);
3227 obj_priv->page_cpu_valid = NULL;
3231 * Set the CPU read domain on a range of the object.
3233 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3234 * not entirely valid. The page_cpu_valid member of the object flags which
3235 * pages have been flushed, and will be respected by
3236 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3237 * of the whole object.
3239 * This function returns when the move is complete, including waiting on
3243 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3244 uint64_t offset, uint64_t size)
3246 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3247 uint32_t old_read_domains;
3250 if (offset == 0 && size == obj->size)
3251 return i915_gem_object_set_to_cpu_domain(obj, 0);
3253 ret = i915_gem_object_flush_gpu_write_domain(obj);
3257 /* Wait on any GPU rendering and flushing to occur. */
3258 ret = i915_gem_object_wait_rendering(obj);
3261 i915_gem_object_flush_gtt_write_domain(obj);
3263 /* If we're already fully in the CPU read domain, we're done. */
3264 if (obj_priv->page_cpu_valid == NULL &&
3265 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3268 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3269 * newly adding I915_GEM_DOMAIN_CPU
3271 if (obj_priv->page_cpu_valid == NULL) {
3272 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3274 if (obj_priv->page_cpu_valid == NULL)
3276 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3277 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3279 /* Flush the cache on any pages that are still invalid from the CPU's
3282 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3284 if (obj_priv->page_cpu_valid[i])
3287 drm_clflush_pages(obj_priv->pages + i, 1);
3289 obj_priv->page_cpu_valid[i] = 1;
3292 /* It should now be out of any other write domains, and we can update
3293 * the domain values for our changes.
3295 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3297 old_read_domains = obj->read_domains;
3298 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3300 trace_i915_gem_object_change_domain(obj,
3308 * Pin an object to the GTT and evaluate the relocations landing in it.
3311 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3312 struct drm_file *file_priv,
3313 struct drm_i915_gem_exec_object2 *entry,
3314 struct drm_i915_gem_relocation_entry *relocs)
3316 struct drm_device *dev = obj->dev;
3317 drm_i915_private_t *dev_priv = dev->dev_private;
3318 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3320 void __iomem *reloc_page;
3323 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3324 obj_priv->tiling_mode != I915_TILING_NONE;
3326 /* Check fence reg constraints and rebind if necessary */
3328 !i915_gem_object_fence_offset_ok(obj,
3329 obj_priv->tiling_mode)) {
3330 ret = i915_gem_object_unbind(obj);
3335 /* Choose the GTT offset for our buffer and put it there. */
3336 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3341 * Pre-965 chips need a fence register set up in order to
3342 * properly handle blits to/from tiled surfaces.
3345 ret = i915_gem_object_get_fence_reg(obj);
3347 i915_gem_object_unpin(obj);
3352 entry->offset = obj_priv->gtt_offset;
3354 /* Apply the relocations, using the GTT aperture to avoid cache
3355 * flushing requirements.
3357 for (i = 0; i < entry->relocation_count; i++) {
3358 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3359 struct drm_gem_object *target_obj;
3360 struct drm_i915_gem_object *target_obj_priv;
3361 uint32_t reloc_val, reloc_offset;
3362 uint32_t __iomem *reloc_entry;
3364 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3365 reloc->target_handle);
3366 if (target_obj == NULL) {
3367 i915_gem_object_unpin(obj);
3370 target_obj_priv = to_intel_bo(target_obj);
3373 DRM_INFO("%s: obj %p offset %08x target %d "
3374 "read %08x write %08x gtt %08x "
3375 "presumed %08x delta %08x\n",
3378 (int) reloc->offset,
3379 (int) reloc->target_handle,
3380 (int) reloc->read_domains,
3381 (int) reloc->write_domain,
3382 (int) target_obj_priv->gtt_offset,
3383 (int) reloc->presumed_offset,
3387 /* The target buffer should have appeared before us in the
3388 * exec_object list, so it should have a GTT space bound by now.
3390 if (target_obj_priv->gtt_space == NULL) {
3391 DRM_ERROR("No GTT space found for object %d\n",
3392 reloc->target_handle);
3393 drm_gem_object_unreference(target_obj);
3394 i915_gem_object_unpin(obj);
3398 /* Validate that the target is in a valid r/w GPU domain */
3399 if (reloc->write_domain & (reloc->write_domain - 1)) {
3400 DRM_ERROR("reloc with multiple write domains: "
3401 "obj %p target %d offset %d "
3402 "read %08x write %08x",
3403 obj, reloc->target_handle,
3404 (int) reloc->offset,
3405 reloc->read_domains,
3406 reloc->write_domain);
3409 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3410 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3411 DRM_ERROR("reloc with read/write CPU domains: "
3412 "obj %p target %d offset %d "
3413 "read %08x write %08x",
3414 obj, reloc->target_handle,
3415 (int) reloc->offset,
3416 reloc->read_domains,
3417 reloc->write_domain);
3418 drm_gem_object_unreference(target_obj);
3419 i915_gem_object_unpin(obj);
3422 if (reloc->write_domain && target_obj->pending_write_domain &&
3423 reloc->write_domain != target_obj->pending_write_domain) {
3424 DRM_ERROR("Write domain conflict: "
3425 "obj %p target %d offset %d "
3426 "new %08x old %08x\n",
3427 obj, reloc->target_handle,
3428 (int) reloc->offset,
3429 reloc->write_domain,
3430 target_obj->pending_write_domain);
3431 drm_gem_object_unreference(target_obj);
3432 i915_gem_object_unpin(obj);
3436 target_obj->pending_read_domains |= reloc->read_domains;
3437 target_obj->pending_write_domain |= reloc->write_domain;
3439 /* If the relocation already has the right value in it, no
3440 * more work needs to be done.
3442 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3443 drm_gem_object_unreference(target_obj);
3447 /* Check that the relocation address is valid... */
3448 if (reloc->offset > obj->size - 4) {
3449 DRM_ERROR("Relocation beyond object bounds: "
3450 "obj %p target %d offset %d size %d.\n",
3451 obj, reloc->target_handle,
3452 (int) reloc->offset, (int) obj->size);
3453 drm_gem_object_unreference(target_obj);
3454 i915_gem_object_unpin(obj);
3457 if (reloc->offset & 3) {
3458 DRM_ERROR("Relocation not 4-byte aligned: "
3459 "obj %p target %d offset %d.\n",
3460 obj, reloc->target_handle,
3461 (int) reloc->offset);
3462 drm_gem_object_unreference(target_obj);
3463 i915_gem_object_unpin(obj);
3467 /* and points to somewhere within the target object. */
3468 if (reloc->delta >= target_obj->size) {
3469 DRM_ERROR("Relocation beyond target object bounds: "
3470 "obj %p target %d delta %d size %d.\n",
3471 obj, reloc->target_handle,
3472 (int) reloc->delta, (int) target_obj->size);
3473 drm_gem_object_unreference(target_obj);
3474 i915_gem_object_unpin(obj);
3478 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3480 drm_gem_object_unreference(target_obj);
3481 i915_gem_object_unpin(obj);
3485 /* Map the page containing the relocation we're going to
3488 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3489 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3492 reloc_entry = (uint32_t __iomem *)(reloc_page +
3493 (reloc_offset & (PAGE_SIZE - 1)));
3494 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3497 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3498 obj, (unsigned int) reloc->offset,
3499 readl(reloc_entry), reloc_val);
3501 writel(reloc_val, reloc_entry);
3502 io_mapping_unmap_atomic(reloc_page);
3504 /* The updated presumed offset for this entry will be
3505 * copied back out to the user.
3507 reloc->presumed_offset = target_obj_priv->gtt_offset;
3509 drm_gem_object_unreference(target_obj);
3514 i915_gem_dump_object(obj, 128, __func__, ~0);
3519 /* Throttle our rendering by waiting until the ring has completed our requests
3520 * emitted over 20 msec ago.
3522 * Note that if we were to use the current jiffies each time around the loop,
3523 * we wouldn't escape the function with any frames outstanding if the time to
3524 * render a frame was over 20ms.
3526 * This should get us reasonable parallelism between CPU and GPU but also
3527 * relatively low latency when blocking on a particular request to finish.
3530 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3532 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3534 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3536 mutex_lock(&dev->struct_mutex);
3537 while (!list_empty(&i915_file_priv->mm.request_list)) {
3538 struct drm_i915_gem_request *request;
3540 request = list_first_entry(&i915_file_priv->mm.request_list,
3541 struct drm_i915_gem_request,
3544 if (time_after_eq(request->emitted_jiffies, recent_enough))
3547 ret = i915_wait_request(dev, request->seqno, request->ring);
3551 mutex_unlock(&dev->struct_mutex);
3557 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3558 uint32_t buffer_count,
3559 struct drm_i915_gem_relocation_entry **relocs)
3561 uint32_t reloc_count = 0, reloc_index = 0, i;
3565 for (i = 0; i < buffer_count; i++) {
3566 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3568 reloc_count += exec_list[i].relocation_count;
3571 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3572 if (*relocs == NULL) {
3573 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3577 for (i = 0; i < buffer_count; i++) {
3578 struct drm_i915_gem_relocation_entry __user *user_relocs;
3580 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3582 ret = copy_from_user(&(*relocs)[reloc_index],
3584 exec_list[i].relocation_count *
3587 drm_free_large(*relocs);
3592 reloc_index += exec_list[i].relocation_count;
3599 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3600 uint32_t buffer_count,
3601 struct drm_i915_gem_relocation_entry *relocs)
3603 uint32_t reloc_count = 0, i;
3609 for (i = 0; i < buffer_count; i++) {
3610 struct drm_i915_gem_relocation_entry __user *user_relocs;
3613 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3615 unwritten = copy_to_user(user_relocs,
3616 &relocs[reloc_count],
3617 exec_list[i].relocation_count *
3625 reloc_count += exec_list[i].relocation_count;
3629 drm_free_large(relocs);
3635 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3636 uint64_t exec_offset)
3638 uint32_t exec_start, exec_len;
3640 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3641 exec_len = (uint32_t) exec->batch_len;
3643 if ((exec_start | exec_len) & 0x7)
3653 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3654 struct drm_gem_object **object_list,
3657 drm_i915_private_t *dev_priv = dev->dev_private;
3658 struct drm_i915_gem_object *obj_priv;
3663 prepare_to_wait(&dev_priv->pending_flip_queue,
3664 &wait, TASK_INTERRUPTIBLE);
3665 for (i = 0; i < count; i++) {
3666 obj_priv = to_intel_bo(object_list[i]);
3667 if (atomic_read(&obj_priv->pending_flip) > 0)
3673 if (!signal_pending(current)) {
3674 mutex_unlock(&dev->struct_mutex);
3676 mutex_lock(&dev->struct_mutex);
3682 finish_wait(&dev_priv->pending_flip_queue, &wait);
3689 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3690 struct drm_file *file_priv,
3691 struct drm_i915_gem_execbuffer2 *args,
3692 struct drm_i915_gem_exec_object2 *exec_list)
3694 drm_i915_private_t *dev_priv = dev->dev_private;
3695 struct drm_gem_object **object_list = NULL;
3696 struct drm_gem_object *batch_obj;
3697 struct drm_i915_gem_object *obj_priv;
3698 struct drm_clip_rect *cliprects = NULL;
3699 struct drm_i915_gem_relocation_entry *relocs = NULL;
3700 int ret = 0, ret2, i, pinned = 0;
3701 uint64_t exec_offset;
3702 uint32_t seqno, flush_domains, reloc_index;
3703 int pin_tries, flips;
3705 struct intel_ring_buffer *ring = NULL;
3708 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3709 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3711 if (args->flags & I915_EXEC_BSD) {
3712 if (!HAS_BSD(dev)) {
3713 DRM_ERROR("execbuf with wrong flag\n");
3716 ring = &dev_priv->bsd_ring;
3718 ring = &dev_priv->render_ring;
3722 if (args->buffer_count < 1) {
3723 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3726 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3727 if (object_list == NULL) {
3728 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3729 args->buffer_count);
3734 if (args->num_cliprects != 0) {
3735 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3737 if (cliprects == NULL) {
3742 ret = copy_from_user(cliprects,
3743 (struct drm_clip_rect __user *)
3744 (uintptr_t) args->cliprects_ptr,
3745 sizeof(*cliprects) * args->num_cliprects);
3747 DRM_ERROR("copy %d cliprects failed: %d\n",
3748 args->num_cliprects, ret);
3753 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3758 mutex_lock(&dev->struct_mutex);
3760 i915_verify_inactive(dev, __FILE__, __LINE__);
3762 if (atomic_read(&dev_priv->mm.wedged)) {
3763 mutex_unlock(&dev->struct_mutex);
3768 if (dev_priv->mm.suspended) {
3769 mutex_unlock(&dev->struct_mutex);
3774 /* Look up object handles */
3776 for (i = 0; i < args->buffer_count; i++) {
3777 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3778 exec_list[i].handle);
3779 if (object_list[i] == NULL) {
3780 DRM_ERROR("Invalid object handle %d at index %d\n",
3781 exec_list[i].handle, i);
3782 /* prevent error path from reading uninitialized data */
3783 args->buffer_count = i + 1;
3788 obj_priv = to_intel_bo(object_list[i]);
3789 if (obj_priv->in_execbuffer) {
3790 DRM_ERROR("Object %p appears more than once in object list\n",
3792 /* prevent error path from reading uninitialized data */
3793 args->buffer_count = i + 1;
3797 obj_priv->in_execbuffer = true;
3798 flips += atomic_read(&obj_priv->pending_flip);
3802 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3803 args->buffer_count);
3808 /* Pin and relocate */
3809 for (pin_tries = 0; ; pin_tries++) {
3813 for (i = 0; i < args->buffer_count; i++) {
3814 object_list[i]->pending_read_domains = 0;
3815 object_list[i]->pending_write_domain = 0;
3816 ret = i915_gem_object_pin_and_relocate(object_list[i],
3819 &relocs[reloc_index]);
3823 reloc_index += exec_list[i].relocation_count;
3829 /* error other than GTT full, or we've already tried again */
3830 if (ret != -ENOSPC || pin_tries >= 1) {
3831 if (ret != -ERESTARTSYS) {
3832 unsigned long long total_size = 0;
3834 for (i = 0; i < args->buffer_count; i++) {
3835 obj_priv = to_intel_bo(object_list[i]);
3837 total_size += object_list[i]->size;
3839 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3840 obj_priv->tiling_mode != I915_TILING_NONE;
3842 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3843 pinned+1, args->buffer_count,
3844 total_size, num_fences,
3846 DRM_ERROR("%d objects [%d pinned], "
3847 "%d object bytes [%d pinned], "
3848 "%d/%d gtt bytes\n",
3849 atomic_read(&dev->object_count),
3850 atomic_read(&dev->pin_count),
3851 atomic_read(&dev->object_memory),
3852 atomic_read(&dev->pin_memory),
3853 atomic_read(&dev->gtt_memory),
3859 /* unpin all of our buffers */
3860 for (i = 0; i < pinned; i++)
3861 i915_gem_object_unpin(object_list[i]);
3864 /* evict everyone we can from the aperture */
3865 ret = i915_gem_evict_everything(dev);
3866 if (ret && ret != -ENOSPC)
3870 /* Set the pending read domains for the batch buffer to COMMAND */
3871 batch_obj = object_list[args->buffer_count-1];
3872 if (batch_obj->pending_write_domain) {
3873 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3877 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3879 /* Sanity check the batch buffer, prior to moving objects */
3880 exec_offset = exec_list[args->buffer_count - 1].offset;
3881 ret = i915_gem_check_execbuffer (args, exec_offset);
3883 DRM_ERROR("execbuf with invalid offset/length\n");
3887 i915_verify_inactive(dev, __FILE__, __LINE__);
3889 /* Zero the global flush/invalidate flags. These
3890 * will be modified as new domains are computed
3893 dev->invalidate_domains = 0;
3894 dev->flush_domains = 0;
3896 for (i = 0; i < args->buffer_count; i++) {
3897 struct drm_gem_object *obj = object_list[i];
3899 /* Compute new gpu domains and update invalidate/flush */
3900 i915_gem_object_set_to_gpu_domain(obj);
3903 i915_verify_inactive(dev, __FILE__, __LINE__);
3905 if (dev->invalidate_domains | dev->flush_domains) {
3907 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3909 dev->invalidate_domains,
3910 dev->flush_domains);
3913 dev->invalidate_domains,
3914 dev->flush_domains);
3915 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
3916 (void)i915_add_request(dev, file_priv,
3918 &dev_priv->render_ring);
3921 (void)i915_add_request(dev, file_priv,
3923 &dev_priv->bsd_ring);
3927 for (i = 0; i < args->buffer_count; i++) {
3928 struct drm_gem_object *obj = object_list[i];
3929 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3930 uint32_t old_write_domain = obj->write_domain;
3932 obj->write_domain = obj->pending_write_domain;
3933 if (obj->write_domain)
3934 list_move_tail(&obj_priv->gpu_write_list,
3935 &dev_priv->mm.gpu_write_list);
3937 list_del_init(&obj_priv->gpu_write_list);
3939 trace_i915_gem_object_change_domain(obj,
3944 i915_verify_inactive(dev, __FILE__, __LINE__);
3947 for (i = 0; i < args->buffer_count; i++) {
3948 i915_gem_object_check_coherency(object_list[i],
3949 exec_list[i].handle);
3954 i915_gem_dump_object(batch_obj,
3960 /* Exec the batchbuffer */
3961 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3962 cliprects, exec_offset);
3964 DRM_ERROR("dispatch failed %d\n", ret);
3969 * Ensure that the commands in the batch buffer are
3970 * finished before the interrupt fires
3972 flush_domains = i915_retire_commands(dev, ring);
3974 i915_verify_inactive(dev, __FILE__, __LINE__);
3977 * Get a seqno representing the execution of the current buffer,
3978 * which we can wait on. We would like to mitigate these interrupts,
3979 * likely by only creating seqnos occasionally (so that we have
3980 * *some* interrupts representing completion of buffers that we can
3981 * wait on when trying to clear up gtt space).
3983 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3985 for (i = 0; i < args->buffer_count; i++) {
3986 struct drm_gem_object *obj = object_list[i];
3987 obj_priv = to_intel_bo(obj);
3989 i915_gem_object_move_to_active(obj, seqno, ring);
3991 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3995 i915_dump_lru(dev, __func__);
3998 i915_verify_inactive(dev, __FILE__, __LINE__);
4001 for (i = 0; i < pinned; i++)
4002 i915_gem_object_unpin(object_list[i]);
4004 for (i = 0; i < args->buffer_count; i++) {
4005 if (object_list[i]) {
4006 obj_priv = to_intel_bo(object_list[i]);
4007 obj_priv->in_execbuffer = false;
4009 drm_gem_object_unreference(object_list[i]);
4012 mutex_unlock(&dev->struct_mutex);
4015 /* Copy the updated relocations out regardless of current error
4016 * state. Failure to update the relocs would mean that the next
4017 * time userland calls execbuf, it would do so with presumed offset
4018 * state that didn't match the actual object state.
4020 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4023 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4029 drm_free_large(object_list);
4036 * Legacy execbuffer just creates an exec2 list from the original exec object
4037 * list array and passes it to the real function.
4040 i915_gem_execbuffer(struct drm_device *dev, void *data,
4041 struct drm_file *file_priv)
4043 struct drm_i915_gem_execbuffer *args = data;
4044 struct drm_i915_gem_execbuffer2 exec2;
4045 struct drm_i915_gem_exec_object *exec_list = NULL;
4046 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4050 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4051 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4054 if (args->buffer_count < 1) {
4055 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4059 /* Copy in the exec list from userland */
4060 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4061 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4062 if (exec_list == NULL || exec2_list == NULL) {
4063 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4064 args->buffer_count);
4065 drm_free_large(exec_list);
4066 drm_free_large(exec2_list);
4069 ret = copy_from_user(exec_list,
4070 (struct drm_i915_relocation_entry __user *)
4071 (uintptr_t) args->buffers_ptr,
4072 sizeof(*exec_list) * args->buffer_count);
4074 DRM_ERROR("copy %d exec entries failed %d\n",
4075 args->buffer_count, ret);
4076 drm_free_large(exec_list);
4077 drm_free_large(exec2_list);
4081 for (i = 0; i < args->buffer_count; i++) {
4082 exec2_list[i].handle = exec_list[i].handle;
4083 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4084 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4085 exec2_list[i].alignment = exec_list[i].alignment;
4086 exec2_list[i].offset = exec_list[i].offset;
4088 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4090 exec2_list[i].flags = 0;
4093 exec2.buffers_ptr = args->buffers_ptr;
4094 exec2.buffer_count = args->buffer_count;
4095 exec2.batch_start_offset = args->batch_start_offset;
4096 exec2.batch_len = args->batch_len;
4097 exec2.DR1 = args->DR1;
4098 exec2.DR4 = args->DR4;
4099 exec2.num_cliprects = args->num_cliprects;
4100 exec2.cliprects_ptr = args->cliprects_ptr;
4101 exec2.flags = I915_EXEC_RENDER;
4103 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4105 /* Copy the new buffer offsets back to the user's exec list. */
4106 for (i = 0; i < args->buffer_count; i++)
4107 exec_list[i].offset = exec2_list[i].offset;
4108 /* ... and back out to userspace */
4109 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4110 (uintptr_t) args->buffers_ptr,
4112 sizeof(*exec_list) * args->buffer_count);
4115 DRM_ERROR("failed to copy %d exec entries "
4116 "back to user (%d)\n",
4117 args->buffer_count, ret);
4121 drm_free_large(exec_list);
4122 drm_free_large(exec2_list);
4127 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4128 struct drm_file *file_priv)
4130 struct drm_i915_gem_execbuffer2 *args = data;
4131 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4135 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4136 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4139 if (args->buffer_count < 1) {
4140 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4144 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4145 if (exec2_list == NULL) {
4146 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4147 args->buffer_count);
4150 ret = copy_from_user(exec2_list,
4151 (struct drm_i915_relocation_entry __user *)
4152 (uintptr_t) args->buffers_ptr,
4153 sizeof(*exec2_list) * args->buffer_count);
4155 DRM_ERROR("copy %d exec entries failed %d\n",
4156 args->buffer_count, ret);
4157 drm_free_large(exec2_list);
4161 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4163 /* Copy the new buffer offsets back to the user's exec list. */
4164 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4165 (uintptr_t) args->buffers_ptr,
4167 sizeof(*exec2_list) * args->buffer_count);
4170 DRM_ERROR("failed to copy %d exec entries "
4171 "back to user (%d)\n",
4172 args->buffer_count, ret);
4176 drm_free_large(exec2_list);
4181 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4183 struct drm_device *dev = obj->dev;
4184 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4187 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4189 i915_verify_inactive(dev, __FILE__, __LINE__);
4191 if (obj_priv->gtt_space != NULL) {
4193 alignment = i915_gem_get_gtt_alignment(obj);
4194 if (obj_priv->gtt_offset & (alignment - 1)) {
4195 ret = i915_gem_object_unbind(obj);
4201 if (obj_priv->gtt_space == NULL) {
4202 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4207 obj_priv->pin_count++;
4209 /* If the object is not active and not pending a flush,
4210 * remove it from the inactive list
4212 if (obj_priv->pin_count == 1) {
4213 atomic_inc(&dev->pin_count);
4214 atomic_add(obj->size, &dev->pin_memory);
4215 if (!obj_priv->active &&
4216 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4217 !list_empty(&obj_priv->list))
4218 list_del_init(&obj_priv->list);
4220 i915_verify_inactive(dev, __FILE__, __LINE__);
4226 i915_gem_object_unpin(struct drm_gem_object *obj)
4228 struct drm_device *dev = obj->dev;
4229 drm_i915_private_t *dev_priv = dev->dev_private;
4230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4232 i915_verify_inactive(dev, __FILE__, __LINE__);
4233 obj_priv->pin_count--;
4234 BUG_ON(obj_priv->pin_count < 0);
4235 BUG_ON(obj_priv->gtt_space == NULL);
4237 /* If the object is no longer pinned, and is
4238 * neither active nor being flushed, then stick it on
4241 if (obj_priv->pin_count == 0) {
4242 if (!obj_priv->active &&
4243 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4244 list_move_tail(&obj_priv->list,
4245 &dev_priv->mm.inactive_list);
4246 atomic_dec(&dev->pin_count);
4247 atomic_sub(obj->size, &dev->pin_memory);
4249 i915_verify_inactive(dev, __FILE__, __LINE__);
4253 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4254 struct drm_file *file_priv)
4256 struct drm_i915_gem_pin *args = data;
4257 struct drm_gem_object *obj;
4258 struct drm_i915_gem_object *obj_priv;
4261 mutex_lock(&dev->struct_mutex);
4263 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4265 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4267 mutex_unlock(&dev->struct_mutex);
4270 obj_priv = to_intel_bo(obj);
4272 if (obj_priv->madv != I915_MADV_WILLNEED) {
4273 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4274 drm_gem_object_unreference(obj);
4275 mutex_unlock(&dev->struct_mutex);
4279 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4280 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4282 drm_gem_object_unreference(obj);
4283 mutex_unlock(&dev->struct_mutex);
4287 obj_priv->user_pin_count++;
4288 obj_priv->pin_filp = file_priv;
4289 if (obj_priv->user_pin_count == 1) {
4290 ret = i915_gem_object_pin(obj, args->alignment);
4292 drm_gem_object_unreference(obj);
4293 mutex_unlock(&dev->struct_mutex);
4298 /* XXX - flush the CPU caches for pinned objects
4299 * as the X server doesn't manage domains yet
4301 i915_gem_object_flush_cpu_write_domain(obj);
4302 args->offset = obj_priv->gtt_offset;
4303 drm_gem_object_unreference(obj);
4304 mutex_unlock(&dev->struct_mutex);
4310 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4311 struct drm_file *file_priv)
4313 struct drm_i915_gem_pin *args = data;
4314 struct drm_gem_object *obj;
4315 struct drm_i915_gem_object *obj_priv;
4317 mutex_lock(&dev->struct_mutex);
4319 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4321 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4323 mutex_unlock(&dev->struct_mutex);
4327 obj_priv = to_intel_bo(obj);
4328 if (obj_priv->pin_filp != file_priv) {
4329 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4331 drm_gem_object_unreference(obj);
4332 mutex_unlock(&dev->struct_mutex);
4335 obj_priv->user_pin_count--;
4336 if (obj_priv->user_pin_count == 0) {
4337 obj_priv->pin_filp = NULL;
4338 i915_gem_object_unpin(obj);
4341 drm_gem_object_unreference(obj);
4342 mutex_unlock(&dev->struct_mutex);
4347 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4348 struct drm_file *file_priv)
4350 struct drm_i915_gem_busy *args = data;
4351 struct drm_gem_object *obj;
4352 struct drm_i915_gem_object *obj_priv;
4354 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4356 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4361 mutex_lock(&dev->struct_mutex);
4362 /* Update the active list for the hardware's current position.
4363 * Otherwise this only updates on a delayed timer or when irqs are
4364 * actually unmasked, and our working set ends up being larger than
4367 i915_gem_retire_requests(dev);
4369 obj_priv = to_intel_bo(obj);
4370 /* Don't count being on the flushing list against the object being
4371 * done. Otherwise, a buffer left on the flushing list but not getting
4372 * flushed (because nobody's flushing that domain) won't ever return
4373 * unbusy and get reused by libdrm's bo cache. The other expected
4374 * consumer of this interface, OpenGL's occlusion queries, also specs
4375 * that the objects get unbusy "eventually" without any interference.
4377 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4379 drm_gem_object_unreference(obj);
4380 mutex_unlock(&dev->struct_mutex);
4385 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4386 struct drm_file *file_priv)
4388 return i915_gem_ring_throttle(dev, file_priv);
4392 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4393 struct drm_file *file_priv)
4395 struct drm_i915_gem_madvise *args = data;
4396 struct drm_gem_object *obj;
4397 struct drm_i915_gem_object *obj_priv;
4399 switch (args->madv) {
4400 case I915_MADV_DONTNEED:
4401 case I915_MADV_WILLNEED:
4407 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4409 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4414 mutex_lock(&dev->struct_mutex);
4415 obj_priv = to_intel_bo(obj);
4417 if (obj_priv->pin_count) {
4418 drm_gem_object_unreference(obj);
4419 mutex_unlock(&dev->struct_mutex);
4421 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4425 if (obj_priv->madv != __I915_MADV_PURGED)
4426 obj_priv->madv = args->madv;
4428 /* if the object is no longer bound, discard its backing storage */
4429 if (i915_gem_object_is_purgeable(obj_priv) &&
4430 obj_priv->gtt_space == NULL)
4431 i915_gem_object_truncate(obj);
4433 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4435 drm_gem_object_unreference(obj);
4436 mutex_unlock(&dev->struct_mutex);
4441 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4444 struct drm_i915_gem_object *obj;
4446 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4450 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4455 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4456 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4458 obj->agp_type = AGP_USER_MEMORY;
4459 obj->base.driver_private = NULL;
4460 obj->fence_reg = I915_FENCE_REG_NONE;
4461 INIT_LIST_HEAD(&obj->list);
4462 INIT_LIST_HEAD(&obj->gpu_write_list);
4463 obj->madv = I915_MADV_WILLNEED;
4465 trace_i915_gem_object_create(&obj->base);
4470 int i915_gem_init_object(struct drm_gem_object *obj)
4477 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4479 struct drm_device *dev = obj->dev;
4480 drm_i915_private_t *dev_priv = dev->dev_private;
4481 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4484 ret = i915_gem_object_unbind(obj);
4485 if (ret == -ERESTARTSYS) {
4486 list_move(&obj_priv->list,
4487 &dev_priv->mm.deferred_free_list);
4491 if (obj_priv->mmap_offset)
4492 i915_gem_free_mmap_offset(obj);
4494 drm_gem_object_release(obj);
4496 kfree(obj_priv->page_cpu_valid);
4497 kfree(obj_priv->bit_17);
4501 void i915_gem_free_object(struct drm_gem_object *obj)
4503 struct drm_device *dev = obj->dev;
4504 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4506 trace_i915_gem_object_destroy(obj);
4508 while (obj_priv->pin_count > 0)
4509 i915_gem_object_unpin(obj);
4511 if (obj_priv->phys_obj)
4512 i915_gem_detach_phys_object(dev, obj);
4514 i915_gem_free_object_tail(obj);
4517 /** Unbinds all inactive objects. */
4519 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4521 drm_i915_private_t *dev_priv = dev->dev_private;
4523 while (!list_empty(&dev_priv->mm.inactive_list)) {
4524 struct drm_gem_object *obj;
4527 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4528 struct drm_i915_gem_object,
4531 ret = i915_gem_object_unbind(obj);
4533 DRM_ERROR("Error unbinding object: %d\n", ret);
4542 i915_gem_idle(struct drm_device *dev)
4544 drm_i915_private_t *dev_priv = dev->dev_private;
4547 mutex_lock(&dev->struct_mutex);
4549 if (dev_priv->mm.suspended ||
4550 (dev_priv->render_ring.gem_object == NULL) ||
4552 dev_priv->bsd_ring.gem_object == NULL)) {
4553 mutex_unlock(&dev->struct_mutex);
4557 ret = i915_gpu_idle(dev);
4559 mutex_unlock(&dev->struct_mutex);
4563 /* Under UMS, be paranoid and evict. */
4564 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4565 ret = i915_gem_evict_from_inactive_list(dev);
4567 mutex_unlock(&dev->struct_mutex);
4572 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4573 * We need to replace this with a semaphore, or something.
4574 * And not confound mm.suspended!
4576 dev_priv->mm.suspended = 1;
4577 del_timer(&dev_priv->hangcheck_timer);
4579 i915_kernel_lost_context(dev);
4580 i915_gem_cleanup_ringbuffer(dev);
4582 mutex_unlock(&dev->struct_mutex);
4584 /* Cancel the retire work handler, which should be idle now. */
4585 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4591 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4592 * over cache flushing.
4595 i915_gem_init_pipe_control(struct drm_device *dev)
4597 drm_i915_private_t *dev_priv = dev->dev_private;
4598 struct drm_gem_object *obj;
4599 struct drm_i915_gem_object *obj_priv;
4602 obj = i915_gem_alloc_object(dev, 4096);
4604 DRM_ERROR("Failed to allocate seqno page\n");
4608 obj_priv = to_intel_bo(obj);
4609 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4611 ret = i915_gem_object_pin(obj, 4096);
4615 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4616 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4617 if (dev_priv->seqno_page == NULL)
4620 dev_priv->seqno_obj = obj;
4621 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4626 i915_gem_object_unpin(obj);
4628 drm_gem_object_unreference(obj);
4635 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4637 drm_i915_private_t *dev_priv = dev->dev_private;
4638 struct drm_gem_object *obj;
4639 struct drm_i915_gem_object *obj_priv;
4641 obj = dev_priv->seqno_obj;
4642 obj_priv = to_intel_bo(obj);
4643 kunmap(obj_priv->pages[0]);
4644 i915_gem_object_unpin(obj);
4645 drm_gem_object_unreference(obj);
4646 dev_priv->seqno_obj = NULL;
4648 dev_priv->seqno_page = NULL;
4652 i915_gem_init_ringbuffer(struct drm_device *dev)
4654 drm_i915_private_t *dev_priv = dev->dev_private;
4657 dev_priv->render_ring = render_ring;
4659 if (!I915_NEED_GFX_HWS(dev)) {
4660 dev_priv->render_ring.status_page.page_addr
4661 = dev_priv->status_page_dmah->vaddr;
4662 memset(dev_priv->render_ring.status_page.page_addr,
4666 if (HAS_PIPE_CONTROL(dev)) {
4667 ret = i915_gem_init_pipe_control(dev);
4672 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4674 goto cleanup_pipe_control;
4677 dev_priv->bsd_ring = bsd_ring;
4678 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4680 goto cleanup_render_ring;
4685 cleanup_render_ring:
4686 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4687 cleanup_pipe_control:
4688 if (HAS_PIPE_CONTROL(dev))
4689 i915_gem_cleanup_pipe_control(dev);
4694 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4696 drm_i915_private_t *dev_priv = dev->dev_private;
4698 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4700 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4701 if (HAS_PIPE_CONTROL(dev))
4702 i915_gem_cleanup_pipe_control(dev);
4706 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4707 struct drm_file *file_priv)
4709 drm_i915_private_t *dev_priv = dev->dev_private;
4712 if (drm_core_check_feature(dev, DRIVER_MODESET))
4715 if (atomic_read(&dev_priv->mm.wedged)) {
4716 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4717 atomic_set(&dev_priv->mm.wedged, 0);
4720 mutex_lock(&dev->struct_mutex);
4721 dev_priv->mm.suspended = 0;
4723 ret = i915_gem_init_ringbuffer(dev);
4725 mutex_unlock(&dev->struct_mutex);
4729 spin_lock(&dev_priv->mm.active_list_lock);
4730 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4731 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4732 spin_unlock(&dev_priv->mm.active_list_lock);
4734 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4735 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4736 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4737 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4738 mutex_unlock(&dev->struct_mutex);
4740 ret = drm_irq_install(dev);
4742 goto cleanup_ringbuffer;
4747 mutex_lock(&dev->struct_mutex);
4748 i915_gem_cleanup_ringbuffer(dev);
4749 dev_priv->mm.suspended = 1;
4750 mutex_unlock(&dev->struct_mutex);
4756 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4757 struct drm_file *file_priv)
4759 if (drm_core_check_feature(dev, DRIVER_MODESET))
4762 drm_irq_uninstall(dev);
4763 return i915_gem_idle(dev);
4767 i915_gem_lastclose(struct drm_device *dev)
4771 if (drm_core_check_feature(dev, DRIVER_MODESET))
4774 ret = i915_gem_idle(dev);
4776 DRM_ERROR("failed to idle hardware: %d\n", ret);
4780 i915_gem_load(struct drm_device *dev)
4783 drm_i915_private_t *dev_priv = dev->dev_private;
4785 spin_lock_init(&dev_priv->mm.active_list_lock);
4786 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4787 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4788 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4789 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4790 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4791 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4792 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4794 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4795 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4797 for (i = 0; i < 16; i++)
4798 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4799 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4800 i915_gem_retire_work_handler);
4801 spin_lock(&shrink_list_lock);
4802 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4803 spin_unlock(&shrink_list_lock);
4805 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4807 u32 tmp = I915_READ(MI_ARB_STATE);
4808 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4809 /* arb state is a masked write, so set bit + bit in mask */
4810 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4811 I915_WRITE(MI_ARB_STATE, tmp);
4815 /* Old X drivers will take 0-2 for front, back, depth buffers */
4816 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4817 dev_priv->fence_reg_start = 3;
4819 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4820 dev_priv->num_fence_regs = 16;
4822 dev_priv->num_fence_regs = 8;
4824 /* Initialize fence registers to zero */
4825 if (IS_I965G(dev)) {
4826 for (i = 0; i < 16; i++)
4827 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4829 for (i = 0; i < 8; i++)
4830 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4831 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4832 for (i = 0; i < 8; i++)
4833 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4835 i915_gem_detect_bit_6_swizzle(dev);
4836 init_waitqueue_head(&dev_priv->pending_flip_queue);
4840 * Create a physically contiguous memory object for this object
4841 * e.g. for cursor + overlay regs
4843 int i915_gem_init_phys_object(struct drm_device *dev,
4846 drm_i915_private_t *dev_priv = dev->dev_private;
4847 struct drm_i915_gem_phys_object *phys_obj;
4850 if (dev_priv->mm.phys_objs[id - 1] || !size)
4853 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4859 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4860 if (!phys_obj->handle) {
4865 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4868 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4876 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4878 drm_i915_private_t *dev_priv = dev->dev_private;
4879 struct drm_i915_gem_phys_object *phys_obj;
4881 if (!dev_priv->mm.phys_objs[id - 1])
4884 phys_obj = dev_priv->mm.phys_objs[id - 1];
4885 if (phys_obj->cur_obj) {
4886 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4890 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4892 drm_pci_free(dev, phys_obj->handle);
4894 dev_priv->mm.phys_objs[id - 1] = NULL;
4897 void i915_gem_free_all_phys_object(struct drm_device *dev)
4901 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4902 i915_gem_free_phys_object(dev, i);
4905 void i915_gem_detach_phys_object(struct drm_device *dev,
4906 struct drm_gem_object *obj)
4908 struct drm_i915_gem_object *obj_priv;
4913 obj_priv = to_intel_bo(obj);
4914 if (!obj_priv->phys_obj)
4917 ret = i915_gem_object_get_pages(obj, 0);
4921 page_count = obj->size / PAGE_SIZE;
4923 for (i = 0; i < page_count; i++) {
4924 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4925 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4927 memcpy(dst, src, PAGE_SIZE);
4928 kunmap_atomic(dst, KM_USER0);
4930 drm_clflush_pages(obj_priv->pages, page_count);
4931 drm_agp_chipset_flush(dev);
4933 i915_gem_object_put_pages(obj);
4935 obj_priv->phys_obj->cur_obj = NULL;
4936 obj_priv->phys_obj = NULL;
4940 i915_gem_attach_phys_object(struct drm_device *dev,
4941 struct drm_gem_object *obj, int id)
4943 drm_i915_private_t *dev_priv = dev->dev_private;
4944 struct drm_i915_gem_object *obj_priv;
4949 if (id > I915_MAX_PHYS_OBJECT)
4952 obj_priv = to_intel_bo(obj);
4954 if (obj_priv->phys_obj) {
4955 if (obj_priv->phys_obj->id == id)
4957 i915_gem_detach_phys_object(dev, obj);
4961 /* create a new object */
4962 if (!dev_priv->mm.phys_objs[id - 1]) {
4963 ret = i915_gem_init_phys_object(dev, id,
4966 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4971 /* bind to the object */
4972 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4973 obj_priv->phys_obj->cur_obj = obj;
4975 ret = i915_gem_object_get_pages(obj, 0);
4977 DRM_ERROR("failed to get page list\n");
4981 page_count = obj->size / PAGE_SIZE;
4983 for (i = 0; i < page_count; i++) {
4984 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4985 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4987 memcpy(dst, src, PAGE_SIZE);
4988 kunmap_atomic(src, KM_USER0);
4991 i915_gem_object_put_pages(obj);
4999 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5000 struct drm_i915_gem_pwrite *args,
5001 struct drm_file *file_priv)
5003 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5006 char __user *user_data;
5008 user_data = (char __user *) (uintptr_t) args->data_ptr;
5009 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5011 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5012 ret = copy_from_user(obj_addr, user_data, args->size);
5016 drm_agp_chipset_flush(dev);
5020 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5022 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5024 /* Clean up our request list when the client is going away, so that
5025 * later retire_requests won't dereference our soon-to-be-gone
5028 mutex_lock(&dev->struct_mutex);
5029 while (!list_empty(&i915_file_priv->mm.request_list))
5030 list_del_init(i915_file_priv->mm.request_list.next);
5031 mutex_unlock(&dev->struct_mutex);
5035 i915_gpu_is_active(struct drm_device *dev)
5037 drm_i915_private_t *dev_priv = dev->dev_private;
5040 spin_lock(&dev_priv->mm.active_list_lock);
5041 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
5042 list_empty(&dev_priv->render_ring.active_list);
5044 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
5045 spin_unlock(&dev_priv->mm.active_list_lock);
5047 return !lists_empty;
5051 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
5053 drm_i915_private_t *dev_priv, *next_dev;
5054 struct drm_i915_gem_object *obj_priv, *next_obj;
5056 int would_deadlock = 1;
5058 /* "fast-path" to count number of available objects */
5059 if (nr_to_scan == 0) {
5060 spin_lock(&shrink_list_lock);
5061 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5062 struct drm_device *dev = dev_priv->dev;
5064 if (mutex_trylock(&dev->struct_mutex)) {
5065 list_for_each_entry(obj_priv,
5066 &dev_priv->mm.inactive_list,
5069 mutex_unlock(&dev->struct_mutex);
5072 spin_unlock(&shrink_list_lock);
5074 return (cnt / 100) * sysctl_vfs_cache_pressure;
5077 spin_lock(&shrink_list_lock);
5080 /* first scan for clean buffers */
5081 list_for_each_entry_safe(dev_priv, next_dev,
5082 &shrink_list, mm.shrink_list) {
5083 struct drm_device *dev = dev_priv->dev;
5085 if (! mutex_trylock(&dev->struct_mutex))
5088 spin_unlock(&shrink_list_lock);
5089 i915_gem_retire_requests(dev);
5091 list_for_each_entry_safe(obj_priv, next_obj,
5092 &dev_priv->mm.inactive_list,
5094 if (i915_gem_object_is_purgeable(obj_priv)) {
5095 i915_gem_object_unbind(&obj_priv->base);
5096 if (--nr_to_scan <= 0)
5101 spin_lock(&shrink_list_lock);
5102 mutex_unlock(&dev->struct_mutex);
5106 if (nr_to_scan <= 0)
5110 /* second pass, evict/count anything still on the inactive list */
5111 list_for_each_entry_safe(dev_priv, next_dev,
5112 &shrink_list, mm.shrink_list) {
5113 struct drm_device *dev = dev_priv->dev;
5115 if (! mutex_trylock(&dev->struct_mutex))
5118 spin_unlock(&shrink_list_lock);
5120 list_for_each_entry_safe(obj_priv, next_obj,
5121 &dev_priv->mm.inactive_list,
5123 if (nr_to_scan > 0) {
5124 i915_gem_object_unbind(&obj_priv->base);
5130 spin_lock(&shrink_list_lock);
5131 mutex_unlock(&dev->struct_mutex);
5140 * We are desperate for pages, so as a last resort, wait
5141 * for the GPU to finish and discard whatever we can.
5142 * This has a dramatic impact to reduce the number of
5143 * OOM-killer events whilst running the GPU aggressively.
5145 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5146 struct drm_device *dev = dev_priv->dev;
5148 if (!mutex_trylock(&dev->struct_mutex))
5151 spin_unlock(&shrink_list_lock);
5153 if (i915_gpu_is_active(dev)) {
5158 spin_lock(&shrink_list_lock);
5159 mutex_unlock(&dev->struct_mutex);
5166 spin_unlock(&shrink_list_lock);
5171 return (cnt / 100) * sysctl_vfs_cache_pressure;
5176 static struct shrinker shrinker = {
5177 .shrink = i915_gem_shrink,
5178 .seeks = DEFAULT_SEEKS,
5182 i915_gem_shrinker_init(void)
5184 register_shrinker(&shrinker);
5188 i915_gem_shrinker_exit(void)
5190 unregister_shrinker(&shrinker);