drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct drm_device *dev)
  91 {
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93         struct completion *x = &dev_priv->error_completion;
  94         unsigned long flags;
  95         int ret;
  96
  97         if (!atomic_read(&dev_priv->mm.wedged))
  98                 return 0;
  99
 100         /*
 101          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 102          * userspace. If it takes that long something really bad is going on and
 103          * we should simply try to bail out and fail as gracefully as possible.
 104          */
 105         ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
 106         if (ret == 0) {
 107                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 108                 return -EIO;
 109         } else if (ret < 0) {
 110                 return ret;
 111         }
 112
 113         if (atomic_read(&dev_priv->mm.wedged)) {
 114                 /* GPU is hung, bump the completion count to account for
 115                  * the token we just consumed so that we never hit zero and
 116                  * end up waiting upon a subsequent completion event that
 117                  * will never happen.
 118                  */
 119                 spin_lock_irqsave(&x->wait.lock, flags);
 120                 x->done++;
 121                 spin_unlock_irqrestore(&x->wait.lock, flags);
 122         }
 123         return 0;
 124 }
 125
 126 int i915_mutex_lock_interruptible(struct drm_device *dev)
 127 {
 128         int ret;
 129
 130         ret = i915_gem_wait_for_error(dev);
 131         if (ret)
 132                 return ret;
 133
 134         ret = mutex_lock_interruptible(&dev->struct_mutex);
 135         if (ret)
 136                 return ret;
 137
 138         WARN_ON(i915_verify_lists(dev));
 139         return 0;
 140 }
 141
 142 static inline bool
 143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 144 {
 145         return obj->gtt_space && !obj->active;
 146 }
 147
 148 int
 149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 150                     struct drm_file *file)
 151 {
 152         struct drm_i915_gem_init *args = data;
 153
 154         if (drm_core_check_feature(dev, DRIVER_MODESET))
 155                 return -ENODEV;
 156
 157         if (args->gtt_start >= args->gtt_end ||
 158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 159                 return -EINVAL;
 160
 161         /* GEM with user mode setting was never supported on ilk and later. */
 162         if (INTEL_INFO(dev)->gen >= 5)
 163                 return -ENODEV;
 164
 165         mutex_lock(&dev->struct_mutex);
 166         i915_gem_init_global_gtt(dev, args->gtt_start,
 167                                  args->gtt_end, args->gtt_end);
 168         mutex_unlock(&dev->struct_mutex);
 169
 170         return 0;
 171 }
 172
 173 int
 174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 175                             struct drm_file *file)
 176 {
 177         struct drm_i915_private *dev_priv = dev->dev_private;
 178         struct drm_i915_gem_get_aperture *args = data;
 179         struct drm_i915_gem_object *obj;
 180         size_t pinned;
 181
 182         pinned = 0;
 183         mutex_lock(&dev->struct_mutex);
 184         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
 185                 if (obj->pin_count)
 186                         pinned += obj->gtt_space->size;
 187         mutex_unlock(&dev->struct_mutex);
 188
 189         args->aper_size = dev_priv->mm.gtt_total;
 190         args->aper_available_size = args->aper_size - pinned;
 191
 192         return 0;
 193 }
 194
 195 static int
 196 i915_gem_create(struct drm_file *file,
 197                 struct drm_device *dev,
 198                 uint64_t size,
 199                 uint32_t *handle_p)
 200 {
 201         struct drm_i915_gem_object *obj;
 202         int ret;
 203         u32 handle;
 204
 205         size = roundup(size, PAGE_SIZE);
 206         if (size == 0)
 207                 return -EINVAL;
 208
 209         /* Allocate the new object */
 210         obj = i915_gem_alloc_object(dev, size);
 211         if (obj == NULL)
 212                 return -ENOMEM;
 213
 214         ret = drm_gem_handle_create(file, &obj->base, &handle);
 215         if (ret) {
 216                 drm_gem_object_release(&obj->base);
 217                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 218                 kfree(obj);
 219                 return ret;
 220         }
 221
 222         /* drop reference from allocate - handle holds it now */
 223         drm_gem_object_unreference(&obj->base);
 224         trace_i915_gem_object_create(obj);
 225
 226         *handle_p = handle;
 227         return 0;
 228 }
 229
 230 int
 231 i915_gem_dumb_create(struct drm_file *file,
 232                      struct drm_device *dev,
 233                      struct drm_mode_create_dumb *args)
 234 {
 235         /* have to work out size/pitch and return them */
 236         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 237         args->size = args->pitch * args->height;
 238         return i915_gem_create(file, dev,
 239                                args->size, &args->handle);
 240 }
 241
 242 int i915_gem_dumb_destroy(struct drm_file *file,
 243                           struct drm_device *dev,
 244                           uint32_t handle)
 245 {
 246         return drm_gem_handle_delete(file, handle);
 247 }
 248
 249 /**
 250  * Creates a new mm object and returns a handle to it.
 251  */
 252 int
 253 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 254                       struct drm_file *file)
 255 {
 256         struct drm_i915_gem_create *args = data;
 257
 258         return i915_gem_create(file, dev,
 259                                args->size, &args->handle);
 260 }
 261
 262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 263 {
 264         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 265
 266         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 267                 obj->tiling_mode != I915_TILING_NONE;
 268 }
 269
 270 static inline int
 271 __copy_to_user_swizzled(char __user *cpu_vaddr,
 272                         const char *gpu_vaddr, int gpu_offset,
 273                         int length)
 274 {
 275         int ret, cpu_offset = 0;
 276
 277         while (length > 0) {
 278                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 279                 int this_length = min(cacheline_end - gpu_offset, length);
 280                 int swizzled_gpu_offset = gpu_offset ^ 64;
 281
 282                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 283                                      gpu_vaddr + swizzled_gpu_offset,
 284                                      this_length);
 285                 if (ret)
 286                         return ret + length;
 287
 288                 cpu_offset += this_length;
 289                 gpu_offset += this_length;
 290                 length -= this_length;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static inline int
 297 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 298                           const char __user *cpu_vaddr,
 299                           int length)
 300 {
 301         int ret, cpu_offset = 0;
 302
 303         while (length > 0) {
 304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 305                 int this_length = min(cacheline_end - gpu_offset, length);
 306                 int swizzled_gpu_offset = gpu_offset ^ 64;
 307
 308                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 309                                        cpu_vaddr + cpu_offset,
 310                                        this_length);
 311                 if (ret)
 312                         return ret + length;
 313
 314                 cpu_offset += this_length;
 315                 gpu_offset += this_length;
 316                 length -= this_length;
 317         }
 318
 319         return 0;
 320 }
 321
 322 /* Per-page copy function for the shmem pread fastpath.
 323  * Flushes invalid cachelines before reading the target if
 324  * needs_clflush is set. */
 325 static int
 326 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 327                  char __user *user_data,
 328                  bool page_do_bit17_swizzling, bool needs_clflush)
 329 {
 330         char *vaddr;
 331         int ret;
 332
 333         if (unlikely(page_do_bit17_swizzling))
 334                 return -EINVAL;
 335
 336         vaddr = kmap_atomic(page);
 337         if (needs_clflush)
 338                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 339                                        page_length);
 340         ret = __copy_to_user_inatomic(user_data,
 341                                       vaddr + shmem_page_offset,
 342                                       page_length);
 343         kunmap_atomic(vaddr);
 344
 345         return ret ? -EFAULT : 0;
 346 }
 347
 348 static void
 349 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 350                              bool swizzled)
 351 {
 352         if (unlikely(swizzled)) {
 353                 unsigned long start = (unsigned long) addr;
 354                 unsigned long end = (unsigned long) addr + length;
 355
 356                 /* For swizzling simply ensure that we always flush both
 357                  * channels. Lame, but simple and it works. Swizzled
 358                  * pwrite/pread is far from a hotpath - current userspace
 359                  * doesn't use it at all. */
 360                 start = round_down(start, 128);
 361                 end = round_up(end, 128);
 362
 363                 drm_clflush_virt_range((void *)start, end - start);
 364         } else {
 365                 drm_clflush_virt_range(addr, length);
 366         }
 367
 368 }
 369
 370 /* Only difference to the fast-path function is that this can handle bit17
 371  * and uses non-atomic copy and kmap functions. */
 372 static int
 373 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 374                  char __user *user_data,
 375                  bool page_do_bit17_swizzling, bool needs_clflush)
 376 {
 377         char *vaddr;
 378         int ret;
 379
 380         vaddr = kmap(page);
 381         if (needs_clflush)
 382                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 383                                              page_length,
 384                                              page_do_bit17_swizzling);
 385
 386         if (page_do_bit17_swizzling)
 387                 ret = __copy_to_user_swizzled(user_data,
 388                                               vaddr, shmem_page_offset,
 389                                               page_length);
 390         else
 391                 ret = __copy_to_user(user_data,
 392                                      vaddr + shmem_page_offset,
 393                                      page_length);
 394         kunmap(page);
 395
 396         return ret ? - EFAULT : 0;
 397 }
 398
 399 static int
 400 i915_gem_shmem_pread(struct drm_device *dev,
 401                      struct drm_i915_gem_object *obj,
 402                      struct drm_i915_gem_pread *args,
 403                      struct drm_file *file)
 404 {
 405         char __user *user_data;
 406         ssize_t remain;
 407         loff_t offset;
 408         int shmem_page_offset, page_length, ret = 0;
 409         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 410         int hit_slowpath = 0;
 411         int prefaulted = 0;
 412         int needs_clflush = 0;
 413         struct scatterlist *sg;
 414         int i;
 415
 416         user_data = (char __user *) (uintptr_t) args->data_ptr;
 417         remain = args->size;
 418
 419         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 420
 421         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 422                 /* If we're not in the cpu read domain, set ourself into the gtt
 423                  * read domain and manually flush cachelines (if required). This
 424                  * optimizes for the case when the gpu will dirty the data
 425                  * anyway again before the next pread happens. */
 426                 if (obj->cache_level == I915_CACHE_NONE)
 427                         needs_clflush = 1;
 428                 if (obj->gtt_space) {
 429                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 430                         if (ret)
 431                                 return ret;
 432                 }
 433         }
 434
 435         ret = i915_gem_object_get_pages(obj);
 436         if (ret)
 437                 return ret;
 438
 439         i915_gem_object_pin_pages(obj);
 440
 441         offset = args->offset;
 442
 443         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 444                 struct page *page;
 445
 446                 if (i < offset >> PAGE_SHIFT)
 447                         continue;
 448
 449                 if (remain <= 0)
 450                         break;
 451
 452                 /* Operation in this page
 453                  *
 454                  * shmem_page_offset = offset within page in shmem file
 455                  * page_length = bytes to copy for this page
 456                  */
 457                 shmem_page_offset = offset_in_page(offset);
 458                 page_length = remain;
 459                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 460                         page_length = PAGE_SIZE - shmem_page_offset;
 461
 462                 page = sg_page(sg);
 463                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 464                         (page_to_phys(page) & (1 << 17)) != 0;
 465
 466                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 467                                        user_data, page_do_bit17_swizzling,
 468                                        needs_clflush);
 469                 if (ret == 0)
 470                         goto next_page;
 471
 472                 hit_slowpath = 1;
 473                 mutex_unlock(&dev->struct_mutex);
 474
 475                 if (!prefaulted) {
 476                         ret = fault_in_multipages_writeable(user_data, remain);
 477                         /* Userspace is tricking us, but we've already clobbered
 478                          * its pages with the prefault and promised to write the
 479                          * data up to the first fault. Hence ignore any errors
 480                          * and just continue. */
 481                         (void)ret;
 482                         prefaulted = 1;
 483                 }
 484
 485                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 486                                        user_data, page_do_bit17_swizzling,
 487                                        needs_clflush);
 488
 489                 mutex_lock(&dev->struct_mutex);
 490
 491 next_page:
 492                 mark_page_accessed(page);
 493
 494                 if (ret)
 495                         goto out;
 496
 497                 remain -= page_length;
 498                 user_data += page_length;
 499                 offset += page_length;
 500         }
 501
 502 out:
 503         i915_gem_object_unpin_pages(obj);
 504
 505         if (hit_slowpath) {
 506                 /* Fixup: Kill any reinstated backing storage pages */
 507                 if (obj->madv == __I915_MADV_PURGED)
 508                         i915_gem_object_truncate(obj);
 509         }
 510
 511         return ret;
 512 }
 513
 514 /**
 515  * Reads data from the object referenced by handle.
 516  *
 517  * On error, the contents of *data are undefined.
 518  */
 519 int
 520 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 521                      struct drm_file *file)
 522 {
 523         struct drm_i915_gem_pread *args = data;
 524         struct drm_i915_gem_object *obj;
 525         int ret = 0;
 526
 527         if (args->size == 0)
 528                 return 0;
 529
 530         if (!access_ok(VERIFY_WRITE,
 531                        (char __user *)(uintptr_t)args->data_ptr,
 532                        args->size))
 533                 return -EFAULT;
 534
 535         ret = i915_mutex_lock_interruptible(dev);
 536         if (ret)
 537                 return ret;
 538
 539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 540         if (&obj->base == NULL) {
 541                 ret = -ENOENT;
 542                 goto unlock;
 543         }
 544
 545         /* Bounds check source.  */
 546         if (args->offset > obj->base.size ||
 547             args->size > obj->base.size - args->offset) {
 548                 ret = -EINVAL;
 549                 goto out;
 550         }
 551
 552         /* prime objects have no backing filp to GEM pread/pwrite
 553          * pages from.
 554          */
 555         if (!obj->base.filp) {
 556                 ret = -EINVAL;
 557                 goto out;
 558         }
 559
 560         trace_i915_gem_object_pread(obj, args->offset, args->size);
 561
 562         ret = i915_gem_shmem_pread(dev, obj, args, file);
 563
 564 out:
 565         drm_gem_object_unreference(&obj->base);
 566 unlock:
 567         mutex_unlock(&dev->struct_mutex);
 568         return ret;
 569 }
 570
 571 /* This is the fast write path which cannot handle
 572  * page faults in the source data
 573  */
 574
 575 static inline int
 576 fast_user_write(struct io_mapping *mapping,
 577                 loff_t page_base, int page_offset,
 578                 char __user *user_data,
 579                 int length)
 580 {
 581         void __iomem *vaddr_atomic;
 582         void *vaddr;
 583         unsigned long unwritten;
 584
 585         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 586         /* We can use the cpu mem copy function because this is X86. */
 587         vaddr = (void __force*)vaddr_atomic + page_offset;
 588         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 589                                                       user_data, length);
 590         io_mapping_unmap_atomic(vaddr_atomic);
 591         return unwritten;
 592 }
 593
 594 /**
 595  * This is the fast pwrite path, where we copy the data directly from the
 596  * user into the GTT, uncached.
 597  */
 598 static int
 599 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 600                          struct drm_i915_gem_object *obj,
 601                          struct drm_i915_gem_pwrite *args,
 602                          struct drm_file *file)
 603 {
 604         drm_i915_private_t *dev_priv = dev->dev_private;
 605         ssize_t remain;
 606         loff_t offset, page_base;
 607         char __user *user_data;
 608         int page_offset, page_length, ret;
 609
 610         ret = i915_gem_object_pin(obj, 0, true, true);
 611         if (ret)
 612                 goto out;
 613
 614         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 615         if (ret)
 616                 goto out_unpin;
 617
 618         ret = i915_gem_object_put_fence(obj);
 619         if (ret)
 620                 goto out_unpin;
 621
 622         user_data = (char __user *) (uintptr_t) args->data_ptr;
 623         remain = args->size;
 624
 625         offset = obj->gtt_offset + args->offset;
 626
 627         while (remain > 0) {
 628                 /* Operation in this page
 629                  *
 630                  * page_base = page offset within aperture
 631                  * page_offset = offset within page
 632                  * page_length = bytes to copy for this page
 633                  */
 634                 page_base = offset & PAGE_MASK;
 635                 page_offset = offset_in_page(offset);
 636                 page_length = remain;
 637                 if ((page_offset + remain) > PAGE_SIZE)
 638                         page_length = PAGE_SIZE - page_offset;
 639
 640                 /* If we get a fault while copying data, then (presumably) our
 641                  * source page isn't available.  Return the error and we'll
 642                  * retry in the slow path.
 643                  */
 644                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 645                                     page_offset, user_data, page_length)) {
 646                         ret = -EFAULT;
 647                         goto out_unpin;
 648                 }
 649
 650                 remain -= page_length;
 651                 user_data += page_length;
 652                 offset += page_length;
 653         }
 654
 655 out_unpin:
 656         i915_gem_object_unpin(obj);
 657 out:
 658         return ret;
 659 }
 660
 661 /* Per-page copy function for the shmem pwrite fastpath.
 662  * Flushes invalid cachelines before writing to the target if
 663  * needs_clflush_before is set and flushes out any written cachelines after
 664  * writing if needs_clflush is set. */
 665 static int
 666 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 667                   char __user *user_data,
 668                   bool page_do_bit17_swizzling,
 669                   bool needs_clflush_before,
 670                   bool needs_clflush_after)
 671 {
 672         char *vaddr;
 673         int ret;
 674
 675         if (unlikely(page_do_bit17_swizzling))
 676                 return -EINVAL;
 677
 678         vaddr = kmap_atomic(page);
 679         if (needs_clflush_before)
 680                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 681                                        page_length);
 682         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 683                                                 user_data,
 684                                                 page_length);
 685         if (needs_clflush_after)
 686                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 687                                        page_length);
 688         kunmap_atomic(vaddr);
 689
 690         return ret ? -EFAULT : 0;
 691 }
 692
 693 /* Only difference to the fast-path function is that this can handle bit17
 694  * and uses non-atomic copy and kmap functions. */
 695 static int
 696 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 697                   char __user *user_data,
 698                   bool page_do_bit17_swizzling,
 699                   bool needs_clflush_before,
 700                   bool needs_clflush_after)
 701 {
 702         char *vaddr;
 703         int ret;
 704
 705         vaddr = kmap(page);
 706         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 707                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 708                                              page_length,
 709                                              page_do_bit17_swizzling);
 710         if (page_do_bit17_swizzling)
 711                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 712                                                 user_data,
 713                                                 page_length);
 714         else
 715                 ret = __copy_from_user(vaddr + shmem_page_offset,
 716                                        user_data,
 717                                        page_length);
 718         if (needs_clflush_after)
 719                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 720                                              page_length,
 721                                              page_do_bit17_swizzling);
 722         kunmap(page);
 723
 724         return ret ? -EFAULT : 0;
 725 }
 726
 727 static int
 728 i915_gem_shmem_pwrite(struct drm_device *dev,
 729                       struct drm_i915_gem_object *obj,
 730                       struct drm_i915_gem_pwrite *args,
 731                       struct drm_file *file)
 732 {
 733         ssize_t remain;
 734         loff_t offset;
 735         char __user *user_data;
 736         int shmem_page_offset, page_length, ret = 0;
 737         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 738         int hit_slowpath = 0;
 739         int needs_clflush_after = 0;
 740         int needs_clflush_before = 0;
 741         int i;
 742         struct scatterlist *sg;
 743
 744         user_data = (char __user *) (uintptr_t) args->data_ptr;
 745         remain = args->size;
 746
 747         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 748
 749         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 750                 /* If we're not in the cpu write domain, set ourself into the gtt
 751                  * write domain and manually flush cachelines (if required). This
 752                  * optimizes for the case when the gpu will use the data
 753                  * right away and we therefore have to clflush anyway. */
 754                 if (obj->cache_level == I915_CACHE_NONE)
 755                         needs_clflush_after = 1;
 756                 if (obj->gtt_space) {
 757                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 758                         if (ret)
 759                                 return ret;
 760                 }
 761         }
 762         /* Same trick applies for invalidate partially written cachelines before
 763          * writing.  */
 764         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 765             && obj->cache_level == I915_CACHE_NONE)
 766                 needs_clflush_before = 1;
 767
 768         ret = i915_gem_object_get_pages(obj);
 769         if (ret)
 770                 return ret;
 771
 772         i915_gem_object_pin_pages(obj);
 773
 774         offset = args->offset;
 775         obj->dirty = 1;
 776
 777         for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
 778                 struct page *page;
 779                 int partial_cacheline_write;
 780
 781                 if (i < offset >> PAGE_SHIFT)
 782                         continue;
 783
 784                 if (remain <= 0)
 785                         break;
 786
 787                 /* Operation in this page
 788                  *
 789                  * shmem_page_offset = offset within page in shmem file
 790                  * page_length = bytes to copy for this page
 791                  */
 792                 shmem_page_offset = offset_in_page(offset);
 793
 794                 page_length = remain;
 795                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 796                         page_length = PAGE_SIZE - shmem_page_offset;
 797
 798                 /* If we don't overwrite a cacheline completely we need to be
 799                  * careful to have up-to-date data by first clflushing. Don't
 800                  * overcomplicate things and flush the entire patch. */
 801                 partial_cacheline_write = needs_clflush_before &&
 802                         ((shmem_page_offset | page_length)
 803                                 & (boot_cpu_data.x86_clflush_size - 1));
 804
 805                 page = sg_page(sg);
 806                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 807                         (page_to_phys(page) & (1 << 17)) != 0;
 808
 809                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 810                                         user_data, page_do_bit17_swizzling,
 811                                         partial_cacheline_write,
 812                                         needs_clflush_after);
 813                 if (ret == 0)
 814                         goto next_page;
 815
 816                 hit_slowpath = 1;
 817                 mutex_unlock(&dev->struct_mutex);
 818                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 819                                         user_data, page_do_bit17_swizzling,
 820                                         partial_cacheline_write,
 821                                         needs_clflush_after);
 822
 823                 mutex_lock(&dev->struct_mutex);
 824
 825 next_page:
 826                 set_page_dirty(page);
 827                 mark_page_accessed(page);
 828
 829                 if (ret)
 830                         goto out;
 831
 832                 remain -= page_length;
 833                 user_data += page_length;
 834                 offset += page_length;
 835         }
 836
 837 out:
 838         i915_gem_object_unpin_pages(obj);
 839
 840         if (hit_slowpath) {
 841                 /* Fixup: Kill any reinstated backing storage pages */
 842                 if (obj->madv == __I915_MADV_PURGED)
 843                         i915_gem_object_truncate(obj);
 844                 /* and flush dirty cachelines in case the object isn't in the cpu write
 845                  * domain anymore. */
 846                 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 847                         i915_gem_clflush_object(obj);
 848                         i915_gem_chipset_flush(dev);
 849                 }
 850         }
 851
 852         if (needs_clflush_after)
 853                 i915_gem_chipset_flush(dev);
 854
 855         return ret;
 856 }
 857
 858 /**
 859  * Writes data to the object referenced by handle.
 860  *
 861  * On error, the contents of the buffer that were to be modified are undefined.
 862  */
 863 int
 864 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 865                       struct drm_file *file)
 866 {
 867         struct drm_i915_gem_pwrite *args = data;
 868         struct drm_i915_gem_object *obj;
 869         int ret;
 870
 871         if (args->size == 0)
 872                 return 0;
 873
 874         if (!access_ok(VERIFY_READ,
 875                        (char __user *)(uintptr_t)args->data_ptr,
 876                        args->size))
 877                 return -EFAULT;
 878
 879         ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
 880                                            args->size);
 881         if (ret)
 882                 return -EFAULT;
 883
 884         ret = i915_mutex_lock_interruptible(dev);
 885         if (ret)
 886                 return ret;
 887
 888         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 889         if (&obj->base == NULL) {
 890                 ret = -ENOENT;
 891                 goto unlock;
 892         }
 893
 894         /* Bounds check destination. */
 895         if (args->offset > obj->base.size ||
 896             args->size > obj->base.size - args->offset) {
 897                 ret = -EINVAL;
 898                 goto out;
 899         }
 900
 901         /* prime objects have no backing filp to GEM pread/pwrite
 902          * pages from.
 903          */
 904         if (!obj->base.filp) {
 905                 ret = -EINVAL;
 906                 goto out;
 907         }
 908
 909         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 910
 911         ret = -EFAULT;
 912         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 913          * it would end up going through the fenced access, and we'll get
 914          * different detiling behavior between reading and writing.
 915          * pread/pwrite currently are reading and writing from the CPU
 916          * perspective, requiring manual detiling by the client.
 917          */
 918         if (obj->phys_obj) {
 919                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 920                 goto out;
 921         }
 922
 923         if (obj->cache_level == I915_CACHE_NONE &&
 924             obj->tiling_mode == I915_TILING_NONE &&
 925             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 926                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 927                 /* Note that the gtt paths might fail with non-page-backed user
 928                  * pointers (e.g. gtt mappings when moving data between
 929                  * textures). Fallback to the shmem path in that case. */
 930         }
 931
 932         if (ret == -EFAULT || ret == -ENOSPC)
 933                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 934
 935 out:
 936         drm_gem_object_unreference(&obj->base);
 937 unlock:
 938         mutex_unlock(&dev->struct_mutex);
 939         return ret;
 940 }
 941
 942 int
 943 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
 944                      bool interruptible)
 945 {
 946         if (atomic_read(&dev_priv->mm.wedged)) {
 947                 struct completion *x = &dev_priv->error_completion;
 948                 bool recovery_complete;
 949                 unsigned long flags;
 950
 951                 /* Give the error handler a chance to run. */
 952                 spin_lock_irqsave(&x->wait.lock, flags);
 953                 recovery_complete = x->done > 0;
 954                 spin_unlock_irqrestore(&x->wait.lock, flags);
 955
 956                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 957                  * -EIO unconditionally for these. */
 958                 if (!interruptible)
 959                         return -EIO;
 960
 961                 /* Recovery complete, but still wedged means reset failure. */
 962                 if (recovery_complete)
 963                         return -EIO;
 964
 965                 return -EAGAIN;
 966         }
 967
 968         return 0;
 969 }
 970
 971 /*
 972  * Compare seqno against outstanding lazy request. Emit a request if they are
 973  * equal.
 974  */
 975 static int
 976 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 977 {
 978         int ret;
 979
 980         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 981
 982         ret = 0;
 983         if (seqno == ring->outstanding_lazy_request)
 984                 ret = i915_add_request(ring, NULL, NULL);
 985
 986         return ret;
 987 }
 988
 989 /**
 990  * __wait_seqno - wait until execution of seqno has finished
 991  * @ring: the ring expected to report seqno
 992  * @seqno: duh!
 993  * @interruptible: do an interruptible wait (normally yes)
 994  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 995  *
 996  * Returns 0 if the seqno was found within the alloted time. Else returns the
 997  * errno with remaining time filled in timeout argument.
 998  */
 999 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1000                         bool interruptible, struct timespec *timeout)
1001 {
1002         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1003         struct timespec before, now, wait_time={1,0};
1004         unsigned long timeout_jiffies;
1005         long end;
1006         bool wait_forever = true;
1007         int ret;
1008
1009         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1010                 return 0;
1011
1012         trace_i915_gem_request_wait_begin(ring, seqno);
1013
1014         if (timeout != NULL) {
1015                 wait_time = *timeout;
1016                 wait_forever = false;
1017         }
1018
1019         timeout_jiffies = timespec_to_jiffies(&wait_time);
1020
1021         if (WARN_ON(!ring->irq_get(ring)))
1022                 return -ENODEV;
1023
1024         /* Record current time in case interrupted by signal, or wedged * */
1025         getrawmonotonic(&before);
1026
1027 #define EXIT_COND \
1028         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029         atomic_read(&dev_priv->mm.wedged))
1030         do {
1031                 if (interruptible)
1032                         end = wait_event_interruptible_timeout(ring->irq_queue,
1033                                                                EXIT_COND,
1034                                                                timeout_jiffies);
1035                 else
1036                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1037                                                  timeout_jiffies);
1038
1039                 ret = i915_gem_check_wedge(dev_priv, interruptible);
1040                 if (ret)
1041                         end = ret;
1042         } while (end == 0 && wait_forever);
1043
1044         getrawmonotonic(&now);
1045
1046         ring->irq_put(ring);
1047         trace_i915_gem_request_wait_end(ring, seqno);
1048 #undef EXIT_COND
1049
1050         if (timeout) {
1051                 struct timespec sleep_time = timespec_sub(now, before);
1052                 *timeout = timespec_sub(*timeout, sleep_time);
1053         }
1054
1055         switch (end) {
1056         case -EIO:
1057         case -EAGAIN: /* Wedged */
1058         case -ERESTARTSYS: /* Signal */
1059                 return (int)end;
1060         case 0: /* Timeout */
1061                 if (timeout)
1062                         set_normalized_timespec(timeout, 0, 0);
1063                 return -ETIME;
1064         default: /* Completed */
1065                 WARN_ON(end < 0); /* We're not aware of other errors */
1066                 return 0;
1067         }
1068 }
1069
1070 /**
1071  * Waits for a sequence number to be signaled, and cleans up the
1072  * request and object lists appropriately for that event.
1073  */
1074 int
1075 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1076 {
1077         struct drm_device *dev = ring->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         bool interruptible = dev_priv->mm.interruptible;
1080         int ret;
1081
1082         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1083         BUG_ON(seqno == 0);
1084
1085         ret = i915_gem_check_wedge(dev_priv, interruptible);
1086         if (ret)
1087                 return ret;
1088
1089         ret = i915_gem_check_olr(ring, seqno);
1090         if (ret)
1091                 return ret;
1092
1093         return __wait_seqno(ring, seqno, interruptible, NULL);
1094 }
1095
1096 /**
1097  * Ensures that all rendering to the object has completed and the object is
1098  * safe to unbind from the GTT or access from the CPU.
1099  */
1100 static __must_check int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1102                                bool readonly)
1103 {
1104         struct intel_ring_buffer *ring = obj->ring;
1105         u32 seqno;
1106         int ret;
1107
1108         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109         if (seqno == 0)
1110                 return 0;
1111
1112         ret = i915_wait_seqno(ring, seqno);
1113         if (ret)
1114                 return ret;
1115
1116         i915_gem_retire_requests_ring(ring);
1117
1118         /* Manually manage the write flush as we may have not yet
1119          * retired the buffer.
1120          */
1121         if (obj->last_write_seqno &&
1122             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1123                 obj->last_write_seqno = 0;
1124                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1125         }
1126
1127         return 0;
1128 }
1129
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131  * as the object state may change during this call.
1132  */
1133 static __must_check int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1135                                             bool readonly)
1136 {
1137         struct drm_device *dev = obj->base.dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct intel_ring_buffer *ring = obj->ring;
1140         u32 seqno;
1141         int ret;
1142
1143         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1144         BUG_ON(!dev_priv->mm.interruptible);
1145
1146         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147         if (seqno == 0)
1148                 return 0;
1149
1150         ret = i915_gem_check_wedge(dev_priv, true);
1151         if (ret)
1152                 return ret;
1153
1154         ret = i915_gem_check_olr(ring, seqno);
1155         if (ret)
1156                 return ret;
1157
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161
1162         i915_gem_retire_requests_ring(ring);
1163
1164         /* Manually manage the write flush as we may have not yet
1165          * retired the buffer.
1166          */
1167         if (obj->last_write_seqno &&
1168             i915_seqno_passed(seqno, obj->last_write_seqno)) {
1169                 obj->last_write_seqno = 0;
1170                 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1171         }
1172
1173         return ret;
1174 }
1175
1176 /**
1177  * Called when user space prepares to use an object with the CPU, either
1178  * through the mmap ioctl's mapping or a GTT mapping.
1179  */
1180 int
1181 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1182                           struct drm_file *file)
1183 {
1184         struct drm_i915_gem_set_domain *args = data;
1185         struct drm_i915_gem_object *obj;
1186         uint32_t read_domains = args->read_domains;
1187         uint32_t write_domain = args->write_domain;
1188         int ret;
1189
1190         /* Only handle setting domains to types used by the CPU. */
1191         if (write_domain & I915_GEM_GPU_DOMAINS)
1192                 return -EINVAL;
1193
1194         if (read_domains & I915_GEM_GPU_DOMAINS)
1195                 return -EINVAL;
1196
1197         /* Having something in the write domain implies it's in the read
1198          * domain, and only that read domain.  Enforce that in the request.
1199          */
1200         if (write_domain != 0 && read_domains != write_domain)
1201                 return -EINVAL;
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret)
1205                 return ret;
1206
1207         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208         if (&obj->base == NULL) {
1209                 ret = -ENOENT;
1210                 goto unlock;
1211         }
1212
1213         /* Try to flush the object off the GPU without holding the lock.
1214          * We will repeat the flush holding the lock in the normal manner
1215          * to catch cases where we are gazumped.
1216          */
1217         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218         if (ret)
1219                 goto unref;
1220
1221         if (read_domains & I915_GEM_DOMAIN_GTT) {
1222                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1223
1224                 /* Silently promote "you're not bound, there was nothing to do"
1225                  * to success, since the client was just asking us to
1226                  * make sure everything was done.
1227                  */
1228                 if (ret == -EINVAL)
1229                         ret = 0;
1230         } else {
1231                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232         }
1233
1234 unref:
1235         drm_gem_object_unreference(&obj->base);
1236 unlock:
1237         mutex_unlock(&dev->struct_mutex);
1238         return ret;
1239 }
1240
1241 /**
1242  * Called when user space has done writes to this buffer
1243  */
1244 int
1245 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1246                          struct drm_file *file)
1247 {
1248         struct drm_i915_gem_sw_finish *args = data;
1249         struct drm_i915_gem_object *obj;
1250         int ret = 0;
1251
1252         ret = i915_mutex_lock_interruptible(dev);
1253         if (ret)
1254                 return ret;
1255
1256         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1257         if (&obj->base == NULL) {
1258                 ret = -ENOENT;
1259                 goto unlock;
1260         }
1261
1262         /* Pinned buffers may be scanout, so flush the cache */
1263         if (obj->pin_count)
1264                 i915_gem_object_flush_cpu_write_domain(obj);
1265
1266         drm_gem_object_unreference(&obj->base);
1267 unlock:
1268         mutex_unlock(&dev->struct_mutex);
1269         return ret;
1270 }
1271
1272 /**
1273  * Maps the contents of an object, returning the address it is mapped
1274  * into.
1275  *
1276  * While the mapping holds a reference on the contents of the object, it doesn't
1277  * imply a ref on the object itself.
1278  */
1279 int
1280 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1281                     struct drm_file *file)
1282 {
1283         struct drm_i915_gem_mmap *args = data;
1284         struct drm_gem_object *obj;
1285         unsigned long addr;
1286
1287         obj = drm_gem_object_lookup(dev, file, args->handle);
1288         if (obj == NULL)
1289                 return -ENOENT;
1290
1291         /* prime objects have no backing filp to GEM mmap
1292          * pages from.
1293          */
1294         if (!obj->filp) {
1295                 drm_gem_object_unreference_unlocked(obj);
1296                 return -EINVAL;
1297         }
1298
1299         addr = vm_mmap(obj->filp, 0, args->size,
1300                        PROT_READ | PROT_WRITE, MAP_SHARED,
1301                        args->offset);
1302         drm_gem_object_unreference_unlocked(obj);
1303         if (IS_ERR((void *)addr))
1304                 return addr;
1305
1306         args->addr_ptr = (uint64_t) addr;
1307
1308         return 0;
1309 }
1310
1311 /**
1312  * i915_gem_fault - fault a page into the GTT
1313  * vma: VMA in question
1314  * vmf: fault info
1315  *
1316  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317  * from userspace.  The fault handler takes care of binding the object to
1318  * the GTT (if needed), allocating and programming a fence register (again,
1319  * only if needed based on whether the old reg is still valid or the object
1320  * is tiled) and inserting a new PTE into the faulting process.
1321  *
1322  * Note that the faulting process may involve evicting existing objects
1323  * from the GTT and/or fence registers to make room.  So performance may
1324  * suffer if the GTT working set is large or there are few fence registers
1325  * left.
1326  */
1327 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1328 {
1329         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1330         struct drm_device *dev = obj->base.dev;
1331         drm_i915_private_t *dev_priv = dev->dev_private;
1332         pgoff_t page_offset;
1333         unsigned long pfn;
1334         int ret = 0;
1335         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1336
1337         /* We don't use vmf->pgoff since that has the fake offset */
1338         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1339                 PAGE_SHIFT;
1340
1341         ret = i915_mutex_lock_interruptible(dev);
1342         if (ret)
1343                 goto out;
1344
1345         trace_i915_gem_object_fault(obj, page_offset, true, write);
1346
1347         /* Now bind it into the GTT if needed */
1348         ret = i915_gem_object_pin(obj, 0, true, false);
1349         if (ret)
1350                 goto unlock;
1351
1352         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1353         if (ret)
1354                 goto unpin;
1355
1356         ret = i915_gem_object_get_fence(obj);
1357         if (ret)
1358                 goto unpin;
1359
1360         obj->fault_mappable = true;
1361
1362         pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1363                 page_offset;
1364
1365         /* Finally, remap it using the new GTT offset */
1366         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1367 unpin:
1368         i915_gem_object_unpin(obj);
1369 unlock:
1370         mutex_unlock(&dev->struct_mutex);
1371 out:
1372         switch (ret) {
1373         case -EIO:
1374                 /* If this -EIO is due to a gpu hang, give the reset code a
1375                  * chance to clean up the mess. Otherwise return the proper
1376                  * SIGBUS. */
1377                 if (!atomic_read(&dev_priv->mm.wedged))
1378                         return VM_FAULT_SIGBUS;
1379         case -EAGAIN:
1380                 /* Give the error handler a chance to run and move the
1381                  * objects off the GPU active list. Next time we service the
1382                  * fault, we should be able to transition the page into the
1383                  * GTT without touching the GPU (and so avoid further
1384                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1385                  * with coherency, just lost writes.
1386                  */
1387                 set_need_resched();
1388         case 0:
1389         case -ERESTARTSYS:
1390         case -EINTR:
1391         case -EBUSY:
1392                 /*
1393                  * EBUSY is ok: this just means that another thread
1394                  * already did the job.
1395                  */
1396                 return VM_FAULT_NOPAGE;
1397         case -ENOMEM:
1398                 return VM_FAULT_OOM;
1399         case -ENOSPC:
1400                 return VM_FAULT_SIGBUS;
1401         default:
1402                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1403                 return VM_FAULT_SIGBUS;
1404         }
1405 }
1406
1407 /**
1408  * i915_gem_release_mmap - remove physical page mappings
1409  * @obj: obj in question
1410  *
1411  * Preserve the reservation of the mmapping with the DRM core code, but
1412  * relinquish ownership of the pages back to the system.
1413  *
1414  * It is vital that we remove the page mapping if we have mapped a tiled
1415  * object through the GTT and then lose the fence register due to
1416  * resource pressure. Similarly if the object has been moved out of the
1417  * aperture, than pages mapped into userspace must be revoked. Removing the
1418  * mapping will then trigger a page fault on the next user access, allowing
1419  * fixup by i915_gem_fault().
1420  */
1421 void
1422 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1423 {
1424         if (!obj->fault_mappable)
1425                 return;
1426
1427         if (obj->base.dev->dev_mapping)
1428                 unmap_mapping_range(obj->base.dev->dev_mapping,
1429                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1430                                     obj->base.size, 1);
1431
1432         obj->fault_mappable = false;
1433 }
1434
1435 static uint32_t
1436 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1437 {
1438         uint32_t gtt_size;
1439
1440         if (INTEL_INFO(dev)->gen >= 4 ||
1441             tiling_mode == I915_TILING_NONE)
1442                 return size;
1443
1444         /* Previous chips need a power-of-two fence region when tiling */
1445         if (INTEL_INFO(dev)->gen == 3)
1446                 gtt_size = 1024*1024;
1447         else
1448                 gtt_size = 512*1024;
1449
1450         while (gtt_size < size)
1451                 gtt_size <<= 1;
1452
1453         return gtt_size;
1454 }
1455
1456 /**
1457  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1458  * @obj: object to check
1459  *
1460  * Return the required GTT alignment for an object, taking into account
1461  * potential fence register mapping.
1462  */
1463 static uint32_t
1464 i915_gem_get_gtt_alignment(struct drm_device *dev,
1465                            uint32_t size,
1466                            int tiling_mode)
1467 {
1468         /*
1469          * Minimum alignment is 4k (GTT page size), but might be greater
1470          * if a fence register is needed for the object.
1471          */
1472         if (INTEL_INFO(dev)->gen >= 4 ||
1473             tiling_mode == I915_TILING_NONE)
1474                 return 4096;
1475
1476         /*
1477          * Previous chips need to be aligned to the size of the smallest
1478          * fence register that can contain the object.
1479          */
1480         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 }
1482
1483 /**
1484  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1485  *                                       unfenced object
1486  * @dev: the device
1487  * @size: size of the object
1488  * @tiling_mode: tiling mode of the object
1489  *
1490  * Return the required GTT alignment for an object, only taking into account
1491  * unfenced tiled surface requirements.
1492  */
1493 uint32_t
1494 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1495                                     uint32_t size,
1496                                     int tiling_mode)
1497 {
1498         /*
1499          * Minimum alignment is 4k (GTT page size) for sane hw.
1500          */
1501         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1502             tiling_mode == I915_TILING_NONE)
1503                 return 4096;
1504
1505         /* Previous hardware however needs to be aligned to a power-of-two
1506          * tile height. The simplest method for determining this is to reuse
1507          * the power-of-tile object size.
1508          */
1509         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1510 }
1511
1512 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1513 {
1514         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1515         int ret;
1516
1517         if (obj->base.map_list.map)
1518                 return 0;
1519
1520         ret = drm_gem_create_mmap_offset(&obj->base);
1521         if (ret != -ENOSPC)
1522                 return ret;
1523
1524         /* Badly fragmented mmap space? The only way we can recover
1525          * space is by destroying unwanted objects. We can't randomly release
1526          * mmap_offsets as userspace expects them to be persistent for the
1527          * lifetime of the objects. The closest we can is to release the
1528          * offsets on purgeable objects by truncating it and marking it purged,
1529          * which prevents userspace from ever using that object again.
1530          */
1531         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1532         ret = drm_gem_create_mmap_offset(&obj->base);
1533         if (ret != -ENOSPC)
1534                 return ret;
1535
1536         i915_gem_shrink_all(dev_priv);
1537         return drm_gem_create_mmap_offset(&obj->base);
1538 }
1539
1540 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1541 {
1542         if (!obj->base.map_list.map)
1543                 return;
1544
1545         drm_gem_free_mmap_offset(&obj->base);
1546 }
1547
1548 int
1549 i915_gem_mmap_gtt(struct drm_file *file,
1550                   struct drm_device *dev,
1551                   uint32_t handle,
1552                   uint64_t *offset)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_i915_gem_object *obj;
1556         int ret;
1557
1558         ret = i915_mutex_lock_interruptible(dev);
1559         if (ret)
1560                 return ret;
1561
1562         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1563         if (&obj->base == NULL) {
1564                 ret = -ENOENT;
1565                 goto unlock;
1566         }
1567
1568         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1569                 ret = -E2BIG;
1570                 goto out;
1571         }
1572
1573         if (obj->madv != I915_MADV_WILLNEED) {
1574                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1575                 ret = -EINVAL;
1576                 goto out;
1577         }
1578
1579         ret = i915_gem_object_create_mmap_offset(obj);
1580         if (ret)
1581                 goto out;
1582
1583         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1584
1585 out:
1586         drm_gem_object_unreference(&obj->base);
1587 unlock:
1588         mutex_unlock(&dev->struct_mutex);
1589         return ret;
1590 }
1591
1592 /**
1593  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1594  * @dev: DRM device
1595  * @data: GTT mapping ioctl data
1596  * @file: GEM object info
1597  *
1598  * Simply returns the fake offset to userspace so it can mmap it.
1599  * The mmap call will end up in drm_gem_mmap(), which will set things
1600  * up so we can get faults in the handler above.
1601  *
1602  * The fault handler will take care of binding the object into the GTT
1603  * (since it may have been evicted to make room for something), allocating
1604  * a fence register, and mapping the appropriate aperture address into
1605  * userspace.
1606  */
1607 int
1608 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1609                         struct drm_file *file)
1610 {
1611         struct drm_i915_gem_mmap_gtt *args = data;
1612
1613         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1614 }
1615
1616 /* Immediately discard the backing storage */
1617 static void
1618 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1619 {
1620         struct inode *inode;
1621
1622         i915_gem_object_free_mmap_offset(obj);
1623
1624         if (obj->base.filp == NULL)
1625                 return;
1626
1627         /* Our goal here is to return as much of the memory as
1628          * is possible back to the system as we are called from OOM.
1629          * To do this we must instruct the shmfs to drop all of its
1630          * backing pages, *now*.
1631          */
1632         inode = obj->base.filp->f_path.dentry->d_inode;
1633         shmem_truncate_range(inode, 0, (loff_t)-1);
1634
1635         obj->madv = __I915_MADV_PURGED;
1636 }
1637
1638 static inline int
1639 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1640 {
1641         return obj->madv == I915_MADV_DONTNEED;
1642 }
1643
1644 static void
1645 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1646 {
1647         int page_count = obj->base.size / PAGE_SIZE;
1648         struct scatterlist *sg;
1649         int ret, i;
1650
1651         BUG_ON(obj->madv == __I915_MADV_PURGED);
1652
1653         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1654         if (ret) {
1655                 /* In the event of a disaster, abandon all caches and
1656                  * hope for the best.
1657                  */
1658                 WARN_ON(ret != -EIO);
1659                 i915_gem_clflush_object(obj);
1660                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1661         }
1662
1663         if (i915_gem_object_needs_bit17_swizzle(obj))
1664                 i915_gem_object_save_bit_17_swizzle(obj);
1665
1666         if (obj->madv == I915_MADV_DONTNEED)
1667                 obj->dirty = 0;
1668
1669         for_each_sg(obj->pages->sgl, sg, page_count, i) {
1670                 struct page *page = sg_page(sg);
1671
1672                 if (obj->dirty)
1673                         set_page_dirty(page);
1674
1675                 if (obj->madv == I915_MADV_WILLNEED)
1676                         mark_page_accessed(page);
1677
1678                 page_cache_release(page);
1679         }
1680         obj->dirty = 0;
1681
1682         sg_free_table(obj->pages);
1683         kfree(obj->pages);
1684 }
1685
1686 static int
1687 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1688 {
1689         const struct drm_i915_gem_object_ops *ops = obj->ops;
1690
1691         if (obj->pages == NULL)
1692                 return 0;
1693
1694         BUG_ON(obj->gtt_space);
1695
1696         if (obj->pages_pin_count)
1697                 return -EBUSY;
1698
1699         ops->put_pages(obj);
1700         obj->pages = NULL;
1701
1702         list_del(&obj->gtt_list);
1703         if (i915_gem_object_is_purgeable(obj))
1704                 i915_gem_object_truncate(obj);
1705
1706         return 0;
1707 }
1708
1709 static long
1710 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1711 {
1712         struct drm_i915_gem_object *obj, *next;
1713         long count = 0;
1714
1715         list_for_each_entry_safe(obj, next,
1716                                  &dev_priv->mm.unbound_list,
1717                                  gtt_list) {
1718                 if (i915_gem_object_is_purgeable(obj) &&
1719                     i915_gem_object_put_pages(obj) == 0) {
1720                         count += obj->base.size >> PAGE_SHIFT;
1721                         if (count >= target)
1722                                 return count;
1723                 }
1724         }
1725
1726         list_for_each_entry_safe(obj, next,
1727                                  &dev_priv->mm.inactive_list,
1728                                  mm_list) {
1729                 if (i915_gem_object_is_purgeable(obj) &&
1730                     i915_gem_object_unbind(obj) == 0 &&
1731                     i915_gem_object_put_pages(obj) == 0) {
1732                         count += obj->base.size >> PAGE_SHIFT;
1733                         if (count >= target)
1734                                 return count;
1735                 }
1736         }
1737
1738         return count;
1739 }
1740
1741 static void
1742 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1743 {
1744         struct drm_i915_gem_object *obj, *next;
1745
1746         i915_gem_evict_everything(dev_priv->dev);
1747
1748         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1749                 i915_gem_object_put_pages(obj);
1750 }
1751
1752 static int
1753 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1754 {
1755         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1756         int page_count, i;
1757         struct address_space *mapping;
1758         struct sg_table *st;
1759         struct scatterlist *sg;
1760         struct page *page;
1761         gfp_t gfp;
1762
1763         /* Assert that the object is not currently in any GPU domain. As it
1764          * wasn't in the GTT, there shouldn't be any way it could have been in
1765          * a GPU cache
1766          */
1767         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1768         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1769
1770         st = kmalloc(sizeof(*st), GFP_KERNEL);
1771         if (st == NULL)
1772                 return -ENOMEM;
1773
1774         page_count = obj->base.size / PAGE_SIZE;
1775         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1776                 sg_free_table(st);
1777                 kfree(st);
1778                 return -ENOMEM;
1779         }
1780
1781         /* Get the list of pages out of our struct file.  They'll be pinned
1782          * at this point until we release them.
1783          *
1784          * Fail silently without starting the shrinker
1785          */
1786         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1787         gfp = mapping_gfp_mask(mapping);
1788         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1789         gfp &= ~(__GFP_IO | __GFP_WAIT);
1790         for_each_sg(st->sgl, sg, page_count, i) {
1791                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1792                 if (IS_ERR(page)) {
1793                         i915_gem_purge(dev_priv, page_count);
1794                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1795                 }
1796                 if (IS_ERR(page)) {
1797                         /* We've tried hard to allocate the memory by reaping
1798                          * our own buffer, now let the real VM do its job and
1799                          * go down in flames if truly OOM.
1800                          */
1801                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1802                         gfp |= __GFP_IO | __GFP_WAIT;
1803
1804                         i915_gem_shrink_all(dev_priv);
1805                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1806                         if (IS_ERR(page))
1807                                 goto err_pages;
1808
1809                         gfp |= __GFP_NORETRY | __GFP_NOWARN;
1810                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1811                 }
1812
1813                 sg_set_page(sg, page, PAGE_SIZE, 0);
1814         }
1815
1816         obj->pages = st;
1817
1818         if (i915_gem_object_needs_bit17_swizzle(obj))
1819                 i915_gem_object_do_bit_17_swizzle(obj);
1820
1821         return 0;
1822
1823 err_pages:
1824         for_each_sg(st->sgl, sg, i, page_count)
1825                 page_cache_release(sg_page(sg));
1826         sg_free_table(st);
1827         kfree(st);
1828         return PTR_ERR(page);
1829 }
1830
1831 /* Ensure that the associated pages are gathered from the backing storage
1832  * and pinned into our object. i915_gem_object_get_pages() may be called
1833  * multiple times before they are released by a single call to
1834  * i915_gem_object_put_pages() - once the pages are no longer referenced
1835  * either as a result of memory pressure (reaping pages under the shrinker)
1836  * or as the object is itself released.
1837  */
1838 int
1839 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1840 {
1841         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1842         const struct drm_i915_gem_object_ops *ops = obj->ops;
1843         int ret;
1844
1845         if (obj->pages)
1846                 return 0;
1847
1848         BUG_ON(obj->pages_pin_count);
1849
1850         ret = ops->get_pages(obj);
1851         if (ret)
1852                 return ret;
1853
1854         list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1855         return 0;
1856 }
1857
1858 void
1859 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1860                                struct intel_ring_buffer *ring)
1861 {
1862         struct drm_device *dev = obj->base.dev;
1863         struct drm_i915_private *dev_priv = dev->dev_private;
1864         u32 seqno = intel_ring_get_seqno(ring);
1865
1866         BUG_ON(ring == NULL);
1867         obj->ring = ring;
1868
1869         /* Add a reference if we're newly entering the active list. */
1870         if (!obj->active) {
1871                 drm_gem_object_reference(&obj->base);
1872                 obj->active = 1;
1873         }
1874
1875         /* Move from whatever list we were on to the tail of execution. */
1876         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1877         list_move_tail(&obj->ring_list, &ring->active_list);
1878
1879         obj->last_read_seqno = seqno;
1880
1881         if (obj->fenced_gpu_access) {
1882                 obj->last_fenced_seqno = seqno;
1883
1884                 /* Bump MRU to take account of the delayed flush */
1885                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1886                         struct drm_i915_fence_reg *reg;
1887
1888                         reg = &dev_priv->fence_regs[obj->fence_reg];
1889                         list_move_tail(&reg->lru_list,
1890                                        &dev_priv->mm.fence_list);
1891                 }
1892         }
1893 }
1894
1895 static void
1896 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1897 {
1898         struct drm_device *dev = obj->base.dev;
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900
1901         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1902         BUG_ON(!obj->active);
1903
1904         if (obj->pin_count) /* are we a framebuffer? */
1905                 intel_mark_fb_idle(obj);
1906
1907         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1908
1909         list_del_init(&obj->ring_list);
1910         obj->ring = NULL;
1911
1912         obj->last_read_seqno = 0;
1913         obj->last_write_seqno = 0;
1914         obj->base.write_domain = 0;
1915
1916         obj->last_fenced_seqno = 0;
1917         obj->fenced_gpu_access = false;
1918
1919         obj->active = 0;
1920         drm_gem_object_unreference(&obj->base);
1921
1922         WARN_ON(i915_verify_lists(dev));
1923 }
1924
1925 static int
1926 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1927 {
1928         struct drm_i915_private *dev_priv = dev->dev_private;
1929         struct intel_ring_buffer *ring;
1930         int ret, i, j;
1931
1932         /* The hardware uses various monotonic 32-bit counters, if we
1933          * detect that they will wraparound we need to idle the GPU
1934          * and reset those counters.
1935          */
1936         ret = 0;
1937         for_each_ring(ring, dev_priv, i) {
1938                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1939                         ret |= ring->sync_seqno[j] != 0;
1940         }
1941         if (ret == 0)
1942                 return ret;
1943
1944         ret = i915_gpu_idle(dev);
1945         if (ret)
1946                 return ret;
1947
1948         i915_gem_retire_requests(dev);
1949         for_each_ring(ring, dev_priv, i) {
1950                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1951                         ring->sync_seqno[j] = 0;
1952         }
1953
1954         return 0;
1955 }
1956
1957 int
1958 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1959 {
1960         struct drm_i915_private *dev_priv = dev->dev_private;
1961
1962         /* reserve 0 for non-seqno */
1963         if (dev_priv->next_seqno == 0) {
1964                 int ret = i915_gem_handle_seqno_wrap(dev);
1965                 if (ret)
1966                         return ret;
1967
1968                 dev_priv->next_seqno = 1;
1969         }
1970
1971         *seqno = dev_priv->next_seqno++;
1972         return 0;
1973 }
1974
1975 int
1976 i915_add_request(struct intel_ring_buffer *ring,
1977                  struct drm_file *file,
1978                  u32 *out_seqno)
1979 {
1980         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1981         struct drm_i915_gem_request *request;
1982         u32 request_ring_position;
1983         int was_empty;
1984         int ret;
1985
1986         /*
1987          * Emit any outstanding flushes - execbuf can fail to emit the flush
1988          * after having emitted the batchbuffer command. Hence we need to fix
1989          * things up similar to emitting the lazy request. The difference here
1990          * is that the flush _must_ happen before the next request, no matter
1991          * what.
1992          */
1993         ret = intel_ring_flush_all_caches(ring);
1994         if (ret)
1995                 return ret;
1996
1997         request = kmalloc(sizeof(*request), GFP_KERNEL);
1998         if (request == NULL)
1999                 return -ENOMEM;
2000
2001
2002         /* Record the position of the start of the request so that
2003          * should we detect the updated seqno part-way through the
2004          * GPU processing the request, we never over-estimate the
2005          * position of the head.
2006          */
2007         request_ring_position = intel_ring_get_tail(ring);
2008
2009         ret = ring->add_request(ring);
2010         if (ret) {
2011                 kfree(request);
2012                 return ret;
2013         }
2014
2015         request->seqno = intel_ring_get_seqno(ring);
2016         request->ring = ring;
2017         request->tail = request_ring_position;
2018         request->emitted_jiffies = jiffies;
2019         was_empty = list_empty(&ring->request_list);
2020         list_add_tail(&request->list, &ring->request_list);
2021         request->file_priv = NULL;
2022
2023         if (file) {
2024                 struct drm_i915_file_private *file_priv = file->driver_priv;
2025
2026                 spin_lock(&file_priv->mm.lock);
2027                 request->file_priv = file_priv;
2028                 list_add_tail(&request->client_list,
2029                               &file_priv->mm.request_list);
2030                 spin_unlock(&file_priv->mm.lock);
2031         }
2032
2033         trace_i915_gem_request_add(ring, request->seqno);
2034         ring->outstanding_lazy_request = 0;
2035
2036         if (!dev_priv->mm.suspended) {
2037                 if (i915_enable_hangcheck) {
2038                         mod_timer(&dev_priv->hangcheck_timer,
2039                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2040                 }
2041                 if (was_empty) {
2042                         queue_delayed_work(dev_priv->wq,
2043                                            &dev_priv->mm.retire_work,
2044                                            round_jiffies_up_relative(HZ));
2045                         intel_mark_busy(dev_priv->dev);
2046                 }
2047         }
2048
2049         if (out_seqno)
2050                 *out_seqno = request->seqno;
2051         return 0;
2052 }
2053
2054 static inline void
2055 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2056 {
2057         struct drm_i915_file_private *file_priv = request->file_priv;
2058
2059         if (!file_priv)
2060                 return;
2061
2062         spin_lock(&file_priv->mm.lock);
2063         if (request->file_priv) {
2064                 list_del(&request->client_list);
2065                 request->file_priv = NULL;
2066         }
2067         spin_unlock(&file_priv->mm.lock);
2068 }
2069
2070 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2071                                       struct intel_ring_buffer *ring)
2072 {
2073         while (!list_empty(&ring->request_list)) {
2074                 struct drm_i915_gem_request *request;
2075
2076                 request = list_first_entry(&ring->request_list,
2077                                            struct drm_i915_gem_request,
2078                                            list);
2079
2080                 list_del(&request->list);
2081                 i915_gem_request_remove_from_client(request);
2082                 kfree(request);
2083         }
2084
2085         while (!list_empty(&ring->active_list)) {
2086                 struct drm_i915_gem_object *obj;
2087
2088                 obj = list_first_entry(&ring->active_list,
2089                                        struct drm_i915_gem_object,
2090                                        ring_list);
2091
2092                 i915_gem_object_move_to_inactive(obj);
2093         }
2094 }
2095
2096 static void i915_gem_reset_fences(struct drm_device *dev)
2097 {
2098         struct drm_i915_private *dev_priv = dev->dev_private;
2099         int i;
2100
2101         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2102                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2103
2104                 i915_gem_write_fence(dev, i, NULL);
2105
2106                 if (reg->obj)
2107                         i915_gem_object_fence_lost(reg->obj);
2108
2109                 reg->pin_count = 0;
2110                 reg->obj = NULL;
2111                 INIT_LIST_HEAD(&reg->lru_list);
2112         }
2113
2114         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2115 }
2116
2117 void i915_gem_reset(struct drm_device *dev)
2118 {
2119         struct drm_i915_private *dev_priv = dev->dev_private;
2120         struct drm_i915_gem_object *obj;
2121         struct intel_ring_buffer *ring;
2122         int i;
2123
2124         for_each_ring(ring, dev_priv, i)
2125                 i915_gem_reset_ring_lists(dev_priv, ring);
2126
2127         /* Move everything out of the GPU domains to ensure we do any
2128          * necessary invalidation upon reuse.
2129          */
2130         list_for_each_entry(obj,
2131                             &dev_priv->mm.inactive_list,
2132                             mm_list)
2133         {
2134                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2135         }
2136
2137         /* The fence registers are invalidated so clear them out */
2138         i915_gem_reset_fences(dev);
2139 }
2140
2141 /**
2142  * This function clears the request list as sequence numbers are passed.
2143  */
2144 void
2145 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2146 {
2147         uint32_t seqno;
2148
2149         if (list_empty(&ring->request_list))
2150                 return;
2151
2152         WARN_ON(i915_verify_lists(ring->dev));
2153
2154         seqno = ring->get_seqno(ring, true);
2155
2156         while (!list_empty(&ring->request_list)) {
2157                 struct drm_i915_gem_request *request;
2158
2159                 request = list_first_entry(&ring->request_list,
2160                                            struct drm_i915_gem_request,
2161                                            list);
2162
2163                 if (!i915_seqno_passed(seqno, request->seqno))
2164                         break;
2165
2166                 trace_i915_gem_request_retire(ring, request->seqno);
2167                 /* We know the GPU must have read the request to have
2168                  * sent us the seqno + interrupt, so use the position
2169                  * of tail of the request to update the last known position
2170                  * of the GPU head.
2171                  */
2172                 ring->last_retired_head = request->tail;
2173
2174                 list_del(&request->list);
2175                 i915_gem_request_remove_from_client(request);
2176                 kfree(request);
2177         }
2178
2179         /* Move any buffers on the active list that are no longer referenced
2180          * by the ringbuffer to the flushing/inactive lists as appropriate.
2181          */
2182         while (!list_empty(&ring->active_list)) {
2183                 struct drm_i915_gem_object *obj;
2184
2185                 obj = list_first_entry(&ring->active_list,
2186                                       struct drm_i915_gem_object,
2187                                       ring_list);
2188
2189                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2190                         break;
2191
2192                 i915_gem_object_move_to_inactive(obj);
2193         }
2194
2195         if (unlikely(ring->trace_irq_seqno &&
2196                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2197                 ring->irq_put(ring);
2198                 ring->trace_irq_seqno = 0;
2199         }
2200
2201         WARN_ON(i915_verify_lists(ring->dev));
2202 }
2203
2204 void
2205 i915_gem_retire_requests(struct drm_device *dev)
2206 {
2207         drm_i915_private_t *dev_priv = dev->dev_private;
2208         struct intel_ring_buffer *ring;
2209         int i;
2210
2211         for_each_ring(ring, dev_priv, i)
2212                 i915_gem_retire_requests_ring(ring);
2213 }
2214
2215 static void
2216 i915_gem_retire_work_handler(struct work_struct *work)
2217 {
2218         drm_i915_private_t *dev_priv;
2219         struct drm_device *dev;
2220         struct intel_ring_buffer *ring;
2221         bool idle;
2222         int i;
2223
2224         dev_priv = container_of(work, drm_i915_private_t,
2225                                 mm.retire_work.work);
2226         dev = dev_priv->dev;
2227
2228         /* Come back later if the device is busy... */
2229         if (!mutex_trylock(&dev->struct_mutex)) {
2230                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2231                                    round_jiffies_up_relative(HZ));
2232                 return;
2233         }
2234
2235         i915_gem_retire_requests(dev);
2236
2237         /* Send a periodic flush down the ring so we don't hold onto GEM
2238          * objects indefinitely.
2239          */
2240         idle = true;
2241         for_each_ring(ring, dev_priv, i) {
2242                 if (ring->gpu_caches_dirty)
2243                         i915_add_request(ring, NULL, NULL);
2244
2245                 idle &= list_empty(&ring->request_list);
2246         }
2247
2248         if (!dev_priv->mm.suspended && !idle)
2249                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2250                                    round_jiffies_up_relative(HZ));
2251         if (idle)
2252                 intel_mark_idle(dev);
2253
2254         mutex_unlock(&dev->struct_mutex);
2255 }
2256
2257 /**
2258  * Ensures that an object will eventually get non-busy by flushing any required
2259  * write domains, emitting any outstanding lazy request and retiring and
2260  * completed requests.
2261  */
2262 static int
2263 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2264 {
2265         int ret;
2266
2267         if (obj->active) {
2268                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2269                 if (ret)
2270                         return ret;
2271
2272                 i915_gem_retire_requests_ring(obj->ring);
2273         }
2274
2275         return 0;
2276 }
2277
2278 /**
2279  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2280  * @DRM_IOCTL_ARGS: standard ioctl arguments
2281  *
2282  * Returns 0 if successful, else an error is returned with the remaining time in
2283  * the timeout parameter.
2284  *  -ETIME: object is still busy after timeout
2285  *  -ERESTARTSYS: signal interrupted the wait
2286  *  -ENONENT: object doesn't exist
2287  * Also possible, but rare:
2288  *  -EAGAIN: GPU wedged
2289  *  -ENOMEM: damn
2290  *  -ENODEV: Internal IRQ fail
2291  *  -E?: The add request failed
2292  *
2293  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2294  * non-zero timeout parameter the wait ioctl will wait for the given number of
2295  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2296  * without holding struct_mutex the object may become re-busied before this
2297  * function completes. A similar but shorter * race condition exists in the busy
2298  * ioctl
2299  */
2300 int
2301 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2302 {
2303         struct drm_i915_gem_wait *args = data;
2304         struct drm_i915_gem_object *obj;
2305         struct intel_ring_buffer *ring = NULL;
2306         struct timespec timeout_stack, *timeout = NULL;
2307         u32 seqno = 0;
2308         int ret = 0;
2309
2310         if (args->timeout_ns >= 0) {
2311                 timeout_stack = ns_to_timespec(args->timeout_ns);
2312                 timeout = &timeout_stack;
2313         }
2314
2315         ret = i915_mutex_lock_interruptible(dev);
2316         if (ret)
2317                 return ret;
2318
2319         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2320         if (&obj->base == NULL) {
2321                 mutex_unlock(&dev->struct_mutex);
2322                 return -ENOENT;
2323         }
2324
2325         /* Need to make sure the object gets inactive eventually. */
2326         ret = i915_gem_object_flush_active(obj);
2327         if (ret)
2328                 goto out;
2329
2330         if (obj->active) {
2331                 seqno = obj->last_read_seqno;
2332                 ring = obj->ring;
2333         }
2334
2335         if (seqno == 0)
2336                  goto out;
2337
2338         /* Do this after OLR check to make sure we make forward progress polling
2339          * on this IOCTL with a 0 timeout (like busy ioctl)
2340          */
2341         if (!args->timeout_ns) {
2342                 ret = -ETIME;
2343                 goto out;
2344         }
2345
2346         drm_gem_object_unreference(&obj->base);
2347         mutex_unlock(&dev->struct_mutex);
2348
2349         ret = __wait_seqno(ring, seqno, true, timeout);
2350         if (timeout) {
2351                 WARN_ON(!timespec_valid(timeout));
2352                 args->timeout_ns = timespec_to_ns(timeout);
2353         }
2354         return ret;
2355
2356 out:
2357         drm_gem_object_unreference(&obj->base);
2358         mutex_unlock(&dev->struct_mutex);
2359         return ret;
2360 }
2361
2362 /**
2363  * i915_gem_object_sync - sync an object to a ring.
2364  *
2365  * @obj: object which may be in use on another ring.
2366  * @to: ring we wish to use the object on. May be NULL.
2367  *
2368  * This code is meant to abstract object synchronization with the GPU.
2369  * Calling with NULL implies synchronizing the object with the CPU
2370  * rather than a particular GPU ring.
2371  *
2372  * Returns 0 if successful, else propagates up the lower layer error.
2373  */
2374 int
2375 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2376                      struct intel_ring_buffer *to)
2377 {
2378         struct intel_ring_buffer *from = obj->ring;
2379         u32 seqno;
2380         int ret, idx;
2381
2382         if (from == NULL || to == from)
2383                 return 0;
2384
2385         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2386                 return i915_gem_object_wait_rendering(obj, false);
2387
2388         idx = intel_ring_sync_index(from, to);
2389
2390         seqno = obj->last_read_seqno;
2391         if (seqno <= from->sync_seqno[idx])
2392                 return 0;
2393
2394         ret = i915_gem_check_olr(obj->ring, seqno);
2395         if (ret)
2396                 return ret;
2397
2398         ret = to->sync_to(to, from, seqno);
2399         if (!ret)
2400                 from->sync_seqno[idx] = seqno;
2401
2402         return ret;
2403 }
2404
2405 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2406 {
2407         u32 old_write_domain, old_read_domains;
2408
2409         /* Act a barrier for all accesses through the GTT */
2410         mb();
2411
2412         /* Force a pagefault for domain tracking on next user access */
2413         i915_gem_release_mmap(obj);
2414
2415         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2416                 return;
2417
2418         old_read_domains = obj->base.read_domains;
2419         old_write_domain = obj->base.write_domain;
2420
2421         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2422         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2423
2424         trace_i915_gem_object_change_domain(obj,
2425                                             old_read_domains,
2426                                             old_write_domain);
2427 }
2428
2429 /**
2430  * Unbinds an object from the GTT aperture.
2431  */
2432 int
2433 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2434 {
2435         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2436         int ret = 0;
2437
2438         if (obj->gtt_space == NULL)
2439                 return 0;
2440
2441         if (obj->pin_count)
2442                 return -EBUSY;
2443
2444         BUG_ON(obj->pages == NULL);
2445
2446         ret = i915_gem_object_finish_gpu(obj);
2447         if (ret)
2448                 return ret;
2449         /* Continue on if we fail due to EIO, the GPU is hung so we
2450          * should be safe and we need to cleanup or else we might
2451          * cause memory corruption through use-after-free.
2452          */
2453
2454         i915_gem_object_finish_gtt(obj);
2455
2456         /* release the fence reg _after_ flushing */
2457         ret = i915_gem_object_put_fence(obj);
2458         if (ret)
2459                 return ret;
2460
2461         trace_i915_gem_object_unbind(obj);
2462
2463         if (obj->has_global_gtt_mapping)
2464                 i915_gem_gtt_unbind_object(obj);
2465         if (obj->has_aliasing_ppgtt_mapping) {
2466                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2467                 obj->has_aliasing_ppgtt_mapping = 0;
2468         }
2469         i915_gem_gtt_finish_object(obj);
2470
2471         list_del(&obj->mm_list);
2472         list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2473         /* Avoid an unnecessary call to unbind on rebind. */
2474         obj->map_and_fenceable = true;
2475
2476         drm_mm_put_block(obj->gtt_space);
2477         obj->gtt_space = NULL;
2478         obj->gtt_offset = 0;
2479
2480         return 0;
2481 }
2482
2483 static int i915_ring_idle(struct intel_ring_buffer *ring)
2484 {
2485         u32 seqno;
2486         int ret;
2487
2488         /* We need to add any requests required to flush the objects and ring */
2489         if (ring->outstanding_lazy_request) {
2490                 ret = i915_add_request(ring, NULL, NULL);
2491                 if (ret)
2492                         return ret;
2493         }
2494
2495         /* Wait upon the last request to be completed */
2496         if (list_empty(&ring->request_list))
2497                 return 0;
2498
2499         seqno = list_entry(ring->request_list.prev,
2500                            struct drm_i915_gem_request,
2501                            list)->seqno;
2502
2503         return i915_wait_seqno(ring, seqno);
2504 }
2505
2506 int i915_gpu_idle(struct drm_device *dev)
2507 {
2508         drm_i915_private_t *dev_priv = dev->dev_private;
2509         struct intel_ring_buffer *ring;
2510         int ret, i;
2511
2512         /* Flush everything onto the inactive list. */
2513         for_each_ring(ring, dev_priv, i) {
2514                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2515                 if (ret)
2516                         return ret;
2517
2518                 ret = i915_ring_idle(ring);
2519                 if (ret)
2520                         return ret;
2521         }
2522
2523         return 0;
2524 }
2525
2526 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2527                                         struct drm_i915_gem_object *obj)
2528 {
2529         drm_i915_private_t *dev_priv = dev->dev_private;
2530         uint64_t val;
2531
2532         if (obj) {
2533                 u32 size = obj->gtt_space->size;
2534
2535                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2536                                  0xfffff000) << 32;
2537                 val |= obj->gtt_offset & 0xfffff000;
2538                 val |= (uint64_t)((obj->stride / 128) - 1) <<
2539                         SANDYBRIDGE_FENCE_PITCH_SHIFT;
2540
2541                 if (obj->tiling_mode == I915_TILING_Y)
2542                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2543                 val |= I965_FENCE_REG_VALID;
2544         } else
2545                 val = 0;
2546
2547         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2548         POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2549 }
2550
2551 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2552                                  struct drm_i915_gem_object *obj)
2553 {
2554         drm_i915_private_t *dev_priv = dev->dev_private;
2555         uint64_t val;
2556
2557         if (obj) {
2558                 u32 size = obj->gtt_space->size;
2559
2560                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2561                                  0xfffff000) << 32;
2562                 val |= obj->gtt_offset & 0xfffff000;
2563                 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2564                 if (obj->tiling_mode == I915_TILING_Y)
2565                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2566                 val |= I965_FENCE_REG_VALID;
2567         } else
2568                 val = 0;
2569
2570         I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2571         POSTING_READ(FENCE_REG_965_0 + reg * 8);
2572 }
2573
2574 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2575                                  struct drm_i915_gem_object *obj)
2576 {
2577         drm_i915_private_t *dev_priv = dev->dev_private;
2578         u32 val;
2579
2580         if (obj) {
2581                 u32 size = obj->gtt_space->size;
2582                 int pitch_val;
2583                 int tile_width;
2584
2585                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2586                      (size & -size) != size ||
2587                      (obj->gtt_offset & (size - 1)),
2588                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2589                      obj->gtt_offset, obj->map_and_fenceable, size);
2590
2591                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2592                         tile_width = 128;
2593                 else
2594                         tile_width = 512;
2595
2596                 /* Note: pitch better be a power of two tile widths */
2597                 pitch_val = obj->stride / tile_width;
2598                 pitch_val = ffs(pitch_val) - 1;
2599
2600                 val = obj->gtt_offset;
2601                 if (obj->tiling_mode == I915_TILING_Y)
2602                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2603                 val |= I915_FENCE_SIZE_BITS(size);
2604                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2605                 val |= I830_FENCE_REG_VALID;
2606         } else
2607                 val = 0;
2608
2609         if (reg < 8)
2610                 reg = FENCE_REG_830_0 + reg * 4;
2611         else
2612                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2613
2614         I915_WRITE(reg, val);
2615         POSTING_READ(reg);
2616 }
2617
2618 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2619                                 struct drm_i915_gem_object *obj)
2620 {
2621         drm_i915_private_t *dev_priv = dev->dev_private;
2622         uint32_t val;
2623
2624         if (obj) {
2625                 u32 size = obj->gtt_space->size;
2626                 uint32_t pitch_val;
2627
2628                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2629                      (size & -size) != size ||
2630                      (obj->gtt_offset & (size - 1)),
2631                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2632                      obj->gtt_offset, size);
2633
2634                 pitch_val = obj->stride / 128;
2635                 pitch_val = ffs(pitch_val) - 1;
2636
2637                 val = obj->gtt_offset;
2638                 if (obj->tiling_mode == I915_TILING_Y)
2639                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2640                 val |= I830_FENCE_SIZE_BITS(size);
2641                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2642                 val |= I830_FENCE_REG_VALID;
2643         } else
2644                 val = 0;
2645
2646         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2647         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2648 }
2649
2650 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2651                                  struct drm_i915_gem_object *obj)
2652 {
2653         switch (INTEL_INFO(dev)->gen) {
2654         case 7:
2655         case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2656         case 5:
2657         case 4: i965_write_fence_reg(dev, reg, obj); break;
2658         case 3: i915_write_fence_reg(dev, reg, obj); break;
2659         case 2: i830_write_fence_reg(dev, reg, obj); break;
2660         default: break;
2661         }
2662 }
2663
2664 static inline int fence_number(struct drm_i915_private *dev_priv,
2665                                struct drm_i915_fence_reg *fence)
2666 {
2667         return fence - dev_priv->fence_regs;
2668 }
2669
2670 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2671                                          struct drm_i915_fence_reg *fence,
2672                                          bool enable)
2673 {
2674         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2675         int reg = fence_number(dev_priv, fence);
2676
2677         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2678
2679         if (enable) {
2680                 obj->fence_reg = reg;
2681                 fence->obj = obj;
2682                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2683         } else {
2684                 obj->fence_reg = I915_FENCE_REG_NONE;
2685                 fence->obj = NULL;
2686                 list_del_init(&fence->lru_list);
2687         }
2688 }
2689
2690 static int
2691 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2692 {
2693         if (obj->last_fenced_seqno) {
2694                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2695                 if (ret)
2696                         return ret;
2697
2698                 obj->last_fenced_seqno = 0;
2699         }
2700
2701         /* Ensure that all CPU reads are completed before installing a fence
2702          * and all writes before removing the fence.
2703          */
2704         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2705                 mb();
2706
2707         obj->fenced_gpu_access = false;
2708         return 0;
2709 }
2710
2711 int
2712 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2713 {
2714         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2715         int ret;
2716
2717         ret = i915_gem_object_flush_fence(obj);
2718         if (ret)
2719                 return ret;
2720
2721         if (obj->fence_reg == I915_FENCE_REG_NONE)
2722                 return 0;
2723
2724         i915_gem_object_update_fence(obj,
2725                                      &dev_priv->fence_regs[obj->fence_reg],
2726                                      false);
2727         i915_gem_object_fence_lost(obj);
2728
2729         return 0;
2730 }
2731
2732 static struct drm_i915_fence_reg *
2733 i915_find_fence_reg(struct drm_device *dev)
2734 {
2735         struct drm_i915_private *dev_priv = dev->dev_private;
2736         struct drm_i915_fence_reg *reg, *avail;
2737         int i;
2738
2739         /* First try to find a free reg */
2740         avail = NULL;
2741         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2742                 reg = &dev_priv->fence_regs[i];
2743                 if (!reg->obj)
2744                         return reg;
2745
2746                 if (!reg->pin_count)
2747                         avail = reg;
2748         }
2749
2750         if (avail == NULL)
2751                 return NULL;
2752
2753         /* None available, try to steal one or wait for a user to finish */
2754         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2755                 if (reg->pin_count)
2756                         continue;
2757
2758                 return reg;
2759         }
2760
2761         return NULL;
2762 }
2763
2764 /**
2765  * i915_gem_object_get_fence - set up fencing for an object
2766  * @obj: object to map through a fence reg
2767  *
2768  * When mapping objects through the GTT, userspace wants to be able to write
2769  * to them without having to worry about swizzling if the object is tiled.
2770  * This function walks the fence regs looking for a free one for @obj,
2771  * stealing one if it can't find any.
2772  *
2773  * It then sets up the reg based on the object's properties: address, pitch
2774  * and tiling format.
2775  *
2776  * For an untiled surface, this removes any existing fence.
2777  */
2778 int
2779 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2780 {
2781         struct drm_device *dev = obj->base.dev;
2782         struct drm_i915_private *dev_priv = dev->dev_private;
2783         bool enable = obj->tiling_mode != I915_TILING_NONE;
2784         struct drm_i915_fence_reg *reg;
2785         int ret;
2786
2787         /* Have we updated the tiling parameters upon the object and so
2788          * will need to serialise the write to the associated fence register?
2789          */
2790         if (obj->fence_dirty) {
2791                 ret = i915_gem_object_flush_fence(obj);
2792                 if (ret)
2793                         return ret;
2794         }
2795
2796         /* Just update our place in the LRU if our fence is getting reused. */
2797         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2798                 reg = &dev_priv->fence_regs[obj->fence_reg];
2799                 if (!obj->fence_dirty) {
2800                         list_move_tail(&reg->lru_list,
2801                                        &dev_priv->mm.fence_list);
2802                         return 0;
2803                 }
2804         } else if (enable) {
2805                 reg = i915_find_fence_reg(dev);
2806                 if (reg == NULL)
2807                         return -EDEADLK;
2808
2809                 if (reg->obj) {
2810                         struct drm_i915_gem_object *old = reg->obj;
2811
2812                         ret = i915_gem_object_flush_fence(old);
2813                         if (ret)
2814                                 return ret;
2815
2816                         i915_gem_object_fence_lost(old);
2817                 }
2818         } else
2819                 return 0;
2820
2821         i915_gem_object_update_fence(obj, reg, enable);
2822         obj->fence_dirty = false;
2823
2824         return 0;
2825 }
2826
2827 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2828                                      struct drm_mm_node *gtt_space,
2829                                      unsigned long cache_level)
2830 {
2831         struct drm_mm_node *other;
2832
2833         /* On non-LLC machines we have to be careful when putting differing
2834          * types of snoopable memory together to avoid the prefetcher
2835          * crossing memory domains and dieing.
2836          */
2837         if (HAS_LLC(dev))
2838                 return true;
2839
2840         if (gtt_space == NULL)
2841                 return true;
2842
2843         if (list_empty(&gtt_space->node_list))
2844                 return true;
2845
2846         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2847         if (other->allocated && !other->hole_follows && other->color != cache_level)
2848                 return false;
2849
2850         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2851         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2852                 return false;
2853
2854         return true;
2855 }
2856
2857 static void i915_gem_verify_gtt(struct drm_device *dev)
2858 {
2859 #if WATCH_GTT
2860         struct drm_i915_private *dev_priv = dev->dev_private;
2861         struct drm_i915_gem_object *obj;
2862         int err = 0;
2863
2864         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2865                 if (obj->gtt_space == NULL) {
2866                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
2867                         err++;
2868                         continue;
2869                 }
2870
2871                 if (obj->cache_level != obj->gtt_space->color) {
2872                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2873                                obj->gtt_space->start,
2874                                obj->gtt_space->start + obj->gtt_space->size,
2875                                obj->cache_level,
2876                                obj->gtt_space->color);
2877                         err++;
2878                         continue;
2879                 }
2880
2881                 if (!i915_gem_valid_gtt_space(dev,
2882                                               obj->gtt_space,
2883                                               obj->cache_level)) {
2884                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2885                                obj->gtt_space->start,
2886                                obj->gtt_space->start + obj->gtt_space->size,
2887                                obj->cache_level);
2888                         err++;
2889                         continue;
2890                 }
2891         }
2892
2893         WARN_ON(err);
2894 #endif
2895 }
2896
2897 /**
2898  * Finds free space in the GTT aperture and binds the object there.
2899  */
2900 static int
2901 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2902                             unsigned alignment,
2903                             bool map_and_fenceable,
2904                             bool nonblocking)
2905 {
2906         struct drm_device *dev = obj->base.dev;
2907         drm_i915_private_t *dev_priv = dev->dev_private;
2908         struct drm_mm_node *free_space;
2909         u32 size, fence_size, fence_alignment, unfenced_alignment;
2910         bool mappable, fenceable;
2911         int ret;
2912
2913         if (obj->madv != I915_MADV_WILLNEED) {
2914                 DRM_ERROR("Attempting to bind a purgeable object\n");
2915                 return -EINVAL;
2916         }
2917
2918         fence_size = i915_gem_get_gtt_size(dev,
2919                                            obj->base.size,
2920                                            obj->tiling_mode);
2921         fence_alignment = i915_gem_get_gtt_alignment(dev,
2922                                                      obj->base.size,
2923                                                      obj->tiling_mode);
2924         unfenced_alignment =
2925                 i915_gem_get_unfenced_gtt_alignment(dev,
2926                                                     obj->base.size,
2927                                                     obj->tiling_mode);
2928
2929         if (alignment == 0)
2930                 alignment = map_and_fenceable ? fence_alignment :
2931                                                 unfenced_alignment;
2932         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2933                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2934                 return -EINVAL;
2935         }
2936
2937         size = map_and_fenceable ? fence_size : obj->base.size;
2938
2939         /* If the object is bigger than the entire aperture, reject it early
2940          * before evicting everything in a vain attempt to find space.
2941          */
2942         if (obj->base.size >
2943             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2944                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2945                 return -E2BIG;
2946         }
2947
2948         ret = i915_gem_object_get_pages(obj);
2949         if (ret)
2950                 return ret;
2951
2952         i915_gem_object_pin_pages(obj);
2953
2954  search_free:
2955         if (map_and_fenceable)
2956                 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2957                                                                size, alignment, obj->cache_level,
2958                                                                0, dev_priv->mm.gtt_mappable_end,
2959                                                                false);
2960         else
2961                 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2962                                                       size, alignment, obj->cache_level,
2963                                                       false);
2964
2965         if (free_space != NULL) {
2966                 if (map_and_fenceable)
2967                         free_space =
2968                                 drm_mm_get_block_range_generic(free_space,
2969                                                                size, alignment, obj->cache_level,
2970                                                                0, dev_priv->mm.gtt_mappable_end,
2971                                                                false);
2972                 else
2973                         free_space =
2974                                 drm_mm_get_block_generic(free_space,
2975                                                          size, alignment, obj->cache_level,
2976                                                          false);
2977         }
2978         if (free_space == NULL) {
2979                 ret = i915_gem_evict_something(dev, size, alignment,
2980                                                obj->cache_level,
2981                                                map_and_fenceable,
2982                                                nonblocking);
2983                 if (ret) {
2984                         i915_gem_object_unpin_pages(obj);
2985                         return ret;
2986                 }
2987
2988                 goto search_free;
2989         }
2990         if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2991                                               free_space,
2992                                               obj->cache_level))) {
2993                 i915_gem_object_unpin_pages(obj);
2994                 drm_mm_put_block(free_space);
2995                 return -EINVAL;
2996         }
2997
2998         ret = i915_gem_gtt_prepare_object(obj);
2999         if (ret) {
3000                 i915_gem_object_unpin_pages(obj);
3001                 drm_mm_put_block(free_space);
3002                 return ret;
3003         }
3004
3005         list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3006         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3007
3008         obj->gtt_space = free_space;
3009         obj->gtt_offset = free_space->start;
3010
3011         fenceable =
3012                 free_space->size == fence_size &&
3013                 (free_space->start & (fence_alignment - 1)) == 0;
3014
3015         mappable =
3016                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3017
3018         obj->map_and_fenceable = mappable && fenceable;
3019
3020         i915_gem_object_unpin_pages(obj);
3021         trace_i915_gem_object_bind(obj, map_and_fenceable);
3022         i915_gem_verify_gtt(dev);
3023         return 0;
3024 }
3025
3026 void
3027 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3028 {
3029         /* If we don't have a page list set up, then we're not pinned
3030          * to GPU, and we can ignore the cache flush because it'll happen
3031          * again at bind time.
3032          */
3033         if (obj->pages == NULL)
3034                 return;
3035
3036         /* If the GPU is snooping the contents of the CPU cache,
3037          * we do not need to manually clear the CPU cache lines.  However,
3038          * the caches are only snooped when the render cache is
3039          * flushed/invalidated.  As we always have to emit invalidations
3040          * and flushes when moving into and out of the RENDER domain, correct
3041          * snooping behaviour occurs naturally as the result of our domain
3042          * tracking.
3043          */
3044         if (obj->cache_level != I915_CACHE_NONE)
3045                 return;
3046
3047         trace_i915_gem_object_clflush(obj);
3048
3049         drm_clflush_sg(obj->pages);
3050 }
3051
3052 /** Flushes the GTT write domain for the object if it's dirty. */
3053 static void
3054 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3055 {
3056         uint32_t old_write_domain;
3057
3058         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3059                 return;
3060
3061         /* No actual flushing is required for the GTT write domain.  Writes
3062          * to it immediately go to main memory as far as we know, so there's
3063          * no chipset flush.  It also doesn't land in render cache.
3064          *
3065          * However, we do have to enforce the order so that all writes through
3066          * the GTT land before any writes to the device, such as updates to
3067          * the GATT itself.
3068          */
3069         wmb();
3070
3071         old_write_domain = obj->base.write_domain;
3072         obj->base.write_domain = 0;
3073
3074         trace_i915_gem_object_change_domain(obj,
3075                                             obj->base.read_domains,
3076                                             old_write_domain);
3077 }
3078
3079 /** Flushes the CPU write domain for the object if it's dirty. */
3080 static void
3081 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3082 {
3083         uint32_t old_write_domain;
3084
3085         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3086                 return;
3087
3088         i915_gem_clflush_object(obj);
3089         i915_gem_chipset_flush(obj->base.dev);
3090         old_write_domain = obj->base.write_domain;
3091         obj->base.write_domain = 0;
3092
3093         trace_i915_gem_object_change_domain(obj,
3094                                             obj->base.read_domains,
3095                                             old_write_domain);
3096 }
3097
3098 /**
3099  * Moves a single object to the GTT read, and possibly write domain.
3100  *
3101  * This function returns when the move is complete, including waiting on
3102  * flushes to occur.
3103  */
3104 int
3105 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3106 {
3107         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3108         uint32_t old_write_domain, old_read_domains;
3109         int ret;
3110
3111         /* Not valid to be called on unbound objects. */
3112         if (obj->gtt_space == NULL)
3113                 return -EINVAL;
3114
3115         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3116                 return 0;
3117
3118         ret = i915_gem_object_wait_rendering(obj, !write);
3119         if (ret)
3120                 return ret;
3121
3122         i915_gem_object_flush_cpu_write_domain(obj);
3123
3124         old_write_domain = obj->base.write_domain;
3125         old_read_domains = obj->base.read_domains;
3126
3127         /* It should now be out of any other write domains, and we can update
3128          * the domain values for our changes.
3129          */
3130         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3131         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3132         if (write) {
3133                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3134                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3135                 obj->dirty = 1;
3136         }
3137
3138         trace_i915_gem_object_change_domain(obj,
3139                                             old_read_domains,
3140                                             old_write_domain);
3141
3142         /* And bump the LRU for this access */
3143         if (i915_gem_object_is_inactive(obj))
3144                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3145
3146         return 0;
3147 }
3148
3149 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3150                                     enum i915_cache_level cache_level)
3151 {
3152         struct drm_device *dev = obj->base.dev;
3153         drm_i915_private_t *dev_priv = dev->dev_private;
3154         int ret;
3155
3156         if (obj->cache_level == cache_level)
3157                 return 0;
3158
3159         if (obj->pin_count) {
3160                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3161                 return -EBUSY;
3162         }
3163
3164         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3165                 ret = i915_gem_object_unbind(obj);
3166                 if (ret)
3167                         return ret;
3168         }
3169
3170         if (obj->gtt_space) {
3171                 ret = i915_gem_object_finish_gpu(obj);
3172                 if (ret)
3173                         return ret;
3174
3175                 i915_gem_object_finish_gtt(obj);
3176
3177                 /* Before SandyBridge, you could not use tiling or fence
3178                  * registers with snooped memory, so relinquish any fences
3179                  * currently pointing to our region in the aperture.
3180                  */
3181                 if (INTEL_INFO(dev)->gen < 6) {
3182                         ret = i915_gem_object_put_fence(obj);
3183                         if (ret)
3184                                 return ret;
3185                 }
3186
3187                 if (obj->has_global_gtt_mapping)
3188                         i915_gem_gtt_bind_object(obj, cache_level);
3189                 if (obj->has_aliasing_ppgtt_mapping)
3190                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3191                                                obj, cache_level);
3192
3193                 obj->gtt_space->color = cache_level;
3194         }
3195
3196         if (cache_level == I915_CACHE_NONE) {
3197                 u32 old_read_domains, old_write_domain;
3198
3199                 /* If we're coming from LLC cached, then we haven't
3200                  * actually been tracking whether the data is in the
3201                  * CPU cache or not, since we only allow one bit set
3202                  * in obj->write_domain and have been skipping the clflushes.
3203                  * Just set it to the CPU cache for now.
3204                  */
3205                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3206                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3207
3208                 old_read_domains = obj->base.read_domains;
3209                 old_write_domain = obj->base.write_domain;
3210
3211                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3212                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3213
3214                 trace_i915_gem_object_change_domain(obj,
3215                                                     old_read_domains,
3216                                                     old_write_domain);
3217         }
3218
3219         obj->cache_level = cache_level;
3220         i915_gem_verify_gtt(dev);
3221         return 0;
3222 }
3223
3224 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3225                                struct drm_file *file)
3226 {
3227         struct drm_i915_gem_caching *args = data;
3228         struct drm_i915_gem_object *obj;
3229         int ret;
3230
3231         ret = i915_mutex_lock_interruptible(dev);
3232         if (ret)
3233                 return ret;
3234
3235         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3236         if (&obj->base == NULL) {
3237                 ret = -ENOENT;
3238                 goto unlock;
3239         }
3240
3241         args->caching = obj->cache_level != I915_CACHE_NONE;
3242
3243         drm_gem_object_unreference(&obj->base);
3244 unlock:
3245         mutex_unlock(&dev->struct_mutex);
3246         return ret;
3247 }
3248
3249 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3250                                struct drm_file *file)
3251 {
3252         struct drm_i915_gem_caching *args = data;
3253         struct drm_i915_gem_object *obj;
3254         enum i915_cache_level level;
3255         int ret;
3256
3257         switch (args->caching) {
3258         case I915_CACHING_NONE:
3259                 level = I915_CACHE_NONE;
3260                 break;
3261         case I915_CACHING_CACHED:
3262                 level = I915_CACHE_LLC;
3263                 break;
3264         default:
3265                 return -EINVAL;
3266         }
3267
3268         ret = i915_mutex_lock_interruptible(dev);
3269         if (ret)
3270                 return ret;
3271
3272         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3273         if (&obj->base == NULL) {
3274                 ret = -ENOENT;
3275                 goto unlock;
3276         }
3277
3278         ret = i915_gem_object_set_cache_level(obj, level);
3279
3280         drm_gem_object_unreference(&obj->base);
3281 unlock:
3282         mutex_unlock(&dev->struct_mutex);
3283         return ret;
3284 }
3285
3286 /*
3287  * Prepare buffer for display plane (scanout, cursors, etc).
3288  * Can be called from an uninterruptible phase (modesetting) and allows
3289  * any flushes to be pipelined (for pageflips).
3290  */
3291 int
3292 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3293                                      u32 alignment,
3294                                      struct intel_ring_buffer *pipelined)
3295 {
3296         u32 old_read_domains, old_write_domain;
3297         int ret;
3298
3299         if (pipelined != obj->ring) {
3300                 ret = i915_gem_object_sync(obj, pipelined);
3301                 if (ret)
3302                         return ret;
3303         }
3304
3305         /* The display engine is not coherent with the LLC cache on gen6.  As
3306          * a result, we make sure that the pinning that is about to occur is
3307          * done with uncached PTEs. This is lowest common denominator for all
3308          * chipsets.
3309          *
3310          * However for gen6+, we could do better by using the GFDT bit instead
3311          * of uncaching, which would allow us to flush all the LLC-cached data
3312          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3313          */
3314         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3315         if (ret)
3316                 return ret;
3317
3318         /* As the user may map the buffer once pinned in the display plane
3319          * (e.g. libkms for the bootup splash), we have to ensure that we
3320          * always use map_and_fenceable for all scanout buffers.
3321          */
3322         ret = i915_gem_object_pin(obj, alignment, true, false);
3323         if (ret)
3324                 return ret;
3325
3326         i915_gem_object_flush_cpu_write_domain(obj);
3327
3328         old_write_domain = obj->base.write_domain;
3329         old_read_domains = obj->base.read_domains;
3330
3331         /* It should now be out of any other write domains, and we can update
3332          * the domain values for our changes.
3333          */
3334         obj->base.write_domain = 0;
3335         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3336
3337         trace_i915_gem_object_change_domain(obj,
3338                                             old_read_domains,
3339                                             old_write_domain);
3340
3341         return 0;
3342 }
3343
3344 int
3345 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3346 {
3347         int ret;
3348
3349         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3350                 return 0;
3351
3352         ret = i915_gem_object_wait_rendering(obj, false);
3353         if (ret)
3354                 return ret;
3355
3356         /* Ensure that we invalidate the GPU's caches and TLBs. */
3357         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3358         return 0;
3359 }
3360
3361 /**
3362  * Moves a single object to the CPU read, and possibly write domain.
3363  *
3364  * This function returns when the move is complete, including waiting on
3365  * flushes to occur.
3366  */
3367 int
3368 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3369 {
3370         uint32_t old_write_domain, old_read_domains;
3371         int ret;
3372
3373         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3374                 return 0;
3375
3376         ret = i915_gem_object_wait_rendering(obj, !write);
3377         if (ret)
3378                 return ret;
3379
3380         i915_gem_object_flush_gtt_write_domain(obj);
3381
3382         old_write_domain = obj->base.write_domain;
3383         old_read_domains = obj->base.read_domains;
3384
3385         /* Flush the CPU cache if it's still invalid. */
3386         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3387                 i915_gem_clflush_object(obj);
3388
3389                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3390         }
3391
3392         /* It should now be out of any other write domains, and we can update
3393          * the domain values for our changes.
3394          */
3395         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3396
3397         /* If we're writing through the CPU, then the GPU read domains will
3398          * need to be invalidated at next use.
3399          */
3400         if (write) {
3401                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3402                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3403         }
3404
3405         trace_i915_gem_object_change_domain(obj,
3406                                             old_read_domains,
3407                                             old_write_domain);
3408
3409         return 0;
3410 }
3411
3412 /* Throttle our rendering by waiting until the ring has completed our requests
3413  * emitted over 20 msec ago.
3414  *
3415  * Note that if we were to use the current jiffies each time around the loop,
3416  * we wouldn't escape the function with any frames outstanding if the time to
3417  * render a frame was over 20ms.
3418  *
3419  * This should get us reasonable parallelism between CPU and GPU but also
3420  * relatively low latency when blocking on a particular request to finish.
3421  */
3422 static int
3423 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3424 {
3425         struct drm_i915_private *dev_priv = dev->dev_private;
3426         struct drm_i915_file_private *file_priv = file->driver_priv;
3427         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3428         struct drm_i915_gem_request *request;
3429         struct intel_ring_buffer *ring = NULL;
3430         u32 seqno = 0;
3431         int ret;
3432
3433         if (atomic_read(&dev_priv->mm.wedged))
3434                 return -EIO;
3435
3436         spin_lock(&file_priv->mm.lock);
3437         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3438                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3439                         break;
3440
3441                 ring = request->ring;
3442                 seqno = request->seqno;
3443         }
3444         spin_unlock(&file_priv->mm.lock);
3445
3446         if (seqno == 0)
3447                 return 0;
3448
3449         ret = __wait_seqno(ring, seqno, true, NULL);
3450         if (ret == 0)
3451                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3452
3453         return ret;
3454 }
3455
3456 int
3457 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3458                     uint32_t alignment,
3459                     bool map_and_fenceable,
3460                     bool nonblocking)
3461 {
3462         int ret;
3463
3464         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3465                 return -EBUSY;
3466
3467         if (obj->gtt_space != NULL) {
3468                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3469                     (map_and_fenceable && !obj->map_and_fenceable)) {
3470                         WARN(obj->pin_count,
3471                              "bo is already pinned with incorrect alignment:"
3472                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3473                              " obj->map_and_fenceable=%d\n",
3474                              obj->gtt_offset, alignment,
3475                              map_and_fenceable,
3476                              obj->map_and_fenceable);
3477                         ret = i915_gem_object_unbind(obj);
3478                         if (ret)
3479                                 return ret;
3480                 }
3481         }
3482
3483         if (obj->gtt_space == NULL) {
3484                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3485
3486                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3487                                                   map_and_fenceable,
3488                                                   nonblocking);
3489                 if (ret)
3490                         return ret;
3491
3492                 if (!dev_priv->mm.aliasing_ppgtt)
3493                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3494         }
3495
3496         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3497                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3498
3499         obj->pin_count++;
3500         obj->pin_mappable |= map_and_fenceable;
3501
3502         return 0;
3503 }
3504
3505 void
3506 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3507 {
3508         BUG_ON(obj->pin_count == 0);
3509         BUG_ON(obj->gtt_space == NULL);
3510
3511         if (--obj->pin_count == 0)
3512                 obj->pin_mappable = false;
3513 }
3514
3515 int
3516 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3517                    struct drm_file *file)
3518 {
3519         struct drm_i915_gem_pin *args = data;
3520         struct drm_i915_gem_object *obj;
3521         int ret;
3522
3523         ret = i915_mutex_lock_interruptible(dev);
3524         if (ret)
3525                 return ret;
3526
3527         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3528         if (&obj->base == NULL) {
3529                 ret = -ENOENT;
3530                 goto unlock;
3531         }
3532
3533         if (obj->madv != I915_MADV_WILLNEED) {
3534                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3535                 ret = -EINVAL;
3536                 goto out;
3537         }
3538
3539         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3540                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3541                           args->handle);
3542                 ret = -EINVAL;
3543                 goto out;
3544         }
3545
3546         obj->user_pin_count++;
3547         obj->pin_filp = file;
3548         if (obj->user_pin_count == 1) {
3549                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3550                 if (ret)
3551                         goto out;
3552         }
3553
3554         /* XXX - flush the CPU caches for pinned objects
3555          * as the X server doesn't manage domains yet
3556          */
3557         i915_gem_object_flush_cpu_write_domain(obj);
3558         args->offset = obj->gtt_offset;
3559 out:
3560         drm_gem_object_unreference(&obj->base);
3561 unlock:
3562         mutex_unlock(&dev->struct_mutex);
3563         return ret;
3564 }
3565
3566 int
3567 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3568                      struct drm_file *file)
3569 {
3570         struct drm_i915_gem_pin *args = data;
3571         struct drm_i915_gem_object *obj;
3572         int ret;
3573
3574         ret = i915_mutex_lock_interruptible(dev);
3575         if (ret)
3576                 return ret;
3577
3578         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3579         if (&obj->base == NULL) {
3580                 ret = -ENOENT;
3581                 goto unlock;
3582         }
3583
3584         if (obj->pin_filp != file) {
3585                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3586                           args->handle);
3587                 ret = -EINVAL;
3588                 goto out;
3589         }
3590         obj->user_pin_count--;
3591         if (obj->user_pin_count == 0) {
3592                 obj->pin_filp = NULL;
3593                 i915_gem_object_unpin(obj);
3594         }
3595
3596 out:
3597         drm_gem_object_unreference(&obj->base);
3598 unlock:
3599         mutex_unlock(&dev->struct_mutex);
3600         return ret;
3601 }
3602
3603 int
3604 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3605                     struct drm_file *file)
3606 {
3607         struct drm_i915_gem_busy *args = data;
3608         struct drm_i915_gem_object *obj;
3609         int ret;
3610
3611         ret = i915_mutex_lock_interruptible(dev);
3612         if (ret)
3613                 return ret;
3614
3615         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3616         if (&obj->base == NULL) {
3617                 ret = -ENOENT;
3618                 goto unlock;
3619         }
3620
3621         /* Count all active objects as busy, even if they are currently not used
3622          * by the gpu. Users of this interface expect objects to eventually
3623          * become non-busy without any further actions, therefore emit any
3624          * necessary flushes here.
3625          */
3626         ret = i915_gem_object_flush_active(obj);
3627
3628         args->busy = obj->active;
3629         if (obj->ring) {
3630                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3631                 args->busy |= intel_ring_flag(obj->ring) << 16;
3632         }
3633
3634         drm_gem_object_unreference(&obj->base);
3635 unlock:
3636         mutex_unlock(&dev->struct_mutex);
3637         return ret;
3638 }
3639
3640 int
3641 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3642                         struct drm_file *file_priv)
3643 {
3644         return i915_gem_ring_throttle(dev, file_priv);
3645 }
3646
3647 int
3648 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3649                        struct drm_file *file_priv)
3650 {
3651         struct drm_i915_gem_madvise *args = data;
3652         struct drm_i915_gem_object *obj;
3653         int ret;
3654
3655         switch (args->madv) {
3656         case I915_MADV_DONTNEED:
3657         case I915_MADV_WILLNEED:
3658             break;
3659         default:
3660             return -EINVAL;
3661         }
3662
3663         ret = i915_mutex_lock_interruptible(dev);
3664         if (ret)
3665                 return ret;
3666
3667         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3668         if (&obj->base == NULL) {
3669                 ret = -ENOENT;
3670                 goto unlock;
3671         }
3672
3673         if (obj->pin_count) {
3674                 ret = -EINVAL;
3675                 goto out;
3676         }
3677
3678         if (obj->madv != __I915_MADV_PURGED)
3679                 obj->madv = args->madv;
3680
3681         /* if the object is no longer attached, discard its backing storage */
3682         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3683                 i915_gem_object_truncate(obj);
3684
3685         args->retained = obj->madv != __I915_MADV_PURGED;
3686
3687 out:
3688         drm_gem_object_unreference(&obj->base);
3689 unlock:
3690         mutex_unlock(&dev->struct_mutex);
3691         return ret;
3692 }
3693
3694 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3695                           const struct drm_i915_gem_object_ops *ops)
3696 {
3697         INIT_LIST_HEAD(&obj->mm_list);
3698         INIT_LIST_HEAD(&obj->gtt_list);
3699         INIT_LIST_HEAD(&obj->ring_list);
3700         INIT_LIST_HEAD(&obj->exec_list);
3701
3702         obj->ops = ops;
3703
3704         obj->fence_reg = I915_FENCE_REG_NONE;
3705         obj->madv = I915_MADV_WILLNEED;
3706         /* Avoid an unnecessary call to unbind on the first bind. */
3707         obj->map_and_fenceable = true;
3708
3709         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3710 }
3711
3712 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3713         .get_pages = i915_gem_object_get_pages_gtt,
3714         .put_pages = i915_gem_object_put_pages_gtt,
3715 };
3716
3717 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3718                                                   size_t size)
3719 {
3720         struct drm_i915_gem_object *obj;
3721         struct address_space *mapping;
3722         u32 mask;
3723
3724         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3725         if (obj == NULL)
3726                 return NULL;
3727
3728         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3729                 kfree(obj);
3730                 return NULL;
3731         }
3732
3733         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3734         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3735                 /* 965gm cannot relocate objects above 4GiB. */
3736                 mask &= ~__GFP_HIGHMEM;
3737                 mask |= __GFP_DMA32;
3738         }
3739
3740         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3741         mapping_set_gfp_mask(mapping, mask);
3742
3743         i915_gem_object_init(obj, &i915_gem_object_ops);
3744
3745         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3746         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3747
3748         if (HAS_LLC(dev)) {
3749                 /* On some devices, we can have the GPU use the LLC (the CPU
3750                  * cache) for about a 10% performance improvement
3751                  * compared to uncached.  Graphics requests other than
3752                  * display scanout are coherent with the CPU in
3753                  * accessing this cache.  This means in this mode we
3754                  * don't need to clflush on the CPU side, and on the
3755                  * GPU side we only need to flush internal caches to
3756                  * get data visible to the CPU.
3757                  *
3758                  * However, we maintain the display planes as UC, and so
3759                  * need to rebind when first used as such.
3760                  */
3761                 obj->cache_level = I915_CACHE_LLC;
3762         } else
3763                 obj->cache_level = I915_CACHE_NONE;
3764
3765         return obj;
3766 }
3767
3768 int i915_gem_init_object(struct drm_gem_object *obj)
3769 {
3770         BUG();
3771
3772         return 0;
3773 }
3774
3775 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3776 {
3777         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3778         struct drm_device *dev = obj->base.dev;
3779         drm_i915_private_t *dev_priv = dev->dev_private;
3780
3781         trace_i915_gem_object_destroy(obj);
3782
3783         if (obj->phys_obj)
3784                 i915_gem_detach_phys_object(dev, obj);
3785
3786         obj->pin_count = 0;
3787         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3788                 bool was_interruptible;
3789
3790                 was_interruptible = dev_priv->mm.interruptible;
3791                 dev_priv->mm.interruptible = false;
3792
3793                 WARN_ON(i915_gem_object_unbind(obj));
3794
3795                 dev_priv->mm.interruptible = was_interruptible;
3796         }
3797
3798         obj->pages_pin_count = 0;
3799         i915_gem_object_put_pages(obj);
3800         i915_gem_object_free_mmap_offset(obj);
3801
3802         BUG_ON(obj->pages);
3803
3804         if (obj->base.import_attach)
3805                 drm_prime_gem_destroy(&obj->base, NULL);
3806
3807         drm_gem_object_release(&obj->base);
3808         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3809
3810         kfree(obj->bit_17);
3811         kfree(obj);
3812 }
3813
3814 int
3815 i915_gem_idle(struct drm_device *dev)
3816 {
3817         drm_i915_private_t *dev_priv = dev->dev_private;
3818         int ret;
3819
3820         mutex_lock(&dev->struct_mutex);
3821
3822         if (dev_priv->mm.suspended) {
3823                 mutex_unlock(&dev->struct_mutex);
3824                 return 0;
3825         }
3826
3827         ret = i915_gpu_idle(dev);
3828         if (ret) {
3829                 mutex_unlock(&dev->struct_mutex);
3830                 return ret;
3831         }
3832         i915_gem_retire_requests(dev);
3833
3834         /* Under UMS, be paranoid and evict. */
3835         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3836                 i915_gem_evict_everything(dev);
3837
3838         i915_gem_reset_fences(dev);
3839
3840         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3841          * We need to replace this with a semaphore, or something.
3842          * And not confound mm.suspended!
3843          */
3844         dev_priv->mm.suspended = 1;
3845         del_timer_sync(&dev_priv->hangcheck_timer);
3846
3847         i915_kernel_lost_context(dev);
3848         i915_gem_cleanup_ringbuffer(dev);
3849
3850         mutex_unlock(&dev->struct_mutex);
3851
3852         /* Cancel the retire work handler, which should be idle now. */
3853         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3854
3855         return 0;
3856 }
3857
3858 void i915_gem_l3_remap(struct drm_device *dev)
3859 {
3860         drm_i915_private_t *dev_priv = dev->dev_private;
3861         u32 misccpctl;
3862         int i;
3863
3864         if (!IS_IVYBRIDGE(dev))
3865                 return;
3866
3867         if (!dev_priv->l3_parity.remap_info)
3868                 return;
3869
3870         misccpctl = I915_READ(GEN7_MISCCPCTL);
3871         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3872         POSTING_READ(GEN7_MISCCPCTL);
3873
3874         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3875                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3876                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3877                         DRM_DEBUG("0x%x was already programmed to %x\n",
3878                                   GEN7_L3LOG_BASE + i, remap);
3879                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3880                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
3881                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3882         }
3883
3884         /* Make sure all the writes land before disabling dop clock gating */
3885         POSTING_READ(GEN7_L3LOG_BASE);
3886
3887         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3888 }
3889
3890 void i915_gem_init_swizzling(struct drm_device *dev)
3891 {
3892         drm_i915_private_t *dev_priv = dev->dev_private;
3893
3894         if (INTEL_INFO(dev)->gen < 5 ||
3895             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3896                 return;
3897
3898         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3899                                  DISP_TILE_SURFACE_SWIZZLING);
3900
3901         if (IS_GEN5(dev))
3902                 return;
3903
3904         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3905         if (IS_GEN6(dev))
3906                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3907         else
3908                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3909 }
3910
3911 static bool
3912 intel_enable_blt(struct drm_device *dev)
3913 {
3914         if (!HAS_BLT(dev))
3915                 return false;
3916
3917         /* The blitter was dysfunctional on early prototypes */
3918         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3919                 DRM_INFO("BLT not supported on this pre-production hardware;"
3920                          " graphics performance will be degraded.\n");
3921                 return false;
3922         }
3923
3924         return true;
3925 }
3926
3927 int
3928 i915_gem_init_hw(struct drm_device *dev)
3929 {
3930         drm_i915_private_t *dev_priv = dev->dev_private;
3931         int ret;
3932
3933         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3934                 return -EIO;
3935
3936         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3937                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3938
3939         i915_gem_l3_remap(dev);
3940
3941         i915_gem_init_swizzling(dev);
3942
3943         ret = intel_init_render_ring_buffer(dev);
3944         if (ret)
3945                 return ret;
3946
3947         if (HAS_BSD(dev)) {
3948                 ret = intel_init_bsd_ring_buffer(dev);
3949                 if (ret)
3950                         goto cleanup_render_ring;
3951         }
3952
3953         if (intel_enable_blt(dev)) {
3954                 ret = intel_init_blt_ring_buffer(dev);
3955                 if (ret)
3956                         goto cleanup_bsd_ring;
3957         }
3958
3959         dev_priv->next_seqno = 1;
3960
3961         /*
3962          * XXX: There was some w/a described somewhere suggesting loading
3963          * contexts before PPGTT.
3964          */
3965         i915_gem_context_init(dev);
3966         i915_gem_init_ppgtt(dev);
3967
3968         return 0;
3969
3970 cleanup_bsd_ring:
3971         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3972 cleanup_render_ring:
3973         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3974         return ret;
3975 }
3976
3977 static bool
3978 intel_enable_ppgtt(struct drm_device *dev)
3979 {
3980         if (i915_enable_ppgtt >= 0)
3981                 return i915_enable_ppgtt;
3982
3983 #ifdef CONFIG_INTEL_IOMMU
3984         /* Disable ppgtt on SNB if VT-d is on. */
3985         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3986                 return false;
3987 #endif
3988
3989         return true;
3990 }
3991
3992 int i915_gem_init(struct drm_device *dev)
3993 {
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         unsigned long gtt_size, mappable_size;
3996         int ret;
3997
3998         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3999         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4000
4001         mutex_lock(&dev->struct_mutex);
4002         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4003                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4004                  * aperture accordingly when using aliasing ppgtt. */
4005                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4006
4007                 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4008
4009                 ret = i915_gem_init_aliasing_ppgtt(dev);
4010                 if (ret) {
4011                         mutex_unlock(&dev->struct_mutex);
4012                         return ret;
4013                 }
4014         } else {
4015                 /* Let GEM Manage all of the aperture.
4016                  *
4017                  * However, leave one page at the end still bound to the scratch
4018                  * page.  There are a number of places where the hardware
4019                  * apparently prefetches past the end of the object, and we've
4020                  * seen multiple hangs with the GPU head pointer stuck in a
4021                  * batchbuffer bound at the last page of the aperture.  One page
4022                  * should be enough to keep any prefetching inside of the
4023                  * aperture.
4024                  */
4025                 i915_gem_init_global_gtt(dev, 0, mappable_size,
4026                                          gtt_size);
4027         }
4028
4029         ret = i915_gem_init_hw(dev);
4030         mutex_unlock(&dev->struct_mutex);
4031         if (ret) {
4032                 i915_gem_cleanup_aliasing_ppgtt(dev);
4033                 return ret;
4034         }
4035
4036         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4037         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4038                 dev_priv->dri1.allow_batchbuffer = 1;
4039         return 0;
4040 }
4041
4042 void
4043 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4044 {
4045         drm_i915_private_t *dev_priv = dev->dev_private;
4046         struct intel_ring_buffer *ring;
4047         int i;
4048
4049         for_each_ring(ring, dev_priv, i)
4050                 intel_cleanup_ring_buffer(ring);
4051 }
4052
4053 int
4054 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4055                        struct drm_file *file_priv)
4056 {
4057         drm_i915_private_t *dev_priv = dev->dev_private;
4058         int ret;
4059
4060         if (drm_core_check_feature(dev, DRIVER_MODESET))
4061                 return 0;
4062
4063         if (atomic_read(&dev_priv->mm.wedged)) {
4064                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4065                 atomic_set(&dev_priv->mm.wedged, 0);
4066         }
4067
4068         mutex_lock(&dev->struct_mutex);
4069         dev_priv->mm.suspended = 0;
4070
4071         ret = i915_gem_init_hw(dev);
4072         if (ret != 0) {
4073                 mutex_unlock(&dev->struct_mutex);
4074                 return ret;
4075         }
4076
4077         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4078         mutex_unlock(&dev->struct_mutex);
4079
4080         ret = drm_irq_install(dev);
4081         if (ret)
4082                 goto cleanup_ringbuffer;
4083
4084         return 0;
4085
4086 cleanup_ringbuffer:
4087         mutex_lock(&dev->struct_mutex);
4088         i915_gem_cleanup_ringbuffer(dev);
4089         dev_priv->mm.suspended = 1;
4090         mutex_unlock(&dev->struct_mutex);
4091
4092         return ret;
4093 }
4094
4095 int
4096 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4097                        struct drm_file *file_priv)
4098 {
4099         if (drm_core_check_feature(dev, DRIVER_MODESET))
4100                 return 0;
4101
4102         drm_irq_uninstall(dev);
4103         return i915_gem_idle(dev);
4104 }
4105
4106 void
4107 i915_gem_lastclose(struct drm_device *dev)
4108 {
4109         int ret;
4110
4111         if (drm_core_check_feature(dev, DRIVER_MODESET))
4112                 return;
4113
4114         ret = i915_gem_idle(dev);
4115         if (ret)
4116                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4117 }
4118
4119 static void
4120 init_ring_lists(struct intel_ring_buffer *ring)
4121 {
4122         INIT_LIST_HEAD(&ring->active_list);
4123         INIT_LIST_HEAD(&ring->request_list);
4124 }
4125
4126 void
4127 i915_gem_load(struct drm_device *dev)
4128 {
4129         int i;
4130         drm_i915_private_t *dev_priv = dev->dev_private;
4131
4132         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4133         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4134         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4135         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4136         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4137         for (i = 0; i < I915_NUM_RINGS; i++)
4138                 init_ring_lists(&dev_priv->ring[i]);
4139         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4140                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4141         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4142                           i915_gem_retire_work_handler);
4143         init_completion(&dev_priv->error_completion);
4144
4145         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4146         if (IS_GEN3(dev)) {
4147                 I915_WRITE(MI_ARB_STATE,
4148                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4149         }
4150
4151         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4152
4153         /* Old X drivers will take 0-2 for front, back, depth buffers */
4154         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4155                 dev_priv->fence_reg_start = 3;
4156
4157         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4158                 dev_priv->num_fence_regs = 16;
4159         else
4160                 dev_priv->num_fence_regs = 8;
4161
4162         /* Initialize fence registers to zero */
4163         i915_gem_reset_fences(dev);
4164
4165         i915_gem_detect_bit_6_swizzle(dev);
4166         init_waitqueue_head(&dev_priv->pending_flip_queue);
4167
4168         dev_priv->mm.interruptible = true;
4169
4170         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4171         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4172         register_shrinker(&dev_priv->mm.inactive_shrinker);
4173 }
4174
4175 /*
4176  * Create a physically contiguous memory object for this object
4177  * e.g. for cursor + overlay regs
4178  */
4179 static int i915_gem_init_phys_object(struct drm_device *dev,
4180                                      int id, int size, int align)
4181 {
4182         drm_i915_private_t *dev_priv = dev->dev_private;
4183         struct drm_i915_gem_phys_object *phys_obj;
4184         int ret;
4185
4186         if (dev_priv->mm.phys_objs[id - 1] || !size)
4187                 return 0;
4188
4189         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4190         if (!phys_obj)
4191                 return -ENOMEM;
4192
4193         phys_obj->id = id;
4194
4195         phys_obj->handle = drm_pci_alloc(dev, size, align);
4196         if (!phys_obj->handle) {
4197                 ret = -ENOMEM;
4198                 goto kfree_obj;
4199         }
4200 #ifdef CONFIG_X86
4201         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4202 #endif
4203
4204         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4205
4206         return 0;
4207 kfree_obj:
4208         kfree(phys_obj);
4209         return ret;
4210 }
4211
4212 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4213 {
4214         drm_i915_private_t *dev_priv = dev->dev_private;
4215         struct drm_i915_gem_phys_object *phys_obj;
4216
4217         if (!dev_priv->mm.phys_objs[id - 1])
4218                 return;
4219
4220         phys_obj = dev_priv->mm.phys_objs[id - 1];
4221         if (phys_obj->cur_obj) {
4222                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4223         }
4224
4225 #ifdef CONFIG_X86
4226         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4227 #endif
4228         drm_pci_free(dev, phys_obj->handle);
4229         kfree(phys_obj);
4230         dev_priv->mm.phys_objs[id - 1] = NULL;
4231 }
4232
4233 void i915_gem_free_all_phys_object(struct drm_device *dev)
4234 {
4235         int i;
4236
4237         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4238                 i915_gem_free_phys_object(dev, i);
4239 }
4240
4241 void i915_gem_detach_phys_object(struct drm_device *dev,
4242                                  struct drm_i915_gem_object *obj)
4243 {
4244         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4245         char *vaddr;
4246         int i;
4247         int page_count;
4248
4249         if (!obj->phys_obj)
4250                 return;
4251         vaddr = obj->phys_obj->handle->vaddr;
4252
4253         page_count = obj->base.size / PAGE_SIZE;
4254         for (i = 0; i < page_count; i++) {
4255                 struct page *page = shmem_read_mapping_page(mapping, i);
4256                 if (!IS_ERR(page)) {
4257                         char *dst = kmap_atomic(page);
4258                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4259                         kunmap_atomic(dst);
4260
4261                         drm_clflush_pages(&page, 1);
4262
4263                         set_page_dirty(page);
4264                         mark_page_accessed(page);
4265                         page_cache_release(page);
4266                 }
4267         }
4268         i915_gem_chipset_flush(dev);
4269
4270         obj->phys_obj->cur_obj = NULL;
4271         obj->phys_obj = NULL;
4272 }
4273
4274 int
4275 i915_gem_attach_phys_object(struct drm_device *dev,
4276                             struct drm_i915_gem_object *obj,
4277                             int id,
4278                             int align)
4279 {
4280         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4281         drm_i915_private_t *dev_priv = dev->dev_private;
4282         int ret = 0;
4283         int page_count;
4284         int i;
4285
4286         if (id > I915_MAX_PHYS_OBJECT)
4287                 return -EINVAL;
4288
4289         if (obj->phys_obj) {
4290                 if (obj->phys_obj->id == id)
4291                         return 0;
4292                 i915_gem_detach_phys_object(dev, obj);
4293         }
4294
4295         /* create a new object */
4296         if (!dev_priv->mm.phys_objs[id - 1]) {
4297                 ret = i915_gem_init_phys_object(dev, id,
4298                                                 obj->base.size, align);
4299                 if (ret) {
4300                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4301                                   id, obj->base.size);
4302                         return ret;
4303                 }
4304         }
4305
4306         /* bind to the object */
4307         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4308         obj->phys_obj->cur_obj = obj;
4309
4310         page_count = obj->base.size / PAGE_SIZE;
4311
4312         for (i = 0; i < page_count; i++) {
4313                 struct page *page;
4314                 char *dst, *src;
4315
4316                 page = shmem_read_mapping_page(mapping, i);
4317                 if (IS_ERR(page))
4318                         return PTR_ERR(page);
4319
4320                 src = kmap_atomic(page);
4321                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4322                 memcpy(dst, src, PAGE_SIZE);
4323                 kunmap_atomic(src);
4324
4325                 mark_page_accessed(page);
4326                 page_cache_release(page);
4327         }
4328
4329         return 0;
4330 }
4331
4332 static int
4333 i915_gem_phys_pwrite(struct drm_device *dev,
4334                      struct drm_i915_gem_object *obj,
4335                      struct drm_i915_gem_pwrite *args,
4336                      struct drm_file *file_priv)
4337 {
4338         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4339         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4340
4341         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4342                 unsigned long unwritten;
4343
4344                 /* The physical object once assigned is fixed for the lifetime
4345                  * of the obj, so we can safely drop the lock and continue
4346                  * to access vaddr.
4347                  */
4348                 mutex_unlock(&dev->struct_mutex);
4349                 unwritten = copy_from_user(vaddr, user_data, args->size);
4350                 mutex_lock(&dev->struct_mutex);
4351                 if (unwritten)
4352                         return -EFAULT;
4353         }
4354
4355         i915_gem_chipset_flush(dev);
4356         return 0;
4357 }
4358
4359 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4360 {
4361         struct drm_i915_file_private *file_priv = file->driver_priv;
4362
4363         /* Clean up our request list when the client is going away, so that
4364          * later retire_requests won't dereference our soon-to-be-gone
4365          * file_priv.
4366          */
4367         spin_lock(&file_priv->mm.lock);
4368         while (!list_empty(&file_priv->mm.request_list)) {
4369                 struct drm_i915_gem_request *request;
4370
4371                 request = list_first_entry(&file_priv->mm.request_list,
4372                                            struct drm_i915_gem_request,
4373                                            client_list);
4374                 list_del(&request->client_list);
4375                 request->file_priv = NULL;
4376         }
4377         spin_unlock(&file_priv->mm.lock);
4378 }
4379
4380 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4381 {
4382         if (!mutex_is_locked(mutex))
4383                 return false;
4384
4385 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4386         return mutex->owner == task;
4387 #else
4388         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4389         return false;
4390 #endif
4391 }
4392
4393 static int
4394 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4395 {
4396         struct drm_i915_private *dev_priv =
4397                 container_of(shrinker,
4398                              struct drm_i915_private,
4399                              mm.inactive_shrinker);
4400         struct drm_device *dev = dev_priv->dev;
4401         struct drm_i915_gem_object *obj;
4402         int nr_to_scan = sc->nr_to_scan;
4403         bool unlock = true;
4404         int cnt;
4405
4406         if (!mutex_trylock(&dev->struct_mutex)) {
4407                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4408                         return 0;
4409
4410                 unlock = false;
4411         }
4412
4413         if (nr_to_scan) {
4414                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4415                 if (nr_to_scan > 0)
4416                         i915_gem_shrink_all(dev_priv);
4417         }
4418
4419         cnt = 0;
4420         list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4421                 if (obj->pages_pin_count == 0)
4422                         cnt += obj->base.size >> PAGE_SHIFT;
4423         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4424                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4425                         cnt += obj->base.size >> PAGE_SHIFT;
4426
4427         if (unlock)
4428                 mutex_unlock(&dev->struct_mutex);
4429         return cnt;
4430 }