2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 static __must_check int
44 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
45 struct i915_address_space *vm,
47 bool map_and_fenceable,
49 static int i915_gem_phys_pwrite(struct drm_device *dev,
50 struct drm_i915_gem_object *obj,
51 struct drm_i915_gem_pwrite *args,
52 struct drm_file *file);
54 static void i915_gem_write_fence(struct drm_device *dev, int reg,
55 struct drm_i915_gem_object *obj);
56 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
57 struct drm_i915_fence_reg *fence,
60 static unsigned long i915_gem_inactive_count(struct shrinker *shrinker,
61 struct shrink_control *sc);
62 static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker,
63 struct shrink_control *sc);
64 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
65 static long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
66 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
68 static bool cpu_cache_is_coherent(struct drm_device *dev,
69 enum i915_cache_level level)
71 return HAS_LLC(dev) || level != I915_CACHE_NONE;
74 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
76 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
79 return obj->pin_display;
82 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
85 i915_gem_release_mmap(obj);
87 /* As we do not have an associated fence register, we will force
88 * a tiling change if we ever need to acquire one.
90 obj->fence_dirty = false;
91 obj->fence_reg = I915_FENCE_REG_NONE;
94 /* some bookkeeping */
95 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
98 spin_lock(&dev_priv->mm.object_stat_lock);
99 dev_priv->mm.object_count++;
100 dev_priv->mm.object_memory += size;
101 spin_unlock(&dev_priv->mm.object_stat_lock);
104 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
107 spin_lock(&dev_priv->mm.object_stat_lock);
108 dev_priv->mm.object_count--;
109 dev_priv->mm.object_memory -= size;
110 spin_unlock(&dev_priv->mm.object_stat_lock);
114 i915_gem_wait_for_error(struct i915_gpu_error *error)
118 #define EXIT_COND (!i915_reset_in_progress(error) || \
119 i915_terminally_wedged(error))
124 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
125 * userspace. If it takes that long something really bad is going on and
126 * we should simply try to bail out and fail as gracefully as possible.
128 ret = wait_event_interruptible_timeout(error->reset_queue,
132 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
134 } else if (ret < 0) {
142 int i915_mutex_lock_interruptible(struct drm_device *dev)
144 struct drm_i915_private *dev_priv = dev->dev_private;
147 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
151 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 WARN_ON(i915_verify_lists(dev));
160 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
162 return i915_gem_obj_bound_any(obj) && !obj->active;
166 i915_gem_init_ioctl(struct drm_device *dev, void *data,
167 struct drm_file *file)
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct drm_i915_gem_init *args = data;
172 if (drm_core_check_feature(dev, DRIVER_MODESET))
175 if (args->gtt_start >= args->gtt_end ||
176 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
179 /* GEM with user mode setting was never supported on ilk and later. */
180 if (INTEL_INFO(dev)->gen >= 5)
183 mutex_lock(&dev->struct_mutex);
184 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
186 dev_priv->gtt.mappable_end = args->gtt_end;
187 mutex_unlock(&dev->struct_mutex);
193 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
194 struct drm_file *file)
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 struct drm_i915_gem_get_aperture *args = data;
198 struct drm_i915_gem_object *obj;
202 mutex_lock(&dev->struct_mutex);
203 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
205 pinned += i915_gem_obj_ggtt_size(obj);
206 mutex_unlock(&dev->struct_mutex);
208 args->aper_size = dev_priv->gtt.base.total;
209 args->aper_available_size = args->aper_size - pinned;
214 void *i915_gem_object_alloc(struct drm_device *dev)
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
220 void i915_gem_object_free(struct drm_i915_gem_object *obj)
222 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
223 kmem_cache_free(dev_priv->slab, obj);
227 i915_gem_create(struct drm_file *file,
228 struct drm_device *dev,
232 struct drm_i915_gem_object *obj;
236 size = roundup(size, PAGE_SIZE);
240 /* Allocate the new object */
241 obj = i915_gem_alloc_object(dev, size);
245 ret = drm_gem_handle_create(file, &obj->base, &handle);
246 /* drop reference from allocate - handle holds it now */
247 drm_gem_object_unreference_unlocked(&obj->base);
256 i915_gem_dumb_create(struct drm_file *file,
257 struct drm_device *dev,
258 struct drm_mode_create_dumb *args)
260 /* have to work out size/pitch and return them */
261 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
262 args->size = args->pitch * args->height;
263 return i915_gem_create(file, dev,
264 args->size, &args->handle);
268 * Creates a new mm object and returns a handle to it.
271 i915_gem_create_ioctl(struct drm_device *dev, void *data,
272 struct drm_file *file)
274 struct drm_i915_gem_create *args = data;
276 return i915_gem_create(file, dev,
277 args->size, &args->handle);
281 __copy_to_user_swizzled(char __user *cpu_vaddr,
282 const char *gpu_vaddr, int gpu_offset,
285 int ret, cpu_offset = 0;
288 int cacheline_end = ALIGN(gpu_offset + 1, 64);
289 int this_length = min(cacheline_end - gpu_offset, length);
290 int swizzled_gpu_offset = gpu_offset ^ 64;
292 ret = __copy_to_user(cpu_vaddr + cpu_offset,
293 gpu_vaddr + swizzled_gpu_offset,
298 cpu_offset += this_length;
299 gpu_offset += this_length;
300 length -= this_length;
307 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
308 const char __user *cpu_vaddr,
311 int ret, cpu_offset = 0;
314 int cacheline_end = ALIGN(gpu_offset + 1, 64);
315 int this_length = min(cacheline_end - gpu_offset, length);
316 int swizzled_gpu_offset = gpu_offset ^ 64;
318 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
319 cpu_vaddr + cpu_offset,
324 cpu_offset += this_length;
325 gpu_offset += this_length;
326 length -= this_length;
332 /* Per-page copy function for the shmem pread fastpath.
333 * Flushes invalid cachelines before reading the target if
334 * needs_clflush is set. */
336 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
337 char __user *user_data,
338 bool page_do_bit17_swizzling, bool needs_clflush)
343 if (unlikely(page_do_bit17_swizzling))
346 vaddr = kmap_atomic(page);
348 drm_clflush_virt_range(vaddr + shmem_page_offset,
350 ret = __copy_to_user_inatomic(user_data,
351 vaddr + shmem_page_offset,
353 kunmap_atomic(vaddr);
355 return ret ? -EFAULT : 0;
359 shmem_clflush_swizzled_range(char *addr, unsigned long length,
362 if (unlikely(swizzled)) {
363 unsigned long start = (unsigned long) addr;
364 unsigned long end = (unsigned long) addr + length;
366 /* For swizzling simply ensure that we always flush both
367 * channels. Lame, but simple and it works. Swizzled
368 * pwrite/pread is far from a hotpath - current userspace
369 * doesn't use it at all. */
370 start = round_down(start, 128);
371 end = round_up(end, 128);
373 drm_clflush_virt_range((void *)start, end - start);
375 drm_clflush_virt_range(addr, length);
380 /* Only difference to the fast-path function is that this can handle bit17
381 * and uses non-atomic copy and kmap functions. */
383 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
384 char __user *user_data,
385 bool page_do_bit17_swizzling, bool needs_clflush)
392 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
394 page_do_bit17_swizzling);
396 if (page_do_bit17_swizzling)
397 ret = __copy_to_user_swizzled(user_data,
398 vaddr, shmem_page_offset,
401 ret = __copy_to_user(user_data,
402 vaddr + shmem_page_offset,
406 return ret ? - EFAULT : 0;
410 i915_gem_shmem_pread(struct drm_device *dev,
411 struct drm_i915_gem_object *obj,
412 struct drm_i915_gem_pread *args,
413 struct drm_file *file)
415 char __user *user_data;
418 int shmem_page_offset, page_length, ret = 0;
419 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
421 int needs_clflush = 0;
422 struct sg_page_iter sg_iter;
424 user_data = to_user_ptr(args->data_ptr);
427 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
429 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
430 /* If we're not in the cpu read domain, set ourself into the gtt
431 * read domain and manually flush cachelines (if required). This
432 * optimizes for the case when the gpu will dirty the data
433 * anyway again before the next pread happens. */
434 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
435 if (i915_gem_obj_bound_any(obj)) {
436 ret = i915_gem_object_set_to_gtt_domain(obj, false);
442 ret = i915_gem_object_get_pages(obj);
446 i915_gem_object_pin_pages(obj);
448 offset = args->offset;
450 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
451 offset >> PAGE_SHIFT) {
452 struct page *page = sg_page_iter_page(&sg_iter);
457 /* Operation in this page
459 * shmem_page_offset = offset within page in shmem file
460 * page_length = bytes to copy for this page
462 shmem_page_offset = offset_in_page(offset);
463 page_length = remain;
464 if ((shmem_page_offset + page_length) > PAGE_SIZE)
465 page_length = PAGE_SIZE - shmem_page_offset;
467 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
468 (page_to_phys(page) & (1 << 17)) != 0;
470 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
471 user_data, page_do_bit17_swizzling,
476 mutex_unlock(&dev->struct_mutex);
478 if (likely(!i915_prefault_disable) && !prefaulted) {
479 ret = fault_in_multipages_writeable(user_data, remain);
480 /* Userspace is tricking us, but we've already clobbered
481 * its pages with the prefault and promised to write the
482 * data up to the first fault. Hence ignore any errors
483 * and just continue. */
488 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
489 user_data, page_do_bit17_swizzling,
492 mutex_lock(&dev->struct_mutex);
495 mark_page_accessed(page);
500 remain -= page_length;
501 user_data += page_length;
502 offset += page_length;
506 i915_gem_object_unpin_pages(obj);
512 * Reads data from the object referenced by handle.
514 * On error, the contents of *data are undefined.
517 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
518 struct drm_file *file)
520 struct drm_i915_gem_pread *args = data;
521 struct drm_i915_gem_object *obj;
527 if (!access_ok(VERIFY_WRITE,
528 to_user_ptr(args->data_ptr),
532 ret = i915_mutex_lock_interruptible(dev);
536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
537 if (&obj->base == NULL) {
542 /* Bounds check source. */
543 if (args->offset > obj->base.size ||
544 args->size > obj->base.size - args->offset) {
549 /* prime objects have no backing filp to GEM pread/pwrite
552 if (!obj->base.filp) {
557 trace_i915_gem_object_pread(obj, args->offset, args->size);
559 ret = i915_gem_shmem_pread(dev, obj, args, file);
562 drm_gem_object_unreference(&obj->base);
564 mutex_unlock(&dev->struct_mutex);
568 /* This is the fast write path which cannot handle
569 * page faults in the source data
573 fast_user_write(struct io_mapping *mapping,
574 loff_t page_base, int page_offset,
575 char __user *user_data,
578 void __iomem *vaddr_atomic;
580 unsigned long unwritten;
582 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
583 /* We can use the cpu mem copy function because this is X86. */
584 vaddr = (void __force*)vaddr_atomic + page_offset;
585 unwritten = __copy_from_user_inatomic_nocache(vaddr,
587 io_mapping_unmap_atomic(vaddr_atomic);
592 * This is the fast pwrite path, where we copy the data directly from the
593 * user into the GTT, uncached.
596 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
597 struct drm_i915_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file)
601 drm_i915_private_t *dev_priv = dev->dev_private;
603 loff_t offset, page_base;
604 char __user *user_data;
605 int page_offset, page_length, ret;
607 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
611 ret = i915_gem_object_set_to_gtt_domain(obj, true);
615 ret = i915_gem_object_put_fence(obj);
619 user_data = to_user_ptr(args->data_ptr);
622 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
625 /* Operation in this page
627 * page_base = page offset within aperture
628 * page_offset = offset within page
629 * page_length = bytes to copy for this page
631 page_base = offset & PAGE_MASK;
632 page_offset = offset_in_page(offset);
633 page_length = remain;
634 if ((page_offset + remain) > PAGE_SIZE)
635 page_length = PAGE_SIZE - page_offset;
637 /* If we get a fault while copying data, then (presumably) our
638 * source page isn't available. Return the error and we'll
639 * retry in the slow path.
641 if (fast_user_write(dev_priv->gtt.mappable, page_base,
642 page_offset, user_data, page_length)) {
647 remain -= page_length;
648 user_data += page_length;
649 offset += page_length;
653 i915_gem_object_unpin(obj);
658 /* Per-page copy function for the shmem pwrite fastpath.
659 * Flushes invalid cachelines before writing to the target if
660 * needs_clflush_before is set and flushes out any written cachelines after
661 * writing if needs_clflush is set. */
663 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
664 char __user *user_data,
665 bool page_do_bit17_swizzling,
666 bool needs_clflush_before,
667 bool needs_clflush_after)
672 if (unlikely(page_do_bit17_swizzling))
675 vaddr = kmap_atomic(page);
676 if (needs_clflush_before)
677 drm_clflush_virt_range(vaddr + shmem_page_offset,
679 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
682 if (needs_clflush_after)
683 drm_clflush_virt_range(vaddr + shmem_page_offset,
685 kunmap_atomic(vaddr);
687 return ret ? -EFAULT : 0;
690 /* Only difference to the fast-path function is that this can handle bit17
691 * and uses non-atomic copy and kmap functions. */
693 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
694 char __user *user_data,
695 bool page_do_bit17_swizzling,
696 bool needs_clflush_before,
697 bool needs_clflush_after)
703 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
704 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
706 page_do_bit17_swizzling);
707 if (page_do_bit17_swizzling)
708 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
712 ret = __copy_from_user(vaddr + shmem_page_offset,
715 if (needs_clflush_after)
716 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
718 page_do_bit17_swizzling);
721 return ret ? -EFAULT : 0;
725 i915_gem_shmem_pwrite(struct drm_device *dev,
726 struct drm_i915_gem_object *obj,
727 struct drm_i915_gem_pwrite *args,
728 struct drm_file *file)
732 char __user *user_data;
733 int shmem_page_offset, page_length, ret = 0;
734 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
735 int hit_slowpath = 0;
736 int needs_clflush_after = 0;
737 int needs_clflush_before = 0;
738 struct sg_page_iter sg_iter;
740 user_data = to_user_ptr(args->data_ptr);
743 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
745 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
746 /* If we're not in the cpu write domain, set ourself into the gtt
747 * write domain and manually flush cachelines (if required). This
748 * optimizes for the case when the gpu will use the data
749 * right away and we therefore have to clflush anyway. */
750 needs_clflush_after = cpu_write_needs_clflush(obj);
751 if (i915_gem_obj_bound_any(obj)) {
752 ret = i915_gem_object_set_to_gtt_domain(obj, true);
757 /* Same trick applies to invalidate partially written cachelines read
759 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
760 needs_clflush_before =
761 !cpu_cache_is_coherent(dev, obj->cache_level);
763 ret = i915_gem_object_get_pages(obj);
767 i915_gem_object_pin_pages(obj);
769 offset = args->offset;
772 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
773 offset >> PAGE_SHIFT) {
774 struct page *page = sg_page_iter_page(&sg_iter);
775 int partial_cacheline_write;
780 /* Operation in this page
782 * shmem_page_offset = offset within page in shmem file
783 * page_length = bytes to copy for this page
785 shmem_page_offset = offset_in_page(offset);
787 page_length = remain;
788 if ((shmem_page_offset + page_length) > PAGE_SIZE)
789 page_length = PAGE_SIZE - shmem_page_offset;
791 /* If we don't overwrite a cacheline completely we need to be
792 * careful to have up-to-date data by first clflushing. Don't
793 * overcomplicate things and flush the entire patch. */
794 partial_cacheline_write = needs_clflush_before &&
795 ((shmem_page_offset | page_length)
796 & (boot_cpu_data.x86_clflush_size - 1));
798 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
799 (page_to_phys(page) & (1 << 17)) != 0;
801 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
809 mutex_unlock(&dev->struct_mutex);
810 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
811 user_data, page_do_bit17_swizzling,
812 partial_cacheline_write,
813 needs_clflush_after);
815 mutex_lock(&dev->struct_mutex);
818 set_page_dirty(page);
819 mark_page_accessed(page);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_unpin_pages(obj);
834 * Fixup: Flush cpu caches in case we didn't flush the dirty
835 * cachelines in-line while writing and the object moved
836 * out of the cpu write domain while we've dropped the lock.
838 if (!needs_clflush_after &&
839 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
840 if (i915_gem_clflush_object(obj, obj->pin_display))
841 i915_gem_chipset_flush(dev);
845 if (needs_clflush_after)
846 i915_gem_chipset_flush(dev);
852 * Writes data to the object referenced by handle.
854 * On error, the contents of the buffer that were to be modified are undefined.
857 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
858 struct drm_file *file)
860 struct drm_i915_gem_pwrite *args = data;
861 struct drm_i915_gem_object *obj;
867 if (!access_ok(VERIFY_READ,
868 to_user_ptr(args->data_ptr),
872 if (likely(!i915_prefault_disable)) {
873 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
879 ret = i915_mutex_lock_interruptible(dev);
883 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
884 if (&obj->base == NULL) {
889 /* Bounds check destination. */
890 if (args->offset > obj->base.size ||
891 args->size > obj->base.size - args->offset) {
896 /* prime objects have no backing filp to GEM pread/pwrite
899 if (!obj->base.filp) {
904 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
907 /* We can only do the GTT pwrite on untiled buffers, as otherwise
908 * it would end up going through the fenced access, and we'll get
909 * different detiling behavior between reading and writing.
910 * pread/pwrite currently are reading and writing from the CPU
911 * perspective, requiring manual detiling by the client.
914 ret = i915_gem_phys_pwrite(dev, obj, args, file);
918 if (obj->tiling_mode == I915_TILING_NONE &&
919 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
920 cpu_write_needs_clflush(obj)) {
921 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
922 /* Note that the gtt paths might fail with non-page-backed user
923 * pointers (e.g. gtt mappings when moving data between
924 * textures). Fallback to the shmem path in that case. */
927 if (ret == -EFAULT || ret == -ENOSPC)
928 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
931 drm_gem_object_unreference(&obj->base);
933 mutex_unlock(&dev->struct_mutex);
938 i915_gem_check_wedge(struct i915_gpu_error *error,
941 if (i915_reset_in_progress(error)) {
942 /* Non-interruptible callers can't handle -EAGAIN, hence return
943 * -EIO unconditionally for these. */
947 /* Recovery complete, but the reset failed ... */
948 if (i915_terminally_wedged(error))
958 * Compare seqno against outstanding lazy request. Emit a request if they are
962 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
966 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
969 if (seqno == ring->outstanding_lazy_request)
970 ret = i915_add_request(ring, NULL);
976 * __wait_seqno - wait until execution of seqno has finished
977 * @ring: the ring expected to report seqno
979 * @reset_counter: reset sequence associated with the given seqno
980 * @interruptible: do an interruptible wait (normally yes)
981 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
983 * Note: It is of utmost importance that the passed in seqno and reset_counter
984 * values have been read by the caller in an smp safe manner. Where read-side
985 * locks are involved, it is sufficient to read the reset_counter before
986 * unlocking the lock that protects the seqno. For lockless tricks, the
987 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
990 * Returns 0 if the seqno was found within the alloted time. Else returns the
991 * errno with remaining time filled in timeout argument.
993 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
994 unsigned reset_counter,
995 bool interruptible, struct timespec *timeout)
997 drm_i915_private_t *dev_priv = ring->dev->dev_private;
998 struct timespec before, now, wait_time={1,0};
999 unsigned long timeout_jiffies;
1001 bool wait_forever = true;
1004 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1006 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1009 trace_i915_gem_request_wait_begin(ring, seqno);
1011 if (timeout != NULL) {
1012 wait_time = *timeout;
1013 wait_forever = false;
1016 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1018 if (WARN_ON(!ring->irq_get(ring)))
1021 /* Record current time in case interrupted by signal, or wedged * */
1022 getrawmonotonic(&before);
1025 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1026 i915_reset_in_progress(&dev_priv->gpu_error) || \
1027 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1030 end = wait_event_interruptible_timeout(ring->irq_queue,
1034 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1037 /* We need to check whether any gpu reset happened in between
1038 * the caller grabbing the seqno and now ... */
1039 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1042 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1044 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1047 } while (end == 0 && wait_forever);
1049 getrawmonotonic(&now);
1051 ring->irq_put(ring);
1052 trace_i915_gem_request_wait_end(ring, seqno);
1056 struct timespec sleep_time = timespec_sub(now, before);
1057 *timeout = timespec_sub(*timeout, sleep_time);
1058 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1059 set_normalized_timespec(timeout, 0, 0);
1064 case -EAGAIN: /* Wedged */
1065 case -ERESTARTSYS: /* Signal */
1067 case 0: /* Timeout */
1069 default: /* Completed */
1070 WARN_ON(end < 0); /* We're not aware of other errors */
1076 * Waits for a sequence number to be signaled, and cleans up the
1077 * request and object lists appropriately for that event.
1080 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1082 struct drm_device *dev = ring->dev;
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 bool interruptible = dev_priv->mm.interruptible;
1087 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1090 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1094 ret = i915_gem_check_olr(ring, seqno);
1098 return __wait_seqno(ring, seqno,
1099 atomic_read(&dev_priv->gpu_error.reset_counter),
1100 interruptible, NULL);
1104 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1105 struct intel_ring_buffer *ring)
1107 i915_gem_retire_requests_ring(ring);
1109 /* Manually manage the write flush as we may have not yet
1110 * retired the buffer.
1112 * Note that the last_write_seqno is always the earlier of
1113 * the two (read/write) seqno, so if we haved successfully waited,
1114 * we know we have passed the last write.
1116 obj->last_write_seqno = 0;
1117 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1123 * Ensures that all rendering to the object has completed and the object is
1124 * safe to unbind from the GTT or access from the CPU.
1126 static __must_check int
1127 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1130 struct intel_ring_buffer *ring = obj->ring;
1134 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1138 ret = i915_wait_seqno(ring, seqno);
1142 return i915_gem_object_wait_rendering__tail(obj, ring);
1145 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1146 * as the object state may change during this call.
1148 static __must_check int
1149 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1152 struct drm_device *dev = obj->base.dev;
1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 struct intel_ring_buffer *ring = obj->ring;
1155 unsigned reset_counter;
1159 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1160 BUG_ON(!dev_priv->mm.interruptible);
1162 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1166 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1170 ret = i915_gem_check_olr(ring, seqno);
1174 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1175 mutex_unlock(&dev->struct_mutex);
1176 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1177 mutex_lock(&dev->struct_mutex);
1181 return i915_gem_object_wait_rendering__tail(obj, ring);
1185 * Called when user space prepares to use an object with the CPU, either
1186 * through the mmap ioctl's mapping or a GTT mapping.
1189 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1190 struct drm_file *file)
1192 struct drm_i915_gem_set_domain *args = data;
1193 struct drm_i915_gem_object *obj;
1194 uint32_t read_domains = args->read_domains;
1195 uint32_t write_domain = args->write_domain;
1198 /* Only handle setting domains to types used by the CPU. */
1199 if (write_domain & I915_GEM_GPU_DOMAINS)
1202 if (read_domains & I915_GEM_GPU_DOMAINS)
1205 /* Having something in the write domain implies it's in the read
1206 * domain, and only that read domain. Enforce that in the request.
1208 if (write_domain != 0 && read_domains != write_domain)
1211 ret = i915_mutex_lock_interruptible(dev);
1215 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1216 if (&obj->base == NULL) {
1221 /* Try to flush the object off the GPU without holding the lock.
1222 * We will repeat the flush holding the lock in the normal manner
1223 * to catch cases where we are gazumped.
1225 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1229 if (read_domains & I915_GEM_DOMAIN_GTT) {
1230 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1232 /* Silently promote "you're not bound, there was nothing to do"
1233 * to success, since the client was just asking us to
1234 * make sure everything was done.
1239 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1243 drm_gem_object_unreference(&obj->base);
1245 mutex_unlock(&dev->struct_mutex);
1250 * Called when user space has done writes to this buffer
1253 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1254 struct drm_file *file)
1256 struct drm_i915_gem_sw_finish *args = data;
1257 struct drm_i915_gem_object *obj;
1260 ret = i915_mutex_lock_interruptible(dev);
1264 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1265 if (&obj->base == NULL) {
1270 /* Pinned buffers may be scanout, so flush the cache */
1271 if (obj->pin_display)
1272 i915_gem_object_flush_cpu_write_domain(obj, true);
1274 drm_gem_object_unreference(&obj->base);
1276 mutex_unlock(&dev->struct_mutex);
1281 * Maps the contents of an object, returning the address it is mapped
1284 * While the mapping holds a reference on the contents of the object, it doesn't
1285 * imply a ref on the object itself.
1288 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1289 struct drm_file *file)
1291 struct drm_i915_gem_mmap *args = data;
1292 struct drm_gem_object *obj;
1295 obj = drm_gem_object_lookup(dev, file, args->handle);
1299 /* prime objects have no backing filp to GEM mmap
1303 drm_gem_object_unreference_unlocked(obj);
1307 addr = vm_mmap(obj->filp, 0, args->size,
1308 PROT_READ | PROT_WRITE, MAP_SHARED,
1310 drm_gem_object_unreference_unlocked(obj);
1311 if (IS_ERR((void *)addr))
1314 args->addr_ptr = (uint64_t) addr;
1320 * i915_gem_fault - fault a page into the GTT
1321 * vma: VMA in question
1324 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1325 * from userspace. The fault handler takes care of binding the object to
1326 * the GTT (if needed), allocating and programming a fence register (again,
1327 * only if needed based on whether the old reg is still valid or the object
1328 * is tiled) and inserting a new PTE into the faulting process.
1330 * Note that the faulting process may involve evicting existing objects
1331 * from the GTT and/or fence registers to make room. So performance may
1332 * suffer if the GTT working set is large or there are few fence registers
1335 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1337 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1338 struct drm_device *dev = obj->base.dev;
1339 drm_i915_private_t *dev_priv = dev->dev_private;
1340 pgoff_t page_offset;
1343 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1345 /* We don't use vmf->pgoff since that has the fake offset */
1346 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1349 ret = i915_mutex_lock_interruptible(dev);
1353 trace_i915_gem_object_fault(obj, page_offset, true, write);
1355 /* Access to snoopable pages through the GTT is incoherent. */
1356 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1361 /* Now bind it into the GTT if needed */
1362 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1366 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1370 ret = i915_gem_object_get_fence(obj);
1374 obj->fault_mappable = true;
1376 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1380 /* Finally, remap it using the new GTT offset */
1381 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1383 i915_gem_object_unpin(obj);
1385 mutex_unlock(&dev->struct_mutex);
1389 /* If this -EIO is due to a gpu hang, give the reset code a
1390 * chance to clean up the mess. Otherwise return the proper
1392 if (i915_terminally_wedged(&dev_priv->gpu_error))
1393 return VM_FAULT_SIGBUS;
1395 /* Give the error handler a chance to run and move the
1396 * objects off the GPU active list. Next time we service the
1397 * fault, we should be able to transition the page into the
1398 * GTT without touching the GPU (and so avoid further
1399 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1400 * with coherency, just lost writes.
1408 * EBUSY is ok: this just means that another thread
1409 * already did the job.
1411 return VM_FAULT_NOPAGE;
1413 return VM_FAULT_OOM;
1415 return VM_FAULT_SIGBUS;
1417 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1418 return VM_FAULT_SIGBUS;
1423 * i915_gem_release_mmap - remove physical page mappings
1424 * @obj: obj in question
1426 * Preserve the reservation of the mmapping with the DRM core code, but
1427 * relinquish ownership of the pages back to the system.
1429 * It is vital that we remove the page mapping if we have mapped a tiled
1430 * object through the GTT and then lose the fence register due to
1431 * resource pressure. Similarly if the object has been moved out of the
1432 * aperture, than pages mapped into userspace must be revoked. Removing the
1433 * mapping will then trigger a page fault on the next user access, allowing
1434 * fixup by i915_gem_fault().
1437 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1439 if (!obj->fault_mappable)
1442 drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1443 obj->fault_mappable = false;
1447 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1451 if (INTEL_INFO(dev)->gen >= 4 ||
1452 tiling_mode == I915_TILING_NONE)
1455 /* Previous chips need a power-of-two fence region when tiling */
1456 if (INTEL_INFO(dev)->gen == 3)
1457 gtt_size = 1024*1024;
1459 gtt_size = 512*1024;
1461 while (gtt_size < size)
1468 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1469 * @obj: object to check
1471 * Return the required GTT alignment for an object, taking into account
1472 * potential fence register mapping.
1475 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1476 int tiling_mode, bool fenced)
1479 * Minimum alignment is 4k (GTT page size), but might be greater
1480 * if a fence register is needed for the object.
1482 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1483 tiling_mode == I915_TILING_NONE)
1487 * Previous chips need to be aligned to the size of the smallest
1488 * fence register that can contain the object.
1490 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1493 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1495 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1498 if (drm_vma_node_has_offset(&obj->base.vma_node))
1501 dev_priv->mm.shrinker_no_lock_stealing = true;
1503 ret = drm_gem_create_mmap_offset(&obj->base);
1507 /* Badly fragmented mmap space? The only way we can recover
1508 * space is by destroying unwanted objects. We can't randomly release
1509 * mmap_offsets as userspace expects them to be persistent for the
1510 * lifetime of the objects. The closest we can is to release the
1511 * offsets on purgeable objects by truncating it and marking it purged,
1512 * which prevents userspace from ever using that object again.
1514 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1515 ret = drm_gem_create_mmap_offset(&obj->base);
1519 i915_gem_shrink_all(dev_priv);
1520 ret = drm_gem_create_mmap_offset(&obj->base);
1522 dev_priv->mm.shrinker_no_lock_stealing = false;
1527 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1529 drm_gem_free_mmap_offset(&obj->base);
1533 i915_gem_mmap_gtt(struct drm_file *file,
1534 struct drm_device *dev,
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 struct drm_i915_gem_object *obj;
1542 ret = i915_mutex_lock_interruptible(dev);
1546 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1547 if (&obj->base == NULL) {
1552 if (obj->base.size > dev_priv->gtt.mappable_end) {
1557 if (obj->madv != I915_MADV_WILLNEED) {
1558 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1563 ret = i915_gem_object_create_mmap_offset(obj);
1567 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1570 drm_gem_object_unreference(&obj->base);
1572 mutex_unlock(&dev->struct_mutex);
1577 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1579 * @data: GTT mapping ioctl data
1580 * @file: GEM object info
1582 * Simply returns the fake offset to userspace so it can mmap it.
1583 * The mmap call will end up in drm_gem_mmap(), which will set things
1584 * up so we can get faults in the handler above.
1586 * The fault handler will take care of binding the object into the GTT
1587 * (since it may have been evicted to make room for something), allocating
1588 * a fence register, and mapping the appropriate aperture address into
1592 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1593 struct drm_file *file)
1595 struct drm_i915_gem_mmap_gtt *args = data;
1597 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1600 /* Immediately discard the backing storage */
1602 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1604 struct inode *inode;
1606 i915_gem_object_free_mmap_offset(obj);
1608 if (obj->base.filp == NULL)
1611 /* Our goal here is to return as much of the memory as
1612 * is possible back to the system as we are called from OOM.
1613 * To do this we must instruct the shmfs to drop all of its
1614 * backing pages, *now*.
1616 inode = file_inode(obj->base.filp);
1617 shmem_truncate_range(inode, 0, (loff_t)-1);
1619 obj->madv = __I915_MADV_PURGED;
1623 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1625 return obj->madv == I915_MADV_DONTNEED;
1629 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1631 struct sg_page_iter sg_iter;
1634 BUG_ON(obj->madv == __I915_MADV_PURGED);
1636 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1638 /* In the event of a disaster, abandon all caches and
1639 * hope for the best.
1641 WARN_ON(ret != -EIO);
1642 i915_gem_clflush_object(obj, true);
1643 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1646 if (i915_gem_object_needs_bit17_swizzle(obj))
1647 i915_gem_object_save_bit_17_swizzle(obj);
1649 if (obj->madv == I915_MADV_DONTNEED)
1652 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1653 struct page *page = sg_page_iter_page(&sg_iter);
1656 set_page_dirty(page);
1658 if (obj->madv == I915_MADV_WILLNEED)
1659 mark_page_accessed(page);
1661 page_cache_release(page);
1665 sg_free_table(obj->pages);
1670 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1672 const struct drm_i915_gem_object_ops *ops = obj->ops;
1674 if (obj->pages == NULL)
1677 if (obj->pages_pin_count)
1680 BUG_ON(i915_gem_obj_bound_any(obj));
1682 /* ->put_pages might need to allocate memory for the bit17 swizzle
1683 * array, hence protect them from being reaped by removing them from gtt
1685 list_del(&obj->global_list);
1687 ops->put_pages(obj);
1690 if (i915_gem_object_is_purgeable(obj))
1691 i915_gem_object_truncate(obj);
1697 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1698 bool purgeable_only)
1700 struct list_head still_bound_list;
1701 struct drm_i915_gem_object *obj, *next;
1704 list_for_each_entry_safe(obj, next,
1705 &dev_priv->mm.unbound_list,
1707 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1708 i915_gem_object_put_pages(obj) == 0) {
1709 count += obj->base.size >> PAGE_SHIFT;
1710 if (count >= target)
1716 * As we may completely rewrite the bound list whilst unbinding
1717 * (due to retiring requests) we have to strictly process only
1718 * one element of the list at the time, and recheck the list
1719 * on every iteration.
1721 INIT_LIST_HEAD(&still_bound_list);
1722 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1723 struct i915_vma *vma, *v;
1725 obj = list_first_entry(&dev_priv->mm.bound_list,
1726 typeof(*obj), global_list);
1727 list_move_tail(&obj->global_list, &still_bound_list);
1729 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1733 * Hold a reference whilst we unbind this object, as we may
1734 * end up waiting for and retiring requests. This might
1735 * release the final reference (held by the active list)
1736 * and result in the object being freed from under us.
1737 * in this object being freed.
1739 * Note 1: Shrinking the bound list is special since only active
1740 * (and hence bound objects) can contain such limbo objects, so
1741 * we don't need special tricks for shrinking the unbound list.
1742 * The only other place where we have to be careful with active
1743 * objects suddenly disappearing due to retiring requests is the
1746 * Note 2: Even though the bound list doesn't hold a reference
1747 * to the object we can safely grab one here: The final object
1748 * unreferencing and the bound_list are both protected by the
1749 * dev->struct_mutex and so we won't ever be able to observe an
1750 * object on the bound_list with a reference count equals 0.
1752 drm_gem_object_reference(&obj->base);
1754 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1755 if (i915_vma_unbind(vma))
1758 if (i915_gem_object_put_pages(obj) == 0)
1759 count += obj->base.size >> PAGE_SHIFT;
1761 drm_gem_object_unreference(&obj->base);
1763 list_splice(&still_bound_list, &dev_priv->mm.bound_list);
1769 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1771 return __i915_gem_shrink(dev_priv, target, true);
1775 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1777 struct drm_i915_gem_object *obj, *next;
1780 i915_gem_evict_everything(dev_priv->dev);
1782 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1784 if (obj->pages_pin_count == 0)
1785 freed += obj->base.size >> PAGE_SHIFT;
1786 i915_gem_object_put_pages(obj);
1792 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1794 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1796 struct address_space *mapping;
1797 struct sg_table *st;
1798 struct scatterlist *sg;
1799 struct sg_page_iter sg_iter;
1801 unsigned long last_pfn = 0; /* suppress gcc warning */
1804 /* Assert that the object is not currently in any GPU domain. As it
1805 * wasn't in the GTT, there shouldn't be any way it could have been in
1808 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1809 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1811 st = kmalloc(sizeof(*st), GFP_KERNEL);
1815 page_count = obj->base.size / PAGE_SIZE;
1816 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1821 /* Get the list of pages out of our struct file. They'll be pinned
1822 * at this point until we release them.
1824 * Fail silently without starting the shrinker
1826 mapping = file_inode(obj->base.filp)->i_mapping;
1827 gfp = mapping_gfp_mask(mapping);
1828 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1829 gfp &= ~(__GFP_IO | __GFP_WAIT);
1832 for (i = 0; i < page_count; i++) {
1833 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1835 i915_gem_purge(dev_priv, page_count);
1836 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1839 /* We've tried hard to allocate the memory by reaping
1840 * our own buffer, now let the real VM do its job and
1841 * go down in flames if truly OOM.
1843 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1844 gfp |= __GFP_IO | __GFP_WAIT;
1846 i915_gem_shrink_all(dev_priv);
1847 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1851 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1852 gfp &= ~(__GFP_IO | __GFP_WAIT);
1854 #ifdef CONFIG_SWIOTLB
1855 if (swiotlb_nr_tbl()) {
1857 sg_set_page(sg, page, PAGE_SIZE, 0);
1862 if (!i || page_to_pfn(page) != last_pfn + 1) {
1866 sg_set_page(sg, page, PAGE_SIZE, 0);
1868 sg->length += PAGE_SIZE;
1870 last_pfn = page_to_pfn(page);
1872 #ifdef CONFIG_SWIOTLB
1873 if (!swiotlb_nr_tbl())
1878 if (i915_gem_object_needs_bit17_swizzle(obj))
1879 i915_gem_object_do_bit_17_swizzle(obj);
1885 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1886 page_cache_release(sg_page_iter_page(&sg_iter));
1889 return PTR_ERR(page);
1892 /* Ensure that the associated pages are gathered from the backing storage
1893 * and pinned into our object. i915_gem_object_get_pages() may be called
1894 * multiple times before they are released by a single call to
1895 * i915_gem_object_put_pages() - once the pages are no longer referenced
1896 * either as a result of memory pressure (reaping pages under the shrinker)
1897 * or as the object is itself released.
1900 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1902 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1903 const struct drm_i915_gem_object_ops *ops = obj->ops;
1909 if (obj->madv != I915_MADV_WILLNEED) {
1910 DRM_ERROR("Attempting to obtain a purgeable object\n");
1914 BUG_ON(obj->pages_pin_count);
1916 ret = ops->get_pages(obj);
1920 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1925 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1926 struct intel_ring_buffer *ring)
1928 struct drm_device *dev = obj->base.dev;
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 u32 seqno = intel_ring_get_seqno(ring);
1932 BUG_ON(ring == NULL);
1933 if (obj->ring != ring && obj->last_write_seqno) {
1934 /* Keep the seqno relative to the current ring */
1935 obj->last_write_seqno = seqno;
1939 /* Add a reference if we're newly entering the active list. */
1941 drm_gem_object_reference(&obj->base);
1945 list_move_tail(&obj->ring_list, &ring->active_list);
1947 obj->last_read_seqno = seqno;
1949 if (obj->fenced_gpu_access) {
1950 obj->last_fenced_seqno = seqno;
1952 /* Bump MRU to take account of the delayed flush */
1953 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1954 struct drm_i915_fence_reg *reg;
1956 reg = &dev_priv->fence_regs[obj->fence_reg];
1957 list_move_tail(®->lru_list,
1958 &dev_priv->mm.fence_list);
1964 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1966 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1967 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1968 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1970 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1971 BUG_ON(!obj->active);
1973 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1975 list_del_init(&obj->ring_list);
1978 obj->last_read_seqno = 0;
1979 obj->last_write_seqno = 0;
1980 obj->base.write_domain = 0;
1982 obj->last_fenced_seqno = 0;
1983 obj->fenced_gpu_access = false;
1986 drm_gem_object_unreference(&obj->base);
1988 WARN_ON(i915_verify_lists(dev));
1992 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 struct intel_ring_buffer *ring;
1998 /* Carefully retire all requests without writing to the rings */
1999 for_each_ring(ring, dev_priv, i) {
2000 ret = intel_ring_idle(ring);
2004 i915_gem_retire_requests(dev);
2006 /* Finally reset hw state */
2007 for_each_ring(ring, dev_priv, i) {
2008 intel_ring_init_seqno(ring, seqno);
2010 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2011 ring->sync_seqno[j] = 0;
2017 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2025 /* HWS page needs to be set less than what we
2026 * will inject to ring
2028 ret = i915_gem_init_seqno(dev, seqno - 1);
2032 /* Carefully set the last_seqno value so that wrap
2033 * detection still works
2035 dev_priv->next_seqno = seqno;
2036 dev_priv->last_seqno = seqno - 1;
2037 if (dev_priv->last_seqno == 0)
2038 dev_priv->last_seqno--;
2044 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2048 /* reserve 0 for non-seqno */
2049 if (dev_priv->next_seqno == 0) {
2050 int ret = i915_gem_init_seqno(dev, 0);
2054 dev_priv->next_seqno = 1;
2057 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2061 int __i915_add_request(struct intel_ring_buffer *ring,
2062 struct drm_file *file,
2063 struct drm_i915_gem_object *obj,
2066 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2067 struct drm_i915_gem_request *request;
2068 u32 request_ring_position, request_start;
2072 request_start = intel_ring_get_tail(ring);
2074 * Emit any outstanding flushes - execbuf can fail to emit the flush
2075 * after having emitted the batchbuffer command. Hence we need to fix
2076 * things up similar to emitting the lazy request. The difference here
2077 * is that the flush _must_ happen before the next request, no matter
2080 ret = intel_ring_flush_all_caches(ring);
2084 request = kmalloc(sizeof(*request), GFP_KERNEL);
2085 if (request == NULL)
2089 /* Record the position of the start of the request so that
2090 * should we detect the updated seqno part-way through the
2091 * GPU processing the request, we never over-estimate the
2092 * position of the head.
2094 request_ring_position = intel_ring_get_tail(ring);
2096 ret = ring->add_request(ring);
2102 request->seqno = intel_ring_get_seqno(ring);
2103 request->ring = ring;
2104 request->head = request_start;
2105 request->tail = request_ring_position;
2106 request->ctx = ring->last_context;
2107 request->batch_obj = obj;
2109 /* Whilst this request exists, batch_obj will be on the
2110 * active_list, and so will hold the active reference. Only when this
2111 * request is retired will the the batch_obj be moved onto the
2112 * inactive_list and lose its active reference. Hence we do not need
2113 * to explicitly hold another reference here.
2117 i915_gem_context_reference(request->ctx);
2119 request->emitted_jiffies = jiffies;
2120 was_empty = list_empty(&ring->request_list);
2121 list_add_tail(&request->list, &ring->request_list);
2122 request->file_priv = NULL;
2125 struct drm_i915_file_private *file_priv = file->driver_priv;
2127 spin_lock(&file_priv->mm.lock);
2128 request->file_priv = file_priv;
2129 list_add_tail(&request->client_list,
2130 &file_priv->mm.request_list);
2131 spin_unlock(&file_priv->mm.lock);
2134 trace_i915_gem_request_add(ring, request->seqno);
2135 ring->outstanding_lazy_request = 0;
2137 if (!dev_priv->ums.mm_suspended) {
2138 i915_queue_hangcheck(ring->dev);
2141 queue_delayed_work(dev_priv->wq,
2142 &dev_priv->mm.retire_work,
2143 round_jiffies_up_relative(HZ));
2144 intel_mark_busy(dev_priv->dev);
2149 *out_seqno = request->seqno;
2154 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2156 struct drm_i915_file_private *file_priv = request->file_priv;
2161 spin_lock(&file_priv->mm.lock);
2162 if (request->file_priv) {
2163 list_del(&request->client_list);
2164 request->file_priv = NULL;
2166 spin_unlock(&file_priv->mm.lock);
2169 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2170 struct i915_address_space *vm)
2172 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2173 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2179 static bool i915_head_inside_request(const u32 acthd_unmasked,
2180 const u32 request_start,
2181 const u32 request_end)
2183 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2185 if (request_start < request_end) {
2186 if (acthd >= request_start && acthd < request_end)
2188 } else if (request_start > request_end) {
2189 if (acthd >= request_start || acthd < request_end)
2196 static struct i915_address_space *
2197 request_to_vm(struct drm_i915_gem_request *request)
2199 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2200 struct i915_address_space *vm;
2202 vm = &dev_priv->gtt.base;
2207 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2208 const u32 acthd, bool *inside)
2210 /* There is a possibility that unmasked head address
2211 * pointing inside the ring, matches the batch_obj address range.
2212 * However this is extremely unlikely.
2214 if (request->batch_obj) {
2215 if (i915_head_inside_object(acthd, request->batch_obj,
2216 request_to_vm(request))) {
2222 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2230 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2231 struct drm_i915_gem_request *request,
2234 struct i915_ctx_hang_stats *hs = NULL;
2235 bool inside, guilty;
2236 unsigned long offset = 0;
2238 /* Innocent until proven guilty */
2241 if (request->batch_obj)
2242 offset = i915_gem_obj_offset(request->batch_obj,
2243 request_to_vm(request));
2245 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2246 i915_request_guilty(request, acthd, &inside)) {
2247 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2249 inside ? "inside" : "flushing",
2251 request->ctx ? request->ctx->id : 0,
2257 /* If contexts are disabled or this is the default context, use
2258 * file_priv->reset_state
2260 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2261 hs = &request->ctx->hang_stats;
2262 else if (request->file_priv)
2263 hs = &request->file_priv->hang_stats;
2269 hs->batch_pending++;
2273 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2275 list_del(&request->list);
2276 i915_gem_request_remove_from_client(request);
2279 i915_gem_context_unreference(request->ctx);
2284 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2285 struct intel_ring_buffer *ring)
2287 u32 completed_seqno;
2290 acthd = intel_ring_get_active_head(ring);
2291 completed_seqno = ring->get_seqno(ring, false);
2293 while (!list_empty(&ring->request_list)) {
2294 struct drm_i915_gem_request *request;
2296 request = list_first_entry(&ring->request_list,
2297 struct drm_i915_gem_request,
2300 if (request->seqno > completed_seqno)
2301 i915_set_reset_status(ring, request, acthd);
2303 i915_gem_free_request(request);
2306 while (!list_empty(&ring->active_list)) {
2307 struct drm_i915_gem_object *obj;
2309 obj = list_first_entry(&ring->active_list,
2310 struct drm_i915_gem_object,
2313 i915_gem_object_move_to_inactive(obj);
2317 void i915_gem_restore_fences(struct drm_device *dev)
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2322 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2323 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2326 * Commit delayed tiling changes if we have an object still
2327 * attached to the fence, otherwise just clear the fence.
2330 i915_gem_object_update_fence(reg->obj, reg,
2331 reg->obj->tiling_mode);
2333 i915_gem_write_fence(dev, i, NULL);
2338 void i915_gem_reset(struct drm_device *dev)
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct intel_ring_buffer *ring;
2344 for_each_ring(ring, dev_priv, i)
2345 i915_gem_reset_ring_lists(dev_priv, ring);
2347 i915_gem_restore_fences(dev);
2351 * This function clears the request list as sequence numbers are passed.
2354 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2358 if (list_empty(&ring->request_list))
2361 WARN_ON(i915_verify_lists(ring->dev));
2363 seqno = ring->get_seqno(ring, true);
2365 while (!list_empty(&ring->request_list)) {
2366 struct drm_i915_gem_request *request;
2368 request = list_first_entry(&ring->request_list,
2369 struct drm_i915_gem_request,
2372 if (!i915_seqno_passed(seqno, request->seqno))
2375 trace_i915_gem_request_retire(ring, request->seqno);
2376 /* We know the GPU must have read the request to have
2377 * sent us the seqno + interrupt, so use the position
2378 * of tail of the request to update the last known position
2381 ring->last_retired_head = request->tail;
2383 i915_gem_free_request(request);
2386 /* Move any buffers on the active list that are no longer referenced
2387 * by the ringbuffer to the flushing/inactive lists as appropriate.
2389 while (!list_empty(&ring->active_list)) {
2390 struct drm_i915_gem_object *obj;
2392 obj = list_first_entry(&ring->active_list,
2393 struct drm_i915_gem_object,
2396 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2399 i915_gem_object_move_to_inactive(obj);
2402 if (unlikely(ring->trace_irq_seqno &&
2403 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2404 ring->irq_put(ring);
2405 ring->trace_irq_seqno = 0;
2408 WARN_ON(i915_verify_lists(ring->dev));
2412 i915_gem_retire_requests(struct drm_device *dev)
2414 drm_i915_private_t *dev_priv = dev->dev_private;
2415 struct intel_ring_buffer *ring;
2418 for_each_ring(ring, dev_priv, i)
2419 i915_gem_retire_requests_ring(ring);
2423 i915_gem_retire_work_handler(struct work_struct *work)
2425 drm_i915_private_t *dev_priv;
2426 struct drm_device *dev;
2427 struct intel_ring_buffer *ring;
2431 dev_priv = container_of(work, drm_i915_private_t,
2432 mm.retire_work.work);
2433 dev = dev_priv->dev;
2435 /* Come back later if the device is busy... */
2436 if (!mutex_trylock(&dev->struct_mutex)) {
2437 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2438 round_jiffies_up_relative(HZ));
2442 i915_gem_retire_requests(dev);
2444 /* Send a periodic flush down the ring so we don't hold onto GEM
2445 * objects indefinitely.
2448 for_each_ring(ring, dev_priv, i) {
2449 if (ring->gpu_caches_dirty)
2450 i915_add_request(ring, NULL);
2452 idle &= list_empty(&ring->request_list);
2455 if (!dev_priv->ums.mm_suspended && !idle)
2456 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2457 round_jiffies_up_relative(HZ));
2459 intel_mark_idle(dev);
2461 mutex_unlock(&dev->struct_mutex);
2465 * Ensures that an object will eventually get non-busy by flushing any required
2466 * write domains, emitting any outstanding lazy request and retiring and
2467 * completed requests.
2470 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2475 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2479 i915_gem_retire_requests_ring(obj->ring);
2486 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2487 * @DRM_IOCTL_ARGS: standard ioctl arguments
2489 * Returns 0 if successful, else an error is returned with the remaining time in
2490 * the timeout parameter.
2491 * -ETIME: object is still busy after timeout
2492 * -ERESTARTSYS: signal interrupted the wait
2493 * -ENONENT: object doesn't exist
2494 * Also possible, but rare:
2495 * -EAGAIN: GPU wedged
2497 * -ENODEV: Internal IRQ fail
2498 * -E?: The add request failed
2500 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2501 * non-zero timeout parameter the wait ioctl will wait for the given number of
2502 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2503 * without holding struct_mutex the object may become re-busied before this
2504 * function completes. A similar but shorter * race condition exists in the busy
2508 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2510 drm_i915_private_t *dev_priv = dev->dev_private;
2511 struct drm_i915_gem_wait *args = data;
2512 struct drm_i915_gem_object *obj;
2513 struct intel_ring_buffer *ring = NULL;
2514 struct timespec timeout_stack, *timeout = NULL;
2515 unsigned reset_counter;
2519 if (args->timeout_ns >= 0) {
2520 timeout_stack = ns_to_timespec(args->timeout_ns);
2521 timeout = &timeout_stack;
2524 ret = i915_mutex_lock_interruptible(dev);
2528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2529 if (&obj->base == NULL) {
2530 mutex_unlock(&dev->struct_mutex);
2534 /* Need to make sure the object gets inactive eventually. */
2535 ret = i915_gem_object_flush_active(obj);
2540 seqno = obj->last_read_seqno;
2547 /* Do this after OLR check to make sure we make forward progress polling
2548 * on this IOCTL with a 0 timeout (like busy ioctl)
2550 if (!args->timeout_ns) {
2555 drm_gem_object_unreference(&obj->base);
2556 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2557 mutex_unlock(&dev->struct_mutex);
2559 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2561 args->timeout_ns = timespec_to_ns(timeout);
2565 drm_gem_object_unreference(&obj->base);
2566 mutex_unlock(&dev->struct_mutex);
2571 * i915_gem_object_sync - sync an object to a ring.
2573 * @obj: object which may be in use on another ring.
2574 * @to: ring we wish to use the object on. May be NULL.
2576 * This code is meant to abstract object synchronization with the GPU.
2577 * Calling with NULL implies synchronizing the object with the CPU
2578 * rather than a particular GPU ring.
2580 * Returns 0 if successful, else propagates up the lower layer error.
2583 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2584 struct intel_ring_buffer *to)
2586 struct intel_ring_buffer *from = obj->ring;
2590 if (from == NULL || to == from)
2593 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2594 return i915_gem_object_wait_rendering(obj, false);
2596 idx = intel_ring_sync_index(from, to);
2598 seqno = obj->last_read_seqno;
2599 if (seqno <= from->sync_seqno[idx])
2602 ret = i915_gem_check_olr(obj->ring, seqno);
2606 ret = to->sync_to(to, from, seqno);
2608 /* We use last_read_seqno because sync_to()
2609 * might have just caused seqno wrap under
2612 from->sync_seqno[idx] = obj->last_read_seqno;
2617 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2619 u32 old_write_domain, old_read_domains;
2621 /* Force a pagefault for domain tracking on next user access */
2622 i915_gem_release_mmap(obj);
2624 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2627 /* Wait for any direct GTT access to complete */
2630 old_read_domains = obj->base.read_domains;
2631 old_write_domain = obj->base.write_domain;
2633 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2634 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2636 trace_i915_gem_object_change_domain(obj,
2641 int i915_vma_unbind(struct i915_vma *vma)
2643 struct drm_i915_gem_object *obj = vma->obj;
2644 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2647 if (list_empty(&vma->vma_link))
2650 if (!drm_mm_node_allocated(&vma->node))
2656 BUG_ON(obj->pages == NULL);
2658 ret = i915_gem_object_finish_gpu(obj);
2661 /* Continue on if we fail due to EIO, the GPU is hung so we
2662 * should be safe and we need to cleanup or else we might
2663 * cause memory corruption through use-after-free.
2666 i915_gem_object_finish_gtt(obj);
2668 /* release the fence reg _after_ flushing */
2669 ret = i915_gem_object_put_fence(obj);
2673 trace_i915_vma_unbind(vma);
2675 if (obj->has_global_gtt_mapping)
2676 i915_gem_gtt_unbind_object(obj);
2677 if (obj->has_aliasing_ppgtt_mapping) {
2678 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2679 obj->has_aliasing_ppgtt_mapping = 0;
2681 i915_gem_gtt_finish_object(obj);
2682 i915_gem_object_unpin_pages(obj);
2684 list_del(&vma->mm_list);
2685 /* Avoid an unnecessary call to unbind on rebind. */
2686 if (i915_is_ggtt(vma->vm))
2687 obj->map_and_fenceable = true;
2689 drm_mm_remove_node(&vma->node);
2692 i915_gem_vma_destroy(vma);
2694 /* Since the unbound list is global, only move to that list if
2695 * no more VMAs exist.
2696 * NB: Until we have real VMAs there will only ever be one */
2697 WARN_ON(!list_empty(&obj->vma_list));
2698 if (list_empty(&obj->vma_list))
2699 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2705 * Unbinds an object from the global GTT aperture.
2708 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2710 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2711 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2713 if (!i915_gem_obj_ggtt_bound(obj))
2719 BUG_ON(obj->pages == NULL);
2721 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2724 int i915_gpu_idle(struct drm_device *dev)
2726 drm_i915_private_t *dev_priv = dev->dev_private;
2727 struct intel_ring_buffer *ring;
2730 /* Flush everything onto the inactive list. */
2731 for_each_ring(ring, dev_priv, i) {
2732 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2736 ret = intel_ring_idle(ring);
2744 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2745 struct drm_i915_gem_object *obj)
2747 drm_i915_private_t *dev_priv = dev->dev_private;
2749 int fence_pitch_shift;
2751 if (INTEL_INFO(dev)->gen >= 6) {
2752 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2753 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2755 fence_reg = FENCE_REG_965_0;
2756 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2759 fence_reg += reg * 8;
2761 /* To w/a incoherency with non-atomic 64-bit register updates,
2762 * we split the 64-bit update into two 32-bit writes. In order
2763 * for a partial fence not to be evaluated between writes, we
2764 * precede the update with write to turn off the fence register,
2765 * and only enable the fence as the last step.
2767 * For extra levels of paranoia, we make sure each step lands
2768 * before applying the next step.
2770 I915_WRITE(fence_reg, 0);
2771 POSTING_READ(fence_reg);
2774 u32 size = i915_gem_obj_ggtt_size(obj);
2777 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2779 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2780 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2781 if (obj->tiling_mode == I915_TILING_Y)
2782 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2783 val |= I965_FENCE_REG_VALID;
2785 I915_WRITE(fence_reg + 4, val >> 32);
2786 POSTING_READ(fence_reg + 4);
2788 I915_WRITE(fence_reg + 0, val);
2789 POSTING_READ(fence_reg);
2791 I915_WRITE(fence_reg + 4, 0);
2792 POSTING_READ(fence_reg + 4);
2796 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2797 struct drm_i915_gem_object *obj)
2799 drm_i915_private_t *dev_priv = dev->dev_private;
2803 u32 size = i915_gem_obj_ggtt_size(obj);
2807 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2808 (size & -size) != size ||
2809 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2810 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2811 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2813 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2818 /* Note: pitch better be a power of two tile widths */
2819 pitch_val = obj->stride / tile_width;
2820 pitch_val = ffs(pitch_val) - 1;
2822 val = i915_gem_obj_ggtt_offset(obj);
2823 if (obj->tiling_mode == I915_TILING_Y)
2824 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2825 val |= I915_FENCE_SIZE_BITS(size);
2826 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2827 val |= I830_FENCE_REG_VALID;
2832 reg = FENCE_REG_830_0 + reg * 4;
2834 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2836 I915_WRITE(reg, val);
2840 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2841 struct drm_i915_gem_object *obj)
2843 drm_i915_private_t *dev_priv = dev->dev_private;
2847 u32 size = i915_gem_obj_ggtt_size(obj);
2850 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2851 (size & -size) != size ||
2852 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2853 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2854 i915_gem_obj_ggtt_offset(obj), size);
2856 pitch_val = obj->stride / 128;
2857 pitch_val = ffs(pitch_val) - 1;
2859 val = i915_gem_obj_ggtt_offset(obj);
2860 if (obj->tiling_mode == I915_TILING_Y)
2861 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2862 val |= I830_FENCE_SIZE_BITS(size);
2863 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2864 val |= I830_FENCE_REG_VALID;
2868 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2869 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2872 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2874 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2877 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2878 struct drm_i915_gem_object *obj)
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2882 /* Ensure that all CPU reads are completed before installing a fence
2883 * and all writes before removing the fence.
2885 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2888 WARN(obj && (!obj->stride || !obj->tiling_mode),
2889 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2890 obj->stride, obj->tiling_mode);
2892 switch (INTEL_INFO(dev)->gen) {
2896 case 4: i965_write_fence_reg(dev, reg, obj); break;
2897 case 3: i915_write_fence_reg(dev, reg, obj); break;
2898 case 2: i830_write_fence_reg(dev, reg, obj); break;
2902 /* And similarly be paranoid that no direct access to this region
2903 * is reordered to before the fence is installed.
2905 if (i915_gem_object_needs_mb(obj))
2909 static inline int fence_number(struct drm_i915_private *dev_priv,
2910 struct drm_i915_fence_reg *fence)
2912 return fence - dev_priv->fence_regs;
2915 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2916 struct drm_i915_fence_reg *fence,
2919 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2920 int reg = fence_number(dev_priv, fence);
2922 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2925 obj->fence_reg = reg;
2927 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2929 obj->fence_reg = I915_FENCE_REG_NONE;
2931 list_del_init(&fence->lru_list);
2933 obj->fence_dirty = false;
2937 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2939 if (obj->last_fenced_seqno) {
2940 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2944 obj->last_fenced_seqno = 0;
2947 obj->fenced_gpu_access = false;
2952 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2954 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2955 struct drm_i915_fence_reg *fence;
2958 ret = i915_gem_object_wait_fence(obj);
2962 if (obj->fence_reg == I915_FENCE_REG_NONE)
2965 fence = &dev_priv->fence_regs[obj->fence_reg];
2967 i915_gem_object_fence_lost(obj);
2968 i915_gem_object_update_fence(obj, fence, false);
2973 static struct drm_i915_fence_reg *
2974 i915_find_fence_reg(struct drm_device *dev)
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct drm_i915_fence_reg *reg, *avail;
2980 /* First try to find a free reg */
2982 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2983 reg = &dev_priv->fence_regs[i];
2987 if (!reg->pin_count)
2994 /* None available, try to steal one or wait for a user to finish */
2995 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3006 * i915_gem_object_get_fence - set up fencing for an object
3007 * @obj: object to map through a fence reg
3009 * When mapping objects through the GTT, userspace wants to be able to write
3010 * to them without having to worry about swizzling if the object is tiled.
3011 * This function walks the fence regs looking for a free one for @obj,
3012 * stealing one if it can't find any.
3014 * It then sets up the reg based on the object's properties: address, pitch
3015 * and tiling format.
3017 * For an untiled surface, this removes any existing fence.
3020 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3022 struct drm_device *dev = obj->base.dev;
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 bool enable = obj->tiling_mode != I915_TILING_NONE;
3025 struct drm_i915_fence_reg *reg;
3028 /* Have we updated the tiling parameters upon the object and so
3029 * will need to serialise the write to the associated fence register?
3031 if (obj->fence_dirty) {
3032 ret = i915_gem_object_wait_fence(obj);
3037 /* Just update our place in the LRU if our fence is getting reused. */
3038 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3039 reg = &dev_priv->fence_regs[obj->fence_reg];
3040 if (!obj->fence_dirty) {
3041 list_move_tail(®->lru_list,
3042 &dev_priv->mm.fence_list);
3045 } else if (enable) {
3046 reg = i915_find_fence_reg(dev);
3051 struct drm_i915_gem_object *old = reg->obj;
3053 ret = i915_gem_object_wait_fence(old);
3057 i915_gem_object_fence_lost(old);
3062 i915_gem_object_update_fence(obj, reg, enable);
3067 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3068 struct drm_mm_node *gtt_space,
3069 unsigned long cache_level)
3071 struct drm_mm_node *other;
3073 /* On non-LLC machines we have to be careful when putting differing
3074 * types of snoopable memory together to avoid the prefetcher
3075 * crossing memory domains and dying.
3080 if (!drm_mm_node_allocated(gtt_space))
3083 if (list_empty(>t_space->node_list))
3086 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3087 if (other->allocated && !other->hole_follows && other->color != cache_level)
3090 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3091 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3097 static void i915_gem_verify_gtt(struct drm_device *dev)
3100 struct drm_i915_private *dev_priv = dev->dev_private;
3101 struct drm_i915_gem_object *obj;
3104 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3105 if (obj->gtt_space == NULL) {
3106 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3111 if (obj->cache_level != obj->gtt_space->color) {
3112 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3113 i915_gem_obj_ggtt_offset(obj),
3114 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3116 obj->gtt_space->color);
3121 if (!i915_gem_valid_gtt_space(dev,
3123 obj->cache_level)) {
3124 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3125 i915_gem_obj_ggtt_offset(obj),
3126 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3138 * Finds free space in the GTT aperture and binds the object there.
3141 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3142 struct i915_address_space *vm,
3144 bool map_and_fenceable,
3147 struct drm_device *dev = obj->base.dev;
3148 drm_i915_private_t *dev_priv = dev->dev_private;
3149 u32 size, fence_size, fence_alignment, unfenced_alignment;
3151 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3152 struct i915_vma *vma;
3155 fence_size = i915_gem_get_gtt_size(dev,
3158 fence_alignment = i915_gem_get_gtt_alignment(dev,
3160 obj->tiling_mode, true);
3161 unfenced_alignment =
3162 i915_gem_get_gtt_alignment(dev,
3164 obj->tiling_mode, false);
3167 alignment = map_and_fenceable ? fence_alignment :
3169 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3170 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3174 size = map_and_fenceable ? fence_size : obj->base.size;
3176 /* If the object is bigger than the entire aperture, reject it early
3177 * before evicting everything in a vain attempt to find space.
3179 if (obj->base.size > gtt_max) {
3180 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3182 map_and_fenceable ? "mappable" : "total",
3187 ret = i915_gem_object_get_pages(obj);
3191 i915_gem_object_pin_pages(obj);
3193 BUG_ON(!i915_is_ggtt(vm));
3195 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3201 /* For now we only ever use 1 vma per object */
3202 WARN_ON(!list_is_singular(&obj->vma_list));
3205 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3207 obj->cache_level, 0, gtt_max,
3208 DRM_MM_SEARCH_DEFAULT);
3210 ret = i915_gem_evict_something(dev, vm, size, alignment,
3219 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3220 obj->cache_level))) {
3222 goto err_remove_node;
3225 ret = i915_gem_gtt_prepare_object(obj);
3227 goto err_remove_node;
3229 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3230 list_add_tail(&vma->mm_list, &vm->inactive_list);
3232 if (i915_is_ggtt(vm)) {
3233 bool mappable, fenceable;
3235 fenceable = (vma->node.size == fence_size &&
3236 (vma->node.start & (fence_alignment - 1)) == 0);
3238 mappable = (vma->node.start + obj->base.size <=
3239 dev_priv->gtt.mappable_end);
3241 obj->map_and_fenceable = mappable && fenceable;
3244 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3246 trace_i915_vma_bind(vma, map_and_fenceable);
3247 i915_gem_verify_gtt(dev);
3251 drm_mm_remove_node(&vma->node);
3253 i915_gem_vma_destroy(vma);
3255 i915_gem_object_unpin_pages(obj);
3260 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3263 /* If we don't have a page list set up, then we're not pinned
3264 * to GPU, and we can ignore the cache flush because it'll happen
3265 * again at bind time.
3267 if (obj->pages == NULL)
3271 * Stolen memory is always coherent with the GPU as it is explicitly
3272 * marked as wc by the system, or the system is cache-coherent.
3277 /* If the GPU is snooping the contents of the CPU cache,
3278 * we do not need to manually clear the CPU cache lines. However,
3279 * the caches are only snooped when the render cache is
3280 * flushed/invalidated. As we always have to emit invalidations
3281 * and flushes when moving into and out of the RENDER domain, correct
3282 * snooping behaviour occurs naturally as the result of our domain
3285 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3288 trace_i915_gem_object_clflush(obj);
3289 drm_clflush_sg(obj->pages);
3294 /** Flushes the GTT write domain for the object if it's dirty. */
3296 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3298 uint32_t old_write_domain;
3300 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3303 /* No actual flushing is required for the GTT write domain. Writes
3304 * to it immediately go to main memory as far as we know, so there's
3305 * no chipset flush. It also doesn't land in render cache.
3307 * However, we do have to enforce the order so that all writes through
3308 * the GTT land before any writes to the device, such as updates to
3313 old_write_domain = obj->base.write_domain;
3314 obj->base.write_domain = 0;
3316 trace_i915_gem_object_change_domain(obj,
3317 obj->base.read_domains,
3321 /** Flushes the CPU write domain for the object if it's dirty. */
3323 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3326 uint32_t old_write_domain;
3328 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3331 if (i915_gem_clflush_object(obj, force))
3332 i915_gem_chipset_flush(obj->base.dev);
3334 old_write_domain = obj->base.write_domain;
3335 obj->base.write_domain = 0;
3337 trace_i915_gem_object_change_domain(obj,
3338 obj->base.read_domains,
3343 * Moves a single object to the GTT read, and possibly write domain.
3345 * This function returns when the move is complete, including waiting on
3349 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3351 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3352 uint32_t old_write_domain, old_read_domains;
3355 /* Not valid to be called on unbound objects. */
3356 if (!i915_gem_obj_bound_any(obj))
3359 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3362 ret = i915_gem_object_wait_rendering(obj, !write);
3366 i915_gem_object_flush_cpu_write_domain(obj, false);
3368 /* Serialise direct access to this object with the barriers for
3369 * coherent writes from the GPU, by effectively invalidating the
3370 * GTT domain upon first access.
3372 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3375 old_write_domain = obj->base.write_domain;
3376 old_read_domains = obj->base.read_domains;
3378 /* It should now be out of any other write domains, and we can update
3379 * the domain values for our changes.
3381 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3382 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3384 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3385 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3389 trace_i915_gem_object_change_domain(obj,
3393 /* And bump the LRU for this access */
3394 if (i915_gem_object_is_inactive(obj)) {
3395 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3396 &dev_priv->gtt.base);
3398 list_move_tail(&vma->mm_list,
3399 &dev_priv->gtt.base.inactive_list);
3406 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3407 enum i915_cache_level cache_level)
3409 struct drm_device *dev = obj->base.dev;
3410 drm_i915_private_t *dev_priv = dev->dev_private;
3411 struct i915_vma *vma;
3414 if (obj->cache_level == cache_level)
3417 if (obj->pin_count) {
3418 DRM_DEBUG("can not change the cache level of pinned objects\n");
3422 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3423 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3424 ret = i915_vma_unbind(vma);
3432 if (i915_gem_obj_bound_any(obj)) {
3433 ret = i915_gem_object_finish_gpu(obj);
3437 i915_gem_object_finish_gtt(obj);
3439 /* Before SandyBridge, you could not use tiling or fence
3440 * registers with snooped memory, so relinquish any fences
3441 * currently pointing to our region in the aperture.
3443 if (INTEL_INFO(dev)->gen < 6) {
3444 ret = i915_gem_object_put_fence(obj);
3449 if (obj->has_global_gtt_mapping)
3450 i915_gem_gtt_bind_object(obj, cache_level);
3451 if (obj->has_aliasing_ppgtt_mapping)
3452 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3456 list_for_each_entry(vma, &obj->vma_list, vma_link)
3457 vma->node.color = cache_level;
3458 obj->cache_level = cache_level;
3460 if (cpu_write_needs_clflush(obj)) {
3461 u32 old_read_domains, old_write_domain;
3463 /* If we're coming from LLC cached, then we haven't
3464 * actually been tracking whether the data is in the
3465 * CPU cache or not, since we only allow one bit set
3466 * in obj->write_domain and have been skipping the clflushes.
3467 * Just set it to the CPU cache for now.
3469 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3471 old_read_domains = obj->base.read_domains;
3472 old_write_domain = obj->base.write_domain;
3474 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3475 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3477 trace_i915_gem_object_change_domain(obj,
3482 i915_gem_verify_gtt(dev);
3486 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3487 struct drm_file *file)
3489 struct drm_i915_gem_caching *args = data;
3490 struct drm_i915_gem_object *obj;
3493 ret = i915_mutex_lock_interruptible(dev);
3497 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3498 if (&obj->base == NULL) {
3503 switch (obj->cache_level) {
3504 case I915_CACHE_LLC:
3505 case I915_CACHE_L3_LLC:
3506 args->caching = I915_CACHING_CACHED;
3510 args->caching = I915_CACHING_DISPLAY;
3514 args->caching = I915_CACHING_NONE;
3518 drm_gem_object_unreference(&obj->base);
3520 mutex_unlock(&dev->struct_mutex);
3524 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3525 struct drm_file *file)
3527 struct drm_i915_gem_caching *args = data;
3528 struct drm_i915_gem_object *obj;
3529 enum i915_cache_level level;
3532 switch (args->caching) {
3533 case I915_CACHING_NONE:
3534 level = I915_CACHE_NONE;
3536 case I915_CACHING_CACHED:
3537 level = I915_CACHE_LLC;
3539 case I915_CACHING_DISPLAY:
3540 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3546 ret = i915_mutex_lock_interruptible(dev);
3550 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3551 if (&obj->base == NULL) {
3556 ret = i915_gem_object_set_cache_level(obj, level);
3558 drm_gem_object_unreference(&obj->base);
3560 mutex_unlock(&dev->struct_mutex);
3564 static bool is_pin_display(struct drm_i915_gem_object *obj)
3566 /* There are 3 sources that pin objects:
3567 * 1. The display engine (scanouts, sprites, cursors);
3568 * 2. Reservations for execbuffer;
3571 * We can ignore reservations as we hold the struct_mutex and
3572 * are only called outside of the reservation path. The user
3573 * can only increment pin_count once, and so if after
3574 * subtracting the potential reference by the user, any pin_count
3575 * remains, it must be due to another use by the display engine.
3577 return obj->pin_count - !!obj->user_pin_count;
3581 * Prepare buffer for display plane (scanout, cursors, etc).
3582 * Can be called from an uninterruptible phase (modesetting) and allows
3583 * any flushes to be pipelined (for pageflips).
3586 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3588 struct intel_ring_buffer *pipelined)
3590 u32 old_read_domains, old_write_domain;
3593 if (pipelined != obj->ring) {
3594 ret = i915_gem_object_sync(obj, pipelined);
3599 /* Mark the pin_display early so that we account for the
3600 * display coherency whilst setting up the cache domains.
3602 obj->pin_display = true;
3604 /* The display engine is not coherent with the LLC cache on gen6. As
3605 * a result, we make sure that the pinning that is about to occur is
3606 * done with uncached PTEs. This is lowest common denominator for all
3609 * However for gen6+, we could do better by using the GFDT bit instead
3610 * of uncaching, which would allow us to flush all the LLC-cached data
3611 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3613 ret = i915_gem_object_set_cache_level(obj,
3614 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3616 goto err_unpin_display;
3618 /* As the user may map the buffer once pinned in the display plane
3619 * (e.g. libkms for the bootup splash), we have to ensure that we
3620 * always use map_and_fenceable for all scanout buffers.
3622 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3624 goto err_unpin_display;
3626 i915_gem_object_flush_cpu_write_domain(obj, true);
3628 old_write_domain = obj->base.write_domain;
3629 old_read_domains = obj->base.read_domains;
3631 /* It should now be out of any other write domains, and we can update
3632 * the domain values for our changes.
3634 obj->base.write_domain = 0;
3635 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3637 trace_i915_gem_object_change_domain(obj,
3644 obj->pin_display = is_pin_display(obj);
3649 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3651 i915_gem_object_unpin(obj);
3652 obj->pin_display = is_pin_display(obj);
3656 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3660 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3663 ret = i915_gem_object_wait_rendering(obj, false);
3667 /* Ensure that we invalidate the GPU's caches and TLBs. */
3668 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3673 * Moves a single object to the CPU read, and possibly write domain.
3675 * This function returns when the move is complete, including waiting on
3679 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3681 uint32_t old_write_domain, old_read_domains;
3684 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3687 ret = i915_gem_object_wait_rendering(obj, !write);
3691 i915_gem_object_flush_gtt_write_domain(obj);
3693 old_write_domain = obj->base.write_domain;
3694 old_read_domains = obj->base.read_domains;
3696 /* Flush the CPU cache if it's still invalid. */
3697 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3698 i915_gem_clflush_object(obj, false);
3700 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3703 /* It should now be out of any other write domains, and we can update
3704 * the domain values for our changes.
3706 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3708 /* If we're writing through the CPU, then the GPU read domains will
3709 * need to be invalidated at next use.
3712 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3713 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3716 trace_i915_gem_object_change_domain(obj,
3723 /* Throttle our rendering by waiting until the ring has completed our requests
3724 * emitted over 20 msec ago.
3726 * Note that if we were to use the current jiffies each time around the loop,
3727 * we wouldn't escape the function with any frames outstanding if the time to
3728 * render a frame was over 20ms.
3730 * This should get us reasonable parallelism between CPU and GPU but also
3731 * relatively low latency when blocking on a particular request to finish.
3734 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 struct drm_i915_file_private *file_priv = file->driver_priv;
3738 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3739 struct drm_i915_gem_request *request;
3740 struct intel_ring_buffer *ring = NULL;
3741 unsigned reset_counter;
3745 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3749 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3753 spin_lock(&file_priv->mm.lock);
3754 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3755 if (time_after_eq(request->emitted_jiffies, recent_enough))
3758 ring = request->ring;
3759 seqno = request->seqno;
3761 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3762 spin_unlock(&file_priv->mm.lock);
3767 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3769 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3775 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3776 struct i915_address_space *vm,
3778 bool map_and_fenceable,
3781 struct i915_vma *vma;
3784 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3787 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3789 vma = i915_gem_obj_to_vma(obj, vm);
3793 vma->node.start & (alignment - 1)) ||
3794 (map_and_fenceable && !obj->map_and_fenceable)) {
3795 WARN(obj->pin_count,
3796 "bo is already pinned with incorrect alignment:"
3797 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3798 " obj->map_and_fenceable=%d\n",
3799 i915_gem_obj_offset(obj, vm), alignment,
3801 obj->map_and_fenceable);
3802 ret = i915_vma_unbind(vma);
3808 if (!i915_gem_obj_bound(obj, vm)) {
3809 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3811 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3817 if (!dev_priv->mm.aliasing_ppgtt)
3818 i915_gem_gtt_bind_object(obj, obj->cache_level);
3821 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3822 i915_gem_gtt_bind_object(obj, obj->cache_level);
3825 obj->pin_mappable |= map_and_fenceable;
3831 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3833 BUG_ON(obj->pin_count == 0);
3834 BUG_ON(!i915_gem_obj_bound_any(obj));
3836 if (--obj->pin_count == 0)
3837 obj->pin_mappable = false;
3841 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3842 struct drm_file *file)
3844 struct drm_i915_gem_pin *args = data;
3845 struct drm_i915_gem_object *obj;
3848 ret = i915_mutex_lock_interruptible(dev);
3852 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3853 if (&obj->base == NULL) {
3858 if (obj->madv != I915_MADV_WILLNEED) {
3859 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3864 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3865 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3871 if (obj->user_pin_count == 0) {
3872 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3877 obj->user_pin_count++;
3878 obj->pin_filp = file;
3880 args->offset = i915_gem_obj_ggtt_offset(obj);
3882 drm_gem_object_unreference(&obj->base);
3884 mutex_unlock(&dev->struct_mutex);
3889 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3890 struct drm_file *file)
3892 struct drm_i915_gem_pin *args = data;
3893 struct drm_i915_gem_object *obj;
3896 ret = i915_mutex_lock_interruptible(dev);
3900 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3901 if (&obj->base == NULL) {
3906 if (obj->pin_filp != file) {
3907 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3912 obj->user_pin_count--;
3913 if (obj->user_pin_count == 0) {
3914 obj->pin_filp = NULL;
3915 i915_gem_object_unpin(obj);
3919 drm_gem_object_unreference(&obj->base);
3921 mutex_unlock(&dev->struct_mutex);
3926 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3927 struct drm_file *file)
3929 struct drm_i915_gem_busy *args = data;
3930 struct drm_i915_gem_object *obj;
3933 ret = i915_mutex_lock_interruptible(dev);
3937 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3938 if (&obj->base == NULL) {
3943 /* Count all active objects as busy, even if they are currently not used
3944 * by the gpu. Users of this interface expect objects to eventually
3945 * become non-busy without any further actions, therefore emit any
3946 * necessary flushes here.
3948 ret = i915_gem_object_flush_active(obj);
3950 args->busy = obj->active;
3952 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3953 args->busy |= intel_ring_flag(obj->ring) << 16;
3956 drm_gem_object_unreference(&obj->base);
3958 mutex_unlock(&dev->struct_mutex);
3963 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3964 struct drm_file *file_priv)
3966 return i915_gem_ring_throttle(dev, file_priv);
3970 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3971 struct drm_file *file_priv)
3973 struct drm_i915_gem_madvise *args = data;
3974 struct drm_i915_gem_object *obj;
3977 switch (args->madv) {
3978 case I915_MADV_DONTNEED:
3979 case I915_MADV_WILLNEED:
3985 ret = i915_mutex_lock_interruptible(dev);
3989 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3990 if (&obj->base == NULL) {
3995 if (obj->pin_count) {
4000 if (obj->madv != __I915_MADV_PURGED)
4001 obj->madv = args->madv;
4003 /* if the object is no longer attached, discard its backing storage */
4004 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4005 i915_gem_object_truncate(obj);
4007 args->retained = obj->madv != __I915_MADV_PURGED;
4010 drm_gem_object_unreference(&obj->base);
4012 mutex_unlock(&dev->struct_mutex);
4016 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4017 const struct drm_i915_gem_object_ops *ops)
4019 INIT_LIST_HEAD(&obj->global_list);
4020 INIT_LIST_HEAD(&obj->ring_list);
4021 INIT_LIST_HEAD(&obj->exec_list);
4022 INIT_LIST_HEAD(&obj->obj_exec_link);
4023 INIT_LIST_HEAD(&obj->vma_list);
4027 obj->fence_reg = I915_FENCE_REG_NONE;
4028 obj->madv = I915_MADV_WILLNEED;
4029 /* Avoid an unnecessary call to unbind on the first bind. */
4030 obj->map_and_fenceable = true;
4032 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4035 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4036 .get_pages = i915_gem_object_get_pages_gtt,
4037 .put_pages = i915_gem_object_put_pages_gtt,
4040 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4043 struct drm_i915_gem_object *obj;
4044 struct address_space *mapping;
4047 obj = i915_gem_object_alloc(dev);
4051 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4052 i915_gem_object_free(obj);
4056 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4057 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4058 /* 965gm cannot relocate objects above 4GiB. */
4059 mask &= ~__GFP_HIGHMEM;
4060 mask |= __GFP_DMA32;
4063 mapping = file_inode(obj->base.filp)->i_mapping;
4064 mapping_set_gfp_mask(mapping, mask);
4066 i915_gem_object_init(obj, &i915_gem_object_ops);
4068 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4069 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4072 /* On some devices, we can have the GPU use the LLC (the CPU
4073 * cache) for about a 10% performance improvement
4074 * compared to uncached. Graphics requests other than
4075 * display scanout are coherent with the CPU in
4076 * accessing this cache. This means in this mode we
4077 * don't need to clflush on the CPU side, and on the
4078 * GPU side we only need to flush internal caches to
4079 * get data visible to the CPU.
4081 * However, we maintain the display planes as UC, and so
4082 * need to rebind when first used as such.
4084 obj->cache_level = I915_CACHE_LLC;
4086 obj->cache_level = I915_CACHE_NONE;
4088 trace_i915_gem_object_create(obj);
4093 int i915_gem_init_object(struct drm_gem_object *obj)
4100 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4102 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4103 struct drm_device *dev = obj->base.dev;
4104 drm_i915_private_t *dev_priv = dev->dev_private;
4105 struct i915_vma *vma, *next;
4107 trace_i915_gem_object_destroy(obj);
4110 i915_gem_detach_phys_object(dev, obj);
4113 /* NB: 0 or 1 elements */
4114 WARN_ON(!list_empty(&obj->vma_list) &&
4115 !list_is_singular(&obj->vma_list));
4116 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4117 int ret = i915_vma_unbind(vma);
4118 if (WARN_ON(ret == -ERESTARTSYS)) {
4119 bool was_interruptible;
4121 was_interruptible = dev_priv->mm.interruptible;
4122 dev_priv->mm.interruptible = false;
4124 WARN_ON(i915_vma_unbind(vma));
4126 dev_priv->mm.interruptible = was_interruptible;
4130 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4131 * before progressing. */
4133 i915_gem_object_unpin_pages(obj);
4135 if (WARN_ON(obj->pages_pin_count))
4136 obj->pages_pin_count = 0;
4137 i915_gem_object_put_pages(obj);
4138 i915_gem_object_free_mmap_offset(obj);
4139 i915_gem_object_release_stolen(obj);
4143 if (obj->base.import_attach)
4144 drm_prime_gem_destroy(&obj->base, NULL);
4146 drm_gem_object_release(&obj->base);
4147 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4150 i915_gem_object_free(obj);
4153 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4154 struct i915_address_space *vm)
4156 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4158 return ERR_PTR(-ENOMEM);
4160 INIT_LIST_HEAD(&vma->vma_link);
4161 INIT_LIST_HEAD(&vma->mm_list);
4162 INIT_LIST_HEAD(&vma->exec_list);
4166 /* Keep GGTT vmas first to make debug easier */
4167 if (i915_is_ggtt(vm))
4168 list_add(&vma->vma_link, &obj->vma_list);
4170 list_add_tail(&vma->vma_link, &obj->vma_list);
4175 void i915_gem_vma_destroy(struct i915_vma *vma)
4177 WARN_ON(vma->node.allocated);
4178 list_del(&vma->vma_link);
4183 i915_gem_idle(struct drm_device *dev)
4185 drm_i915_private_t *dev_priv = dev->dev_private;
4188 if (dev_priv->ums.mm_suspended) {
4189 mutex_unlock(&dev->struct_mutex);
4193 ret = i915_gpu_idle(dev);
4195 mutex_unlock(&dev->struct_mutex);
4198 i915_gem_retire_requests(dev);
4200 /* Under UMS, be paranoid and evict. */
4201 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4202 i915_gem_evict_everything(dev);
4204 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4206 i915_kernel_lost_context(dev);
4207 i915_gem_cleanup_ringbuffer(dev);
4209 /* Cancel the retire work handler, which should be idle now. */
4210 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4215 void i915_gem_l3_remap(struct drm_device *dev)
4217 drm_i915_private_t *dev_priv = dev->dev_private;
4221 if (!HAS_L3_GPU_CACHE(dev))
4224 if (!dev_priv->l3_parity.remap_info)
4227 misccpctl = I915_READ(GEN7_MISCCPCTL);
4228 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4229 POSTING_READ(GEN7_MISCCPCTL);
4231 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4232 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4233 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4234 DRM_DEBUG("0x%x was already programmed to %x\n",
4235 GEN7_L3LOG_BASE + i, remap);
4236 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4237 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4238 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4241 /* Make sure all the writes land before disabling dop clock gating */
4242 POSTING_READ(GEN7_L3LOG_BASE);
4244 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4247 void i915_gem_init_swizzling(struct drm_device *dev)
4249 drm_i915_private_t *dev_priv = dev->dev_private;
4251 if (INTEL_INFO(dev)->gen < 5 ||
4252 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4255 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4256 DISP_TILE_SURFACE_SWIZZLING);
4261 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4263 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4264 else if (IS_GEN7(dev))
4265 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4271 intel_enable_blt(struct drm_device *dev)
4276 /* The blitter was dysfunctional on early prototypes */
4277 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4278 DRM_INFO("BLT not supported on this pre-production hardware;"
4279 " graphics performance will be degraded.\n");
4286 static int i915_gem_init_rings(struct drm_device *dev)
4288 struct drm_i915_private *dev_priv = dev->dev_private;
4291 ret = intel_init_render_ring_buffer(dev);
4296 ret = intel_init_bsd_ring_buffer(dev);
4298 goto cleanup_render_ring;
4301 if (intel_enable_blt(dev)) {
4302 ret = intel_init_blt_ring_buffer(dev);
4304 goto cleanup_bsd_ring;
4307 if (HAS_VEBOX(dev)) {
4308 ret = intel_init_vebox_ring_buffer(dev);
4310 goto cleanup_blt_ring;
4314 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4316 goto cleanup_vebox_ring;
4321 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4323 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4325 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4326 cleanup_render_ring:
4327 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4333 i915_gem_init_hw(struct drm_device *dev)
4335 drm_i915_private_t *dev_priv = dev->dev_private;
4338 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4341 if (dev_priv->ellc_size)
4342 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4344 if (HAS_PCH_NOP(dev)) {
4345 u32 temp = I915_READ(GEN7_MSG_CTL);
4346 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4347 I915_WRITE(GEN7_MSG_CTL, temp);
4350 i915_gem_l3_remap(dev);
4352 i915_gem_init_swizzling(dev);
4354 ret = i915_gem_init_rings(dev);
4359 * XXX: There was some w/a described somewhere suggesting loading
4360 * contexts before PPGTT.
4362 i915_gem_context_init(dev);
4363 if (dev_priv->mm.aliasing_ppgtt) {
4364 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4366 i915_gem_cleanup_aliasing_ppgtt(dev);
4367 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4374 int i915_gem_init(struct drm_device *dev)
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4379 mutex_lock(&dev->struct_mutex);
4381 if (IS_VALLEYVIEW(dev)) {
4382 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4383 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4384 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4385 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4388 i915_gem_init_global_gtt(dev);
4390 ret = i915_gem_init_hw(dev);
4391 mutex_unlock(&dev->struct_mutex);
4393 i915_gem_cleanup_aliasing_ppgtt(dev);
4397 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4398 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4399 dev_priv->dri1.allow_batchbuffer = 1;
4404 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4406 drm_i915_private_t *dev_priv = dev->dev_private;
4407 struct intel_ring_buffer *ring;
4410 for_each_ring(ring, dev_priv, i)
4411 intel_cleanup_ring_buffer(ring);
4415 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4416 struct drm_file *file_priv)
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4421 if (drm_core_check_feature(dev, DRIVER_MODESET))
4424 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4425 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4426 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4429 mutex_lock(&dev->struct_mutex);
4430 dev_priv->ums.mm_suspended = 0;
4432 ret = i915_gem_init_hw(dev);
4434 mutex_unlock(&dev->struct_mutex);
4438 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4439 mutex_unlock(&dev->struct_mutex);
4441 ret = drm_irq_install(dev);
4443 goto cleanup_ringbuffer;
4448 mutex_lock(&dev->struct_mutex);
4449 i915_gem_cleanup_ringbuffer(dev);
4450 dev_priv->ums.mm_suspended = 1;
4451 mutex_unlock(&dev->struct_mutex);
4457 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4458 struct drm_file *file_priv)
4460 struct drm_i915_private *dev_priv = dev->dev_private;
4463 if (drm_core_check_feature(dev, DRIVER_MODESET))
4466 drm_irq_uninstall(dev);
4468 mutex_lock(&dev->struct_mutex);
4469 ret = i915_gem_idle(dev);
4471 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4472 * We need to replace this with a semaphore, or something.
4473 * And not confound ums.mm_suspended!
4476 dev_priv->ums.mm_suspended = 1;
4477 mutex_unlock(&dev->struct_mutex);
4483 i915_gem_lastclose(struct drm_device *dev)
4487 if (drm_core_check_feature(dev, DRIVER_MODESET))
4490 mutex_lock(&dev->struct_mutex);
4491 ret = i915_gem_idle(dev);
4493 DRM_ERROR("failed to idle hardware: %d\n", ret);
4494 mutex_unlock(&dev->struct_mutex);
4498 init_ring_lists(struct intel_ring_buffer *ring)
4500 INIT_LIST_HEAD(&ring->active_list);
4501 INIT_LIST_HEAD(&ring->request_list);
4504 static void i915_init_vm(struct drm_i915_private *dev_priv,
4505 struct i915_address_space *vm)
4507 vm->dev = dev_priv->dev;
4508 INIT_LIST_HEAD(&vm->active_list);
4509 INIT_LIST_HEAD(&vm->inactive_list);
4510 INIT_LIST_HEAD(&vm->global_link);
4511 list_add(&vm->global_link, &dev_priv->vm_list);
4515 i915_gem_load(struct drm_device *dev)
4517 drm_i915_private_t *dev_priv = dev->dev_private;
4521 kmem_cache_create("i915_gem_object",
4522 sizeof(struct drm_i915_gem_object), 0,
4526 INIT_LIST_HEAD(&dev_priv->vm_list);
4527 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4529 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4530 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4531 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4532 for (i = 0; i < I915_NUM_RINGS; i++)
4533 init_ring_lists(&dev_priv->ring[i]);
4534 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4535 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4536 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4537 i915_gem_retire_work_handler);
4538 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4540 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4542 I915_WRITE(MI_ARB_STATE,
4543 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4546 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4548 /* Old X drivers will take 0-2 for front, back, depth buffers */
4549 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4550 dev_priv->fence_reg_start = 3;
4552 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4553 dev_priv->num_fence_regs = 32;
4554 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4555 dev_priv->num_fence_regs = 16;
4557 dev_priv->num_fence_regs = 8;
4559 /* Initialize fence registers to zero */
4560 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4561 i915_gem_restore_fences(dev);
4563 i915_gem_detect_bit_6_swizzle(dev);
4564 init_waitqueue_head(&dev_priv->pending_flip_queue);
4566 dev_priv->mm.interruptible = true;
4568 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4569 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4570 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4571 register_shrinker(&dev_priv->mm.inactive_shrinker);
4575 * Create a physically contiguous memory object for this object
4576 * e.g. for cursor + overlay regs
4578 static int i915_gem_init_phys_object(struct drm_device *dev,
4579 int id, int size, int align)
4581 drm_i915_private_t *dev_priv = dev->dev_private;
4582 struct drm_i915_gem_phys_object *phys_obj;
4585 if (dev_priv->mm.phys_objs[id - 1] || !size)
4588 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4594 phys_obj->handle = drm_pci_alloc(dev, size, align);
4595 if (!phys_obj->handle) {
4600 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4603 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4611 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4613 drm_i915_private_t *dev_priv = dev->dev_private;
4614 struct drm_i915_gem_phys_object *phys_obj;
4616 if (!dev_priv->mm.phys_objs[id - 1])
4619 phys_obj = dev_priv->mm.phys_objs[id - 1];
4620 if (phys_obj->cur_obj) {
4621 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4625 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4627 drm_pci_free(dev, phys_obj->handle);
4629 dev_priv->mm.phys_objs[id - 1] = NULL;
4632 void i915_gem_free_all_phys_object(struct drm_device *dev)
4636 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4637 i915_gem_free_phys_object(dev, i);
4640 void i915_gem_detach_phys_object(struct drm_device *dev,
4641 struct drm_i915_gem_object *obj)
4643 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4650 vaddr = obj->phys_obj->handle->vaddr;
4652 page_count = obj->base.size / PAGE_SIZE;
4653 for (i = 0; i < page_count; i++) {
4654 struct page *page = shmem_read_mapping_page(mapping, i);
4655 if (!IS_ERR(page)) {
4656 char *dst = kmap_atomic(page);
4657 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4660 drm_clflush_pages(&page, 1);
4662 set_page_dirty(page);
4663 mark_page_accessed(page);
4664 page_cache_release(page);
4667 i915_gem_chipset_flush(dev);
4669 obj->phys_obj->cur_obj = NULL;
4670 obj->phys_obj = NULL;
4674 i915_gem_attach_phys_object(struct drm_device *dev,
4675 struct drm_i915_gem_object *obj,
4679 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4680 drm_i915_private_t *dev_priv = dev->dev_private;
4685 if (id > I915_MAX_PHYS_OBJECT)
4688 if (obj->phys_obj) {
4689 if (obj->phys_obj->id == id)
4691 i915_gem_detach_phys_object(dev, obj);
4694 /* create a new object */
4695 if (!dev_priv->mm.phys_objs[id - 1]) {
4696 ret = i915_gem_init_phys_object(dev, id,
4697 obj->base.size, align);
4699 DRM_ERROR("failed to init phys object %d size: %zu\n",
4700 id, obj->base.size);
4705 /* bind to the object */
4706 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4707 obj->phys_obj->cur_obj = obj;
4709 page_count = obj->base.size / PAGE_SIZE;
4711 for (i = 0; i < page_count; i++) {
4715 page = shmem_read_mapping_page(mapping, i);
4717 return PTR_ERR(page);
4719 src = kmap_atomic(page);
4720 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4721 memcpy(dst, src, PAGE_SIZE);
4724 mark_page_accessed(page);
4725 page_cache_release(page);
4732 i915_gem_phys_pwrite(struct drm_device *dev,
4733 struct drm_i915_gem_object *obj,
4734 struct drm_i915_gem_pwrite *args,
4735 struct drm_file *file_priv)
4737 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4738 char __user *user_data = to_user_ptr(args->data_ptr);
4740 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4741 unsigned long unwritten;
4743 /* The physical object once assigned is fixed for the lifetime
4744 * of the obj, so we can safely drop the lock and continue
4747 mutex_unlock(&dev->struct_mutex);
4748 unwritten = copy_from_user(vaddr, user_data, args->size);
4749 mutex_lock(&dev->struct_mutex);
4754 i915_gem_chipset_flush(dev);
4758 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4760 struct drm_i915_file_private *file_priv = file->driver_priv;
4762 /* Clean up our request list when the client is going away, so that
4763 * later retire_requests won't dereference our soon-to-be-gone
4766 spin_lock(&file_priv->mm.lock);
4767 while (!list_empty(&file_priv->mm.request_list)) {
4768 struct drm_i915_gem_request *request;
4770 request = list_first_entry(&file_priv->mm.request_list,
4771 struct drm_i915_gem_request,
4773 list_del(&request->client_list);
4774 request->file_priv = NULL;
4776 spin_unlock(&file_priv->mm.lock);
4779 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4781 if (!mutex_is_locked(mutex))
4784 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4785 return mutex->owner == task;
4787 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4792 static unsigned long
4793 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
4795 struct drm_i915_private *dev_priv =
4796 container_of(shrinker,
4797 struct drm_i915_private,
4798 mm.inactive_shrinker);
4799 struct drm_device *dev = dev_priv->dev;
4800 struct drm_i915_gem_object *obj;
4802 unsigned long count;
4804 if (!mutex_trylock(&dev->struct_mutex)) {
4805 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4808 if (dev_priv->mm.shrinker_no_lock_stealing)
4815 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4816 if (obj->pages_pin_count == 0)
4817 count += obj->base.size >> PAGE_SHIFT;
4819 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4823 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4824 count += obj->base.size >> PAGE_SHIFT;
4828 mutex_unlock(&dev->struct_mutex);
4832 /* All the new VM stuff */
4833 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4834 struct i915_address_space *vm)
4836 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4837 struct i915_vma *vma;
4839 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4840 vm = &dev_priv->gtt.base;
4842 BUG_ON(list_empty(&o->vma_list));
4843 list_for_each_entry(vma, &o->vma_list, vma_link) {
4845 return vma->node.start;
4851 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4852 struct i915_address_space *vm)
4854 struct i915_vma *vma;
4856 list_for_each_entry(vma, &o->vma_list, vma_link)
4857 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4863 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4865 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4866 struct i915_address_space *vm;
4868 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4869 if (i915_gem_obj_bound(o, vm))
4875 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4876 struct i915_address_space *vm)
4878 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4879 struct i915_vma *vma;
4881 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4882 vm = &dev_priv->gtt.base;
4884 BUG_ON(list_empty(&o->vma_list));
4886 list_for_each_entry(vma, &o->vma_list, vma_link)
4888 return vma->node.size;
4893 static unsigned long
4894 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
4896 struct drm_i915_private *dev_priv =
4897 container_of(shrinker,
4898 struct drm_i915_private,
4899 mm.inactive_shrinker);
4900 struct drm_device *dev = dev_priv->dev;
4901 int nr_to_scan = sc->nr_to_scan;
4902 unsigned long freed;
4905 if (!mutex_trylock(&dev->struct_mutex)) {
4906 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4909 if (dev_priv->mm.shrinker_no_lock_stealing)
4915 freed = i915_gem_purge(dev_priv, nr_to_scan);
4916 if (freed < nr_to_scan)
4917 freed += __i915_gem_shrink(dev_priv, nr_to_scan,
4919 if (freed < nr_to_scan)
4920 freed += i915_gem_shrink_all(dev_priv);
4923 mutex_unlock(&dev->struct_mutex);
4927 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4928 struct i915_address_space *vm)
4930 struct i915_vma *vma;
4931 list_for_each_entry(vma, &obj->vma_list, vma_link)
4939 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4940 struct i915_address_space *vm)
4942 struct i915_vma *vma;
4944 vma = i915_gem_obj_to_vma(obj, vm);
4946 vma = i915_gem_vma_create(obj, vm);