drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                                           bool write);
  43 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                                   uint64_t offset,
  45                                                                   uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                                     unsigned alignment,
  49                                                     bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     int nr_to_scan,
  60                                     gfp_t gfp_mask);
  61
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 int
  79 i915_gem_check_is_wedged(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         /* Success, we reset the GPU! */
  94         if (!atomic_read(&dev_priv->mm.wedged))
  95                 return 0;
  96
  97         /* GPU is hung, bump the completion count to account for
  98          * the token we just consumed so that we never hit zero and
  99          * end up waiting upon a subsequent completion event that
 100          * will never happen.
 101          */
 102         spin_lock_irqsave(&x->wait.lock, flags);
 103         x->done++;
 104         spin_unlock_irqrestore(&x->wait.lock, flags);
 105         return -EIO;
 106 }
 107
 108 int i915_mutex_lock_interruptible(struct drm_device *dev)
 109 {
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         int ret;
 112
 113         ret = i915_gem_check_is_wedged(dev);
 114         if (ret)
 115                 return ret;
 116
 117         ret = mutex_lock_interruptible(&dev->struct_mutex);
 118         if (ret)
 119                 return ret;
 120
 121         if (atomic_read(&dev_priv->mm.wedged)) {
 122                 mutex_unlock(&dev->struct_mutex);
 123                 return -EAGAIN;
 124         }
 125
 126         WARN_ON(i915_verify_lists(dev));
 127         return 0;
 128 }
 129
 130 static inline bool
 131 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 132 {
 133         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 134 }
 135
 136 void i915_gem_do_init(struct drm_device *dev,
 137                       unsigned long start,
 138                       unsigned long mappable_end,
 139                       unsigned long end)
 140 {
 141         drm_i915_private_t *dev_priv = dev->dev_private;
 142
 143         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 144
 145         dev_priv->mm.gtt_start = start;
 146         dev_priv->mm.gtt_mappable_end = mappable_end;
 147         dev_priv->mm.gtt_end = end;
 148         dev_priv->mm.gtt_total = end - start;
 149         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 150
 151         /* Take over this portion of the GTT */
 152         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 153 }
 154
 155 int
 156 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 157                     struct drm_file *file)
 158 {
 159         struct drm_i915_gem_init *args = data;
 160
 161         if (args->gtt_start >= args->gtt_end ||
 162             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 163                 return -EINVAL;
 164
 165         mutex_lock(&dev->struct_mutex);
 166         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 167         mutex_unlock(&dev->struct_mutex);
 168
 169         return 0;
 170 }
 171
 172 int
 173 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 174                             struct drm_file *file)
 175 {
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177         struct drm_i915_gem_get_aperture *args = data;
 178         struct drm_i915_gem_object *obj;
 179         size_t pinned;
 180
 181         if (!(dev->driver->driver_features & DRIVER_GEM))
 182                 return -ENODEV;
 183
 184         pinned = 0;
 185         mutex_lock(&dev->struct_mutex);
 186         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 187                 pinned += obj->gtt_space->size;
 188         mutex_unlock(&dev->struct_mutex);
 189
 190         args->aper_size = dev_priv->mm.gtt_total;
 191         args->aper_available_size = args->aper_size -pinned;
 192
 193         return 0;
 194 }
 195
 196 static int
 197 i915_gem_create(struct drm_file *file,
 198                 struct drm_device *dev,
 199                 uint64_t size,
 200                 uint32_t *handle_p)
 201 {
 202         struct drm_i915_gem_object *obj;
 203         int ret;
 204         u32 handle;
 205
 206         size = roundup(size, PAGE_SIZE);
 207
 208         /* Allocate the new object */
 209         obj = i915_gem_alloc_object(dev, size);
 210         if (obj == NULL)
 211                 return -ENOMEM;
 212
 213         ret = drm_gem_handle_create(file, &obj->base, &handle);
 214         if (ret) {
 215                 drm_gem_object_release(&obj->base);
 216                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 217                 kfree(obj);
 218                 return ret;
 219         }
 220
 221         /* drop reference from allocate - handle holds it now */
 222         drm_gem_object_unreference(&obj->base);
 223         trace_i915_gem_object_create(obj);
 224
 225         *handle_p = handle;
 226         return 0;
 227 }
 228
 229 int
 230 i915_gem_dumb_create(struct drm_file *file,
 231                      struct drm_device *dev,
 232                      struct drm_mode_create_dumb *args)
 233 {
 234         /* have to work out size/pitch and return them */
 235         args->pitch = ALIGN(args->width & ((args->bpp + 1) / 8), 64);
 236         args->size = args->pitch * args->height;
 237         return i915_gem_create(file, dev,
 238                                args->size, &args->handle);
 239 }
 240
 241 int i915_gem_dumb_destroy(struct drm_file *file,
 242                           struct drm_device *dev,
 243                           uint32_t handle)
 244 {
 245         return drm_gem_handle_delete(file, handle);
 246 }
 247
 248 /**
 249  * Creates a new mm object and returns a handle to it.
 250  */
 251 int
 252 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 253                       struct drm_file *file)
 254 {
 255         struct drm_i915_gem_create *args = data;
 256         return i915_gem_create(file, dev,
 257                                args->size, &args->handle);
 258 }
 259
 260 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 261 {
 262         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 263
 264         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 265                 obj->tiling_mode != I915_TILING_NONE;
 266 }
 267
 268 static inline void
 269 slow_shmem_copy(struct page *dst_page,
 270                 int dst_offset,
 271                 struct page *src_page,
 272                 int src_offset,
 273                 int length)
 274 {
 275         char *dst_vaddr, *src_vaddr;
 276
 277         dst_vaddr = kmap(dst_page);
 278         src_vaddr = kmap(src_page);
 279
 280         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 281
 282         kunmap(src_page);
 283         kunmap(dst_page);
 284 }
 285
 286 static inline void
 287 slow_shmem_bit17_copy(struct page *gpu_page,
 288                       int gpu_offset,
 289                       struct page *cpu_page,
 290                       int cpu_offset,
 291                       int length,
 292                       int is_read)
 293 {
 294         char *gpu_vaddr, *cpu_vaddr;
 295
 296         /* Use the unswizzled path if this page isn't affected. */
 297         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 298                 if (is_read)
 299                         return slow_shmem_copy(cpu_page, cpu_offset,
 300                                                gpu_page, gpu_offset, length);
 301                 else
 302                         return slow_shmem_copy(gpu_page, gpu_offset,
 303                                                cpu_page, cpu_offset, length);
 304         }
 305
 306         gpu_vaddr = kmap(gpu_page);
 307         cpu_vaddr = kmap(cpu_page);
 308
 309         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 310          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 311          */
 312         while (length > 0) {
 313                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 314                 int this_length = min(cacheline_end - gpu_offset, length);
 315                 int swizzled_gpu_offset = gpu_offset ^ 64;
 316
 317                 if (is_read) {
 318                         memcpy(cpu_vaddr + cpu_offset,
 319                                gpu_vaddr + swizzled_gpu_offset,
 320                                this_length);
 321                 } else {
 322                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 323                                cpu_vaddr + cpu_offset,
 324                                this_length);
 325                 }
 326                 cpu_offset += this_length;
 327                 gpu_offset += this_length;
 328                 length -= this_length;
 329         }
 330
 331         kunmap(cpu_page);
 332         kunmap(gpu_page);
 333 }
 334
 335 /**
 336  * This is the fast shmem pread path, which attempts to copy_from_user directly
 337  * from the backing pages of the object to the user's address space.  On a
 338  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 339  */
 340 static int
 341 i915_gem_shmem_pread_fast(struct drm_device *dev,
 342                           struct drm_i915_gem_object *obj,
 343                           struct drm_i915_gem_pread *args,
 344                           struct drm_file *file)
 345 {
 346         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 347         ssize_t remain;
 348         loff_t offset;
 349         char __user *user_data;
 350         int page_offset, page_length;
 351
 352         user_data = (char __user *) (uintptr_t) args->data_ptr;
 353         remain = args->size;
 354
 355         offset = args->offset;
 356
 357         while (remain > 0) {
 358                 struct page *page;
 359                 char *vaddr;
 360                 int ret;
 361
 362                 /* Operation in this page
 363                  *
 364                  * page_offset = offset within page
 365                  * page_length = bytes to copy for this page
 366                  */
 367                 page_offset = offset & (PAGE_SIZE-1);
 368                 page_length = remain;
 369                 if ((page_offset + remain) > PAGE_SIZE)
 370                         page_length = PAGE_SIZE - page_offset;
 371
 372                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 373                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 374                 if (IS_ERR(page))
 375                         return PTR_ERR(page);
 376
 377                 vaddr = kmap_atomic(page);
 378                 ret = __copy_to_user_inatomic(user_data,
 379                                               vaddr + page_offset,
 380                                               page_length);
 381                 kunmap_atomic(vaddr);
 382
 383                 mark_page_accessed(page);
 384                 page_cache_release(page);
 385                 if (ret)
 386                         return -EFAULT;
 387
 388                 remain -= page_length;
 389                 user_data += page_length;
 390                 offset += page_length;
 391         }
 392
 393         return 0;
 394 }
 395
 396 /**
 397  * This is the fallback shmem pread path, which allocates temporary storage
 398  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 399  * can copy out of the object's backing pages while holding the struct mutex
 400  * and not take page faults.
 401  */
 402 static int
 403 i915_gem_shmem_pread_slow(struct drm_device *dev,
 404                           struct drm_i915_gem_object *obj,
 405                           struct drm_i915_gem_pread *args,
 406                           struct drm_file *file)
 407 {
 408         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 409         struct mm_struct *mm = current->mm;
 410         struct page **user_pages;
 411         ssize_t remain;
 412         loff_t offset, pinned_pages, i;
 413         loff_t first_data_page, last_data_page, num_pages;
 414         int shmem_page_offset;
 415         int data_page_index, data_page_offset;
 416         int page_length;
 417         int ret;
 418         uint64_t data_ptr = args->data_ptr;
 419         int do_bit17_swizzling;
 420
 421         remain = args->size;
 422
 423         /* Pin the user pages containing the data.  We can't fault while
 424          * holding the struct mutex, yet we want to hold it while
 425          * dereferencing the user data.
 426          */
 427         first_data_page = data_ptr / PAGE_SIZE;
 428         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 429         num_pages = last_data_page - first_data_page + 1;
 430
 431         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 432         if (user_pages == NULL)
 433                 return -ENOMEM;
 434
 435         mutex_unlock(&dev->struct_mutex);
 436         down_read(&mm->mmap_sem);
 437         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 438                                       num_pages, 1, 0, user_pages, NULL);
 439         up_read(&mm->mmap_sem);
 440         mutex_lock(&dev->struct_mutex);
 441         if (pinned_pages < num_pages) {
 442                 ret = -EFAULT;
 443                 goto out;
 444         }
 445
 446         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 447                                                         args->offset,
 448                                                         args->size);
 449         if (ret)
 450                 goto out;
 451
 452         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 453
 454         offset = args->offset;
 455
 456         while (remain > 0) {
 457                 struct page *page;
 458
 459                 /* Operation in this page
 460                  *
 461                  * shmem_page_offset = offset within page in shmem file
 462                  * data_page_index = page number in get_user_pages return
 463                  * data_page_offset = offset with data_page_index page.
 464                  * page_length = bytes to copy for this page
 465                  */
 466                 shmem_page_offset = offset & ~PAGE_MASK;
 467                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 468                 data_page_offset = data_ptr & ~PAGE_MASK;
 469
 470                 page_length = remain;
 471                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 472                         page_length = PAGE_SIZE - shmem_page_offset;
 473                 if ((data_page_offset + page_length) > PAGE_SIZE)
 474                         page_length = PAGE_SIZE - data_page_offset;
 475
 476                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 477                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 478                 if (IS_ERR(page))
 479                         return PTR_ERR(page);
 480
 481                 if (do_bit17_swizzling) {
 482                         slow_shmem_bit17_copy(page,
 483                                               shmem_page_offset,
 484                                               user_pages[data_page_index],
 485                                               data_page_offset,
 486                                               page_length,
 487                                               1);
 488                 } else {
 489                         slow_shmem_copy(user_pages[data_page_index],
 490                                         data_page_offset,
 491                                         page,
 492                                         shmem_page_offset,
 493                                         page_length);
 494                 }
 495
 496                 mark_page_accessed(page);
 497                 page_cache_release(page);
 498
 499                 remain -= page_length;
 500                 data_ptr += page_length;
 501                 offset += page_length;
 502         }
 503
 504 out:
 505         for (i = 0; i < pinned_pages; i++) {
 506                 SetPageDirty(user_pages[i]);
 507                 mark_page_accessed(user_pages[i]);
 508                 page_cache_release(user_pages[i]);
 509         }
 510         drm_free_large(user_pages);
 511
 512         return ret;
 513 }
 514
 515 /**
 516  * Reads data from the object referenced by handle.
 517  *
 518  * On error, the contents of *data are undefined.
 519  */
 520 int
 521 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 522                      struct drm_file *file)
 523 {
 524         struct drm_i915_gem_pread *args = data;
 525         struct drm_i915_gem_object *obj;
 526         int ret = 0;
 527
 528         if (args->size == 0)
 529                 return 0;
 530
 531         if (!access_ok(VERIFY_WRITE,
 532                        (char __user *)(uintptr_t)args->data_ptr,
 533                        args->size))
 534                 return -EFAULT;
 535
 536         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 537                                        args->size);
 538         if (ret)
 539                 return -EFAULT;
 540
 541         ret = i915_mutex_lock_interruptible(dev);
 542         if (ret)
 543                 return ret;
 544
 545         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 546         if (obj == NULL) {
 547                 ret = -ENOENT;
 548                 goto unlock;
 549         }
 550
 551         /* Bounds check source.  */
 552         if (args->offset > obj->base.size ||
 553             args->size > obj->base.size - args->offset) {
 554                 ret = -EINVAL;
 555                 goto out;
 556         }
 557
 558         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 559                                                         args->offset,
 560                                                         args->size);
 561         if (ret)
 562                 goto out;
 563
 564         ret = -EFAULT;
 565         if (!i915_gem_object_needs_bit17_swizzle(obj))
 566                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 567         if (ret == -EFAULT)
 568                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 569
 570 out:
 571         drm_gem_object_unreference(&obj->base);
 572 unlock:
 573         mutex_unlock(&dev->struct_mutex);
 574         return ret;
 575 }
 576
 577 /* This is the fast write path which cannot handle
 578  * page faults in the source data
 579  */
 580
 581 static inline int
 582 fast_user_write(struct io_mapping *mapping,
 583                 loff_t page_base, int page_offset,
 584                 char __user *user_data,
 585                 int length)
 586 {
 587         char *vaddr_atomic;
 588         unsigned long unwritten;
 589
 590         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 591         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 592                                                       user_data, length);
 593         io_mapping_unmap_atomic(vaddr_atomic);
 594         return unwritten;
 595 }
 596
 597 /* Here's the write path which can sleep for
 598  * page faults
 599  */
 600
 601 static inline void
 602 slow_kernel_write(struct io_mapping *mapping,
 603                   loff_t gtt_base, int gtt_offset,
 604                   struct page *user_page, int user_offset,
 605                   int length)
 606 {
 607         char __iomem *dst_vaddr;
 608         char *src_vaddr;
 609
 610         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 611         src_vaddr = kmap(user_page);
 612
 613         memcpy_toio(dst_vaddr + gtt_offset,
 614                     src_vaddr + user_offset,
 615                     length);
 616
 617         kunmap(user_page);
 618         io_mapping_unmap(dst_vaddr);
 619 }
 620
 621 /**
 622  * This is the fast pwrite path, where we copy the data directly from the
 623  * user into the GTT, uncached.
 624  */
 625 static int
 626 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 627                          struct drm_i915_gem_object *obj,
 628                          struct drm_i915_gem_pwrite *args,
 629                          struct drm_file *file)
 630 {
 631         drm_i915_private_t *dev_priv = dev->dev_private;
 632         ssize_t remain;
 633         loff_t offset, page_base;
 634         char __user *user_data;
 635         int page_offset, page_length;
 636
 637         user_data = (char __user *) (uintptr_t) args->data_ptr;
 638         remain = args->size;
 639
 640         offset = obj->gtt_offset + args->offset;
 641
 642         while (remain > 0) {
 643                 /* Operation in this page
 644                  *
 645                  * page_base = page offset within aperture
 646                  * page_offset = offset within page
 647                  * page_length = bytes to copy for this page
 648                  */
 649                 page_base = (offset & ~(PAGE_SIZE-1));
 650                 page_offset = offset & (PAGE_SIZE-1);
 651                 page_length = remain;
 652                 if ((page_offset + remain) > PAGE_SIZE)
 653                         page_length = PAGE_SIZE - page_offset;
 654
 655                 /* If we get a fault while copying data, then (presumably) our
 656                  * source page isn't available.  Return the error and we'll
 657                  * retry in the slow path.
 658                  */
 659                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 660                                     page_offset, user_data, page_length))
 661
 662                         return -EFAULT;
 663
 664                 remain -= page_length;
 665                 user_data += page_length;
 666                 offset += page_length;
 667         }
 668
 669         return 0;
 670 }
 671
 672 /**
 673  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 674  * the memory and maps it using kmap_atomic for copying.
 675  *
 676  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 677  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 678  */
 679 static int
 680 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 681                          struct drm_i915_gem_object *obj,
 682                          struct drm_i915_gem_pwrite *args,
 683                          struct drm_file *file)
 684 {
 685         drm_i915_private_t *dev_priv = dev->dev_private;
 686         ssize_t remain;
 687         loff_t gtt_page_base, offset;
 688         loff_t first_data_page, last_data_page, num_pages;
 689         loff_t pinned_pages, i;
 690         struct page **user_pages;
 691         struct mm_struct *mm = current->mm;
 692         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 693         int ret;
 694         uint64_t data_ptr = args->data_ptr;
 695
 696         remain = args->size;
 697
 698         /* Pin the user pages containing the data.  We can't fault while
 699          * holding the struct mutex, and all of the pwrite implementations
 700          * want to hold it while dereferencing the user data.
 701          */
 702         first_data_page = data_ptr / PAGE_SIZE;
 703         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 704         num_pages = last_data_page - first_data_page + 1;
 705
 706         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 707         if (user_pages == NULL)
 708                 return -ENOMEM;
 709
 710         mutex_unlock(&dev->struct_mutex);
 711         down_read(&mm->mmap_sem);
 712         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 713                                       num_pages, 0, 0, user_pages, NULL);
 714         up_read(&mm->mmap_sem);
 715         mutex_lock(&dev->struct_mutex);
 716         if (pinned_pages < num_pages) {
 717                 ret = -EFAULT;
 718                 goto out_unpin_pages;
 719         }
 720
 721         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 722         if (ret)
 723                 goto out_unpin_pages;
 724
 725         ret = i915_gem_object_put_fence(obj);
 726         if (ret)
 727                 goto out_unpin_pages;
 728
 729         offset = obj->gtt_offset + args->offset;
 730
 731         while (remain > 0) {
 732                 /* Operation in this page
 733                  *
 734                  * gtt_page_base = page offset within aperture
 735                  * gtt_page_offset = offset within page in aperture
 736                  * data_page_index = page number in get_user_pages return
 737                  * data_page_offset = offset with data_page_index page.
 738                  * page_length = bytes to copy for this page
 739                  */
 740                 gtt_page_base = offset & PAGE_MASK;
 741                 gtt_page_offset = offset & ~PAGE_MASK;
 742                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 743                 data_page_offset = data_ptr & ~PAGE_MASK;
 744
 745                 page_length = remain;
 746                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 747                         page_length = PAGE_SIZE - gtt_page_offset;
 748                 if ((data_page_offset + page_length) > PAGE_SIZE)
 749                         page_length = PAGE_SIZE - data_page_offset;
 750
 751                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 752                                   gtt_page_base, gtt_page_offset,
 753                                   user_pages[data_page_index],
 754                                   data_page_offset,
 755                                   page_length);
 756
 757                 remain -= page_length;
 758                 offset += page_length;
 759                 data_ptr += page_length;
 760         }
 761
 762 out_unpin_pages:
 763         for (i = 0; i < pinned_pages; i++)
 764                 page_cache_release(user_pages[i]);
 765         drm_free_large(user_pages);
 766
 767         return ret;
 768 }
 769
 770 /**
 771  * This is the fast shmem pwrite path, which attempts to directly
 772  * copy_from_user into the kmapped pages backing the object.
 773  */
 774 static int
 775 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 776                            struct drm_i915_gem_object *obj,
 777                            struct drm_i915_gem_pwrite *args,
 778                            struct drm_file *file)
 779 {
 780         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 781         ssize_t remain;
 782         loff_t offset;
 783         char __user *user_data;
 784         int page_offset, page_length;
 785
 786         user_data = (char __user *) (uintptr_t) args->data_ptr;
 787         remain = args->size;
 788
 789         offset = args->offset;
 790         obj->dirty = 1;
 791
 792         while (remain > 0) {
 793                 struct page *page;
 794                 char *vaddr;
 795                 int ret;
 796
 797                 /* Operation in this page
 798                  *
 799                  * page_offset = offset within page
 800                  * page_length = bytes to copy for this page
 801                  */
 802                 page_offset = offset & (PAGE_SIZE-1);
 803                 page_length = remain;
 804                 if ((page_offset + remain) > PAGE_SIZE)
 805                         page_length = PAGE_SIZE - page_offset;
 806
 807                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 808                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 809                 if (IS_ERR(page))
 810                         return PTR_ERR(page);
 811
 812                 vaddr = kmap_atomic(page, KM_USER0);
 813                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 814                                                 user_data,
 815                                                 page_length);
 816                 kunmap_atomic(vaddr, KM_USER0);
 817
 818                 set_page_dirty(page);
 819                 mark_page_accessed(page);
 820                 page_cache_release(page);
 821
 822                 /* If we get a fault while copying data, then (presumably) our
 823                  * source page isn't available.  Return the error and we'll
 824                  * retry in the slow path.
 825                  */
 826                 if (ret)
 827                         return -EFAULT;
 828
 829                 remain -= page_length;
 830                 user_data += page_length;
 831                 offset += page_length;
 832         }
 833
 834         return 0;
 835 }
 836
 837 /**
 838  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 839  * the memory and maps it using kmap_atomic for copying.
 840  *
 841  * This avoids taking mmap_sem for faulting on the user's address while the
 842  * struct_mutex is held.
 843  */
 844 static int
 845 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 846                            struct drm_i915_gem_object *obj,
 847                            struct drm_i915_gem_pwrite *args,
 848                            struct drm_file *file)
 849 {
 850         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 851         struct mm_struct *mm = current->mm;
 852         struct page **user_pages;
 853         ssize_t remain;
 854         loff_t offset, pinned_pages, i;
 855         loff_t first_data_page, last_data_page, num_pages;
 856         int shmem_page_offset;
 857         int data_page_index,  data_page_offset;
 858         int page_length;
 859         int ret;
 860         uint64_t data_ptr = args->data_ptr;
 861         int do_bit17_swizzling;
 862
 863         remain = args->size;
 864
 865         /* Pin the user pages containing the data.  We can't fault while
 866          * holding the struct mutex, and all of the pwrite implementations
 867          * want to hold it while dereferencing the user data.
 868          */
 869         first_data_page = data_ptr / PAGE_SIZE;
 870         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 871         num_pages = last_data_page - first_data_page + 1;
 872
 873         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 874         if (user_pages == NULL)
 875                 return -ENOMEM;
 876
 877         mutex_unlock(&dev->struct_mutex);
 878         down_read(&mm->mmap_sem);
 879         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 880                                       num_pages, 0, 0, user_pages, NULL);
 881         up_read(&mm->mmap_sem);
 882         mutex_lock(&dev->struct_mutex);
 883         if (pinned_pages < num_pages) {
 884                 ret = -EFAULT;
 885                 goto out;
 886         }
 887
 888         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 889         if (ret)
 890                 goto out;
 891
 892         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 893
 894         offset = args->offset;
 895         obj->dirty = 1;
 896
 897         while (remain > 0) {
 898                 struct page *page;
 899
 900                 /* Operation in this page
 901                  *
 902                  * shmem_page_offset = offset within page in shmem file
 903                  * data_page_index = page number in get_user_pages return
 904                  * data_page_offset = offset with data_page_index page.
 905                  * page_length = bytes to copy for this page
 906                  */
 907                 shmem_page_offset = offset & ~PAGE_MASK;
 908                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 909                 data_page_offset = data_ptr & ~PAGE_MASK;
 910
 911                 page_length = remain;
 912                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 913                         page_length = PAGE_SIZE - shmem_page_offset;
 914                 if ((data_page_offset + page_length) > PAGE_SIZE)
 915                         page_length = PAGE_SIZE - data_page_offset;
 916
 917                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 918                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 919                 if (IS_ERR(page)) {
 920                         ret = PTR_ERR(page);
 921                         goto out;
 922                 }
 923
 924                 if (do_bit17_swizzling) {
 925                         slow_shmem_bit17_copy(page,
 926                                               shmem_page_offset,
 927                                               user_pages[data_page_index],
 928                                               data_page_offset,
 929                                               page_length,
 930                                               0);
 931                 } else {
 932                         slow_shmem_copy(page,
 933                                         shmem_page_offset,
 934                                         user_pages[data_page_index],
 935                                         data_page_offset,
 936                                         page_length);
 937                 }
 938
 939                 set_page_dirty(page);
 940                 mark_page_accessed(page);
 941                 page_cache_release(page);
 942
 943                 remain -= page_length;
 944                 data_ptr += page_length;
 945                 offset += page_length;
 946         }
 947
 948 out:
 949         for (i = 0; i < pinned_pages; i++)
 950                 page_cache_release(user_pages[i]);
 951         drm_free_large(user_pages);
 952
 953         return ret;
 954 }
 955
 956 /**
 957  * Writes data to the object referenced by handle.
 958  *
 959  * On error, the contents of the buffer that were to be modified are undefined.
 960  */
 961 int
 962 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 963                       struct drm_file *file)
 964 {
 965         struct drm_i915_gem_pwrite *args = data;
 966         struct drm_i915_gem_object *obj;
 967         int ret;
 968
 969         if (args->size == 0)
 970                 return 0;
 971
 972         if (!access_ok(VERIFY_READ,
 973                        (char __user *)(uintptr_t)args->data_ptr,
 974                        args->size))
 975                 return -EFAULT;
 976
 977         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 978                                       args->size);
 979         if (ret)
 980                 return -EFAULT;
 981
 982         ret = i915_mutex_lock_interruptible(dev);
 983         if (ret)
 984                 return ret;
 985
 986         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 987         if (obj == NULL) {
 988                 ret = -ENOENT;
 989                 goto unlock;
 990         }
 991
 992         /* Bounds check destination. */
 993         if (args->offset > obj->base.size ||
 994             args->size > obj->base.size - args->offset) {
 995                 ret = -EINVAL;
 996                 goto out;
 997         }
 998
 999         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1000          * it would end up going through the fenced access, and we'll get
1001          * different detiling behavior between reading and writing.
1002          * pread/pwrite currently are reading and writing from the CPU
1003          * perspective, requiring manual detiling by the client.
1004          */
1005         if (obj->phys_obj)
1006                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1007         else if (obj->gtt_space &&
1008                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1009                 ret = i915_gem_object_pin(obj, 0, true);
1010                 if (ret)
1011                         goto out;
1012
1013                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1014                 if (ret)
1015                         goto out_unpin;
1016
1017                 ret = i915_gem_object_put_fence(obj);
1018                 if (ret)
1019                         goto out_unpin;
1020
1021                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1022                 if (ret == -EFAULT)
1023                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1024
1025 out_unpin:
1026                 i915_gem_object_unpin(obj);
1027         } else {
1028                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1029                 if (ret)
1030                         goto out;
1031
1032                 ret = -EFAULT;
1033                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1034                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1035                 if (ret == -EFAULT)
1036                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1037         }
1038
1039 out:
1040         drm_gem_object_unreference(&obj->base);
1041 unlock:
1042         mutex_unlock(&dev->struct_mutex);
1043         return ret;
1044 }
1045
1046 /**
1047  * Called when user space prepares to use an object with the CPU, either
1048  * through the mmap ioctl's mapping or a GTT mapping.
1049  */
1050 int
1051 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1052                           struct drm_file *file)
1053 {
1054         struct drm_i915_gem_set_domain *args = data;
1055         struct drm_i915_gem_object *obj;
1056         uint32_t read_domains = args->read_domains;
1057         uint32_t write_domain = args->write_domain;
1058         int ret;
1059
1060         if (!(dev->driver->driver_features & DRIVER_GEM))
1061                 return -ENODEV;
1062
1063         /* Only handle setting domains to types used by the CPU. */
1064         if (write_domain & I915_GEM_GPU_DOMAINS)
1065                 return -EINVAL;
1066
1067         if (read_domains & I915_GEM_GPU_DOMAINS)
1068                 return -EINVAL;
1069
1070         /* Having something in the write domain implies it's in the read
1071          * domain, and only that read domain.  Enforce that in the request.
1072          */
1073         if (write_domain != 0 && read_domains != write_domain)
1074                 return -EINVAL;
1075
1076         ret = i915_mutex_lock_interruptible(dev);
1077         if (ret)
1078                 return ret;
1079
1080         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1081         if (obj == NULL) {
1082                 ret = -ENOENT;
1083                 goto unlock;
1084         }
1085
1086         if (read_domains & I915_GEM_DOMAIN_GTT) {
1087                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1088
1089                 /* Silently promote "you're not bound, there was nothing to do"
1090                  * to success, since the client was just asking us to
1091                  * make sure everything was done.
1092                  */
1093                 if (ret == -EINVAL)
1094                         ret = 0;
1095         } else {
1096                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1097         }
1098
1099         drm_gem_object_unreference(&obj->base);
1100 unlock:
1101         mutex_unlock(&dev->struct_mutex);
1102         return ret;
1103 }
1104
1105 /**
1106  * Called when user space has done writes to this buffer
1107  */
1108 int
1109 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1110                          struct drm_file *file)
1111 {
1112         struct drm_i915_gem_sw_finish *args = data;
1113         struct drm_i915_gem_object *obj;
1114         int ret = 0;
1115
1116         if (!(dev->driver->driver_features & DRIVER_GEM))
1117                 return -ENODEV;
1118
1119         ret = i915_mutex_lock_interruptible(dev);
1120         if (ret)
1121                 return ret;
1122
1123         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1124         if (obj == NULL) {
1125                 ret = -ENOENT;
1126                 goto unlock;
1127         }
1128
1129         /* Pinned buffers may be scanout, so flush the cache */
1130         if (obj->pin_count)
1131                 i915_gem_object_flush_cpu_write_domain(obj);
1132
1133         drm_gem_object_unreference(&obj->base);
1134 unlock:
1135         mutex_unlock(&dev->struct_mutex);
1136         return ret;
1137 }
1138
1139 /**
1140  * Maps the contents of an object, returning the address it is mapped
1141  * into.
1142  *
1143  * While the mapping holds a reference on the contents of the object, it doesn't
1144  * imply a ref on the object itself.
1145  */
1146 int
1147 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1148                     struct drm_file *file)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_i915_gem_mmap *args = data;
1152         struct drm_gem_object *obj;
1153         loff_t offset;
1154         unsigned long addr;
1155
1156         if (!(dev->driver->driver_features & DRIVER_GEM))
1157                 return -ENODEV;
1158
1159         obj = drm_gem_object_lookup(dev, file, args->handle);
1160         if (obj == NULL)
1161                 return -ENOENT;
1162
1163         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1164                 drm_gem_object_unreference_unlocked(obj);
1165                 return -E2BIG;
1166         }
1167
1168         offset = args->offset;
1169
1170         down_write(&current->mm->mmap_sem);
1171         addr = do_mmap(obj->filp, 0, args->size,
1172                        PROT_READ | PROT_WRITE, MAP_SHARED,
1173                        args->offset);
1174         up_write(&current->mm->mmap_sem);
1175         drm_gem_object_unreference_unlocked(obj);
1176         if (IS_ERR((void *)addr))
1177                 return addr;
1178
1179         args->addr_ptr = (uint64_t) addr;
1180
1181         return 0;
1182 }
1183
1184 /**
1185  * i915_gem_fault - fault a page into the GTT
1186  * vma: VMA in question
1187  * vmf: fault info
1188  *
1189  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1190  * from userspace.  The fault handler takes care of binding the object to
1191  * the GTT (if needed), allocating and programming a fence register (again,
1192  * only if needed based on whether the old reg is still valid or the object
1193  * is tiled) and inserting a new PTE into the faulting process.
1194  *
1195  * Note that the faulting process may involve evicting existing objects
1196  * from the GTT and/or fence registers to make room.  So performance may
1197  * suffer if the GTT working set is large or there are few fence registers
1198  * left.
1199  */
1200 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1201 {
1202         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1203         struct drm_device *dev = obj->base.dev;
1204         drm_i915_private_t *dev_priv = dev->dev_private;
1205         pgoff_t page_offset;
1206         unsigned long pfn;
1207         int ret = 0;
1208         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1209
1210         /* We don't use vmf->pgoff since that has the fake offset */
1211         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1212                 PAGE_SHIFT;
1213
1214         /* Now bind it into the GTT if needed */
1215         mutex_lock(&dev->struct_mutex);
1216
1217         if (!obj->map_and_fenceable) {
1218                 ret = i915_gem_object_unbind(obj);
1219                 if (ret)
1220                         goto unlock;
1221         }
1222         if (!obj->gtt_space) {
1223                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1224                 if (ret)
1225                         goto unlock;
1226         }
1227
1228         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1229         if (ret)
1230                 goto unlock;
1231
1232         if (obj->tiling_mode == I915_TILING_NONE)
1233                 ret = i915_gem_object_put_fence(obj);
1234         else
1235                 ret = i915_gem_object_get_fence(obj, NULL, true);
1236         if (ret)
1237                 goto unlock;
1238
1239         if (i915_gem_object_is_inactive(obj))
1240                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1241
1242         obj->fault_mappable = true;
1243
1244         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1245                 page_offset;
1246
1247         /* Finally, remap it using the new GTT offset */
1248         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1249 unlock:
1250         mutex_unlock(&dev->struct_mutex);
1251
1252         switch (ret) {
1253         case -EAGAIN:
1254                 set_need_resched();
1255         case 0:
1256         case -ERESTARTSYS:
1257                 return VM_FAULT_NOPAGE;
1258         case -ENOMEM:
1259                 return VM_FAULT_OOM;
1260         default:
1261                 return VM_FAULT_SIGBUS;
1262         }
1263 }
1264
1265 /**
1266  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1267  * @obj: obj in question
1268  *
1269  * GEM memory mapping works by handing back to userspace a fake mmap offset
1270  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1271  * up the object based on the offset and sets up the various memory mapping
1272  * structures.
1273  *
1274  * This routine allocates and attaches a fake offset for @obj.
1275  */
1276 static int
1277 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1278 {
1279         struct drm_device *dev = obj->base.dev;
1280         struct drm_gem_mm *mm = dev->mm_private;
1281         struct drm_map_list *list;
1282         struct drm_local_map *map;
1283         int ret = 0;
1284
1285         /* Set the object up for mmap'ing */
1286         list = &obj->base.map_list;
1287         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1288         if (!list->map)
1289                 return -ENOMEM;
1290
1291         map = list->map;
1292         map->type = _DRM_GEM;
1293         map->size = obj->base.size;
1294         map->handle = obj;
1295
1296         /* Get a DRM GEM mmap offset allocated... */
1297         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1298                                                     obj->base.size / PAGE_SIZE,
1299                                                     0, 0);
1300         if (!list->file_offset_node) {
1301                 DRM_ERROR("failed to allocate offset for bo %d\n",
1302                           obj->base.name);
1303                 ret = -ENOSPC;
1304                 goto out_free_list;
1305         }
1306
1307         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1308                                                   obj->base.size / PAGE_SIZE,
1309                                                   0);
1310         if (!list->file_offset_node) {
1311                 ret = -ENOMEM;
1312                 goto out_free_list;
1313         }
1314
1315         list->hash.key = list->file_offset_node->start;
1316         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1317         if (ret) {
1318                 DRM_ERROR("failed to add to map hash\n");
1319                 goto out_free_mm;
1320         }
1321
1322         return 0;
1323
1324 out_free_mm:
1325         drm_mm_put_block(list->file_offset_node);
1326 out_free_list:
1327         kfree(list->map);
1328         list->map = NULL;
1329
1330         return ret;
1331 }
1332
1333 /**
1334  * i915_gem_release_mmap - remove physical page mappings
1335  * @obj: obj in question
1336  *
1337  * Preserve the reservation of the mmapping with the DRM core code, but
1338  * relinquish ownership of the pages back to the system.
1339  *
1340  * It is vital that we remove the page mapping if we have mapped a tiled
1341  * object through the GTT and then lose the fence register due to
1342  * resource pressure. Similarly if the object has been moved out of the
1343  * aperture, than pages mapped into userspace must be revoked. Removing the
1344  * mapping will then trigger a page fault on the next user access, allowing
1345  * fixup by i915_gem_fault().
1346  */
1347 void
1348 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1349 {
1350         if (!obj->fault_mappable)
1351                 return;
1352
1353         unmap_mapping_range(obj->base.dev->dev_mapping,
1354                             (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1355                             obj->base.size, 1);
1356
1357         obj->fault_mappable = false;
1358 }
1359
1360 static void
1361 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1362 {
1363         struct drm_device *dev = obj->base.dev;
1364         struct drm_gem_mm *mm = dev->mm_private;
1365         struct drm_map_list *list = &obj->base.map_list;
1366
1367         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1368         drm_mm_put_block(list->file_offset_node);
1369         kfree(list->map);
1370         list->map = NULL;
1371 }
1372
1373 static uint32_t
1374 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1375 {
1376         struct drm_device *dev = obj->base.dev;
1377         uint32_t size;
1378
1379         if (INTEL_INFO(dev)->gen >= 4 ||
1380             obj->tiling_mode == I915_TILING_NONE)
1381                 return obj->base.size;
1382
1383         /* Previous chips need a power-of-two fence region when tiling */
1384         if (INTEL_INFO(dev)->gen == 3)
1385                 size = 1024*1024;
1386         else
1387                 size = 512*1024;
1388
1389         while (size < obj->base.size)
1390                 size <<= 1;
1391
1392         return size;
1393 }
1394
1395 /**
1396  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1397  * @obj: object to check
1398  *
1399  * Return the required GTT alignment for an object, taking into account
1400  * potential fence register mapping.
1401  */
1402 static uint32_t
1403 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1404 {
1405         struct drm_device *dev = obj->base.dev;
1406
1407         /*
1408          * Minimum alignment is 4k (GTT page size), but might be greater
1409          * if a fence register is needed for the object.
1410          */
1411         if (INTEL_INFO(dev)->gen >= 4 ||
1412             obj->tiling_mode == I915_TILING_NONE)
1413                 return 4096;
1414
1415         /*
1416          * Previous chips need to be aligned to the size of the smallest
1417          * fence register that can contain the object.
1418          */
1419         return i915_gem_get_gtt_size(obj);
1420 }
1421
1422 /**
1423  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1424  *                                       unfenced object
1425  * @obj: object to check
1426  *
1427  * Return the required GTT alignment for an object, only taking into account
1428  * unfenced tiled surface requirements.
1429  */
1430 static uint32_t
1431 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1432 {
1433         struct drm_device *dev = obj->base.dev;
1434         int tile_height;
1435
1436         /*
1437          * Minimum alignment is 4k (GTT page size) for sane hw.
1438          */
1439         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1440             obj->tiling_mode == I915_TILING_NONE)
1441                 return 4096;
1442
1443         /*
1444          * Older chips need unfenced tiled buffers to be aligned to the left
1445          * edge of an even tile row (where tile rows are counted as if the bo is
1446          * placed in a fenced gtt region).
1447          */
1448         if (IS_GEN2(dev) ||
1449             (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1450                 tile_height = 32;
1451         else
1452                 tile_height = 8;
1453
1454         return tile_height * obj->stride * 2;
1455 }
1456
1457 int
1458 i915_gem_mmap_gtt(struct drm_file *file,
1459                   struct drm_device *dev,
1460                   uint32_t handle,
1461                   uint64_t *offset)
1462 {
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         struct drm_i915_gem_object *obj;
1465         int ret;
1466
1467         if (!(dev->driver->driver_features & DRIVER_GEM))
1468                 return -ENODEV;
1469
1470         ret = i915_mutex_lock_interruptible(dev);
1471         if (ret)
1472                 return ret;
1473
1474         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1475         if (obj == NULL) {
1476                 ret = -ENOENT;
1477                 goto unlock;
1478         }
1479
1480         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1481                 ret = -E2BIG;
1482                 goto unlock;
1483         }
1484
1485         if (obj->madv != I915_MADV_WILLNEED) {
1486                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1487                 ret = -EINVAL;
1488                 goto out;
1489         }
1490
1491         if (!obj->base.map_list.map) {
1492                 ret = i915_gem_create_mmap_offset(obj);
1493                 if (ret)
1494                         goto out;
1495         }
1496
1497         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1498
1499 out:
1500         drm_gem_object_unreference(&obj->base);
1501 unlock:
1502         mutex_unlock(&dev->struct_mutex);
1503         return ret;
1504 }
1505
1506 /**
1507  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1508  * @dev: DRM device
1509  * @data: GTT mapping ioctl data
1510  * @file: GEM object info
1511  *
1512  * Simply returns the fake offset to userspace so it can mmap it.
1513  * The mmap call will end up in drm_gem_mmap(), which will set things
1514  * up so we can get faults in the handler above.
1515  *
1516  * The fault handler will take care of binding the object into the GTT
1517  * (since it may have been evicted to make room for something), allocating
1518  * a fence register, and mapping the appropriate aperture address into
1519  * userspace.
1520  */
1521 int
1522 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1523                         struct drm_file *file)
1524 {
1525         struct drm_i915_gem_mmap_gtt *args = data;
1526
1527         if (!(dev->driver->driver_features & DRIVER_GEM))
1528                 return -ENODEV;
1529
1530         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1531 }
1532
1533
1534 static int
1535 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1536                               gfp_t gfpmask)
1537 {
1538         int page_count, i;
1539         struct address_space *mapping;
1540         struct inode *inode;
1541         struct page *page;
1542
1543         /* Get the list of pages out of our struct file.  They'll be pinned
1544          * at this point until we release them.
1545          */
1546         page_count = obj->base.size / PAGE_SIZE;
1547         BUG_ON(obj->pages != NULL);
1548         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1549         if (obj->pages == NULL)
1550                 return -ENOMEM;
1551
1552         inode = obj->base.filp->f_path.dentry->d_inode;
1553         mapping = inode->i_mapping;
1554         for (i = 0; i < page_count; i++) {
1555                 page = read_cache_page_gfp(mapping, i,
1556                                            GFP_HIGHUSER |
1557                                            __GFP_COLD |
1558                                            __GFP_RECLAIMABLE |
1559                                            gfpmask);
1560                 if (IS_ERR(page))
1561                         goto err_pages;
1562
1563                 obj->pages[i] = page;
1564         }
1565
1566         if (obj->tiling_mode != I915_TILING_NONE)
1567                 i915_gem_object_do_bit_17_swizzle(obj);
1568
1569         return 0;
1570
1571 err_pages:
1572         while (i--)
1573                 page_cache_release(obj->pages[i]);
1574
1575         drm_free_large(obj->pages);
1576         obj->pages = NULL;
1577         return PTR_ERR(page);
1578 }
1579
1580 static void
1581 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1582 {
1583         int page_count = obj->base.size / PAGE_SIZE;
1584         int i;
1585
1586         BUG_ON(obj->madv == __I915_MADV_PURGED);
1587
1588         if (obj->tiling_mode != I915_TILING_NONE)
1589                 i915_gem_object_save_bit_17_swizzle(obj);
1590
1591         if (obj->madv == I915_MADV_DONTNEED)
1592                 obj->dirty = 0;
1593
1594         for (i = 0; i < page_count; i++) {
1595                 if (obj->dirty)
1596                         set_page_dirty(obj->pages[i]);
1597
1598                 if (obj->madv == I915_MADV_WILLNEED)
1599                         mark_page_accessed(obj->pages[i]);
1600
1601                 page_cache_release(obj->pages[i]);
1602         }
1603         obj->dirty = 0;
1604
1605         drm_free_large(obj->pages);
1606         obj->pages = NULL;
1607 }
1608
1609 void
1610 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1611                                struct intel_ring_buffer *ring,
1612                                u32 seqno)
1613 {
1614         struct drm_device *dev = obj->base.dev;
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616
1617         BUG_ON(ring == NULL);
1618         obj->ring = ring;
1619
1620         /* Add a reference if we're newly entering the active list. */
1621         if (!obj->active) {
1622                 drm_gem_object_reference(&obj->base);
1623                 obj->active = 1;
1624         }
1625
1626         /* Move from whatever list we were on to the tail of execution. */
1627         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1628         list_move_tail(&obj->ring_list, &ring->active_list);
1629
1630         obj->last_rendering_seqno = seqno;
1631         if (obj->fenced_gpu_access) {
1632                 struct drm_i915_fence_reg *reg;
1633
1634                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1635
1636                 obj->last_fenced_seqno = seqno;
1637                 obj->last_fenced_ring = ring;
1638
1639                 reg = &dev_priv->fence_regs[obj->fence_reg];
1640                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1641         }
1642 }
1643
1644 static void
1645 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1646 {
1647         list_del_init(&obj->ring_list);
1648         obj->last_rendering_seqno = 0;
1649 }
1650
1651 static void
1652 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1653 {
1654         struct drm_device *dev = obj->base.dev;
1655         drm_i915_private_t *dev_priv = dev->dev_private;
1656
1657         BUG_ON(!obj->active);
1658         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1659
1660         i915_gem_object_move_off_active(obj);
1661 }
1662
1663 static void
1664 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1665 {
1666         struct drm_device *dev = obj->base.dev;
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668
1669         if (obj->pin_count != 0)
1670                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1671         else
1672                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1673
1674         BUG_ON(!list_empty(&obj->gpu_write_list));
1675         BUG_ON(!obj->active);
1676         obj->ring = NULL;
1677
1678         i915_gem_object_move_off_active(obj);
1679         obj->fenced_gpu_access = false;
1680
1681         obj->active = 0;
1682         obj->pending_gpu_write = false;
1683         drm_gem_object_unreference(&obj->base);
1684
1685         WARN_ON(i915_verify_lists(dev));
1686 }
1687
1688 /* Immediately discard the backing storage */
1689 static void
1690 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1691 {
1692         struct inode *inode;
1693
1694         /* Our goal here is to return as much of the memory as
1695          * is possible back to the system as we are called from OOM.
1696          * To do this we must instruct the shmfs to drop all of its
1697          * backing pages, *now*. Here we mirror the actions taken
1698          * when by shmem_delete_inode() to release the backing store.
1699          */
1700         inode = obj->base.filp->f_path.dentry->d_inode;
1701         truncate_inode_pages(inode->i_mapping, 0);
1702         if (inode->i_op->truncate_range)
1703                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1704
1705         obj->madv = __I915_MADV_PURGED;
1706 }
1707
1708 static inline int
1709 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1710 {
1711         return obj->madv == I915_MADV_DONTNEED;
1712 }
1713
1714 static void
1715 i915_gem_process_flushing_list(struct drm_device *dev,
1716                                uint32_t flush_domains,
1717                                struct intel_ring_buffer *ring)
1718 {
1719         struct drm_i915_gem_object *obj, *next;
1720
1721         list_for_each_entry_safe(obj, next,
1722                                  &ring->gpu_write_list,
1723                                  gpu_write_list) {
1724                 if (obj->base.write_domain & flush_domains) {
1725                         uint32_t old_write_domain = obj->base.write_domain;
1726
1727                         obj->base.write_domain = 0;
1728                         list_del_init(&obj->gpu_write_list);
1729                         i915_gem_object_move_to_active(obj, ring,
1730                                                        i915_gem_next_request_seqno(dev, ring));
1731
1732                         trace_i915_gem_object_change_domain(obj,
1733                                                             obj->base.read_domains,
1734                                                             old_write_domain);
1735                 }
1736         }
1737 }
1738
1739 int
1740 i915_add_request(struct drm_device *dev,
1741                  struct drm_file *file,
1742                  struct drm_i915_gem_request *request,
1743                  struct intel_ring_buffer *ring)
1744 {
1745         drm_i915_private_t *dev_priv = dev->dev_private;
1746         struct drm_i915_file_private *file_priv = NULL;
1747         uint32_t seqno;
1748         int was_empty;
1749         int ret;
1750
1751         BUG_ON(request == NULL);
1752
1753         if (file != NULL)
1754                 file_priv = file->driver_priv;
1755
1756         ret = ring->add_request(ring, &seqno);
1757         if (ret)
1758             return ret;
1759
1760         ring->outstanding_lazy_request = false;
1761
1762         request->seqno = seqno;
1763         request->ring = ring;
1764         request->emitted_jiffies = jiffies;
1765         was_empty = list_empty(&ring->request_list);
1766         list_add_tail(&request->list, &ring->request_list);
1767
1768         if (file_priv) {
1769                 spin_lock(&file_priv->mm.lock);
1770                 request->file_priv = file_priv;
1771                 list_add_tail(&request->client_list,
1772                               &file_priv->mm.request_list);
1773                 spin_unlock(&file_priv->mm.lock);
1774         }
1775
1776         if (!dev_priv->mm.suspended) {
1777                 mod_timer(&dev_priv->hangcheck_timer,
1778                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1779                 if (was_empty)
1780                         queue_delayed_work(dev_priv->wq,
1781                                            &dev_priv->mm.retire_work, HZ);
1782         }
1783         return 0;
1784 }
1785
1786 static inline void
1787 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1788 {
1789         struct drm_i915_file_private *file_priv = request->file_priv;
1790
1791         if (!file_priv)
1792                 return;
1793
1794         spin_lock(&file_priv->mm.lock);
1795         list_del(&request->client_list);
1796         request->file_priv = NULL;
1797         spin_unlock(&file_priv->mm.lock);
1798 }
1799
1800 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1801                                       struct intel_ring_buffer *ring)
1802 {
1803         while (!list_empty(&ring->request_list)) {
1804                 struct drm_i915_gem_request *request;
1805
1806                 request = list_first_entry(&ring->request_list,
1807                                            struct drm_i915_gem_request,
1808                                            list);
1809
1810                 list_del(&request->list);
1811                 i915_gem_request_remove_from_client(request);
1812                 kfree(request);
1813         }
1814
1815         while (!list_empty(&ring->active_list)) {
1816                 struct drm_i915_gem_object *obj;
1817
1818                 obj = list_first_entry(&ring->active_list,
1819                                        struct drm_i915_gem_object,
1820                                        ring_list);
1821
1822                 obj->base.write_domain = 0;
1823                 list_del_init(&obj->gpu_write_list);
1824                 i915_gem_object_move_to_inactive(obj);
1825         }
1826 }
1827
1828 static void i915_gem_reset_fences(struct drm_device *dev)
1829 {
1830         struct drm_i915_private *dev_priv = dev->dev_private;
1831         int i;
1832
1833         for (i = 0; i < 16; i++) {
1834                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1835                 struct drm_i915_gem_object *obj = reg->obj;
1836
1837                 if (!obj)
1838                         continue;
1839
1840                 if (obj->tiling_mode)
1841                         i915_gem_release_mmap(obj);
1842
1843                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1844                 reg->obj->fenced_gpu_access = false;
1845                 reg->obj->last_fenced_seqno = 0;
1846                 reg->obj->last_fenced_ring = NULL;
1847                 i915_gem_clear_fence_reg(dev, reg);
1848         }
1849 }
1850
1851 void i915_gem_reset(struct drm_device *dev)
1852 {
1853         struct drm_i915_private *dev_priv = dev->dev_private;
1854         struct drm_i915_gem_object *obj;
1855         int i;
1856
1857         for (i = 0; i < I915_NUM_RINGS; i++)
1858                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1859
1860         /* Remove anything from the flushing lists. The GPU cache is likely
1861          * to be lost on reset along with the data, so simply move the
1862          * lost bo to the inactive list.
1863          */
1864         while (!list_empty(&dev_priv->mm.flushing_list)) {
1865                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1866                                       struct drm_i915_gem_object,
1867                                       mm_list);
1868
1869                 obj->base.write_domain = 0;
1870                 list_del_init(&obj->gpu_write_list);
1871                 i915_gem_object_move_to_inactive(obj);
1872         }
1873
1874         /* Move everything out of the GPU domains to ensure we do any
1875          * necessary invalidation upon reuse.
1876          */
1877         list_for_each_entry(obj,
1878                             &dev_priv->mm.inactive_list,
1879                             mm_list)
1880         {
1881                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1882         }
1883
1884         /* The fence registers are invalidated so clear them out */
1885         i915_gem_reset_fences(dev);
1886 }
1887
1888 /**
1889  * This function clears the request list as sequence numbers are passed.
1890  */
1891 static void
1892 i915_gem_retire_requests_ring(struct drm_device *dev,
1893                               struct intel_ring_buffer *ring)
1894 {
1895         drm_i915_private_t *dev_priv = dev->dev_private;
1896         uint32_t seqno;
1897         int i;
1898
1899         if (!ring->status_page.page_addr ||
1900             list_empty(&ring->request_list))
1901                 return;
1902
1903         WARN_ON(i915_verify_lists(dev));
1904
1905         seqno = ring->get_seqno(ring);
1906
1907         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1908                 if (seqno >= ring->sync_seqno[i])
1909                         ring->sync_seqno[i] = 0;
1910
1911         while (!list_empty(&ring->request_list)) {
1912                 struct drm_i915_gem_request *request;
1913
1914                 request = list_first_entry(&ring->request_list,
1915                                            struct drm_i915_gem_request,
1916                                            list);
1917
1918                 if (!i915_seqno_passed(seqno, request->seqno))
1919                         break;
1920
1921                 trace_i915_gem_request_retire(dev, request->seqno);
1922
1923                 list_del(&request->list);
1924                 i915_gem_request_remove_from_client(request);
1925                 kfree(request);
1926         }
1927
1928         /* Move any buffers on the active list that are no longer referenced
1929          * by the ringbuffer to the flushing/inactive lists as appropriate.
1930          */
1931         while (!list_empty(&ring->active_list)) {
1932                 struct drm_i915_gem_object *obj;
1933
1934                 obj= list_first_entry(&ring->active_list,
1935                                       struct drm_i915_gem_object,
1936                                       ring_list);
1937
1938                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1939                         break;
1940
1941                 if (obj->base.write_domain != 0)
1942                         i915_gem_object_move_to_flushing(obj);
1943                 else
1944                         i915_gem_object_move_to_inactive(obj);
1945         }
1946
1947         if (unlikely (dev_priv->trace_irq_seqno &&
1948                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1949                 ring->irq_put(ring);
1950                 dev_priv->trace_irq_seqno = 0;
1951         }
1952
1953         WARN_ON(i915_verify_lists(dev));
1954 }
1955
1956 void
1957 i915_gem_retire_requests(struct drm_device *dev)
1958 {
1959         drm_i915_private_t *dev_priv = dev->dev_private;
1960         int i;
1961
1962         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1963             struct drm_i915_gem_object *obj, *next;
1964
1965             /* We must be careful that during unbind() we do not
1966              * accidentally infinitely recurse into retire requests.
1967              * Currently:
1968              *   retire -> free -> unbind -> wait -> retire_ring
1969              */
1970             list_for_each_entry_safe(obj, next,
1971                                      &dev_priv->mm.deferred_free_list,
1972                                      mm_list)
1973                     i915_gem_free_object_tail(obj);
1974         }
1975
1976         for (i = 0; i < I915_NUM_RINGS; i++)
1977                 i915_gem_retire_requests_ring(dev, &dev_priv->ring[i]);
1978 }
1979
1980 static void
1981 i915_gem_retire_work_handler(struct work_struct *work)
1982 {
1983         drm_i915_private_t *dev_priv;
1984         struct drm_device *dev;
1985         bool idle;
1986         int i;
1987
1988         dev_priv = container_of(work, drm_i915_private_t,
1989                                 mm.retire_work.work);
1990         dev = dev_priv->dev;
1991
1992         /* Come back later if the device is busy... */
1993         if (!mutex_trylock(&dev->struct_mutex)) {
1994                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1995                 return;
1996         }
1997
1998         i915_gem_retire_requests(dev);
1999
2000         /* Send a periodic flush down the ring so we don't hold onto GEM
2001          * objects indefinitely.
2002          */
2003         idle = true;
2004         for (i = 0; i < I915_NUM_RINGS; i++) {
2005                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2006
2007                 if (!list_empty(&ring->gpu_write_list)) {
2008                         struct drm_i915_gem_request *request;
2009                         int ret;
2010
2011                         ret = i915_gem_flush_ring(dev, ring, 0,
2012                                                   I915_GEM_GPU_DOMAINS);
2013                         request = kzalloc(sizeof(*request), GFP_KERNEL);
2014                         if (ret || request == NULL ||
2015                             i915_add_request(dev, NULL, request, ring))
2016                             kfree(request);
2017                 }
2018
2019                 idle &= list_empty(&ring->request_list);
2020         }
2021
2022         if (!dev_priv->mm.suspended && !idle)
2023                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2024
2025         mutex_unlock(&dev->struct_mutex);
2026 }
2027
2028 int
2029 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
2030                      bool interruptible, struct intel_ring_buffer *ring)
2031 {
2032         drm_i915_private_t *dev_priv = dev->dev_private;
2033         u32 ier;
2034         int ret = 0;
2035
2036         BUG_ON(seqno == 0);
2037
2038         if (atomic_read(&dev_priv->mm.wedged))
2039                 return -EAGAIN;
2040
2041         if (seqno == ring->outstanding_lazy_request) {
2042                 struct drm_i915_gem_request *request;
2043
2044                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2045                 if (request == NULL)
2046                         return -ENOMEM;
2047
2048                 ret = i915_add_request(dev, NULL, request, ring);
2049                 if (ret) {
2050                         kfree(request);
2051                         return ret;
2052                 }
2053
2054                 seqno = request->seqno;
2055         }
2056
2057         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2058                 if (HAS_PCH_SPLIT(dev))
2059                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2060                 else
2061                         ier = I915_READ(IER);
2062                 if (!ier) {
2063                         DRM_ERROR("something (likely vbetool) disabled "
2064                                   "interrupts, re-enabling\n");
2065                         i915_driver_irq_preinstall(dev);
2066                         i915_driver_irq_postinstall(dev);
2067                 }
2068
2069                 trace_i915_gem_request_wait_begin(dev, seqno);
2070
2071                 ring->waiting_seqno = seqno;
2072                 if (ring->irq_get(ring)) {
2073                         if (interruptible)
2074                                 ret = wait_event_interruptible(ring->irq_queue,
2075                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2076                                                                || atomic_read(&dev_priv->mm.wedged));
2077                         else
2078                                 wait_event(ring->irq_queue,
2079                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2080                                            || atomic_read(&dev_priv->mm.wedged));
2081
2082                         ring->irq_put(ring);
2083                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2084                                                       seqno) ||
2085                                     atomic_read(&dev_priv->mm.wedged), 3000))
2086                         ret = -EBUSY;
2087                 ring->waiting_seqno = 0;
2088
2089                 trace_i915_gem_request_wait_end(dev, seqno);
2090         }
2091         if (atomic_read(&dev_priv->mm.wedged))
2092                 ret = -EAGAIN;
2093
2094         if (ret && ret != -ERESTARTSYS)
2095                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2096                           __func__, ret, seqno, ring->get_seqno(ring),
2097                           dev_priv->next_seqno);
2098
2099         /* Directly dispatch request retiring.  While we have the work queue
2100          * to handle this, the waiter on a request often wants an associated
2101          * buffer to have made it to the inactive list, and we would need
2102          * a separate wait queue to handle that.
2103          */
2104         if (ret == 0)
2105                 i915_gem_retire_requests_ring(dev, ring);
2106
2107         return ret;
2108 }
2109
2110 /**
2111  * Waits for a sequence number to be signaled, and cleans up the
2112  * request and object lists appropriately for that event.
2113  */
2114 static int
2115 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2116                   struct intel_ring_buffer *ring)
2117 {
2118         return i915_do_wait_request(dev, seqno, 1, ring);
2119 }
2120
2121 /**
2122  * Ensures that all rendering to the object has completed and the object is
2123  * safe to unbind from the GTT or access from the CPU.
2124  */
2125 int
2126 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2127                                bool interruptible)
2128 {
2129         struct drm_device *dev = obj->base.dev;
2130         int ret;
2131
2132         /* This function only exists to support waiting for existing rendering,
2133          * not for emitting required flushes.
2134          */
2135         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2136
2137         /* If there is rendering queued on the buffer being evicted, wait for
2138          * it.
2139          */
2140         if (obj->active) {
2141                 ret = i915_do_wait_request(dev,
2142                                            obj->last_rendering_seqno,
2143                                            interruptible,
2144                                            obj->ring);
2145                 if (ret)
2146                         return ret;
2147         }
2148
2149         return 0;
2150 }
2151
2152 /**
2153  * Unbinds an object from the GTT aperture.
2154  */
2155 int
2156 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2157 {
2158         int ret = 0;
2159
2160         if (obj->gtt_space == NULL)
2161                 return 0;
2162
2163         if (obj->pin_count != 0) {
2164                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2165                 return -EINVAL;
2166         }
2167
2168         /* blow away mappings if mapped through GTT */
2169         i915_gem_release_mmap(obj);
2170
2171         /* Move the object to the CPU domain to ensure that
2172          * any possible CPU writes while it's not in the GTT
2173          * are flushed when we go to remap it. This will
2174          * also ensure that all pending GPU writes are finished
2175          * before we unbind.
2176          */
2177         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2178         if (ret == -ERESTARTSYS)
2179                 return ret;
2180         /* Continue on if we fail due to EIO, the GPU is hung so we
2181          * should be safe and we need to cleanup or else we might
2182          * cause memory corruption through use-after-free.
2183          */
2184         if (ret) {
2185                 i915_gem_clflush_object(obj);
2186                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2187         }
2188
2189         /* release the fence reg _after_ flushing */
2190         ret = i915_gem_object_put_fence(obj);
2191         if (ret == -ERESTARTSYS)
2192                 return ret;
2193
2194         i915_gem_gtt_unbind_object(obj);
2195         i915_gem_object_put_pages_gtt(obj);
2196
2197         list_del_init(&obj->gtt_list);
2198         list_del_init(&obj->mm_list);
2199         /* Avoid an unnecessary call to unbind on rebind. */
2200         obj->map_and_fenceable = true;
2201
2202         drm_mm_put_block(obj->gtt_space);
2203         obj->gtt_space = NULL;
2204         obj->gtt_offset = 0;
2205
2206         if (i915_gem_object_is_purgeable(obj))
2207                 i915_gem_object_truncate(obj);
2208
2209         trace_i915_gem_object_unbind(obj);
2210
2211         return ret;
2212 }
2213
2214 int
2215 i915_gem_flush_ring(struct drm_device *dev,
2216                     struct intel_ring_buffer *ring,
2217                     uint32_t invalidate_domains,
2218                     uint32_t flush_domains)
2219 {
2220         int ret;
2221
2222         ret = ring->flush(ring, invalidate_domains, flush_domains);
2223         if (ret)
2224                 return ret;
2225
2226         i915_gem_process_flushing_list(dev, flush_domains, ring);
2227         return 0;
2228 }
2229
2230 static int i915_ring_idle(struct drm_device *dev,
2231                           struct intel_ring_buffer *ring)
2232 {
2233         int ret;
2234
2235         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2236                 return 0;
2237
2238         if (!list_empty(&ring->gpu_write_list)) {
2239                 ret = i915_gem_flush_ring(dev, ring,
2240                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2241                 if (ret)
2242                         return ret;
2243         }
2244
2245         return i915_wait_request(dev,
2246                                  i915_gem_next_request_seqno(dev, ring),
2247                                  ring);
2248 }
2249
2250 int
2251 i915_gpu_idle(struct drm_device *dev)
2252 {
2253         drm_i915_private_t *dev_priv = dev->dev_private;
2254         bool lists_empty;
2255         int ret, i;
2256
2257         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2258                        list_empty(&dev_priv->mm.active_list));
2259         if (lists_empty)
2260                 return 0;
2261
2262         /* Flush everything onto the inactive list. */
2263         for (i = 0; i < I915_NUM_RINGS; i++) {
2264                 ret = i915_ring_idle(dev, &dev_priv->ring[i]);
2265                 if (ret)
2266                         return ret;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2273                                        struct intel_ring_buffer *pipelined)
2274 {
2275         struct drm_device *dev = obj->base.dev;
2276         drm_i915_private_t *dev_priv = dev->dev_private;
2277         u32 size = obj->gtt_space->size;
2278         int regnum = obj->fence_reg;
2279         uint64_t val;
2280
2281         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2282                          0xfffff000) << 32;
2283         val |= obj->gtt_offset & 0xfffff000;
2284         val |= (uint64_t)((obj->stride / 128) - 1) <<
2285                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2286
2287         if (obj->tiling_mode == I915_TILING_Y)
2288                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2289         val |= I965_FENCE_REG_VALID;
2290
2291         if (pipelined) {
2292                 int ret = intel_ring_begin(pipelined, 6);
2293                 if (ret)
2294                         return ret;
2295
2296                 intel_ring_emit(pipelined, MI_NOOP);
2297                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2298                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2299                 intel_ring_emit(pipelined, (u32)val);
2300                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2301                 intel_ring_emit(pipelined, (u32)(val >> 32));
2302                 intel_ring_advance(pipelined);
2303         } else
2304                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2305
2306         return 0;
2307 }
2308
2309 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2310                                 struct intel_ring_buffer *pipelined)
2311 {
2312         struct drm_device *dev = obj->base.dev;
2313         drm_i915_private_t *dev_priv = dev->dev_private;
2314         u32 size = obj->gtt_space->size;
2315         int regnum = obj->fence_reg;
2316         uint64_t val;
2317
2318         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2319                     0xfffff000) << 32;
2320         val |= obj->gtt_offset & 0xfffff000;
2321         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2322         if (obj->tiling_mode == I915_TILING_Y)
2323                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2324         val |= I965_FENCE_REG_VALID;
2325
2326         if (pipelined) {
2327                 int ret = intel_ring_begin(pipelined, 6);
2328                 if (ret)
2329                         return ret;
2330
2331                 intel_ring_emit(pipelined, MI_NOOP);
2332                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2333                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2334                 intel_ring_emit(pipelined, (u32)val);
2335                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2336                 intel_ring_emit(pipelined, (u32)(val >> 32));
2337                 intel_ring_advance(pipelined);
2338         } else
2339                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2340
2341         return 0;
2342 }
2343
2344 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2345                                 struct intel_ring_buffer *pipelined)
2346 {
2347         struct drm_device *dev = obj->base.dev;
2348         drm_i915_private_t *dev_priv = dev->dev_private;
2349         u32 size = obj->gtt_space->size;
2350         u32 fence_reg, val, pitch_val;
2351         int tile_width;
2352
2353         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2354                  (size & -size) != size ||
2355                  (obj->gtt_offset & (size - 1)),
2356                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2357                  obj->gtt_offset, obj->map_and_fenceable, size))
2358                 return -EINVAL;
2359
2360         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2361                 tile_width = 128;
2362         else
2363                 tile_width = 512;
2364
2365         /* Note: pitch better be a power of two tile widths */
2366         pitch_val = obj->stride / tile_width;
2367         pitch_val = ffs(pitch_val) - 1;
2368
2369         val = obj->gtt_offset;
2370         if (obj->tiling_mode == I915_TILING_Y)
2371                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2372         val |= I915_FENCE_SIZE_BITS(size);
2373         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2374         val |= I830_FENCE_REG_VALID;
2375
2376         fence_reg = obj->fence_reg;
2377         if (fence_reg < 8)
2378                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2379         else
2380                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2381
2382         if (pipelined) {
2383                 int ret = intel_ring_begin(pipelined, 4);
2384                 if (ret)
2385                         return ret;
2386
2387                 intel_ring_emit(pipelined, MI_NOOP);
2388                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2389                 intel_ring_emit(pipelined, fence_reg);
2390                 intel_ring_emit(pipelined, val);
2391                 intel_ring_advance(pipelined);
2392         } else
2393                 I915_WRITE(fence_reg, val);
2394
2395         return 0;
2396 }
2397
2398 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2399                                 struct intel_ring_buffer *pipelined)
2400 {
2401         struct drm_device *dev = obj->base.dev;
2402         drm_i915_private_t *dev_priv = dev->dev_private;
2403         u32 size = obj->gtt_space->size;
2404         int regnum = obj->fence_reg;
2405         uint32_t val;
2406         uint32_t pitch_val;
2407
2408         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2409                  (size & -size) != size ||
2410                  (obj->gtt_offset & (size - 1)),
2411                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2412                  obj->gtt_offset, size))
2413                 return -EINVAL;
2414
2415         pitch_val = obj->stride / 128;
2416         pitch_val = ffs(pitch_val) - 1;
2417
2418         val = obj->gtt_offset;
2419         if (obj->tiling_mode == I915_TILING_Y)
2420                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2421         val |= I830_FENCE_SIZE_BITS(size);
2422         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2423         val |= I830_FENCE_REG_VALID;
2424
2425         if (pipelined) {
2426                 int ret = intel_ring_begin(pipelined, 4);
2427                 if (ret)
2428                         return ret;
2429
2430                 intel_ring_emit(pipelined, MI_NOOP);
2431                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2432                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2433                 intel_ring_emit(pipelined, val);
2434                 intel_ring_advance(pipelined);
2435         } else
2436                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2437
2438         return 0;
2439 }
2440
2441 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2442 {
2443         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2444 }
2445
2446 static int
2447 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2448                             struct intel_ring_buffer *pipelined,
2449                             bool interruptible)
2450 {
2451         int ret;
2452
2453         if (obj->fenced_gpu_access) {
2454                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2455                         ret = i915_gem_flush_ring(obj->base.dev,
2456                                                   obj->last_fenced_ring,
2457                                                   0, obj->base.write_domain);
2458                         if (ret)
2459                                 return ret;
2460                 }
2461
2462                 obj->fenced_gpu_access = false;
2463         }
2464
2465         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2466                 if (!ring_passed_seqno(obj->last_fenced_ring,
2467                                        obj->last_fenced_seqno)) {
2468                         ret = i915_do_wait_request(obj->base.dev,
2469                                                    obj->last_fenced_seqno,
2470                                                    interruptible,
2471                                                    obj->last_fenced_ring);
2472                         if (ret)
2473                                 return ret;
2474                 }
2475
2476                 obj->last_fenced_seqno = 0;
2477                 obj->last_fenced_ring = NULL;
2478         }
2479
2480         /* Ensure that all CPU reads are completed before installing a fence
2481          * and all writes before removing the fence.
2482          */
2483         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2484                 mb();
2485
2486         return 0;
2487 }
2488
2489 int
2490 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2491 {
2492         int ret;
2493
2494         if (obj->tiling_mode)
2495                 i915_gem_release_mmap(obj);
2496
2497         ret = i915_gem_object_flush_fence(obj, NULL, true);
2498         if (ret)
2499                 return ret;
2500
2501         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2502                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2503                 i915_gem_clear_fence_reg(obj->base.dev,
2504                                          &dev_priv->fence_regs[obj->fence_reg]);
2505
2506                 obj->fence_reg = I915_FENCE_REG_NONE;
2507         }
2508
2509         return 0;
2510 }
2511
2512 static struct drm_i915_fence_reg *
2513 i915_find_fence_reg(struct drm_device *dev,
2514                     struct intel_ring_buffer *pipelined)
2515 {
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517         struct drm_i915_fence_reg *reg, *first, *avail;
2518         int i;
2519
2520         /* First try to find a free reg */
2521         avail = NULL;
2522         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2523                 reg = &dev_priv->fence_regs[i];
2524                 if (!reg->obj)
2525                         return reg;
2526
2527                 if (!reg->obj->pin_count)
2528                         avail = reg;
2529         }
2530
2531         if (avail == NULL)
2532                 return NULL;
2533
2534         /* None available, try to steal one or wait for a user to finish */
2535         avail = first = NULL;
2536         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2537                 if (reg->obj->pin_count)
2538                         continue;
2539
2540                 if (first == NULL)
2541                         first = reg;
2542
2543                 if (!pipelined ||
2544                     !reg->obj->last_fenced_ring ||
2545                     reg->obj->last_fenced_ring == pipelined) {
2546                         avail = reg;
2547                         break;
2548                 }
2549         }
2550
2551         if (avail == NULL)
2552                 avail = first;
2553
2554         return avail;
2555 }
2556
2557 /**
2558  * i915_gem_object_get_fence - set up a fence reg for an object
2559  * @obj: object to map through a fence reg
2560  * @pipelined: ring on which to queue the change, or NULL for CPU access
2561  * @interruptible: must we wait uninterruptibly for the register to retire?
2562  *
2563  * When mapping objects through the GTT, userspace wants to be able to write
2564  * to them without having to worry about swizzling if the object is tiled.
2565  *
2566  * This function walks the fence regs looking for a free one for @obj,
2567  * stealing one if it can't find any.
2568  *
2569  * It then sets up the reg based on the object's properties: address, pitch
2570  * and tiling format.
2571  */
2572 int
2573 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2574                           struct intel_ring_buffer *pipelined,
2575                           bool interruptible)
2576 {
2577         struct drm_device *dev = obj->base.dev;
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579         struct drm_i915_fence_reg *reg;
2580         int ret;
2581
2582         /* XXX disable pipelining. There are bugs. Shocking. */
2583         pipelined = NULL;
2584
2585         /* Just update our place in the LRU if our fence is getting reused. */
2586         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2587                 reg = &dev_priv->fence_regs[obj->fence_reg];
2588                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2589
2590                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2591                         pipelined = NULL;
2592
2593                 if (!pipelined) {
2594                         if (reg->setup_seqno) {
2595                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2596                                                        reg->setup_seqno)) {
2597                                         ret = i915_do_wait_request(obj->base.dev,
2598                                                                    reg->setup_seqno,
2599                                                                    interruptible,
2600                                                                    obj->last_fenced_ring);
2601                                         if (ret)
2602                                                 return ret;
2603                                 }
2604
2605                                 reg->setup_seqno = 0;
2606                         }
2607                 } else if (obj->last_fenced_ring &&
2608                            obj->last_fenced_ring != pipelined) {
2609                         ret = i915_gem_object_flush_fence(obj,
2610                                                           pipelined,
2611                                                           interruptible);
2612                         if (ret)
2613                                 return ret;
2614                 } else if (obj->tiling_changed) {
2615                         if (obj->fenced_gpu_access) {
2616                                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2617                                         ret = i915_gem_flush_ring(obj->base.dev, obj->ring,
2618                                                                   0, obj->base.write_domain);
2619                                         if (ret)
2620                                                 return ret;
2621                                 }
2622
2623                                 obj->fenced_gpu_access = false;
2624                         }
2625                 }
2626
2627                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2628                         pipelined = NULL;
2629                 BUG_ON(!pipelined && reg->setup_seqno);
2630
2631                 if (obj->tiling_changed) {
2632                         if (pipelined) {
2633                                 reg->setup_seqno =
2634                                         i915_gem_next_request_seqno(dev, pipelined);
2635                                 obj->last_fenced_seqno = reg->setup_seqno;
2636                                 obj->last_fenced_ring = pipelined;
2637                         }
2638                         goto update;
2639                 }
2640
2641                 return 0;
2642         }
2643
2644         reg = i915_find_fence_reg(dev, pipelined);
2645         if (reg == NULL)
2646                 return -ENOSPC;
2647
2648         ret = i915_gem_object_flush_fence(obj, pipelined, interruptible);
2649         if (ret)
2650                 return ret;
2651
2652         if (reg->obj) {
2653                 struct drm_i915_gem_object *old = reg->obj;
2654
2655                 drm_gem_object_reference(&old->base);
2656
2657                 if (old->tiling_mode)
2658                         i915_gem_release_mmap(old);
2659
2660                 ret = i915_gem_object_flush_fence(old,
2661                                                   pipelined,
2662                                                   interruptible);
2663                 if (ret) {
2664                         drm_gem_object_unreference(&old->base);
2665                         return ret;
2666                 }
2667
2668                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2669                         pipelined = NULL;
2670
2671                 old->fence_reg = I915_FENCE_REG_NONE;
2672                 old->last_fenced_ring = pipelined;
2673                 old->last_fenced_seqno =
2674                         pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2675
2676                 drm_gem_object_unreference(&old->base);
2677         } else if (obj->last_fenced_seqno == 0)
2678                 pipelined = NULL;
2679
2680         reg->obj = obj;
2681         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2682         obj->fence_reg = reg - dev_priv->fence_regs;
2683         obj->last_fenced_ring = pipelined;
2684
2685         reg->setup_seqno =
2686                 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2687         obj->last_fenced_seqno = reg->setup_seqno;
2688
2689 update:
2690         obj->tiling_changed = false;
2691         switch (INTEL_INFO(dev)->gen) {
2692         case 6:
2693                 ret = sandybridge_write_fence_reg(obj, pipelined);
2694                 break;
2695         case 5:
2696         case 4:
2697                 ret = i965_write_fence_reg(obj, pipelined);
2698                 break;
2699         case 3:
2700                 ret = i915_write_fence_reg(obj, pipelined);
2701                 break;
2702         case 2:
2703                 ret = i830_write_fence_reg(obj, pipelined);
2704                 break;
2705         }
2706
2707         return ret;
2708 }
2709
2710 /**
2711  * i915_gem_clear_fence_reg - clear out fence register info
2712  * @obj: object to clear
2713  *
2714  * Zeroes out the fence register itself and clears out the associated
2715  * data structures in dev_priv and obj.
2716  */
2717 static void
2718 i915_gem_clear_fence_reg(struct drm_device *dev,
2719                          struct drm_i915_fence_reg *reg)
2720 {
2721         drm_i915_private_t *dev_priv = dev->dev_private;
2722         uint32_t fence_reg = reg - dev_priv->fence_regs;
2723
2724         switch (INTEL_INFO(dev)->gen) {
2725         case 6:
2726                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2727                 break;
2728         case 5:
2729         case 4:
2730                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2731                 break;
2732         case 3:
2733                 if (fence_reg >= 8)
2734                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2735                 else
2736         case 2:
2737                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2738
2739                 I915_WRITE(fence_reg, 0);
2740                 break;
2741         }
2742
2743         list_del_init(&reg->lru_list);
2744         reg->obj = NULL;
2745         reg->setup_seqno = 0;
2746 }
2747
2748 /**
2749  * Finds free space in the GTT aperture and binds the object there.
2750  */
2751 static int
2752 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2753                             unsigned alignment,
2754                             bool map_and_fenceable)
2755 {
2756         struct drm_device *dev = obj->base.dev;
2757         drm_i915_private_t *dev_priv = dev->dev_private;
2758         struct drm_mm_node *free_space;
2759         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2760         u32 size, fence_size, fence_alignment, unfenced_alignment;
2761         bool mappable, fenceable;
2762         int ret;
2763
2764         if (obj->madv != I915_MADV_WILLNEED) {
2765                 DRM_ERROR("Attempting to bind a purgeable object\n");
2766                 return -EINVAL;
2767         }
2768
2769         fence_size = i915_gem_get_gtt_size(obj);
2770         fence_alignment = i915_gem_get_gtt_alignment(obj);
2771         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2772
2773         if (alignment == 0)
2774                 alignment = map_and_fenceable ? fence_alignment :
2775                                                 unfenced_alignment;
2776         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2777                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2778                 return -EINVAL;
2779         }
2780
2781         size = map_and_fenceable ? fence_size : obj->base.size;
2782
2783         /* If the object is bigger than the entire aperture, reject it early
2784          * before evicting everything in a vain attempt to find space.
2785          */
2786         if (obj->base.size >
2787             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2788                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2789                 return -E2BIG;
2790         }
2791
2792  search_free:
2793         if (map_and_fenceable)
2794                 free_space =
2795                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2796                                                     size, alignment, 0,
2797                                                     dev_priv->mm.gtt_mappable_end,
2798                                                     0);
2799         else
2800                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2801                                                 size, alignment, 0);
2802
2803         if (free_space != NULL) {
2804                 if (map_and_fenceable)
2805                         obj->gtt_space =
2806                                 drm_mm_get_block_range_generic(free_space,
2807                                                                size, alignment, 0,
2808                                                                dev_priv->mm.gtt_mappable_end,
2809                                                                0);
2810                 else
2811                         obj->gtt_space =
2812                                 drm_mm_get_block(free_space, size, alignment);
2813         }
2814         if (obj->gtt_space == NULL) {
2815                 /* If the gtt is empty and we're still having trouble
2816                  * fitting our object in, we're out of memory.
2817                  */
2818                 ret = i915_gem_evict_something(dev, size, alignment,
2819                                                map_and_fenceable);
2820                 if (ret)
2821                         return ret;
2822
2823                 goto search_free;
2824         }
2825
2826         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2827         if (ret) {
2828                 drm_mm_put_block(obj->gtt_space);
2829                 obj->gtt_space = NULL;
2830
2831                 if (ret == -ENOMEM) {
2832                         /* first try to reclaim some memory by clearing the GTT */
2833                         ret = i915_gem_evict_everything(dev, false);
2834                         if (ret) {
2835                                 /* now try to shrink everyone else */
2836                                 if (gfpmask) {
2837                                         gfpmask = 0;
2838                                         goto search_free;
2839                                 }
2840
2841                                 return -ENOMEM;
2842                         }
2843
2844                         goto search_free;
2845                 }
2846
2847                 return ret;
2848         }
2849
2850         ret = i915_gem_gtt_bind_object(obj);
2851         if (ret) {
2852                 i915_gem_object_put_pages_gtt(obj);
2853                 drm_mm_put_block(obj->gtt_space);
2854                 obj->gtt_space = NULL;
2855
2856                 if (i915_gem_evict_everything(dev, false))
2857                         return ret;
2858
2859                 goto search_free;
2860         }
2861
2862         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2863         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2864
2865         /* Assert that the object is not currently in any GPU domain. As it
2866          * wasn't in the GTT, there shouldn't be any way it could have been in
2867          * a GPU cache
2868          */
2869         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2870         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2871
2872         obj->gtt_offset = obj->gtt_space->start;
2873
2874         fenceable =
2875                 obj->gtt_space->size == fence_size &&
2876                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2877
2878         mappable =
2879                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2880
2881         obj->map_and_fenceable = mappable && fenceable;
2882
2883         trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable);
2884         return 0;
2885 }
2886
2887 void
2888 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2889 {
2890         /* If we don't have a page list set up, then we're not pinned
2891          * to GPU, and we can ignore the cache flush because it'll happen
2892          * again at bind time.
2893          */
2894         if (obj->pages == NULL)
2895                 return;
2896
2897         trace_i915_gem_object_clflush(obj);
2898
2899         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2900 }
2901
2902 /** Flushes any GPU write domain for the object if it's dirty. */
2903 static int
2904 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2905 {
2906         struct drm_device *dev = obj->base.dev;
2907
2908         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2909                 return 0;
2910
2911         /* Queue the GPU write cache flushing we need. */
2912         return i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
2913 }
2914
2915 /** Flushes the GTT write domain for the object if it's dirty. */
2916 static void
2917 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2918 {
2919         uint32_t old_write_domain;
2920
2921         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2922                 return;
2923
2924         /* No actual flushing is required for the GTT write domain.  Writes
2925          * to it immediately go to main memory as far as we know, so there's
2926          * no chipset flush.  It also doesn't land in render cache.
2927          *
2928          * However, we do have to enforce the order so that all writes through
2929          * the GTT land before any writes to the device, such as updates to
2930          * the GATT itself.
2931          */
2932         wmb();
2933
2934         i915_gem_release_mmap(obj);
2935
2936         old_write_domain = obj->base.write_domain;
2937         obj->base.write_domain = 0;
2938
2939         trace_i915_gem_object_change_domain(obj,
2940                                             obj->base.read_domains,
2941                                             old_write_domain);
2942 }
2943
2944 /** Flushes the CPU write domain for the object if it's dirty. */
2945 static void
2946 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2947 {
2948         uint32_t old_write_domain;
2949
2950         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2951                 return;
2952
2953         i915_gem_clflush_object(obj);
2954         intel_gtt_chipset_flush();
2955         old_write_domain = obj->base.write_domain;
2956         obj->base.write_domain = 0;
2957
2958         trace_i915_gem_object_change_domain(obj,
2959                                             obj->base.read_domains,
2960                                             old_write_domain);
2961 }
2962
2963 /**
2964  * Moves a single object to the GTT read, and possibly write domain.
2965  *
2966  * This function returns when the move is complete, including waiting on
2967  * flushes to occur.
2968  */
2969 int
2970 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2971 {
2972         uint32_t old_write_domain, old_read_domains;
2973         int ret;
2974
2975         /* Not valid to be called on unbound objects. */
2976         if (obj->gtt_space == NULL)
2977                 return -EINVAL;
2978
2979         ret = i915_gem_object_flush_gpu_write_domain(obj);
2980         if (ret)
2981                 return ret;
2982
2983         if (obj->pending_gpu_write || write) {
2984                 ret = i915_gem_object_wait_rendering(obj, true);
2985                 if (ret)
2986                         return ret;
2987         }
2988
2989         i915_gem_object_flush_cpu_write_domain(obj);
2990
2991         old_write_domain = obj->base.write_domain;
2992         old_read_domains = obj->base.read_domains;
2993
2994         /* It should now be out of any other write domains, and we can update
2995          * the domain values for our changes.
2996          */
2997         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2998         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2999         if (write) {
3000                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3001                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3002                 obj->dirty = 1;
3003         }
3004
3005         trace_i915_gem_object_change_domain(obj,
3006                                             old_read_domains,
3007                                             old_write_domain);
3008
3009         return 0;
3010 }
3011
3012 /*
3013  * Prepare buffer for display plane. Use uninterruptible for possible flush
3014  * wait, as in modesetting process we're not supposed to be interrupted.
3015  */
3016 int
3017 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
3018                                      struct intel_ring_buffer *pipelined)
3019 {
3020         uint32_t old_read_domains;
3021         int ret;
3022
3023         /* Not valid to be called on unbound objects. */
3024         if (obj->gtt_space == NULL)
3025                 return -EINVAL;
3026
3027         ret = i915_gem_object_flush_gpu_write_domain(obj);
3028         if (ret)
3029                 return ret;
3030
3031
3032         /* Currently, we are always called from an non-interruptible context. */
3033         if (pipelined != obj->ring) {
3034                 ret = i915_gem_object_wait_rendering(obj, false);
3035                 if (ret)
3036                         return ret;
3037         }
3038
3039         i915_gem_object_flush_cpu_write_domain(obj);
3040
3041         old_read_domains = obj->base.read_domains;
3042         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3043
3044         trace_i915_gem_object_change_domain(obj,
3045                                             old_read_domains,
3046                                             obj->base.write_domain);
3047
3048         return 0;
3049 }
3050
3051 int
3052 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
3053                           bool interruptible)
3054 {
3055         int ret;
3056
3057         if (!obj->active)
3058                 return 0;
3059
3060         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3061                 ret = i915_gem_flush_ring(obj->base.dev, obj->ring,
3062                                           0, obj->base.write_domain);
3063                 if (ret)
3064                         return ret;
3065         }
3066
3067         return i915_gem_object_wait_rendering(obj, interruptible);
3068 }
3069
3070 /**
3071  * Moves a single object to the CPU read, and possibly write domain.
3072  *
3073  * This function returns when the move is complete, including waiting on
3074  * flushes to occur.
3075  */
3076 static int
3077 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3078 {
3079         uint32_t old_write_domain, old_read_domains;
3080         int ret;
3081
3082         ret = i915_gem_object_flush_gpu_write_domain(obj);
3083         if (ret)
3084                 return ret;
3085
3086         ret = i915_gem_object_wait_rendering(obj, true);
3087         if (ret)
3088                 return ret;
3089
3090         i915_gem_object_flush_gtt_write_domain(obj);
3091
3092         /* If we have a partially-valid cache of the object in the CPU,
3093          * finish invalidating it and free the per-page flags.
3094          */
3095         i915_gem_object_set_to_full_cpu_read_domain(obj);
3096
3097         old_write_domain = obj->base.write_domain;
3098         old_read_domains = obj->base.read_domains;
3099
3100         /* Flush the CPU cache if it's still invalid. */
3101         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3102                 i915_gem_clflush_object(obj);
3103
3104                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3105         }
3106
3107         /* It should now be out of any other write domains, and we can update
3108          * the domain values for our changes.
3109          */
3110         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3111
3112         /* If we're writing through the CPU, then the GPU read domains will
3113          * need to be invalidated at next use.
3114          */
3115         if (write) {
3116                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3117                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3118         }
3119
3120         trace_i915_gem_object_change_domain(obj,
3121                                             old_read_domains,
3122                                             old_write_domain);
3123
3124         return 0;
3125 }
3126
3127 /**
3128  * Moves the object from a partially CPU read to a full one.
3129  *
3130  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3131  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3132  */
3133 static void
3134 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3135 {
3136         if (!obj->page_cpu_valid)
3137                 return;
3138
3139         /* If we're partially in the CPU read domain, finish moving it in.
3140          */
3141         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3142                 int i;
3143
3144                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3145                         if (obj->page_cpu_valid[i])
3146                                 continue;
3147                         drm_clflush_pages(obj->pages + i, 1);
3148                 }
3149         }
3150
3151         /* Free the page_cpu_valid mappings which are now stale, whether
3152          * or not we've got I915_GEM_DOMAIN_CPU.
3153          */
3154         kfree(obj->page_cpu_valid);
3155         obj->page_cpu_valid = NULL;
3156 }
3157
3158 /**
3159  * Set the CPU read domain on a range of the object.
3160  *
3161  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3162  * not entirely valid.  The page_cpu_valid member of the object flags which
3163  * pages have been flushed, and will be respected by
3164  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3165  * of the whole object.
3166  *
3167  * This function returns when the move is complete, including waiting on
3168  * flushes to occur.
3169  */
3170 static int
3171 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3172                                           uint64_t offset, uint64_t size)
3173 {
3174         uint32_t old_read_domains;
3175         int i, ret;
3176
3177         if (offset == 0 && size == obj->base.size)
3178                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3179
3180         ret = i915_gem_object_flush_gpu_write_domain(obj);
3181         if (ret)
3182                 return ret;
3183
3184         ret = i915_gem_object_wait_rendering(obj, true);
3185         if (ret)
3186                 return ret;
3187
3188         i915_gem_object_flush_gtt_write_domain(obj);
3189
3190         /* If we're already fully in the CPU read domain, we're done. */
3191         if (obj->page_cpu_valid == NULL &&
3192             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3193                 return 0;
3194
3195         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3196          * newly adding I915_GEM_DOMAIN_CPU
3197          */
3198         if (obj->page_cpu_valid == NULL) {
3199                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3200                                               GFP_KERNEL);
3201                 if (obj->page_cpu_valid == NULL)
3202                         return -ENOMEM;
3203         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3204                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3205
3206         /* Flush the cache on any pages that are still invalid from the CPU's
3207          * perspective.
3208          */
3209         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3210              i++) {
3211                 if (obj->page_cpu_valid[i])
3212                         continue;
3213
3214                 drm_clflush_pages(obj->pages + i, 1);
3215
3216                 obj->page_cpu_valid[i] = 1;
3217         }
3218
3219         /* It should now be out of any other write domains, and we can update
3220          * the domain values for our changes.
3221          */
3222         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3223
3224         old_read_domains = obj->base.read_domains;
3225         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3226
3227         trace_i915_gem_object_change_domain(obj,
3228                                             old_read_domains,
3229                                             obj->base.write_domain);
3230
3231         return 0;
3232 }
3233
3234 /* Throttle our rendering by waiting until the ring has completed our requests
3235  * emitted over 20 msec ago.
3236  *
3237  * Note that if we were to use the current jiffies each time around the loop,
3238  * we wouldn't escape the function with any frames outstanding if the time to
3239  * render a frame was over 20ms.
3240  *
3241  * This should get us reasonable parallelism between CPU and GPU but also
3242  * relatively low latency when blocking on a particular request to finish.
3243  */
3244 static int
3245 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3246 {
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         struct drm_i915_file_private *file_priv = file->driver_priv;
3249         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3250         struct drm_i915_gem_request *request;
3251         struct intel_ring_buffer *ring = NULL;
3252         u32 seqno = 0;
3253         int ret;
3254
3255         spin_lock(&file_priv->mm.lock);
3256         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3257                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3258                         break;
3259
3260                 ring = request->ring;
3261                 seqno = request->seqno;
3262         }
3263         spin_unlock(&file_priv->mm.lock);
3264
3265         if (seqno == 0)
3266                 return 0;
3267
3268         ret = 0;
3269         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3270                 /* And wait for the seqno passing without holding any locks and
3271                  * causing extra latency for others. This is safe as the irq
3272                  * generation is designed to be run atomically and so is
3273                  * lockless.
3274                  */
3275                 if (ring->irq_get(ring)) {
3276                         ret = wait_event_interruptible(ring->irq_queue,
3277                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3278                                                        || atomic_read(&dev_priv->mm.wedged));
3279                         ring->irq_put(ring);
3280
3281                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3282                                 ret = -EIO;
3283                 }
3284         }
3285
3286         if (ret == 0)
3287                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3288
3289         return ret;
3290 }
3291
3292 int
3293 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3294                     uint32_t alignment,
3295                     bool map_and_fenceable)
3296 {
3297         struct drm_device *dev = obj->base.dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         int ret;
3300
3301         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3302         WARN_ON(i915_verify_lists(dev));
3303
3304         if (obj->gtt_space != NULL) {
3305                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3306                     (map_and_fenceable && !obj->map_and_fenceable)) {
3307                         WARN(obj->pin_count,
3308                              "bo is already pinned with incorrect alignment:"
3309                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3310                              " obj->map_and_fenceable=%d\n",
3311                              obj->gtt_offset, alignment,
3312                              map_and_fenceable,
3313                              obj->map_and_fenceable);
3314                         ret = i915_gem_object_unbind(obj);
3315                         if (ret)
3316                                 return ret;
3317                 }
3318         }
3319
3320         if (obj->gtt_space == NULL) {
3321                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3322                                                   map_and_fenceable);
3323                 if (ret)
3324                         return ret;
3325         }
3326
3327         if (obj->pin_count++ == 0) {
3328                 if (!obj->active)
3329                         list_move_tail(&obj->mm_list,
3330                                        &dev_priv->mm.pinned_list);
3331         }
3332         obj->pin_mappable |= map_and_fenceable;
3333
3334         WARN_ON(i915_verify_lists(dev));
3335         return 0;
3336 }
3337
3338 void
3339 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3340 {
3341         struct drm_device *dev = obj->base.dev;
3342         drm_i915_private_t *dev_priv = dev->dev_private;
3343
3344         WARN_ON(i915_verify_lists(dev));
3345         BUG_ON(obj->pin_count == 0);
3346         BUG_ON(obj->gtt_space == NULL);
3347
3348         if (--obj->pin_count == 0) {
3349                 if (!obj->active)
3350                         list_move_tail(&obj->mm_list,
3351                                        &dev_priv->mm.inactive_list);
3352                 obj->pin_mappable = false;
3353         }
3354         WARN_ON(i915_verify_lists(dev));
3355 }
3356
3357 int
3358 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3359                    struct drm_file *file)
3360 {
3361         struct drm_i915_gem_pin *args = data;
3362         struct drm_i915_gem_object *obj;
3363         int ret;
3364
3365         ret = i915_mutex_lock_interruptible(dev);
3366         if (ret)
3367                 return ret;
3368
3369         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3370         if (obj == NULL) {
3371                 ret = -ENOENT;
3372                 goto unlock;
3373         }
3374
3375         if (obj->madv != I915_MADV_WILLNEED) {
3376                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3377                 ret = -EINVAL;
3378                 goto out;
3379         }
3380
3381         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3382                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3383                           args->handle);
3384                 ret = -EINVAL;
3385                 goto out;
3386         }
3387
3388         obj->user_pin_count++;
3389         obj->pin_filp = file;
3390         if (obj->user_pin_count == 1) {
3391                 ret = i915_gem_object_pin(obj, args->alignment, true);
3392                 if (ret)
3393                         goto out;
3394         }
3395
3396         /* XXX - flush the CPU caches for pinned objects
3397          * as the X server doesn't manage domains yet
3398          */
3399         i915_gem_object_flush_cpu_write_domain(obj);
3400         args->offset = obj->gtt_offset;
3401 out:
3402         drm_gem_object_unreference(&obj->base);
3403 unlock:
3404         mutex_unlock(&dev->struct_mutex);
3405         return ret;
3406 }
3407
3408 int
3409 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3410                      struct drm_file *file)
3411 {
3412         struct drm_i915_gem_pin *args = data;
3413         struct drm_i915_gem_object *obj;
3414         int ret;
3415
3416         ret = i915_mutex_lock_interruptible(dev);
3417         if (ret)
3418                 return ret;
3419
3420         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3421         if (obj == NULL) {
3422                 ret = -ENOENT;
3423                 goto unlock;
3424         }
3425
3426         if (obj->pin_filp != file) {
3427                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3428                           args->handle);
3429                 ret = -EINVAL;
3430                 goto out;
3431         }
3432         obj->user_pin_count--;
3433         if (obj->user_pin_count == 0) {
3434                 obj->pin_filp = NULL;
3435                 i915_gem_object_unpin(obj);
3436         }
3437
3438 out:
3439         drm_gem_object_unreference(&obj->base);
3440 unlock:
3441         mutex_unlock(&dev->struct_mutex);
3442         return ret;
3443 }
3444
3445 int
3446 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3447                     struct drm_file *file)
3448 {
3449         struct drm_i915_gem_busy *args = data;
3450         struct drm_i915_gem_object *obj;
3451         int ret;
3452
3453         ret = i915_mutex_lock_interruptible(dev);
3454         if (ret)
3455                 return ret;
3456
3457         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3458         if (obj == NULL) {
3459                 ret = -ENOENT;
3460                 goto unlock;
3461         }
3462
3463         /* Count all active objects as busy, even if they are currently not used
3464          * by the gpu. Users of this interface expect objects to eventually
3465          * become non-busy without any further actions, therefore emit any
3466          * necessary flushes here.
3467          */
3468         args->busy = obj->active;
3469         if (args->busy) {
3470                 /* Unconditionally flush objects, even when the gpu still uses this
3471                  * object. Userspace calling this function indicates that it wants to
3472                  * use this buffer rather sooner than later, so issuing the required
3473                  * flush earlier is beneficial.
3474                  */
3475                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3476                         ret = i915_gem_flush_ring(dev, obj->ring,
3477                                                   0, obj->base.write_domain);
3478                 } else if (obj->ring->outstanding_lazy_request ==
3479                            obj->last_rendering_seqno) {
3480                         struct drm_i915_gem_request *request;
3481
3482                         /* This ring is not being cleared by active usage,
3483                          * so emit a request to do so.
3484                          */
3485                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3486                         if (request)
3487                                 ret = i915_add_request(dev,
3488                                                        NULL, request,
3489                                                        obj->ring);
3490                         else
3491                                 ret = -ENOMEM;
3492                 }
3493
3494                 /* Update the active list for the hardware's current position.
3495                  * Otherwise this only updates on a delayed timer or when irqs
3496                  * are actually unmasked, and our working set ends up being
3497                  * larger than required.
3498                  */
3499                 i915_gem_retire_requests_ring(dev, obj->ring);
3500
3501                 args->busy = obj->active;
3502         }
3503
3504         drm_gem_object_unreference(&obj->base);
3505 unlock:
3506         mutex_unlock(&dev->struct_mutex);
3507         return ret;
3508 }
3509
3510 int
3511 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3512                         struct drm_file *file_priv)
3513 {
3514     return i915_gem_ring_throttle(dev, file_priv);
3515 }
3516
3517 int
3518 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3519                        struct drm_file *file_priv)
3520 {
3521         struct drm_i915_gem_madvise *args = data;
3522         struct drm_i915_gem_object *obj;
3523         int ret;
3524
3525         switch (args->madv) {
3526         case I915_MADV_DONTNEED:
3527         case I915_MADV_WILLNEED:
3528             break;
3529         default:
3530             return -EINVAL;
3531         }
3532
3533         ret = i915_mutex_lock_interruptible(dev);
3534         if (ret)
3535                 return ret;
3536
3537         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3538         if (obj == NULL) {
3539                 ret = -ENOENT;
3540                 goto unlock;
3541         }
3542
3543         if (obj->pin_count) {
3544                 ret = -EINVAL;
3545                 goto out;
3546         }
3547
3548         if (obj->madv != __I915_MADV_PURGED)
3549                 obj->madv = args->madv;
3550
3551         /* if the object is no longer bound, discard its backing storage */
3552         if (i915_gem_object_is_purgeable(obj) &&
3553             obj->gtt_space == NULL)
3554                 i915_gem_object_truncate(obj);
3555
3556         args->retained = obj->madv != __I915_MADV_PURGED;
3557
3558 out:
3559         drm_gem_object_unreference(&obj->base);
3560 unlock:
3561         mutex_unlock(&dev->struct_mutex);
3562         return ret;
3563 }
3564
3565 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3566                                                   size_t size)
3567 {
3568         struct drm_i915_private *dev_priv = dev->dev_private;
3569         struct drm_i915_gem_object *obj;
3570
3571         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3572         if (obj == NULL)
3573                 return NULL;
3574
3575         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3576                 kfree(obj);
3577                 return NULL;
3578         }
3579
3580         i915_gem_info_add_obj(dev_priv, size);
3581
3582         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3583         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3584
3585         obj->agp_type = AGP_USER_MEMORY;
3586         obj->base.driver_private = NULL;
3587         obj->fence_reg = I915_FENCE_REG_NONE;
3588         INIT_LIST_HEAD(&obj->mm_list);
3589         INIT_LIST_HEAD(&obj->gtt_list);
3590         INIT_LIST_HEAD(&obj->ring_list);
3591         INIT_LIST_HEAD(&obj->exec_list);
3592         INIT_LIST_HEAD(&obj->gpu_write_list);
3593         obj->madv = I915_MADV_WILLNEED;
3594         /* Avoid an unnecessary call to unbind on the first bind. */
3595         obj->map_and_fenceable = true;
3596
3597         return obj;
3598 }
3599
3600 int i915_gem_init_object(struct drm_gem_object *obj)
3601 {
3602         BUG();
3603
3604         return 0;
3605 }
3606
3607 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3608 {
3609         struct drm_device *dev = obj->base.dev;
3610         drm_i915_private_t *dev_priv = dev->dev_private;
3611         int ret;
3612
3613         ret = i915_gem_object_unbind(obj);
3614         if (ret == -ERESTARTSYS) {
3615                 list_move(&obj->mm_list,
3616                           &dev_priv->mm.deferred_free_list);
3617                 return;
3618         }
3619
3620         if (obj->base.map_list.map)
3621                 i915_gem_free_mmap_offset(obj);
3622
3623         drm_gem_object_release(&obj->base);
3624         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3625
3626         kfree(obj->page_cpu_valid);
3627         kfree(obj->bit_17);
3628         kfree(obj);
3629 }
3630
3631 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3632 {
3633         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3634         struct drm_device *dev = obj->base.dev;
3635
3636         trace_i915_gem_object_destroy(obj);
3637
3638         while (obj->pin_count > 0)
3639                 i915_gem_object_unpin(obj);
3640
3641         if (obj->phys_obj)
3642                 i915_gem_detach_phys_object(dev, obj);
3643
3644         i915_gem_free_object_tail(obj);
3645 }
3646
3647 int
3648 i915_gem_idle(struct drm_device *dev)
3649 {
3650         drm_i915_private_t *dev_priv = dev->dev_private;
3651         int ret;
3652
3653         mutex_lock(&dev->struct_mutex);
3654
3655         if (dev_priv->mm.suspended) {
3656                 mutex_unlock(&dev->struct_mutex);
3657                 return 0;
3658         }
3659
3660         ret = i915_gpu_idle(dev);
3661         if (ret) {
3662                 mutex_unlock(&dev->struct_mutex);
3663                 return ret;
3664         }
3665
3666         /* Under UMS, be paranoid and evict. */
3667         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3668                 ret = i915_gem_evict_inactive(dev, false);
3669                 if (ret) {
3670                         mutex_unlock(&dev->struct_mutex);
3671                         return ret;
3672                 }
3673         }
3674
3675         i915_gem_reset_fences(dev);
3676
3677         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3678          * We need to replace this with a semaphore, or something.
3679          * And not confound mm.suspended!
3680          */
3681         dev_priv->mm.suspended = 1;
3682         del_timer_sync(&dev_priv->hangcheck_timer);
3683
3684         i915_kernel_lost_context(dev);
3685         i915_gem_cleanup_ringbuffer(dev);
3686
3687         mutex_unlock(&dev->struct_mutex);
3688
3689         /* Cancel the retire work handler, which should be idle now. */
3690         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3691
3692         return 0;
3693 }
3694
3695 int
3696 i915_gem_init_ringbuffer(struct drm_device *dev)
3697 {
3698         drm_i915_private_t *dev_priv = dev->dev_private;
3699         int ret;
3700
3701         ret = intel_init_render_ring_buffer(dev);
3702         if (ret)
3703                 return ret;
3704
3705         if (HAS_BSD(dev)) {
3706                 ret = intel_init_bsd_ring_buffer(dev);
3707                 if (ret)
3708                         goto cleanup_render_ring;
3709         }
3710
3711         if (HAS_BLT(dev)) {
3712                 ret = intel_init_blt_ring_buffer(dev);
3713                 if (ret)
3714                         goto cleanup_bsd_ring;
3715         }
3716
3717         dev_priv->next_seqno = 1;
3718
3719         return 0;
3720
3721 cleanup_bsd_ring:
3722         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3723 cleanup_render_ring:
3724         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3725         return ret;
3726 }
3727
3728 void
3729 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3730 {
3731         drm_i915_private_t *dev_priv = dev->dev_private;
3732         int i;
3733
3734         for (i = 0; i < I915_NUM_RINGS; i++)
3735                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3736 }
3737
3738 int
3739 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3740                        struct drm_file *file_priv)
3741 {
3742         drm_i915_private_t *dev_priv = dev->dev_private;
3743         int ret, i;
3744
3745         if (drm_core_check_feature(dev, DRIVER_MODESET))
3746                 return 0;
3747
3748         if (atomic_read(&dev_priv->mm.wedged)) {
3749                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3750                 atomic_set(&dev_priv->mm.wedged, 0);
3751         }
3752
3753         mutex_lock(&dev->struct_mutex);
3754         dev_priv->mm.suspended = 0;
3755
3756         ret = i915_gem_init_ringbuffer(dev);
3757         if (ret != 0) {
3758                 mutex_unlock(&dev->struct_mutex);
3759                 return ret;
3760         }
3761
3762         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3763         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3764         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3765         for (i = 0; i < I915_NUM_RINGS; i++) {
3766                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3767                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3768         }
3769         mutex_unlock(&dev->struct_mutex);
3770
3771         ret = drm_irq_install(dev);
3772         if (ret)
3773                 goto cleanup_ringbuffer;
3774
3775         return 0;
3776
3777 cleanup_ringbuffer:
3778         mutex_lock(&dev->struct_mutex);
3779         i915_gem_cleanup_ringbuffer(dev);
3780         dev_priv->mm.suspended = 1;
3781         mutex_unlock(&dev->struct_mutex);
3782
3783         return ret;
3784 }
3785
3786 int
3787 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3788                        struct drm_file *file_priv)
3789 {
3790         if (drm_core_check_feature(dev, DRIVER_MODESET))
3791                 return 0;
3792
3793         drm_irq_uninstall(dev);
3794         return i915_gem_idle(dev);
3795 }
3796
3797 void
3798 i915_gem_lastclose(struct drm_device *dev)
3799 {
3800         int ret;
3801
3802         if (drm_core_check_feature(dev, DRIVER_MODESET))
3803                 return;
3804
3805         ret = i915_gem_idle(dev);
3806         if (ret)
3807                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3808 }
3809
3810 static void
3811 init_ring_lists(struct intel_ring_buffer *ring)
3812 {
3813         INIT_LIST_HEAD(&ring->active_list);
3814         INIT_LIST_HEAD(&ring->request_list);
3815         INIT_LIST_HEAD(&ring->gpu_write_list);
3816 }
3817
3818 void
3819 i915_gem_load(struct drm_device *dev)
3820 {
3821         int i;
3822         drm_i915_private_t *dev_priv = dev->dev_private;
3823
3824         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3825         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3826         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3827         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3828         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3829         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3830         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3831         for (i = 0; i < I915_NUM_RINGS; i++)
3832                 init_ring_lists(&dev_priv->ring[i]);
3833         for (i = 0; i < 16; i++)
3834                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3835         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3836                           i915_gem_retire_work_handler);
3837         init_completion(&dev_priv->error_completion);
3838
3839         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3840         if (IS_GEN3(dev)) {
3841                 u32 tmp = I915_READ(MI_ARB_STATE);
3842                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3843                         /* arb state is a masked write, so set bit + bit in mask */
3844                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3845                         I915_WRITE(MI_ARB_STATE, tmp);
3846                 }
3847         }
3848
3849         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3850
3851         /* Old X drivers will take 0-2 for front, back, depth buffers */
3852         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3853                 dev_priv->fence_reg_start = 3;
3854
3855         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3856                 dev_priv->num_fence_regs = 16;
3857         else
3858                 dev_priv->num_fence_regs = 8;
3859
3860         /* Initialize fence registers to zero */
3861         switch (INTEL_INFO(dev)->gen) {
3862         case 6:
3863                 for (i = 0; i < 16; i++)
3864                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3865                 break;
3866         case 5:
3867         case 4:
3868                 for (i = 0; i < 16; i++)
3869                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3870                 break;
3871         case 3:
3872                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3873                         for (i = 0; i < 8; i++)
3874                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3875         case 2:
3876                 for (i = 0; i < 8; i++)
3877                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3878                 break;
3879         }
3880         i915_gem_detect_bit_6_swizzle(dev);
3881         init_waitqueue_head(&dev_priv->pending_flip_queue);
3882
3883         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3884         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3885         register_shrinker(&dev_priv->mm.inactive_shrinker);
3886 }
3887
3888 /*
3889  * Create a physically contiguous memory object for this object
3890  * e.g. for cursor + overlay regs
3891  */
3892 static int i915_gem_init_phys_object(struct drm_device *dev,
3893                                      int id, int size, int align)
3894 {
3895         drm_i915_private_t *dev_priv = dev->dev_private;
3896         struct drm_i915_gem_phys_object *phys_obj;
3897         int ret;
3898
3899         if (dev_priv->mm.phys_objs[id - 1] || !size)
3900                 return 0;
3901
3902         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3903         if (!phys_obj)
3904                 return -ENOMEM;
3905
3906         phys_obj->id = id;
3907
3908         phys_obj->handle = drm_pci_alloc(dev, size, align);
3909         if (!phys_obj->handle) {
3910                 ret = -ENOMEM;
3911                 goto kfree_obj;
3912         }
3913 #ifdef CONFIG_X86
3914         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3915 #endif
3916
3917         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3918
3919         return 0;
3920 kfree_obj:
3921         kfree(phys_obj);
3922         return ret;
3923 }
3924
3925 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3926 {
3927         drm_i915_private_t *dev_priv = dev->dev_private;
3928         struct drm_i915_gem_phys_object *phys_obj;
3929
3930         if (!dev_priv->mm.phys_objs[id - 1])
3931                 return;
3932
3933         phys_obj = dev_priv->mm.phys_objs[id - 1];
3934         if (phys_obj->cur_obj) {
3935                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3936         }
3937
3938 #ifdef CONFIG_X86
3939         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3940 #endif
3941         drm_pci_free(dev, phys_obj->handle);
3942         kfree(phys_obj);
3943         dev_priv->mm.phys_objs[id - 1] = NULL;
3944 }
3945
3946 void i915_gem_free_all_phys_object(struct drm_device *dev)
3947 {
3948         int i;
3949
3950         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3951                 i915_gem_free_phys_object(dev, i);
3952 }
3953
3954 void i915_gem_detach_phys_object(struct drm_device *dev,
3955                                  struct drm_i915_gem_object *obj)
3956 {
3957         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3958         char *vaddr;
3959         int i;
3960         int page_count;
3961
3962         if (!obj->phys_obj)
3963                 return;
3964         vaddr = obj->phys_obj->handle->vaddr;
3965
3966         page_count = obj->base.size / PAGE_SIZE;
3967         for (i = 0; i < page_count; i++) {
3968                 struct page *page = read_cache_page_gfp(mapping, i,
3969                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3970                 if (!IS_ERR(page)) {
3971                         char *dst = kmap_atomic(page);
3972                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3973                         kunmap_atomic(dst);
3974
3975                         drm_clflush_pages(&page, 1);
3976
3977                         set_page_dirty(page);
3978                         mark_page_accessed(page);
3979                         page_cache_release(page);
3980                 }
3981         }
3982         intel_gtt_chipset_flush();
3983
3984         obj->phys_obj->cur_obj = NULL;
3985         obj->phys_obj = NULL;
3986 }
3987
3988 int
3989 i915_gem_attach_phys_object(struct drm_device *dev,
3990                             struct drm_i915_gem_object *obj,
3991                             int id,
3992                             int align)
3993 {
3994         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3995         drm_i915_private_t *dev_priv = dev->dev_private;
3996         int ret = 0;
3997         int page_count;
3998         int i;
3999
4000         if (id > I915_MAX_PHYS_OBJECT)
4001                 return -EINVAL;
4002
4003         if (obj->phys_obj) {
4004                 if (obj->phys_obj->id == id)
4005                         return 0;
4006                 i915_gem_detach_phys_object(dev, obj);
4007         }
4008
4009         /* create a new object */
4010         if (!dev_priv->mm.phys_objs[id - 1]) {
4011                 ret = i915_gem_init_phys_object(dev, id,
4012                                                 obj->base.size, align);
4013                 if (ret) {
4014                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4015                                   id, obj->base.size);
4016                         return ret;
4017                 }
4018         }
4019
4020         /* bind to the object */
4021         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4022         obj->phys_obj->cur_obj = obj;
4023
4024         page_count = obj->base.size / PAGE_SIZE;
4025
4026         for (i = 0; i < page_count; i++) {
4027                 struct page *page;
4028                 char *dst, *src;
4029
4030                 page = read_cache_page_gfp(mapping, i,
4031                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
4032                 if (IS_ERR(page))
4033                         return PTR_ERR(page);
4034
4035                 src = kmap_atomic(page);
4036                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4037                 memcpy(dst, src, PAGE_SIZE);
4038                 kunmap_atomic(src);
4039
4040                 mark_page_accessed(page);
4041                 page_cache_release(page);
4042         }
4043
4044         return 0;
4045 }
4046
4047 static int
4048 i915_gem_phys_pwrite(struct drm_device *dev,
4049                      struct drm_i915_gem_object *obj,
4050                      struct drm_i915_gem_pwrite *args,
4051                      struct drm_file *file_priv)
4052 {
4053         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4054         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4055
4056         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4057                 unsigned long unwritten;
4058
4059                 /* The physical object once assigned is fixed for the lifetime
4060                  * of the obj, so we can safely drop the lock and continue
4061                  * to access vaddr.
4062                  */
4063                 mutex_unlock(&dev->struct_mutex);
4064                 unwritten = copy_from_user(vaddr, user_data, args->size);
4065                 mutex_lock(&dev->struct_mutex);
4066                 if (unwritten)
4067                         return -EFAULT;
4068         }
4069
4070         intel_gtt_chipset_flush();
4071         return 0;
4072 }
4073
4074 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4075 {
4076         struct drm_i915_file_private *file_priv = file->driver_priv;
4077
4078         /* Clean up our request list when the client is going away, so that
4079          * later retire_requests won't dereference our soon-to-be-gone
4080          * file_priv.
4081          */
4082         spin_lock(&file_priv->mm.lock);
4083         while (!list_empty(&file_priv->mm.request_list)) {
4084                 struct drm_i915_gem_request *request;
4085
4086                 request = list_first_entry(&file_priv->mm.request_list,
4087                                            struct drm_i915_gem_request,
4088                                            client_list);
4089                 list_del(&request->client_list);
4090                 request->file_priv = NULL;
4091         }
4092         spin_unlock(&file_priv->mm.lock);
4093 }
4094
4095 static int
4096 i915_gpu_is_active(struct drm_device *dev)
4097 {
4098         drm_i915_private_t *dev_priv = dev->dev_private;
4099         int lists_empty;
4100
4101         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4102                       list_empty(&dev_priv->mm.active_list);
4103
4104         return !lists_empty;
4105 }
4106
4107 static int
4108 i915_gem_inactive_shrink(struct shrinker *shrinker,
4109                          int nr_to_scan,
4110                          gfp_t gfp_mask)
4111 {
4112         struct drm_i915_private *dev_priv =
4113                 container_of(shrinker,
4114                              struct drm_i915_private,
4115                              mm.inactive_shrinker);
4116         struct drm_device *dev = dev_priv->dev;
4117         struct drm_i915_gem_object *obj, *next;
4118         int cnt;
4119
4120         if (!mutex_trylock(&dev->struct_mutex))
4121                 return 0;
4122
4123         /* "fast-path" to count number of available objects */
4124         if (nr_to_scan == 0) {
4125                 cnt = 0;
4126                 list_for_each_entry(obj,
4127                                     &dev_priv->mm.inactive_list,
4128                                     mm_list)
4129                         cnt++;
4130                 mutex_unlock(&dev->struct_mutex);
4131                 return cnt / 100 * sysctl_vfs_cache_pressure;
4132         }
4133
4134 rescan:
4135         /* first scan for clean buffers */
4136         i915_gem_retire_requests(dev);
4137
4138         list_for_each_entry_safe(obj, next,
4139                                  &dev_priv->mm.inactive_list,
4140                                  mm_list) {
4141                 if (i915_gem_object_is_purgeable(obj)) {
4142                         if (i915_gem_object_unbind(obj) == 0 &&
4143                             --nr_to_scan == 0)
4144                                 break;
4145                 }
4146         }
4147
4148         /* second pass, evict/count anything still on the inactive list */
4149         cnt = 0;
4150         list_for_each_entry_safe(obj, next,
4151                                  &dev_priv->mm.inactive_list,
4152                                  mm_list) {
4153                 if (nr_to_scan &&
4154                     i915_gem_object_unbind(obj) == 0)
4155                         nr_to_scan--;
4156                 else
4157                         cnt++;
4158         }
4159
4160         if (nr_to_scan && i915_gpu_is_active(dev)) {
4161                 /*
4162                  * We are desperate for pages, so as a last resort, wait
4163                  * for the GPU to finish and discard whatever we can.
4164                  * This has a dramatic impact to reduce the number of
4165                  * OOM-killer events whilst running the GPU aggressively.
4166                  */
4167                 if (i915_gpu_idle(dev) == 0)
4168                         goto rescan;
4169         }
4170         mutex_unlock(&dev->struct_mutex);
4171         return cnt / 100 * sysctl_vfs_cache_pressure;
4172 }