2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
95 const struct i915_ggtt_view i915_ggtt_view_normal;
96 const struct i915_ggtt_view i915_ggtt_view_rotated = {
97 .type = I915_GGTT_VIEW_ROTATED
100 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
102 bool has_aliasing_ppgtt;
105 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
106 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
108 if (intel_vgpu_active(dev))
109 has_full_ppgtt = false; /* emulation is too hard */
112 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
113 * execlists, the sole mechanism available to submit work.
115 if (INTEL_INFO(dev)->gen < 9 &&
116 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
119 if (enable_ppgtt == 1)
122 if (enable_ppgtt == 2 && has_full_ppgtt)
125 #ifdef CONFIG_INTEL_IOMMU
126 /* Disable ppgtt on SNB if VT-d is on. */
127 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
128 DRM_INFO("Disabling PPGTT because VT-d is on\n");
133 /* Early VLV doesn't have this */
134 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
135 dev->pdev->revision < 0xb) {
136 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
143 return has_aliasing_ppgtt ? 1 : 0;
146 static void ppgtt_bind_vma(struct i915_vma *vma,
147 enum i915_cache_level cache_level,
152 /* Currently applicable only to VLV */
154 pte_flags |= PTE_READ_ONLY;
156 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
157 cache_level, pte_flags);
160 static void ppgtt_unbind_vma(struct i915_vma *vma)
162 vma->vm->clear_range(vma->vm,
168 static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr,
169 enum i915_cache_level level,
172 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
176 case I915_CACHE_NONE:
177 pte |= PPAT_UNCACHED_INDEX;
180 pte |= PPAT_DISPLAY_ELLC_INDEX;
183 pte |= PPAT_CACHED_INDEX;
190 static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev,
192 enum i915_cache_level level)
194 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
196 if (level != I915_CACHE_NONE)
197 pde |= PPAT_CACHED_PDE_INDEX;
199 pde |= PPAT_UNCACHED_INDEX;
203 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
204 enum i915_cache_level level,
205 bool valid, u32 unused)
207 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
208 pte |= GEN6_PTE_ADDR_ENCODE(addr);
211 case I915_CACHE_L3_LLC:
213 pte |= GEN6_PTE_CACHE_LLC;
215 case I915_CACHE_NONE:
216 pte |= GEN6_PTE_UNCACHED;
225 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
226 enum i915_cache_level level,
227 bool valid, u32 unused)
229 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
230 pte |= GEN6_PTE_ADDR_ENCODE(addr);
233 case I915_CACHE_L3_LLC:
234 pte |= GEN7_PTE_CACHE_L3_LLC;
237 pte |= GEN6_PTE_CACHE_LLC;
239 case I915_CACHE_NONE:
240 pte |= GEN6_PTE_UNCACHED;
249 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
250 enum i915_cache_level level,
251 bool valid, u32 flags)
253 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
254 pte |= GEN6_PTE_ADDR_ENCODE(addr);
256 if (!(flags & PTE_READ_ONLY))
257 pte |= BYT_PTE_WRITEABLE;
259 if (level != I915_CACHE_NONE)
260 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
265 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
266 enum i915_cache_level level,
267 bool valid, u32 unused)
269 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
270 pte |= HSW_PTE_ADDR_ENCODE(addr);
272 if (level != I915_CACHE_NONE)
273 pte |= HSW_WB_LLC_AGE3;
278 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
279 enum i915_cache_level level,
280 bool valid, u32 unused)
282 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
283 pte |= HSW_PTE_ADDR_ENCODE(addr);
286 case I915_CACHE_NONE:
289 pte |= HSW_WT_ELLC_LLC_AGE3;
292 pte |= HSW_WB_ELLC_LLC_AGE3;
299 #define i915_dma_unmap_single(px, dev) \
300 __i915_dma_unmap_single((px)->daddr, dev)
302 static inline void __i915_dma_unmap_single(dma_addr_t daddr,
303 struct drm_device *dev)
305 struct device *device = &dev->pdev->dev;
307 dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
311 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
312 * @px: Page table/dir/etc to get a DMA map for
315 * Page table allocations are unified across all gens. They always require a
316 * single 4k allocation, as well as a DMA mapping. If we keep the structs
317 * symmetric here, the simple macro covers us for every page table type.
319 * Return: 0 if success.
321 #define i915_dma_map_single(px, dev) \
322 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
324 static inline int i915_dma_map_page_single(struct page *page,
325 struct drm_device *dev,
328 struct device *device = &dev->pdev->dev;
330 *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
331 if (dma_mapping_error(device, *daddr))
337 static void unmap_and_free_pt(struct i915_page_table *pt,
338 struct drm_device *dev)
340 if (WARN_ON(!pt->page))
343 i915_dma_unmap_single(pt, dev);
344 __free_page(pt->page);
345 kfree(pt->used_ptes);
349 static void gen8_initialize_pt(struct i915_address_space *vm,
350 struct i915_page_table *pt)
352 gen8_pte_t *pt_vaddr, scratch_pte;
355 pt_vaddr = kmap_atomic(pt->page);
356 scratch_pte = gen8_pte_encode(vm->scratch.addr,
357 I915_CACHE_LLC, true);
359 for (i = 0; i < GEN8_PTES; i++)
360 pt_vaddr[i] = scratch_pte;
362 if (!HAS_LLC(vm->dev))
363 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
364 kunmap_atomic(pt_vaddr);
367 static struct i915_page_table *alloc_pt_single(struct drm_device *dev)
369 struct i915_page_table *pt;
370 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
371 GEN8_PTES : GEN6_PTES;
374 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
376 return ERR_PTR(-ENOMEM);
378 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
384 pt->page = alloc_page(GFP_KERNEL);
388 ret = i915_dma_map_single(pt, dev);
395 __free_page(pt->page);
397 kfree(pt->used_ptes);
404 static void unmap_and_free_pd(struct i915_page_directory *pd,
405 struct drm_device *dev)
408 i915_dma_unmap_single(pd, dev);
409 __free_page(pd->page);
410 kfree(pd->used_pdes);
415 static struct i915_page_directory *alloc_pd_single(struct drm_device *dev)
417 struct i915_page_directory *pd;
420 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
422 return ERR_PTR(-ENOMEM);
424 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
425 sizeof(*pd->used_pdes), GFP_KERNEL);
429 pd->page = alloc_page(GFP_KERNEL);
433 ret = i915_dma_map_single(pd, dev);
440 __free_page(pd->page);
442 kfree(pd->used_pdes);
449 /* Broadwell Page Directory Pointer Descriptors */
450 static int gen8_write_pdp(struct intel_engine_cs *ring,
458 ret = intel_ring_begin(ring, 6);
462 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
463 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
464 intel_ring_emit(ring, upper_32_bits(addr));
465 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
466 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
467 intel_ring_emit(ring, lower_32_bits(addr));
468 intel_ring_advance(ring);
473 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
474 struct intel_engine_cs *ring)
478 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
479 struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
480 dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr;
481 /* The page directory might be NULL, but we need to clear out
482 * whatever the previous context might have used. */
483 ret = gen8_write_pdp(ring, i, pd_daddr);
491 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
496 struct i915_hw_ppgtt *ppgtt =
497 container_of(vm, struct i915_hw_ppgtt, base);
498 gen8_pte_t *pt_vaddr, scratch_pte;
499 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
500 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
501 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
502 unsigned num_entries = length >> PAGE_SHIFT;
503 unsigned last_pte, i;
505 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
506 I915_CACHE_LLC, use_scratch);
508 while (num_entries) {
509 struct i915_page_directory *pd;
510 struct i915_page_table *pt;
511 struct page *page_table;
513 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
516 pd = ppgtt->pdp.page_directory[pdpe];
518 if (WARN_ON(!pd->page_table[pde]))
521 pt = pd->page_table[pde];
523 if (WARN_ON(!pt->page))
526 page_table = pt->page;
528 last_pte = pte + num_entries;
529 if (last_pte > GEN8_PTES)
530 last_pte = GEN8_PTES;
532 pt_vaddr = kmap_atomic(page_table);
534 for (i = pte; i < last_pte; i++) {
535 pt_vaddr[i] = scratch_pte;
539 if (!HAS_LLC(ppgtt->base.dev))
540 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
541 kunmap_atomic(pt_vaddr);
544 if (++pde == I915_PDES) {
551 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
552 struct sg_table *pages,
554 enum i915_cache_level cache_level, u32 unused)
556 struct i915_hw_ppgtt *ppgtt =
557 container_of(vm, struct i915_hw_ppgtt, base);
558 gen8_pte_t *pt_vaddr;
559 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
560 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
561 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
562 struct sg_page_iter sg_iter;
566 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
567 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
570 if (pt_vaddr == NULL) {
571 struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
572 struct i915_page_table *pt = pd->page_table[pde];
573 struct page *page_table = pt->page;
575 pt_vaddr = kmap_atomic(page_table);
579 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
581 if (++pte == GEN8_PTES) {
582 if (!HAS_LLC(ppgtt->base.dev))
583 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
584 kunmap_atomic(pt_vaddr);
586 if (++pde == I915_PDES) {
594 if (!HAS_LLC(ppgtt->base.dev))
595 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
596 kunmap_atomic(pt_vaddr);
600 static void __gen8_do_map_pt(gen8_pde_t * const pde,
601 struct i915_page_table *pt,
602 struct drm_device *dev)
605 gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC);
609 static void gen8_initialize_pd(struct i915_address_space *vm,
610 struct i915_page_directory *pd)
612 struct i915_hw_ppgtt *ppgtt =
613 container_of(vm, struct i915_hw_ppgtt, base);
614 gen8_pde_t *page_directory;
615 struct i915_page_table *pt;
618 page_directory = kmap_atomic(pd->page);
619 pt = ppgtt->scratch_pt;
620 for (i = 0; i < I915_PDES; i++)
621 /* Map the PDE to the page table */
622 __gen8_do_map_pt(page_directory + i, pt, vm->dev);
624 if (!HAS_LLC(vm->dev))
625 drm_clflush_virt_range(page_directory, PAGE_SIZE);
626 kunmap_atomic(page_directory);
629 static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
636 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
637 if (WARN_ON(!pd->page_table[i]))
640 unmap_and_free_pt(pd->page_table[i], dev);
641 pd->page_table[i] = NULL;
645 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
647 struct i915_hw_ppgtt *ppgtt =
648 container_of(vm, struct i915_hw_ppgtt, base);
651 for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
652 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
655 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
656 unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
659 unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev);
660 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
664 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
665 * @ppgtt: Master ppgtt structure.
666 * @pd: Page directory for this address range.
667 * @start: Starting virtual address to begin allocations.
668 * @length Size of the allocations.
669 * @new_pts: Bitmap set by function with new allocations. Likely used by the
670 * caller to free on error.
672 * Allocate the required number of page tables. Extremely similar to
673 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
674 * the page directory boundary (instead of the page directory pointer). That
675 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
676 * possible, and likely that the caller will need to use multiple calls of this
677 * function to achieve the appropriate allocation.
679 * Return: 0 if success; negative error code otherwise.
681 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
682 struct i915_page_directory *pd,
685 unsigned long *new_pts)
687 struct drm_device *dev = ppgtt->base.dev;
688 struct i915_page_table *pt;
692 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
693 /* Don't reallocate page tables */
695 /* Scratch is never allocated this way */
696 WARN_ON(pt == ppgtt->scratch_pt);
700 pt = alloc_pt_single(dev);
704 gen8_initialize_pt(&ppgtt->base, pt);
705 pd->page_table[pde] = pt;
706 set_bit(pde, new_pts);
712 for_each_set_bit(pde, new_pts, I915_PDES)
713 unmap_and_free_pt(pd->page_table[pde], dev);
719 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
720 * @ppgtt: Master ppgtt structure.
721 * @pdp: Page directory pointer for this address range.
722 * @start: Starting virtual address to begin allocations.
723 * @length Size of the allocations.
724 * @new_pds Bitmap set by function with new allocations. Likely used by the
725 * caller to free on error.
727 * Allocate the required number of page directories starting at the pde index of
728 * @start, and ending at the pde index @start + @length. This function will skip
729 * over already allocated page directories within the range, and only allocate
730 * new ones, setting the appropriate pointer within the pdp as well as the
731 * correct position in the bitmap @new_pds.
733 * The function will only allocate the pages within the range for a give page
734 * directory pointer. In other words, if @start + @length straddles a virtually
735 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
736 * required by the caller, This is not currently possible, and the BUG in the
737 * code will prevent it.
739 * Return: 0 if success; negative error code otherwise.
741 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
742 struct i915_page_directory_pointer *pdp,
745 unsigned long *new_pds)
747 struct drm_device *dev = ppgtt->base.dev;
748 struct i915_page_directory *pd;
752 WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
754 /* FIXME: PPGTT container_of won't work for 64b */
755 WARN_ON((start + length) > 0x800000000ULL);
757 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
761 pd = alloc_pd_single(dev);
765 gen8_initialize_pd(&ppgtt->base, pd);
766 pdp->page_directory[pdpe] = pd;
767 set_bit(pdpe, new_pds);
773 for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
774 unmap_and_free_pd(pdp->page_directory[pdpe], dev);
780 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
784 for (i = 0; i < GEN8_LEGACY_PDPES; i++)
790 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
791 * of these are based on the number of PDPEs in the system.
794 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
795 unsigned long ***new_pts)
801 pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
805 pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
811 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
812 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
813 sizeof(unsigned long), GFP_KERNEL);
824 free_gen8_temp_bitmaps(pds, pts);
828 static int gen8_alloc_va_range(struct i915_address_space *vm,
832 struct i915_hw_ppgtt *ppgtt =
833 container_of(vm, struct i915_hw_ppgtt, base);
834 unsigned long *new_page_dirs, **new_page_tables;
835 struct i915_page_directory *pd;
836 const uint64_t orig_start = start;
837 const uint64_t orig_length = length;
843 /* Disallow 64b address on 32b platforms. Nothing is wrong with doing
844 * this in hardware, but a lot of the drm code is not prepared to handle
845 * 64b offset on 32b platforms.
846 * This will be addressed when 48b PPGTT is added */
847 if (start + length > 0x100000000ULL)
851 /* Wrap is never okay since we can only represent 48b, and we don't
852 * actually use the other side of the canonical address space.
854 if (WARN_ON(start + length < start))
857 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
861 /* Do the allocations first so we can easily bail out */
862 ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
865 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
869 /* For every page directory referenced, allocate page tables */
870 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
871 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
872 new_page_tables[pdpe]);
878 length = orig_length;
880 /* Allocations have completed successfully, so set the bitmaps, and do
882 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
883 gen8_pde_t *const page_directory = kmap_atomic(pd->page);
884 struct i915_page_table *pt;
885 uint64_t pd_len = gen8_clamp_pd(start, length);
886 uint64_t pd_start = start;
889 /* Every pd should be allocated, we just did that above. */
892 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
893 /* Same reasoning as pd */
896 WARN_ON(!gen8_pte_count(pd_start, pd_len));
898 /* Set our used ptes within the page table */
899 bitmap_set(pt->used_ptes,
900 gen8_pte_index(pd_start),
901 gen8_pte_count(pd_start, pd_len));
903 /* Our pde is now pointing to the pagetable, pt */
904 set_bit(pde, pd->used_pdes);
906 /* Map the PDE to the page table */
907 __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
909 /* NB: We haven't yet mapped ptes to pages. At this
910 * point we're still relying on insert_entries() */
913 if (!HAS_LLC(vm->dev))
914 drm_clflush_virt_range(page_directory, PAGE_SIZE);
916 kunmap_atomic(page_directory);
918 set_bit(pdpe, ppgtt->pdp.used_pdpes);
921 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
926 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
927 unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev);
930 for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
931 unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev);
933 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
938 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
939 * with a net effect resembling a 2-level page table in normal x86 terms. Each
940 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
944 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
946 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
947 if (IS_ERR(ppgtt->scratch_pt))
948 return PTR_ERR(ppgtt->scratch_pt);
950 ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev);
951 if (IS_ERR(ppgtt->scratch_pd))
952 return PTR_ERR(ppgtt->scratch_pd);
954 gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
955 gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
957 ppgtt->base.start = 0;
958 ppgtt->base.total = 1ULL << 32;
959 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
960 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
961 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
962 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
963 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
964 ppgtt->base.bind_vma = ppgtt_bind_vma;
966 ppgtt->switch_mm = gen8_mm_switch;
971 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
973 struct i915_address_space *vm = &ppgtt->base;
974 struct i915_page_table *unused;
975 gen6_pte_t scratch_pte;
977 uint32_t pte, pde, temp;
978 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
980 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
982 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
984 gen6_pte_t *pt_vaddr;
985 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
986 pd_entry = readl(ppgtt->pd_addr + pde);
987 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
989 if (pd_entry != expected)
990 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
994 seq_printf(m, "\tPDE: %x\n", pd_entry);
996 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
997 for (pte = 0; pte < GEN6_PTES; pte+=4) {
999 (pde * PAGE_SIZE * GEN6_PTES) +
1003 for (i = 0; i < 4; i++)
1004 if (pt_vaddr[pte + i] != scratch_pte)
1009 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1010 for (i = 0; i < 4; i++) {
1011 if (pt_vaddr[pte + i] != scratch_pte)
1012 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1014 seq_puts(m, " SCRATCH ");
1018 kunmap_atomic(pt_vaddr);
1022 /* Write pde (index) from the page directory @pd to the page table @pt */
1023 static void gen6_write_pde(struct i915_page_directory *pd,
1024 const int pde, struct i915_page_table *pt)
1026 /* Caller needs to make sure the write completes if necessary */
1027 struct i915_hw_ppgtt *ppgtt =
1028 container_of(pd, struct i915_hw_ppgtt, pd);
1031 pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr);
1032 pd_entry |= GEN6_PDE_VALID;
1034 writel(pd_entry, ppgtt->pd_addr + pde);
1037 /* Write all the page tables found in the ppgtt structure to incrementing page
1039 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1040 struct i915_page_directory *pd,
1041 uint32_t start, uint32_t length)
1043 struct i915_page_table *pt;
1046 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1047 gen6_write_pde(pd, pde, pt);
1049 /* Make sure write is complete before other code can use this page
1050 * table. Also require for WC mapped PTEs */
1051 readl(dev_priv->gtt.gsm);
1054 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1056 BUG_ON(ppgtt->pd.pd_offset & 0x3f);
1058 return (ppgtt->pd.pd_offset / 64) << 16;
1061 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1062 struct intel_engine_cs *ring)
1066 /* NB: TLBs must be flushed and invalidated before a switch */
1067 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1071 ret = intel_ring_begin(ring, 6);
1075 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1076 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1077 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1078 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1079 intel_ring_emit(ring, get_pd_offset(ppgtt));
1080 intel_ring_emit(ring, MI_NOOP);
1081 intel_ring_advance(ring);
1086 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1087 struct intel_engine_cs *ring)
1089 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1091 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1092 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1096 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1097 struct intel_engine_cs *ring)
1101 /* NB: TLBs must be flushed and invalidated before a switch */
1102 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1106 ret = intel_ring_begin(ring, 6);
1110 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1111 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1112 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1113 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1114 intel_ring_emit(ring, get_pd_offset(ppgtt));
1115 intel_ring_emit(ring, MI_NOOP);
1116 intel_ring_advance(ring);
1118 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1119 if (ring->id != RCS) {
1120 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1128 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1129 struct intel_engine_cs *ring)
1131 struct drm_device *dev = ppgtt->base.dev;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1135 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1136 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1138 POSTING_READ(RING_PP_DIR_DCLV(ring));
1143 static void gen8_ppgtt_enable(struct drm_device *dev)
1145 struct drm_i915_private *dev_priv = dev->dev_private;
1146 struct intel_engine_cs *ring;
1149 for_each_ring(ring, dev_priv, j) {
1150 I915_WRITE(RING_MODE_GEN7(ring),
1151 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1155 static void gen7_ppgtt_enable(struct drm_device *dev)
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 struct intel_engine_cs *ring;
1159 uint32_t ecochk, ecobits;
1162 ecobits = I915_READ(GAC_ECO_BITS);
1163 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1165 ecochk = I915_READ(GAM_ECOCHK);
1166 if (IS_HASWELL(dev)) {
1167 ecochk |= ECOCHK_PPGTT_WB_HSW;
1169 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1170 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1172 I915_WRITE(GAM_ECOCHK, ecochk);
1174 for_each_ring(ring, dev_priv, i) {
1175 /* GFX_MODE is per-ring on gen7+ */
1176 I915_WRITE(RING_MODE_GEN7(ring),
1177 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1181 static void gen6_ppgtt_enable(struct drm_device *dev)
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 uint32_t ecochk, gab_ctl, ecobits;
1186 ecobits = I915_READ(GAC_ECO_BITS);
1187 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1188 ECOBITS_PPGTT_CACHE64B);
1190 gab_ctl = I915_READ(GAB_CTL);
1191 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1193 ecochk = I915_READ(GAM_ECOCHK);
1194 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1196 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1199 /* PPGTT support for Sandybdrige/Gen6 and later */
1200 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1205 struct i915_hw_ppgtt *ppgtt =
1206 container_of(vm, struct i915_hw_ppgtt, base);
1207 gen6_pte_t *pt_vaddr, scratch_pte;
1208 unsigned first_entry = start >> PAGE_SHIFT;
1209 unsigned num_entries = length >> PAGE_SHIFT;
1210 unsigned act_pt = first_entry / GEN6_PTES;
1211 unsigned first_pte = first_entry % GEN6_PTES;
1212 unsigned last_pte, i;
1214 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1216 while (num_entries) {
1217 last_pte = first_pte + num_entries;
1218 if (last_pte > GEN6_PTES)
1219 last_pte = GEN6_PTES;
1221 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1223 for (i = first_pte; i < last_pte; i++)
1224 pt_vaddr[i] = scratch_pte;
1226 kunmap_atomic(pt_vaddr);
1228 num_entries -= last_pte - first_pte;
1234 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1235 struct sg_table *pages,
1237 enum i915_cache_level cache_level, u32 flags)
1239 struct i915_hw_ppgtt *ppgtt =
1240 container_of(vm, struct i915_hw_ppgtt, base);
1241 gen6_pte_t *pt_vaddr;
1242 unsigned first_entry = start >> PAGE_SHIFT;
1243 unsigned act_pt = first_entry / GEN6_PTES;
1244 unsigned act_pte = first_entry % GEN6_PTES;
1245 struct sg_page_iter sg_iter;
1248 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1249 if (pt_vaddr == NULL)
1250 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1253 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1254 cache_level, true, flags);
1256 if (++act_pte == GEN6_PTES) {
1257 kunmap_atomic(pt_vaddr);
1264 kunmap_atomic(pt_vaddr);
1267 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1268 * are switching between contexts with the same LRCA, we also must do a force
1271 static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1273 /* If current vm != vm, */
1274 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1277 static void gen6_initialize_pt(struct i915_address_space *vm,
1278 struct i915_page_table *pt)
1280 gen6_pte_t *pt_vaddr, scratch_pte;
1283 WARN_ON(vm->scratch.addr == 0);
1285 scratch_pte = vm->pte_encode(vm->scratch.addr,
1286 I915_CACHE_LLC, true, 0);
1288 pt_vaddr = kmap_atomic(pt->page);
1290 for (i = 0; i < GEN6_PTES; i++)
1291 pt_vaddr[i] = scratch_pte;
1293 kunmap_atomic(pt_vaddr);
1296 static int gen6_alloc_va_range(struct i915_address_space *vm,
1297 uint64_t start, uint64_t length)
1299 DECLARE_BITMAP(new_page_tables, I915_PDES);
1300 struct drm_device *dev = vm->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 struct i915_hw_ppgtt *ppgtt =
1303 container_of(vm, struct i915_hw_ppgtt, base);
1304 struct i915_page_table *pt;
1305 const uint32_t start_save = start, length_save = length;
1309 WARN_ON(upper_32_bits(start));
1311 bitmap_zero(new_page_tables, I915_PDES);
1313 /* The allocation is done in two stages so that we can bail out with
1314 * minimal amount of pain. The first stage finds new page tables that
1315 * need allocation. The second stage marks use ptes within the page
1318 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1319 if (pt != ppgtt->scratch_pt) {
1320 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1324 /* We've already allocated a page table */
1325 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1327 pt = alloc_pt_single(dev);
1333 gen6_initialize_pt(vm, pt);
1335 ppgtt->pd.page_table[pde] = pt;
1336 set_bit(pde, new_page_tables);
1337 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1341 length = length_save;
1343 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1344 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1346 bitmap_zero(tmp_bitmap, GEN6_PTES);
1347 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1348 gen6_pte_count(start, length));
1350 if (test_and_clear_bit(pde, new_page_tables))
1351 gen6_write_pde(&ppgtt->pd, pde, pt);
1353 trace_i915_page_table_entry_map(vm, pde, pt,
1354 gen6_pte_index(start),
1355 gen6_pte_count(start, length),
1357 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1361 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1363 /* Make sure write is complete before other code can use this page
1364 * table. Also require for WC mapped PTEs */
1365 readl(dev_priv->gtt.gsm);
1367 mark_tlbs_dirty(ppgtt);
1371 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1372 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1374 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1375 unmap_and_free_pt(pt, vm->dev);
1378 mark_tlbs_dirty(ppgtt);
1382 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1384 struct i915_hw_ppgtt *ppgtt =
1385 container_of(vm, struct i915_hw_ppgtt, base);
1386 struct i915_page_table *pt;
1390 drm_mm_remove_node(&ppgtt->node);
1392 gen6_for_all_pdes(pt, ppgtt, pde) {
1393 if (pt != ppgtt->scratch_pt)
1394 unmap_and_free_pt(pt, ppgtt->base.dev);
1397 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1398 unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev);
1401 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1403 struct drm_device *dev = ppgtt->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 bool retried = false;
1408 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1409 * allocator works in address space sizes, so it's multiplied by page
1410 * size. We allocate at the top of the GTT to avoid fragmentation.
1412 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1413 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
1414 if (IS_ERR(ppgtt->scratch_pt))
1415 return PTR_ERR(ppgtt->scratch_pt);
1417 gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1420 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1421 &ppgtt->node, GEN6_PD_SIZE,
1423 0, dev_priv->gtt.base.total,
1425 if (ret == -ENOSPC && !retried) {
1426 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1427 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1429 0, dev_priv->gtt.base.total,
1442 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1443 DRM_DEBUG("Forced to use aperture for PDEs\n");
1448 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1452 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1454 return gen6_ppgtt_allocate_page_directories(ppgtt);
1457 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1458 uint64_t start, uint64_t length)
1460 struct i915_page_table *unused;
1463 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1464 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1467 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1469 struct drm_device *dev = ppgtt->base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1473 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1475 ppgtt->switch_mm = gen6_mm_switch;
1476 } else if (IS_HASWELL(dev)) {
1477 ppgtt->switch_mm = hsw_mm_switch;
1478 } else if (IS_GEN7(dev)) {
1479 ppgtt->switch_mm = gen7_mm_switch;
1483 if (intel_vgpu_active(dev))
1484 ppgtt->switch_mm = vgpu_mm_switch;
1486 ret = gen6_ppgtt_alloc(ppgtt);
1490 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1491 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1492 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1493 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1494 ppgtt->base.bind_vma = ppgtt_bind_vma;
1495 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1496 ppgtt->base.start = 0;
1497 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1498 ppgtt->debug_dump = gen6_dump_ppgtt;
1500 ppgtt->pd.pd_offset =
1501 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1503 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1504 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
1506 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1508 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1510 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1511 ppgtt->node.size >> 20,
1512 ppgtt->node.start / PAGE_SIZE);
1514 DRM_DEBUG("Adding PPGTT at offset %x\n",
1515 ppgtt->pd.pd_offset << 10);
1520 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1524 ppgtt->base.dev = dev;
1525 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1527 if (INTEL_INFO(dev)->gen < 8)
1528 return gen6_ppgtt_init(ppgtt);
1530 return gen8_ppgtt_init(ppgtt);
1532 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1537 ret = __hw_ppgtt_init(dev, ppgtt);
1539 kref_init(&ppgtt->ref);
1540 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1542 i915_init_vm(dev_priv, &ppgtt->base);
1548 int i915_ppgtt_init_hw(struct drm_device *dev)
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 struct intel_engine_cs *ring;
1552 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1555 /* In the case of execlists, PPGTT is enabled by the context descriptor
1556 * and the PDPs are contained within the context itself. We don't
1557 * need to do anything here. */
1558 if (i915.enable_execlists)
1561 if (!USES_PPGTT(dev))
1565 gen6_ppgtt_enable(dev);
1566 else if (IS_GEN7(dev))
1567 gen7_ppgtt_enable(dev);
1568 else if (INTEL_INFO(dev)->gen >= 8)
1569 gen8_ppgtt_enable(dev);
1571 MISSING_CASE(INTEL_INFO(dev)->gen);
1574 for_each_ring(ring, dev_priv, i) {
1575 ret = ppgtt->switch_mm(ppgtt, ring);
1583 struct i915_hw_ppgtt *
1584 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1586 struct i915_hw_ppgtt *ppgtt;
1589 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1591 return ERR_PTR(-ENOMEM);
1593 ret = i915_ppgtt_init(dev, ppgtt);
1596 return ERR_PTR(ret);
1599 ppgtt->file_priv = fpriv;
1601 trace_i915_ppgtt_create(&ppgtt->base);
1606 void i915_ppgtt_release(struct kref *kref)
1608 struct i915_hw_ppgtt *ppgtt =
1609 container_of(kref, struct i915_hw_ppgtt, ref);
1611 trace_i915_ppgtt_release(&ppgtt->base);
1613 /* vmas should already be unbound */
1614 WARN_ON(!list_empty(&ppgtt->base.active_list));
1615 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1617 list_del(&ppgtt->base.global_link);
1618 drm_mm_takedown(&ppgtt->base.mm);
1620 ppgtt->base.cleanup(&ppgtt->base);
1624 extern int intel_iommu_gfx_mapped;
1625 /* Certain Gen5 chipsets require require idling the GPU before
1626 * unmapping anything from the GTT when VT-d is enabled.
1628 static inline bool needs_idle_maps(struct drm_device *dev)
1630 #ifdef CONFIG_INTEL_IOMMU
1631 /* Query intel_iommu to see if we need the workaround. Presumably that
1634 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1640 static bool do_idling(struct drm_i915_private *dev_priv)
1642 bool ret = dev_priv->mm.interruptible;
1644 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1645 dev_priv->mm.interruptible = false;
1646 if (i915_gpu_idle(dev_priv->dev)) {
1647 DRM_ERROR("Couldn't idle GPU\n");
1648 /* Wait a bit, in hopes it avoids the hang */
1656 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1658 if (unlikely(dev_priv->gtt.do_idle_maps))
1659 dev_priv->mm.interruptible = interruptible;
1662 void i915_check_and_clear_faults(struct drm_device *dev)
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 struct intel_engine_cs *ring;
1668 if (INTEL_INFO(dev)->gen < 6)
1671 for_each_ring(ring, dev_priv, i) {
1673 fault_reg = I915_READ(RING_FAULT_REG(ring));
1674 if (fault_reg & RING_FAULT_VALID) {
1675 DRM_DEBUG_DRIVER("Unexpected fault\n"
1677 "\tAddress space: %s\n"
1680 fault_reg & PAGE_MASK,
1681 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1682 RING_FAULT_SRCID(fault_reg),
1683 RING_FAULT_FAULT_TYPE(fault_reg));
1684 I915_WRITE(RING_FAULT_REG(ring),
1685 fault_reg & ~RING_FAULT_VALID);
1688 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1691 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1693 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1694 intel_gtt_chipset_flush();
1696 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1697 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1701 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1705 /* Don't bother messing with faults pre GEN6 as we have little
1706 * documentation supporting that it's a good idea.
1708 if (INTEL_INFO(dev)->gen < 6)
1711 i915_check_and_clear_faults(dev);
1713 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1714 dev_priv->gtt.base.start,
1715 dev_priv->gtt.base.total,
1718 i915_ggtt_flush(dev_priv);
1721 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1723 if (obj->has_dma_mapping)
1726 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1727 obj->pages->sgl, obj->pages->nents,
1728 PCI_DMA_BIDIRECTIONAL))
1734 static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1739 iowrite32((u32)pte, addr);
1740 iowrite32(pte >> 32, addr + 4);
1744 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1745 struct sg_table *st,
1747 enum i915_cache_level level, u32 unused)
1749 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1750 unsigned first_entry = start >> PAGE_SHIFT;
1751 gen8_pte_t __iomem *gtt_entries =
1752 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1754 struct sg_page_iter sg_iter;
1755 dma_addr_t addr = 0; /* shut up gcc */
1757 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1758 addr = sg_dma_address(sg_iter.sg) +
1759 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1760 gen8_set_pte(>t_entries[i],
1761 gen8_pte_encode(addr, level, true));
1766 * XXX: This serves as a posting read to make sure that the PTE has
1767 * actually been updated. There is some concern that even though
1768 * registers and PTEs are within the same BAR that they are potentially
1769 * of NUMA access patterns. Therefore, even with the way we assume
1770 * hardware should work, we must keep this posting read for paranoia.
1773 WARN_ON(readq(>t_entries[i-1])
1774 != gen8_pte_encode(addr, level, true));
1776 /* This next bit makes the above posting read even more important. We
1777 * want to flush the TLBs only after we're certain all the PTE updates
1780 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1781 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1785 * Binds an object into the global gtt with the specified cache level. The object
1786 * will be accessible to the GPU via commands whose operands reference offsets
1787 * within the global GTT as well as accessible by the GPU through the GMADR
1788 * mapped BAR (dev_priv->mm.gtt->gtt).
1790 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1791 struct sg_table *st,
1793 enum i915_cache_level level, u32 flags)
1795 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1796 unsigned first_entry = start >> PAGE_SHIFT;
1797 gen6_pte_t __iomem *gtt_entries =
1798 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1800 struct sg_page_iter sg_iter;
1801 dma_addr_t addr = 0;
1803 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1804 addr = sg_page_iter_dma_address(&sg_iter);
1805 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
1809 /* XXX: This serves as a posting read to make sure that the PTE has
1810 * actually been updated. There is some concern that even though
1811 * registers and PTEs are within the same BAR that they are potentially
1812 * of NUMA access patterns. Therefore, even with the way we assume
1813 * hardware should work, we must keep this posting read for paranoia.
1816 unsigned long gtt = readl(>t_entries[i-1]);
1817 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1820 /* This next bit makes the above posting read even more important. We
1821 * want to flush the TLBs only after we're certain all the PTE updates
1824 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1825 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1828 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1833 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1834 unsigned first_entry = start >> PAGE_SHIFT;
1835 unsigned num_entries = length >> PAGE_SHIFT;
1836 gen8_pte_t scratch_pte, __iomem *gtt_base =
1837 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1838 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1841 if (WARN(num_entries > max_entries,
1842 "First entry = %d; Num entries = %d (max=%d)\n",
1843 first_entry, num_entries, max_entries))
1844 num_entries = max_entries;
1846 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1849 for (i = 0; i < num_entries; i++)
1850 gen8_set_pte(>t_base[i], scratch_pte);
1854 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1859 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1860 unsigned first_entry = start >> PAGE_SHIFT;
1861 unsigned num_entries = length >> PAGE_SHIFT;
1862 gen6_pte_t scratch_pte, __iomem *gtt_base =
1863 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1864 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1867 if (WARN(num_entries > max_entries,
1868 "First entry = %d; Num entries = %d (max=%d)\n",
1869 first_entry, num_entries, max_entries))
1870 num_entries = max_entries;
1872 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1874 for (i = 0; i < num_entries; i++)
1875 iowrite32(scratch_pte, >t_base[i]);
1879 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1880 struct sg_table *pages,
1882 enum i915_cache_level cache_level, u32 unused)
1884 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1885 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1887 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1891 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1896 unsigned first_entry = start >> PAGE_SHIFT;
1897 unsigned num_entries = length >> PAGE_SHIFT;
1898 intel_gtt_clear_range(first_entry, num_entries);
1901 static void ggtt_bind_vma(struct i915_vma *vma,
1902 enum i915_cache_level cache_level,
1905 struct drm_device *dev = vma->vm->dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct drm_i915_gem_object *obj = vma->obj;
1908 struct sg_table *pages = obj->pages;
1911 /* Currently applicable only to VLV */
1913 pte_flags |= PTE_READ_ONLY;
1915 if (i915_is_ggtt(vma->vm))
1916 pages = vma->ggtt_view.pages;
1918 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1919 vma->vm->insert_entries(vma->vm, pages,
1921 cache_level, pte_flags);
1923 vma->bound |= GLOBAL_BIND;
1926 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1927 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1928 appgtt->base.insert_entries(&appgtt->base, pages,
1930 cache_level, pte_flags);
1934 static void ggtt_unbind_vma(struct i915_vma *vma)
1936 struct drm_device *dev = vma->vm->dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 struct drm_i915_gem_object *obj = vma->obj;
1940 if (vma->bound & GLOBAL_BIND) {
1941 vma->vm->clear_range(vma->vm,
1947 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1948 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1949 appgtt->base.clear_range(&appgtt->base,
1956 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1958 struct drm_device *dev = obj->base.dev;
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1962 interruptible = do_idling(dev_priv);
1964 if (!obj->has_dma_mapping)
1965 dma_unmap_sg(&dev->pdev->dev,
1966 obj->pages->sgl, obj->pages->nents,
1967 PCI_DMA_BIDIRECTIONAL);
1969 undo_idling(dev_priv, interruptible);
1972 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1973 unsigned long color,
1977 if (node->color != color)
1980 if (!list_empty(&node->node_list)) {
1981 node = list_entry(node->node_list.next,
1984 if (node->allocated && node->color != color)
1989 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1990 unsigned long start,
1991 unsigned long mappable_end,
1994 /* Let GEM Manage all of the aperture.
1996 * However, leave one page at the end still bound to the scratch page.
1997 * There are a number of places where the hardware apparently prefetches
1998 * past the end of the object, and we've seen multiple hangs with the
1999 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2000 * aperture. One page should be enough to keep any prefetching inside
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2005 struct drm_mm_node *entry;
2006 struct drm_i915_gem_object *obj;
2007 unsigned long hole_start, hole_end;
2010 BUG_ON(mappable_end > end);
2012 /* Subtract the guard page ... */
2013 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2015 dev_priv->gtt.base.start = start;
2016 dev_priv->gtt.base.total = end - start;
2018 if (intel_vgpu_active(dev)) {
2019 ret = intel_vgt_balloon(dev);
2025 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2027 /* Mark any preallocated objects as occupied */
2028 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2029 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2031 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2032 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2034 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2035 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2037 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2040 vma->bound |= GLOBAL_BIND;
2043 /* Clear any non-preallocated blocks */
2044 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2045 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2046 hole_start, hole_end);
2047 ggtt_vm->clear_range(ggtt_vm, hole_start,
2048 hole_end - hole_start, true);
2051 /* And finally clear the reserved guard page */
2052 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2054 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2055 struct i915_hw_ppgtt *ppgtt;
2057 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2061 ret = __hw_ppgtt_init(dev, ppgtt);
2063 ppgtt->base.cleanup(&ppgtt->base);
2068 if (ppgtt->base.allocate_va_range)
2069 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2072 ppgtt->base.cleanup(&ppgtt->base);
2077 ppgtt->base.clear_range(&ppgtt->base,
2082 dev_priv->mm.aliasing_ppgtt = ppgtt;
2088 void i915_gem_init_global_gtt(struct drm_device *dev)
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091 unsigned long gtt_size, mappable_size;
2093 gtt_size = dev_priv->gtt.base.total;
2094 mappable_size = dev_priv->gtt.mappable_end;
2096 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2099 void i915_global_gtt_cleanup(struct drm_device *dev)
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct i915_address_space *vm = &dev_priv->gtt.base;
2104 if (dev_priv->mm.aliasing_ppgtt) {
2105 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2107 ppgtt->base.cleanup(&ppgtt->base);
2110 if (drm_mm_initialized(&vm->mm)) {
2111 if (intel_vgpu_active(dev))
2112 intel_vgt_deballoon();
2114 drm_mm_takedown(&vm->mm);
2115 list_del(&vm->global_link);
2121 static int setup_scratch_page(struct drm_device *dev)
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2125 dma_addr_t dma_addr;
2127 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2130 set_pages_uc(page, 1);
2132 #ifdef CONFIG_INTEL_IOMMU
2133 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2134 PCI_DMA_BIDIRECTIONAL);
2135 if (pci_dma_mapping_error(dev->pdev, dma_addr))
2138 dma_addr = page_to_phys(page);
2140 dev_priv->gtt.base.scratch.page = page;
2141 dev_priv->gtt.base.scratch.addr = dma_addr;
2146 static void teardown_scratch_page(struct drm_device *dev)
2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 struct page *page = dev_priv->gtt.base.scratch.page;
2151 set_pages_wb(page, 1);
2152 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
2153 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
2157 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2159 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2160 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2161 return snb_gmch_ctl << 20;
2164 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2166 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2167 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2169 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2171 #ifdef CONFIG_X86_32
2172 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2173 if (bdw_gmch_ctl > 4)
2177 return bdw_gmch_ctl << 20;
2180 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2182 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2183 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2186 return 1 << (20 + gmch_ctrl);
2191 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2193 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2194 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2195 return snb_gmch_ctl << 25; /* 32 MB units */
2198 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2200 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2201 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2202 return bdw_gmch_ctl << 25; /* 32 MB units */
2205 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2207 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2208 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2211 * 0x0 to 0x10: 32MB increments starting at 0MB
2212 * 0x11 to 0x16: 4MB increments starting at 8MB
2213 * 0x17 to 0x1d: 4MB increments start at 36MB
2215 if (gmch_ctrl < 0x11)
2216 return gmch_ctrl << 25;
2217 else if (gmch_ctrl < 0x17)
2218 return (gmch_ctrl - 0x11 + 2) << 22;
2220 return (gmch_ctrl - 0x17 + 9) << 22;
2223 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2225 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2226 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2228 if (gen9_gmch_ctl < 0xf0)
2229 return gen9_gmch_ctl << 25; /* 32 MB units */
2231 /* 4MB increments starting at 0xf0 for 4MB */
2232 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2235 static int ggtt_probe_common(struct drm_device *dev,
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 phys_addr_t gtt_phys_addr;
2242 /* For Modern GENs the PTEs and register space are split in the BAR */
2243 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2244 (pci_resource_len(dev->pdev, 0) / 2);
2247 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2248 * dropped. For WC mappings in general we have 64 byte burst writes
2249 * when the WC buffer is flushed, so we can't use it, but have to
2250 * resort to an uncached mapping. The WC issue is easily caught by the
2251 * readback check when writing GTT PTE entries.
2253 if (IS_BROXTON(dev))
2254 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2256 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2257 if (!dev_priv->gtt.gsm) {
2258 DRM_ERROR("Failed to map the gtt page table\n");
2262 ret = setup_scratch_page(dev);
2264 DRM_ERROR("Scratch setup failed\n");
2265 /* iounmap will also get called at remove, but meh */
2266 iounmap(dev_priv->gtt.gsm);
2272 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2273 * bits. When using advanced contexts each context stores its own PAT, but
2274 * writing this data shouldn't be harmful even in those cases. */
2275 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2279 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2280 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2281 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2282 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2283 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2284 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2285 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2286 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2288 if (!USES_PPGTT(dev_priv->dev))
2289 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2290 * so RTL will always use the value corresponding to
2292 * So let's disable cache for GGTT to avoid screen corruptions.
2293 * MOCS still can be used though.
2294 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2295 * before this patch, i.e. the same uncached + snooping access
2296 * like on gen6/7 seems to be in effect.
2297 * - So this just fixes blitter/render access. Again it looks
2298 * like it's not just uncached access, but uncached + snooping.
2299 * So we can still hold onto all our assumptions wrt cpu
2300 * clflushing on LLC machines.
2302 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2304 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2305 * write would work. */
2306 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2307 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2310 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2315 * Map WB on BDW to snooped on CHV.
2317 * Only the snoop bit has meaning for CHV, the rest is
2320 * The hardware will never snoop for certain types of accesses:
2321 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2322 * - PPGTT page tables
2323 * - some other special cycles
2325 * As with BDW, we also need to consider the following for GT accesses:
2326 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2327 * so RTL will always use the value corresponding to
2329 * Which means we must set the snoop bit in PAT entry 0
2330 * in order to keep the global status page working.
2332 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2336 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2337 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2338 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2339 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2341 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2342 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2345 static int gen8_gmch_probe(struct drm_device *dev,
2348 phys_addr_t *mappable_base,
2349 unsigned long *mappable_end)
2351 struct drm_i915_private *dev_priv = dev->dev_private;
2352 unsigned int gtt_size;
2356 /* TODO: We're not aware of mappable constraints on gen8 yet */
2357 *mappable_base = pci_resource_start(dev->pdev, 2);
2358 *mappable_end = pci_resource_len(dev->pdev, 2);
2360 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2361 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2363 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2365 if (INTEL_INFO(dev)->gen >= 9) {
2366 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2367 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2368 } else if (IS_CHERRYVIEW(dev)) {
2369 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2370 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2372 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2373 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2376 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2378 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2379 chv_setup_private_ppat(dev_priv);
2381 bdw_setup_private_ppat(dev_priv);
2383 ret = ggtt_probe_common(dev, gtt_size);
2385 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2386 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2387 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2388 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2393 static int gen6_gmch_probe(struct drm_device *dev,
2396 phys_addr_t *mappable_base,
2397 unsigned long *mappable_end)
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 unsigned int gtt_size;
2404 *mappable_base = pci_resource_start(dev->pdev, 2);
2405 *mappable_end = pci_resource_len(dev->pdev, 2);
2407 /* 64/512MB is the current min/max we actually know of, but this is just
2408 * a coarse sanity check.
2410 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2411 DRM_ERROR("Unknown GMADR size (%lx)\n",
2412 dev_priv->gtt.mappable_end);
2416 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2417 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2418 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2420 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2422 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2423 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2425 ret = ggtt_probe_common(dev, gtt_size);
2427 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2428 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2429 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2430 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2435 static void gen6_gmch_remove(struct i915_address_space *vm)
2438 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2441 teardown_scratch_page(vm->dev);
2444 static int i915_gmch_probe(struct drm_device *dev,
2447 phys_addr_t *mappable_base,
2448 unsigned long *mappable_end)
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2453 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2455 DRM_ERROR("failed to set up gmch\n");
2459 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2461 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2462 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2463 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2464 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2465 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2467 if (unlikely(dev_priv->gtt.do_idle_maps))
2468 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2473 static void i915_gmch_remove(struct i915_address_space *vm)
2475 intel_gmch_remove();
2478 int i915_gem_gtt_init(struct drm_device *dev)
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct i915_gtt *gtt = &dev_priv->gtt;
2484 if (INTEL_INFO(dev)->gen <= 5) {
2485 gtt->gtt_probe = i915_gmch_probe;
2486 gtt->base.cleanup = i915_gmch_remove;
2487 } else if (INTEL_INFO(dev)->gen < 8) {
2488 gtt->gtt_probe = gen6_gmch_probe;
2489 gtt->base.cleanup = gen6_gmch_remove;
2490 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2491 gtt->base.pte_encode = iris_pte_encode;
2492 else if (IS_HASWELL(dev))
2493 gtt->base.pte_encode = hsw_pte_encode;
2494 else if (IS_VALLEYVIEW(dev))
2495 gtt->base.pte_encode = byt_pte_encode;
2496 else if (INTEL_INFO(dev)->gen >= 7)
2497 gtt->base.pte_encode = ivb_pte_encode;
2499 gtt->base.pte_encode = snb_pte_encode;
2501 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2502 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2505 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
2506 >t->mappable_base, >t->mappable_end);
2510 gtt->base.dev = dev;
2512 /* GMADR is the PCI mmio aperture into the global GTT. */
2513 DRM_INFO("Memory usable by graphics device = %zdM\n",
2514 gtt->base.total >> 20);
2515 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2516 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2517 #ifdef CONFIG_INTEL_IOMMU
2518 if (intel_iommu_gfx_mapped)
2519 DRM_INFO("VT-d active for gfx access\n");
2522 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2523 * user's requested state against the hardware/driver capabilities. We
2524 * do this now so that we can print out any log messages once rather
2525 * than every time we check intel_enable_ppgtt().
2527 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2528 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2533 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2535 struct drm_i915_private *dev_priv = dev->dev_private;
2536 struct drm_i915_gem_object *obj;
2537 struct i915_address_space *vm;
2539 i915_check_and_clear_faults(dev);
2541 /* First fill our portion of the GTT with scratch pages */
2542 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2543 dev_priv->gtt.base.start,
2544 dev_priv->gtt.base.total,
2547 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2548 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2549 &dev_priv->gtt.base);
2553 i915_gem_clflush_object(obj, obj->pin_display);
2554 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2558 if (INTEL_INFO(dev)->gen >= 8) {
2559 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2560 chv_setup_private_ppat(dev_priv);
2562 bdw_setup_private_ppat(dev_priv);
2567 if (USES_PPGTT(dev)) {
2568 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2569 /* TODO: Perhaps it shouldn't be gen6 specific */
2571 struct i915_hw_ppgtt *ppgtt =
2572 container_of(vm, struct i915_hw_ppgtt,
2575 if (i915_is_ggtt(vm))
2576 ppgtt = dev_priv->mm.aliasing_ppgtt;
2578 gen6_write_page_range(dev_priv, &ppgtt->pd,
2579 0, ppgtt->base.total);
2583 i915_ggtt_flush(dev_priv);
2586 static struct i915_vma *
2587 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2588 struct i915_address_space *vm,
2589 const struct i915_ggtt_view *ggtt_view)
2591 struct i915_vma *vma;
2593 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2594 return ERR_PTR(-EINVAL);
2596 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2598 return ERR_PTR(-ENOMEM);
2600 INIT_LIST_HEAD(&vma->vma_link);
2601 INIT_LIST_HEAD(&vma->mm_list);
2602 INIT_LIST_HEAD(&vma->exec_list);
2606 if (i915_is_ggtt(vm))
2607 vma->ggtt_view = *ggtt_view;
2609 list_add_tail(&vma->vma_link, &obj->vma_list);
2610 if (!i915_is_ggtt(vm))
2611 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2617 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2618 struct i915_address_space *vm)
2620 struct i915_vma *vma;
2622 vma = i915_gem_obj_to_vma(obj, vm);
2624 vma = __i915_gem_vma_create(obj, vm,
2625 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2631 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2632 const struct i915_ggtt_view *view)
2634 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2635 struct i915_vma *vma;
2638 return ERR_PTR(-EINVAL);
2640 vma = i915_gem_obj_to_ggtt_view(obj, view);
2646 vma = __i915_gem_vma_create(obj, ggtt, view);
2653 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2654 struct sg_table *st)
2656 unsigned int column, row;
2657 unsigned int src_idx;
2658 struct scatterlist *sg = st->sgl;
2662 for (column = 0; column < width; column++) {
2663 src_idx = width * (height - 1) + column;
2664 for (row = 0; row < height; row++) {
2666 /* We don't need the pages, but need to initialize
2667 * the entries so the sg list can be happily traversed.
2668 * The only thing we need are DMA addresses.
2670 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2671 sg_dma_address(sg) = in[src_idx];
2672 sg_dma_len(sg) = PAGE_SIZE;
2679 static struct sg_table *
2680 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2681 struct drm_i915_gem_object *obj)
2683 struct drm_device *dev = obj->base.dev;
2684 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2685 unsigned long size, pages, rot_pages;
2686 struct sg_page_iter sg_iter;
2688 dma_addr_t *page_addr_list;
2689 struct sg_table *st;
2690 unsigned int tile_pitch, tile_height;
2691 unsigned int width_pages, height_pages;
2694 pages = obj->base.size / PAGE_SIZE;
2696 /* Calculate tiling geometry. */
2697 tile_height = intel_tile_height(dev, rot_info->pixel_format,
2698 rot_info->fb_modifier);
2699 tile_pitch = PAGE_SIZE / tile_height;
2700 width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch);
2701 height_pages = DIV_ROUND_UP(rot_info->height, tile_height);
2702 rot_pages = width_pages * height_pages;
2703 size = rot_pages * PAGE_SIZE;
2705 /* Allocate a temporary list of source pages for random access. */
2706 page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
2707 if (!page_addr_list)
2708 return ERR_PTR(ret);
2710 /* Allocate target SG list. */
2711 st = kmalloc(sizeof(*st), GFP_KERNEL);
2715 ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
2719 /* Populate source page list from the object. */
2721 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2722 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2726 /* Rotate the pages. */
2727 rotate_pages(page_addr_list, width_pages, height_pages, st);
2730 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2731 size, rot_info->pitch, rot_info->height,
2732 rot_info->pixel_format, width_pages, height_pages,
2735 drm_free_large(page_addr_list);
2742 drm_free_large(page_addr_list);
2745 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2746 size, ret, rot_info->pitch, rot_info->height,
2747 rot_info->pixel_format, width_pages, height_pages,
2749 return ERR_PTR(ret);
2753 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2757 if (vma->ggtt_view.pages)
2760 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2761 vma->ggtt_view.pages = vma->obj->pages;
2762 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2763 vma->ggtt_view.pages =
2764 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2766 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2767 vma->ggtt_view.type);
2769 if (!vma->ggtt_view.pages) {
2770 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2771 vma->ggtt_view.type);
2773 } else if (IS_ERR(vma->ggtt_view.pages)) {
2774 ret = PTR_ERR(vma->ggtt_view.pages);
2775 vma->ggtt_view.pages = NULL;
2776 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2777 vma->ggtt_view.type, ret);
2784 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2786 * @cache_level: mapping cache level
2787 * @flags: flags like global or local mapping
2789 * DMA addresses are taken from the scatter-gather table of this object (or of
2790 * this VMA in case of non-default GGTT views) and PTE entries set up.
2791 * Note that DMA addresses are also the only part of the SG table we care about.
2793 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2799 if (vma->vm->allocate_va_range) {
2800 trace_i915_va_alloc(vma->vm, vma->node.start,
2802 VM_TO_TRACE_NAME(vma->vm));
2804 ret = vma->vm->allocate_va_range(vma->vm,
2811 if (i915_is_ggtt(vma->vm)) {
2812 ret = i915_get_ggtt_vma_pages(vma);
2817 if (flags & PIN_GLOBAL)
2818 bind_flags |= GLOBAL_BIND;
2819 if (flags & PIN_USER)
2820 bind_flags |= LOCAL_BIND;
2822 if (flags & PIN_UPDATE)
2823 bind_flags |= vma->bound;
2825 bind_flags &= ~vma->bound;
2828 vma->vm->bind_vma(vma, cache_level, bind_flags);
2830 vma->bound |= bind_flags;