2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
98 const struct i915_ggtt_view i915_ggtt_view_normal;
99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
105 bool has_aliasing_ppgtt;
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
122 if (enable_ppgtt == 1)
125 if (enable_ppgtt == 2 && has_full_ppgtt)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
146 return has_aliasing_ppgtt ? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
155 /* Currently applicable only to VLV */
157 pte_flags |= PTE_READ_ONLY;
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
165 static void ppgtt_unbind_vma(struct i915_vma *vma)
167 vma->vm->clear_range(vma->vm,
173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
181 case I915_CACHE_NONE:
182 pte |= PPAT_UNCACHED_INDEX;
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
188 pte |= PPAT_CACHED_INDEX;
195 static gen8_pde_t gen8_pde_encode(struct drm_device *dev,
197 enum i915_cache_level level)
199 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
201 if (level != I915_CACHE_NONE)
202 pde |= PPAT_CACHED_PDE_INDEX;
204 pde |= PPAT_UNCACHED_INDEX;
208 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
209 enum i915_cache_level level,
210 bool valid, u32 unused)
212 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
213 pte |= GEN6_PTE_ADDR_ENCODE(addr);
216 case I915_CACHE_L3_LLC:
218 pte |= GEN6_PTE_CACHE_LLC;
220 case I915_CACHE_NONE:
221 pte |= GEN6_PTE_UNCACHED;
230 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
231 enum i915_cache_level level,
232 bool valid, u32 unused)
234 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
235 pte |= GEN6_PTE_ADDR_ENCODE(addr);
238 case I915_CACHE_L3_LLC:
239 pte |= GEN7_PTE_CACHE_L3_LLC;
242 pte |= GEN6_PTE_CACHE_LLC;
244 case I915_CACHE_NONE:
245 pte |= GEN6_PTE_UNCACHED;
254 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
255 enum i915_cache_level level,
256 bool valid, u32 flags)
258 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
259 pte |= GEN6_PTE_ADDR_ENCODE(addr);
261 if (!(flags & PTE_READ_ONLY))
262 pte |= BYT_PTE_WRITEABLE;
264 if (level != I915_CACHE_NONE)
265 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
270 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
271 enum i915_cache_level level,
272 bool valid, u32 unused)
274 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
275 pte |= HSW_PTE_ADDR_ENCODE(addr);
277 if (level != I915_CACHE_NONE)
278 pte |= HSW_WB_LLC_AGE3;
283 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
284 enum i915_cache_level level,
285 bool valid, u32 unused)
287 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
288 pte |= HSW_PTE_ADDR_ENCODE(addr);
291 case I915_CACHE_NONE:
294 pte |= HSW_WT_ELLC_LLC_AGE3;
297 pte |= HSW_WB_ELLC_LLC_AGE3;
304 #define i915_dma_unmap_single(px, dev) \
305 __i915_dma_unmap_single((px)->daddr, dev)
307 static void __i915_dma_unmap_single(dma_addr_t daddr,
308 struct drm_device *dev)
310 struct device *device = &dev->pdev->dev;
312 dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
316 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
317 * @px: Page table/dir/etc to get a DMA map for
320 * Page table allocations are unified across all gens. They always require a
321 * single 4k allocation, as well as a DMA mapping. If we keep the structs
322 * symmetric here, the simple macro covers us for every page table type.
324 * Return: 0 if success.
326 #define i915_dma_map_single(px, dev) \
327 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
329 static int i915_dma_map_page_single(struct page *page,
330 struct drm_device *dev,
333 struct device *device = &dev->pdev->dev;
335 *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
336 if (dma_mapping_error(device, *daddr))
342 static void unmap_and_free_pt(struct i915_page_table *pt,
343 struct drm_device *dev)
345 if (WARN_ON(!pt->page))
348 i915_dma_unmap_single(pt, dev);
349 __free_page(pt->page);
350 kfree(pt->used_ptes);
354 static void gen8_initialize_pt(struct i915_address_space *vm,
355 struct i915_page_table *pt)
357 gen8_pte_t *pt_vaddr, scratch_pte;
360 pt_vaddr = kmap_atomic(pt->page);
361 scratch_pte = gen8_pte_encode(vm->scratch.addr,
362 I915_CACHE_LLC, true);
364 for (i = 0; i < GEN8_PTES; i++)
365 pt_vaddr[i] = scratch_pte;
367 if (!HAS_LLC(vm->dev))
368 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
369 kunmap_atomic(pt_vaddr);
372 static struct i915_page_table *alloc_pt(struct drm_device *dev)
374 struct i915_page_table *pt;
375 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
376 GEN8_PTES : GEN6_PTES;
379 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
381 return ERR_PTR(-ENOMEM);
383 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
389 pt->page = alloc_page(GFP_KERNEL);
393 ret = i915_dma_map_single(pt, dev);
400 __free_page(pt->page);
402 kfree(pt->used_ptes);
409 static void unmap_and_free_pd(struct i915_page_directory *pd,
410 struct drm_device *dev)
413 i915_dma_unmap_single(pd, dev);
414 __free_page(pd->page);
415 kfree(pd->used_pdes);
420 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
422 struct i915_page_directory *pd;
425 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
427 return ERR_PTR(-ENOMEM);
429 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
430 sizeof(*pd->used_pdes), GFP_KERNEL);
434 pd->page = alloc_page(GFP_KERNEL);
438 ret = i915_dma_map_single(pd, dev);
445 __free_page(pd->page);
447 kfree(pd->used_pdes);
454 /* Broadwell Page Directory Pointer Descriptors */
455 static int gen8_write_pdp(struct drm_i915_gem_request *req,
459 struct intel_engine_cs *ring = req->ring;
464 ret = intel_ring_begin(ring, 6);
468 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
469 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
470 intel_ring_emit(ring, upper_32_bits(addr));
471 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
472 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
473 intel_ring_emit(ring, lower_32_bits(addr));
474 intel_ring_advance(ring);
479 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
480 struct drm_i915_gem_request *req)
484 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
485 struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
486 dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr;
487 /* The page directory might be NULL, but we need to clear out
488 * whatever the previous context might have used. */
489 ret = gen8_write_pdp(req, i, pd_daddr);
497 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
502 struct i915_hw_ppgtt *ppgtt =
503 container_of(vm, struct i915_hw_ppgtt, base);
504 gen8_pte_t *pt_vaddr, scratch_pte;
505 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
506 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
507 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
508 unsigned num_entries = length >> PAGE_SHIFT;
509 unsigned last_pte, i;
511 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
512 I915_CACHE_LLC, use_scratch);
514 while (num_entries) {
515 struct i915_page_directory *pd;
516 struct i915_page_table *pt;
517 struct page *page_table;
519 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
522 pd = ppgtt->pdp.page_directory[pdpe];
524 if (WARN_ON(!pd->page_table[pde]))
527 pt = pd->page_table[pde];
529 if (WARN_ON(!pt->page))
532 page_table = pt->page;
534 last_pte = pte + num_entries;
535 if (last_pte > GEN8_PTES)
536 last_pte = GEN8_PTES;
538 pt_vaddr = kmap_atomic(page_table);
540 for (i = pte; i < last_pte; i++) {
541 pt_vaddr[i] = scratch_pte;
545 if (!HAS_LLC(ppgtt->base.dev))
546 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
547 kunmap_atomic(pt_vaddr);
550 if (++pde == I915_PDES) {
557 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
558 struct sg_table *pages,
560 enum i915_cache_level cache_level, u32 unused)
562 struct i915_hw_ppgtt *ppgtt =
563 container_of(vm, struct i915_hw_ppgtt, base);
564 gen8_pte_t *pt_vaddr;
565 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
566 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
567 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
568 struct sg_page_iter sg_iter;
572 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
573 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
576 if (pt_vaddr == NULL) {
577 struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
578 struct i915_page_table *pt = pd->page_table[pde];
579 struct page *page_table = pt->page;
581 pt_vaddr = kmap_atomic(page_table);
585 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
587 if (++pte == GEN8_PTES) {
588 if (!HAS_LLC(ppgtt->base.dev))
589 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
590 kunmap_atomic(pt_vaddr);
592 if (++pde == I915_PDES) {
600 if (!HAS_LLC(ppgtt->base.dev))
601 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
602 kunmap_atomic(pt_vaddr);
606 static void __gen8_do_map_pt(gen8_pde_t * const pde,
607 struct i915_page_table *pt,
608 struct drm_device *dev)
611 gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC);
615 static void gen8_initialize_pd(struct i915_address_space *vm,
616 struct i915_page_directory *pd)
618 struct i915_hw_ppgtt *ppgtt =
619 container_of(vm, struct i915_hw_ppgtt, base);
620 gen8_pde_t *page_directory;
621 struct i915_page_table *pt;
624 page_directory = kmap_atomic(pd->page);
625 pt = ppgtt->scratch_pt;
626 for (i = 0; i < I915_PDES; i++)
627 /* Map the PDE to the page table */
628 __gen8_do_map_pt(page_directory + i, pt, vm->dev);
630 if (!HAS_LLC(vm->dev))
631 drm_clflush_virt_range(page_directory, PAGE_SIZE);
632 kunmap_atomic(page_directory);
635 static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
642 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
643 if (WARN_ON(!pd->page_table[i]))
646 unmap_and_free_pt(pd->page_table[i], dev);
647 pd->page_table[i] = NULL;
651 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
653 struct i915_hw_ppgtt *ppgtt =
654 container_of(vm, struct i915_hw_ppgtt, base);
657 for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
658 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
661 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
662 unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
665 unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev);
666 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
670 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
671 * @ppgtt: Master ppgtt structure.
672 * @pd: Page directory for this address range.
673 * @start: Starting virtual address to begin allocations.
674 * @length Size of the allocations.
675 * @new_pts: Bitmap set by function with new allocations. Likely used by the
676 * caller to free on error.
678 * Allocate the required number of page tables. Extremely similar to
679 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
680 * the page directory boundary (instead of the page directory pointer). That
681 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
682 * possible, and likely that the caller will need to use multiple calls of this
683 * function to achieve the appropriate allocation.
685 * Return: 0 if success; negative error code otherwise.
687 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
688 struct i915_page_directory *pd,
691 unsigned long *new_pts)
693 struct drm_device *dev = ppgtt->base.dev;
694 struct i915_page_table *pt;
698 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
699 /* Don't reallocate page tables */
701 /* Scratch is never allocated this way */
702 WARN_ON(pt == ppgtt->scratch_pt);
710 gen8_initialize_pt(&ppgtt->base, pt);
711 pd->page_table[pde] = pt;
712 set_bit(pde, new_pts);
718 for_each_set_bit(pde, new_pts, I915_PDES)
719 unmap_and_free_pt(pd->page_table[pde], dev);
725 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
726 * @ppgtt: Master ppgtt structure.
727 * @pdp: Page directory pointer for this address range.
728 * @start: Starting virtual address to begin allocations.
729 * @length Size of the allocations.
730 * @new_pds Bitmap set by function with new allocations. Likely used by the
731 * caller to free on error.
733 * Allocate the required number of page directories starting at the pde index of
734 * @start, and ending at the pde index @start + @length. This function will skip
735 * over already allocated page directories within the range, and only allocate
736 * new ones, setting the appropriate pointer within the pdp as well as the
737 * correct position in the bitmap @new_pds.
739 * The function will only allocate the pages within the range for a give page
740 * directory pointer. In other words, if @start + @length straddles a virtually
741 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
742 * required by the caller, This is not currently possible, and the BUG in the
743 * code will prevent it.
745 * Return: 0 if success; negative error code otherwise.
747 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
748 struct i915_page_directory_pointer *pdp,
751 unsigned long *new_pds)
753 struct drm_device *dev = ppgtt->base.dev;
754 struct i915_page_directory *pd;
758 WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
760 /* FIXME: upper bound must not overflow 32 bits */
761 WARN_ON((start + length) > (1ULL << 32));
763 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
771 gen8_initialize_pd(&ppgtt->base, pd);
772 pdp->page_directory[pdpe] = pd;
773 set_bit(pdpe, new_pds);
779 for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
780 unmap_and_free_pd(pdp->page_directory[pdpe], dev);
786 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
790 for (i = 0; i < GEN8_LEGACY_PDPES; i++)
796 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
797 * of these are based on the number of PDPEs in the system.
800 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
801 unsigned long ***new_pts)
807 pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
811 pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
817 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
818 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
819 sizeof(unsigned long), GFP_KERNEL);
830 free_gen8_temp_bitmaps(pds, pts);
834 static int gen8_alloc_va_range(struct i915_address_space *vm,
838 struct i915_hw_ppgtt *ppgtt =
839 container_of(vm, struct i915_hw_ppgtt, base);
840 unsigned long *new_page_dirs, **new_page_tables;
841 struct i915_page_directory *pd;
842 const uint64_t orig_start = start;
843 const uint64_t orig_length = length;
848 /* Wrap is never okay since we can only represent 48b, and we don't
849 * actually use the other side of the canonical address space.
851 if (WARN_ON(start + length < start))
854 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
858 /* Do the allocations first so we can easily bail out */
859 ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
862 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
866 /* For every page directory referenced, allocate page tables */
867 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
868 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
869 new_page_tables[pdpe]);
875 length = orig_length;
877 /* Allocations have completed successfully, so set the bitmaps, and do
879 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
880 gen8_pde_t *const page_directory = kmap_atomic(pd->page);
881 struct i915_page_table *pt;
882 uint64_t pd_len = gen8_clamp_pd(start, length);
883 uint64_t pd_start = start;
886 /* Every pd should be allocated, we just did that above. */
889 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
890 /* Same reasoning as pd */
893 WARN_ON(!gen8_pte_count(pd_start, pd_len));
895 /* Set our used ptes within the page table */
896 bitmap_set(pt->used_ptes,
897 gen8_pte_index(pd_start),
898 gen8_pte_count(pd_start, pd_len));
900 /* Our pde is now pointing to the pagetable, pt */
901 set_bit(pde, pd->used_pdes);
903 /* Map the PDE to the page table */
904 __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
906 /* NB: We haven't yet mapped ptes to pages. At this
907 * point we're still relying on insert_entries() */
910 if (!HAS_LLC(vm->dev))
911 drm_clflush_virt_range(page_directory, PAGE_SIZE);
913 kunmap_atomic(page_directory);
915 set_bit(pdpe, ppgtt->pdp.used_pdpes);
918 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
923 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
924 unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev);
927 for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
928 unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev);
930 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
935 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
936 * with a net effect resembling a 2-level page table in normal x86 terms. Each
937 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
941 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
943 ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev);
944 if (IS_ERR(ppgtt->scratch_pt))
945 return PTR_ERR(ppgtt->scratch_pt);
947 ppgtt->scratch_pd = alloc_pd(ppgtt->base.dev);
948 if (IS_ERR(ppgtt->scratch_pd))
949 return PTR_ERR(ppgtt->scratch_pd);
951 gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
952 gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
954 ppgtt->base.start = 0;
955 ppgtt->base.total = 1ULL << 32;
956 if (IS_ENABLED(CONFIG_X86_32))
957 /* While we have a proliferation of size_t variables
958 * we cannot represent the full ppgtt size on 32bit,
959 * so limit it to the same size as the GGTT (currently
962 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
963 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
964 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
965 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
966 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
967 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
968 ppgtt->base.bind_vma = ppgtt_bind_vma;
970 ppgtt->switch_mm = gen8_mm_switch;
975 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
977 struct i915_address_space *vm = &ppgtt->base;
978 struct i915_page_table *unused;
979 gen6_pte_t scratch_pte;
981 uint32_t pte, pde, temp;
982 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
984 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
986 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
988 gen6_pte_t *pt_vaddr;
989 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
990 pd_entry = readl(ppgtt->pd_addr + pde);
991 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
993 if (pd_entry != expected)
994 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
998 seq_printf(m, "\tPDE: %x\n", pd_entry);
1000 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
1001 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1003 (pde * PAGE_SIZE * GEN6_PTES) +
1007 for (i = 0; i < 4; i++)
1008 if (pt_vaddr[pte + i] != scratch_pte)
1013 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1014 for (i = 0; i < 4; i++) {
1015 if (pt_vaddr[pte + i] != scratch_pte)
1016 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1018 seq_puts(m, " SCRATCH ");
1022 kunmap_atomic(pt_vaddr);
1026 /* Write pde (index) from the page directory @pd to the page table @pt */
1027 static void gen6_write_pde(struct i915_page_directory *pd,
1028 const int pde, struct i915_page_table *pt)
1030 /* Caller needs to make sure the write completes if necessary */
1031 struct i915_hw_ppgtt *ppgtt =
1032 container_of(pd, struct i915_hw_ppgtt, pd);
1035 pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr);
1036 pd_entry |= GEN6_PDE_VALID;
1038 writel(pd_entry, ppgtt->pd_addr + pde);
1041 /* Write all the page tables found in the ppgtt structure to incrementing page
1043 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1044 struct i915_page_directory *pd,
1045 uint32_t start, uint32_t length)
1047 struct i915_page_table *pt;
1050 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1051 gen6_write_pde(pd, pde, pt);
1053 /* Make sure write is complete before other code can use this page
1054 * table. Also require for WC mapped PTEs */
1055 readl(dev_priv->gtt.gsm);
1058 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1060 BUG_ON(ppgtt->pd.pd_offset & 0x3f);
1062 return (ppgtt->pd.pd_offset / 64) << 16;
1065 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1066 struct drm_i915_gem_request *req)
1068 struct intel_engine_cs *ring = req->ring;
1071 /* NB: TLBs must be flushed and invalidated before a switch */
1072 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1076 ret = intel_ring_begin(ring, 6);
1080 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1081 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1082 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1083 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1084 intel_ring_emit(ring, get_pd_offset(ppgtt));
1085 intel_ring_emit(ring, MI_NOOP);
1086 intel_ring_advance(ring);
1091 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1092 struct drm_i915_gem_request *req)
1094 struct intel_engine_cs *ring = req->ring;
1095 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1097 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1098 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1102 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1103 struct drm_i915_gem_request *req)
1105 struct intel_engine_cs *ring = req->ring;
1108 /* NB: TLBs must be flushed and invalidated before a switch */
1109 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1113 ret = intel_ring_begin(ring, 6);
1117 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1118 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1119 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1120 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1121 intel_ring_emit(ring, get_pd_offset(ppgtt));
1122 intel_ring_emit(ring, MI_NOOP);
1123 intel_ring_advance(ring);
1125 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1126 if (ring->id != RCS) {
1127 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1135 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1136 struct drm_i915_gem_request *req)
1138 struct intel_engine_cs *ring = req->ring;
1139 struct drm_device *dev = ppgtt->base.dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1143 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1144 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1146 POSTING_READ(RING_PP_DIR_DCLV(ring));
1151 static void gen8_ppgtt_enable(struct drm_device *dev)
1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 struct intel_engine_cs *ring;
1157 for_each_ring(ring, dev_priv, j) {
1158 I915_WRITE(RING_MODE_GEN7(ring),
1159 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1163 static void gen7_ppgtt_enable(struct drm_device *dev)
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 struct intel_engine_cs *ring;
1167 uint32_t ecochk, ecobits;
1170 ecobits = I915_READ(GAC_ECO_BITS);
1171 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1173 ecochk = I915_READ(GAM_ECOCHK);
1174 if (IS_HASWELL(dev)) {
1175 ecochk |= ECOCHK_PPGTT_WB_HSW;
1177 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1178 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1180 I915_WRITE(GAM_ECOCHK, ecochk);
1182 for_each_ring(ring, dev_priv, i) {
1183 /* GFX_MODE is per-ring on gen7+ */
1184 I915_WRITE(RING_MODE_GEN7(ring),
1185 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1189 static void gen6_ppgtt_enable(struct drm_device *dev)
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 uint32_t ecochk, gab_ctl, ecobits;
1194 ecobits = I915_READ(GAC_ECO_BITS);
1195 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1196 ECOBITS_PPGTT_CACHE64B);
1198 gab_ctl = I915_READ(GAB_CTL);
1199 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1201 ecochk = I915_READ(GAM_ECOCHK);
1202 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1204 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1207 /* PPGTT support for Sandybdrige/Gen6 and later */
1208 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1213 struct i915_hw_ppgtt *ppgtt =
1214 container_of(vm, struct i915_hw_ppgtt, base);
1215 gen6_pte_t *pt_vaddr, scratch_pte;
1216 unsigned first_entry = start >> PAGE_SHIFT;
1217 unsigned num_entries = length >> PAGE_SHIFT;
1218 unsigned act_pt = first_entry / GEN6_PTES;
1219 unsigned first_pte = first_entry % GEN6_PTES;
1220 unsigned last_pte, i;
1222 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1224 while (num_entries) {
1225 last_pte = first_pte + num_entries;
1226 if (last_pte > GEN6_PTES)
1227 last_pte = GEN6_PTES;
1229 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1231 for (i = first_pte; i < last_pte; i++)
1232 pt_vaddr[i] = scratch_pte;
1234 kunmap_atomic(pt_vaddr);
1236 num_entries -= last_pte - first_pte;
1242 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1243 struct sg_table *pages,
1245 enum i915_cache_level cache_level, u32 flags)
1247 struct i915_hw_ppgtt *ppgtt =
1248 container_of(vm, struct i915_hw_ppgtt, base);
1249 gen6_pte_t *pt_vaddr;
1250 unsigned first_entry = start >> PAGE_SHIFT;
1251 unsigned act_pt = first_entry / GEN6_PTES;
1252 unsigned act_pte = first_entry % GEN6_PTES;
1253 struct sg_page_iter sg_iter;
1256 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1257 if (pt_vaddr == NULL)
1258 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1261 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1262 cache_level, true, flags);
1264 if (++act_pte == GEN6_PTES) {
1265 kunmap_atomic(pt_vaddr);
1272 kunmap_atomic(pt_vaddr);
1275 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1276 * are switching between contexts with the same LRCA, we also must do a force
1279 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1281 /* If current vm != vm, */
1282 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1285 static void gen6_initialize_pt(struct i915_address_space *vm,
1286 struct i915_page_table *pt)
1288 gen6_pte_t *pt_vaddr, scratch_pte;
1291 WARN_ON(vm->scratch.addr == 0);
1293 scratch_pte = vm->pte_encode(vm->scratch.addr,
1294 I915_CACHE_LLC, true, 0);
1296 pt_vaddr = kmap_atomic(pt->page);
1298 for (i = 0; i < GEN6_PTES; i++)
1299 pt_vaddr[i] = scratch_pte;
1301 kunmap_atomic(pt_vaddr);
1304 static int gen6_alloc_va_range(struct i915_address_space *vm,
1305 uint64_t start, uint64_t length)
1307 DECLARE_BITMAP(new_page_tables, I915_PDES);
1308 struct drm_device *dev = vm->dev;
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 struct i915_hw_ppgtt *ppgtt =
1311 container_of(vm, struct i915_hw_ppgtt, base);
1312 struct i915_page_table *pt;
1313 const uint32_t start_save = start, length_save = length;
1317 WARN_ON(upper_32_bits(start));
1319 bitmap_zero(new_page_tables, I915_PDES);
1321 /* The allocation is done in two stages so that we can bail out with
1322 * minimal amount of pain. The first stage finds new page tables that
1323 * need allocation. The second stage marks use ptes within the page
1326 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1327 if (pt != ppgtt->scratch_pt) {
1328 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1332 /* We've already allocated a page table */
1333 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1341 gen6_initialize_pt(vm, pt);
1343 ppgtt->pd.page_table[pde] = pt;
1344 set_bit(pde, new_page_tables);
1345 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1349 length = length_save;
1351 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1352 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1354 bitmap_zero(tmp_bitmap, GEN6_PTES);
1355 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1356 gen6_pte_count(start, length));
1358 if (test_and_clear_bit(pde, new_page_tables))
1359 gen6_write_pde(&ppgtt->pd, pde, pt);
1361 trace_i915_page_table_entry_map(vm, pde, pt,
1362 gen6_pte_index(start),
1363 gen6_pte_count(start, length),
1365 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1369 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1371 /* Make sure write is complete before other code can use this page
1372 * table. Also require for WC mapped PTEs */
1373 readl(dev_priv->gtt.gsm);
1375 mark_tlbs_dirty(ppgtt);
1379 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1380 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1382 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1383 unmap_and_free_pt(pt, vm->dev);
1386 mark_tlbs_dirty(ppgtt);
1390 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1392 struct i915_hw_ppgtt *ppgtt =
1393 container_of(vm, struct i915_hw_ppgtt, base);
1394 struct i915_page_table *pt;
1398 drm_mm_remove_node(&ppgtt->node);
1400 gen6_for_all_pdes(pt, ppgtt, pde) {
1401 if (pt != ppgtt->scratch_pt)
1402 unmap_and_free_pt(pt, ppgtt->base.dev);
1405 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1406 unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev);
1409 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1411 struct drm_device *dev = ppgtt->base.dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 bool retried = false;
1416 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1417 * allocator works in address space sizes, so it's multiplied by page
1418 * size. We allocate at the top of the GTT to avoid fragmentation.
1420 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1421 ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev);
1422 if (IS_ERR(ppgtt->scratch_pt))
1423 return PTR_ERR(ppgtt->scratch_pt);
1425 gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1428 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1429 &ppgtt->node, GEN6_PD_SIZE,
1431 0, dev_priv->gtt.base.total,
1433 if (ret == -ENOSPC && !retried) {
1434 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1435 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1437 0, dev_priv->gtt.base.total,
1450 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1451 DRM_DEBUG("Forced to use aperture for PDEs\n");
1456 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1460 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1462 return gen6_ppgtt_allocate_page_directories(ppgtt);
1465 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1466 uint64_t start, uint64_t length)
1468 struct i915_page_table *unused;
1471 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1472 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1475 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1477 struct drm_device *dev = ppgtt->base.dev;
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1481 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1483 ppgtt->switch_mm = gen6_mm_switch;
1484 } else if (IS_HASWELL(dev)) {
1485 ppgtt->switch_mm = hsw_mm_switch;
1486 } else if (IS_GEN7(dev)) {
1487 ppgtt->switch_mm = gen7_mm_switch;
1491 if (intel_vgpu_active(dev))
1492 ppgtt->switch_mm = vgpu_mm_switch;
1494 ret = gen6_ppgtt_alloc(ppgtt);
1498 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1499 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1500 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1501 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1502 ppgtt->base.bind_vma = ppgtt_bind_vma;
1503 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1504 ppgtt->base.start = 0;
1505 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1506 ppgtt->debug_dump = gen6_dump_ppgtt;
1508 ppgtt->pd.pd_offset =
1509 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1511 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1512 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
1514 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1516 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1518 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1519 ppgtt->node.size >> 20,
1520 ppgtt->node.start / PAGE_SIZE);
1522 DRM_DEBUG("Adding PPGTT at offset %x\n",
1523 ppgtt->pd.pd_offset << 10);
1528 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1532 ppgtt->base.dev = dev;
1533 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1535 if (INTEL_INFO(dev)->gen < 8)
1536 return gen6_ppgtt_init(ppgtt);
1538 return gen8_ppgtt_init(ppgtt);
1540 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1545 ret = __hw_ppgtt_init(dev, ppgtt);
1547 kref_init(&ppgtt->ref);
1548 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1550 i915_init_vm(dev_priv, &ppgtt->base);
1556 int i915_ppgtt_init_hw(struct drm_device *dev)
1558 /* In the case of execlists, PPGTT is enabled by the context descriptor
1559 * and the PDPs are contained within the context itself. We don't
1560 * need to do anything here. */
1561 if (i915.enable_execlists)
1564 if (!USES_PPGTT(dev))
1568 gen6_ppgtt_enable(dev);
1569 else if (IS_GEN7(dev))
1570 gen7_ppgtt_enable(dev);
1571 else if (INTEL_INFO(dev)->gen >= 8)
1572 gen8_ppgtt_enable(dev);
1574 MISSING_CASE(INTEL_INFO(dev)->gen);
1579 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
1581 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
1582 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1584 if (i915.enable_execlists)
1590 return ppgtt->switch_mm(ppgtt, req);
1593 struct i915_hw_ppgtt *
1594 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1596 struct i915_hw_ppgtt *ppgtt;
1599 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1601 return ERR_PTR(-ENOMEM);
1603 ret = i915_ppgtt_init(dev, ppgtt);
1606 return ERR_PTR(ret);
1609 ppgtt->file_priv = fpriv;
1611 trace_i915_ppgtt_create(&ppgtt->base);
1616 void i915_ppgtt_release(struct kref *kref)
1618 struct i915_hw_ppgtt *ppgtt =
1619 container_of(kref, struct i915_hw_ppgtt, ref);
1621 trace_i915_ppgtt_release(&ppgtt->base);
1623 /* vmas should already be unbound */
1624 WARN_ON(!list_empty(&ppgtt->base.active_list));
1625 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1627 list_del(&ppgtt->base.global_link);
1628 drm_mm_takedown(&ppgtt->base.mm);
1630 ppgtt->base.cleanup(&ppgtt->base);
1634 extern int intel_iommu_gfx_mapped;
1635 /* Certain Gen5 chipsets require require idling the GPU before
1636 * unmapping anything from the GTT when VT-d is enabled.
1638 static bool needs_idle_maps(struct drm_device *dev)
1640 #ifdef CONFIG_INTEL_IOMMU
1641 /* Query intel_iommu to see if we need the workaround. Presumably that
1644 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1650 static bool do_idling(struct drm_i915_private *dev_priv)
1652 bool ret = dev_priv->mm.interruptible;
1654 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1655 dev_priv->mm.interruptible = false;
1656 if (i915_gpu_idle(dev_priv->dev)) {
1657 DRM_ERROR("Couldn't idle GPU\n");
1658 /* Wait a bit, in hopes it avoids the hang */
1666 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1668 if (unlikely(dev_priv->gtt.do_idle_maps))
1669 dev_priv->mm.interruptible = interruptible;
1672 void i915_check_and_clear_faults(struct drm_device *dev)
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 struct intel_engine_cs *ring;
1678 if (INTEL_INFO(dev)->gen < 6)
1681 for_each_ring(ring, dev_priv, i) {
1683 fault_reg = I915_READ(RING_FAULT_REG(ring));
1684 if (fault_reg & RING_FAULT_VALID) {
1685 DRM_DEBUG_DRIVER("Unexpected fault\n"
1687 "\tAddress space: %s\n"
1690 fault_reg & PAGE_MASK,
1691 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1692 RING_FAULT_SRCID(fault_reg),
1693 RING_FAULT_FAULT_TYPE(fault_reg));
1694 I915_WRITE(RING_FAULT_REG(ring),
1695 fault_reg & ~RING_FAULT_VALID);
1698 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1701 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1703 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1704 intel_gtt_chipset_flush();
1706 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1707 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1711 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1715 /* Don't bother messing with faults pre GEN6 as we have little
1716 * documentation supporting that it's a good idea.
1718 if (INTEL_INFO(dev)->gen < 6)
1721 i915_check_and_clear_faults(dev);
1723 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1724 dev_priv->gtt.base.start,
1725 dev_priv->gtt.base.total,
1728 i915_ggtt_flush(dev_priv);
1731 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1733 if (obj->has_dma_mapping)
1736 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1737 obj->pages->sgl, obj->pages->nents,
1738 PCI_DMA_BIDIRECTIONAL))
1744 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1749 iowrite32((u32)pte, addr);
1750 iowrite32(pte >> 32, addr + 4);
1754 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1755 struct sg_table *st,
1757 enum i915_cache_level level, u32 unused)
1759 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1760 unsigned first_entry = start >> PAGE_SHIFT;
1761 gen8_pte_t __iomem *gtt_entries =
1762 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1764 struct sg_page_iter sg_iter;
1765 dma_addr_t addr = 0; /* shut up gcc */
1767 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1768 addr = sg_dma_address(sg_iter.sg) +
1769 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1770 gen8_set_pte(>t_entries[i],
1771 gen8_pte_encode(addr, level, true));
1776 * XXX: This serves as a posting read to make sure that the PTE has
1777 * actually been updated. There is some concern that even though
1778 * registers and PTEs are within the same BAR that they are potentially
1779 * of NUMA access patterns. Therefore, even with the way we assume
1780 * hardware should work, we must keep this posting read for paranoia.
1783 WARN_ON(readq(>t_entries[i-1])
1784 != gen8_pte_encode(addr, level, true));
1786 /* This next bit makes the above posting read even more important. We
1787 * want to flush the TLBs only after we're certain all the PTE updates
1790 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1791 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1795 * Binds an object into the global gtt with the specified cache level. The object
1796 * will be accessible to the GPU via commands whose operands reference offsets
1797 * within the global GTT as well as accessible by the GPU through the GMADR
1798 * mapped BAR (dev_priv->mm.gtt->gtt).
1800 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1801 struct sg_table *st,
1803 enum i915_cache_level level, u32 flags)
1805 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1806 unsigned first_entry = start >> PAGE_SHIFT;
1807 gen6_pte_t __iomem *gtt_entries =
1808 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1810 struct sg_page_iter sg_iter;
1811 dma_addr_t addr = 0;
1813 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1814 addr = sg_page_iter_dma_address(&sg_iter);
1815 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
1819 /* XXX: This serves as a posting read to make sure that the PTE has
1820 * actually been updated. There is some concern that even though
1821 * registers and PTEs are within the same BAR that they are potentially
1822 * of NUMA access patterns. Therefore, even with the way we assume
1823 * hardware should work, we must keep this posting read for paranoia.
1826 unsigned long gtt = readl(>t_entries[i-1]);
1827 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1830 /* This next bit makes the above posting read even more important. We
1831 * want to flush the TLBs only after we're certain all the PTE updates
1834 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1835 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1838 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1843 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1844 unsigned first_entry = start >> PAGE_SHIFT;
1845 unsigned num_entries = length >> PAGE_SHIFT;
1846 gen8_pte_t scratch_pte, __iomem *gtt_base =
1847 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1848 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1851 if (WARN(num_entries > max_entries,
1852 "First entry = %d; Num entries = %d (max=%d)\n",
1853 first_entry, num_entries, max_entries))
1854 num_entries = max_entries;
1856 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1859 for (i = 0; i < num_entries; i++)
1860 gen8_set_pte(>t_base[i], scratch_pte);
1864 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1869 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1870 unsigned first_entry = start >> PAGE_SHIFT;
1871 unsigned num_entries = length >> PAGE_SHIFT;
1872 gen6_pte_t scratch_pte, __iomem *gtt_base =
1873 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1874 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1877 if (WARN(num_entries > max_entries,
1878 "First entry = %d; Num entries = %d (max=%d)\n",
1879 first_entry, num_entries, max_entries))
1880 num_entries = max_entries;
1882 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1884 for (i = 0; i < num_entries; i++)
1885 iowrite32(scratch_pte, >t_base[i]);
1889 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1890 struct sg_table *pages,
1892 enum i915_cache_level cache_level, u32 unused)
1894 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1895 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1897 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1901 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1906 unsigned first_entry = start >> PAGE_SHIFT;
1907 unsigned num_entries = length >> PAGE_SHIFT;
1908 intel_gtt_clear_range(first_entry, num_entries);
1911 static int ggtt_bind_vma(struct i915_vma *vma,
1912 enum i915_cache_level cache_level,
1915 struct drm_device *dev = vma->vm->dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct drm_i915_gem_object *obj = vma->obj;
1918 struct sg_table *pages = obj->pages;
1922 ret = i915_get_ggtt_vma_pages(vma);
1925 pages = vma->ggtt_view.pages;
1927 /* Currently applicable only to VLV */
1929 pte_flags |= PTE_READ_ONLY;
1932 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1933 vma->vm->insert_entries(vma->vm, pages,
1935 cache_level, pte_flags);
1938 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1939 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1940 appgtt->base.insert_entries(&appgtt->base, pages,
1942 cache_level, pte_flags);
1948 static void ggtt_unbind_vma(struct i915_vma *vma)
1950 struct drm_device *dev = vma->vm->dev;
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1952 struct drm_i915_gem_object *obj = vma->obj;
1953 const uint64_t size = min_t(uint64_t,
1957 if (vma->bound & GLOBAL_BIND) {
1958 vma->vm->clear_range(vma->vm,
1964 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1965 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1967 appgtt->base.clear_range(&appgtt->base,
1974 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1976 struct drm_device *dev = obj->base.dev;
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1980 interruptible = do_idling(dev_priv);
1982 if (!obj->has_dma_mapping)
1983 dma_unmap_sg(&dev->pdev->dev,
1984 obj->pages->sgl, obj->pages->nents,
1985 PCI_DMA_BIDIRECTIONAL);
1987 undo_idling(dev_priv, interruptible);
1990 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1991 unsigned long color,
1995 if (node->color != color)
1998 if (!list_empty(&node->node_list)) {
1999 node = list_entry(node->node_list.next,
2002 if (node->allocated && node->color != color)
2007 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2008 unsigned long start,
2009 unsigned long mappable_end,
2012 /* Let GEM Manage all of the aperture.
2014 * However, leave one page at the end still bound to the scratch page.
2015 * There are a number of places where the hardware apparently prefetches
2016 * past the end of the object, and we've seen multiple hangs with the
2017 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2018 * aperture. One page should be enough to keep any prefetching inside
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2023 struct drm_mm_node *entry;
2024 struct drm_i915_gem_object *obj;
2025 unsigned long hole_start, hole_end;
2028 BUG_ON(mappable_end > end);
2030 /* Subtract the guard page ... */
2031 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2033 dev_priv->gtt.base.start = start;
2034 dev_priv->gtt.base.total = end - start;
2036 if (intel_vgpu_active(dev)) {
2037 ret = intel_vgt_balloon(dev);
2043 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2045 /* Mark any preallocated objects as occupied */
2046 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2047 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2049 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2050 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2052 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2053 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2055 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2058 vma->bound |= GLOBAL_BIND;
2061 /* Clear any non-preallocated blocks */
2062 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2063 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2064 hole_start, hole_end);
2065 ggtt_vm->clear_range(ggtt_vm, hole_start,
2066 hole_end - hole_start, true);
2069 /* And finally clear the reserved guard page */
2070 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2072 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2073 struct i915_hw_ppgtt *ppgtt;
2075 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2079 ret = __hw_ppgtt_init(dev, ppgtt);
2081 ppgtt->base.cleanup(&ppgtt->base);
2086 if (ppgtt->base.allocate_va_range)
2087 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2090 ppgtt->base.cleanup(&ppgtt->base);
2095 ppgtt->base.clear_range(&ppgtt->base,
2100 dev_priv->mm.aliasing_ppgtt = ppgtt;
2106 void i915_gem_init_global_gtt(struct drm_device *dev)
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 unsigned long gtt_size, mappable_size;
2111 gtt_size = dev_priv->gtt.base.total;
2112 mappable_size = dev_priv->gtt.mappable_end;
2114 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2117 void i915_global_gtt_cleanup(struct drm_device *dev)
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct i915_address_space *vm = &dev_priv->gtt.base;
2122 if (dev_priv->mm.aliasing_ppgtt) {
2123 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2125 ppgtt->base.cleanup(&ppgtt->base);
2128 if (drm_mm_initialized(&vm->mm)) {
2129 if (intel_vgpu_active(dev))
2130 intel_vgt_deballoon();
2132 drm_mm_takedown(&vm->mm);
2133 list_del(&vm->global_link);
2139 static int setup_scratch_page(struct drm_device *dev)
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2143 dma_addr_t dma_addr;
2145 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2148 set_pages_uc(page, 1);
2150 #ifdef CONFIG_INTEL_IOMMU
2151 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2152 PCI_DMA_BIDIRECTIONAL);
2153 if (pci_dma_mapping_error(dev->pdev, dma_addr)) {
2158 dma_addr = page_to_phys(page);
2160 dev_priv->gtt.base.scratch.page = page;
2161 dev_priv->gtt.base.scratch.addr = dma_addr;
2166 static void teardown_scratch_page(struct drm_device *dev)
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct page *page = dev_priv->gtt.base.scratch.page;
2171 set_pages_wb(page, 1);
2172 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
2173 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
2177 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2179 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2180 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2181 return snb_gmch_ctl << 20;
2184 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2186 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2187 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2189 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2191 #ifdef CONFIG_X86_32
2192 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2193 if (bdw_gmch_ctl > 4)
2197 return bdw_gmch_ctl << 20;
2200 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2202 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2203 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2206 return 1 << (20 + gmch_ctrl);
2211 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2213 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2214 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2215 return snb_gmch_ctl << 25; /* 32 MB units */
2218 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2220 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2221 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2222 return bdw_gmch_ctl << 25; /* 32 MB units */
2225 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2227 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2228 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2231 * 0x0 to 0x10: 32MB increments starting at 0MB
2232 * 0x11 to 0x16: 4MB increments starting at 8MB
2233 * 0x17 to 0x1d: 4MB increments start at 36MB
2235 if (gmch_ctrl < 0x11)
2236 return gmch_ctrl << 25;
2237 else if (gmch_ctrl < 0x17)
2238 return (gmch_ctrl - 0x11 + 2) << 22;
2240 return (gmch_ctrl - 0x17 + 9) << 22;
2243 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2245 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2246 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2248 if (gen9_gmch_ctl < 0xf0)
2249 return gen9_gmch_ctl << 25; /* 32 MB units */
2251 /* 4MB increments starting at 0xf0 for 4MB */
2252 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2255 static int ggtt_probe_common(struct drm_device *dev,
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 phys_addr_t gtt_phys_addr;
2262 /* For Modern GENs the PTEs and register space are split in the BAR */
2263 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2264 (pci_resource_len(dev->pdev, 0) / 2);
2267 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2268 * dropped. For WC mappings in general we have 64 byte burst writes
2269 * when the WC buffer is flushed, so we can't use it, but have to
2270 * resort to an uncached mapping. The WC issue is easily caught by the
2271 * readback check when writing GTT PTE entries.
2273 if (IS_BROXTON(dev))
2274 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2276 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2277 if (!dev_priv->gtt.gsm) {
2278 DRM_ERROR("Failed to map the gtt page table\n");
2282 ret = setup_scratch_page(dev);
2284 DRM_ERROR("Scratch setup failed\n");
2285 /* iounmap will also get called at remove, but meh */
2286 iounmap(dev_priv->gtt.gsm);
2292 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2293 * bits. When using advanced contexts each context stores its own PAT, but
2294 * writing this data shouldn't be harmful even in those cases. */
2295 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2299 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2300 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2301 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2302 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2303 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2304 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2305 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2306 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2308 if (!USES_PPGTT(dev_priv->dev))
2309 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2310 * so RTL will always use the value corresponding to
2312 * So let's disable cache for GGTT to avoid screen corruptions.
2313 * MOCS still can be used though.
2314 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2315 * before this patch, i.e. the same uncached + snooping access
2316 * like on gen6/7 seems to be in effect.
2317 * - So this just fixes blitter/render access. Again it looks
2318 * like it's not just uncached access, but uncached + snooping.
2319 * So we can still hold onto all our assumptions wrt cpu
2320 * clflushing on LLC machines.
2322 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2324 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2325 * write would work. */
2326 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2327 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2330 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2335 * Map WB on BDW to snooped on CHV.
2337 * Only the snoop bit has meaning for CHV, the rest is
2340 * The hardware will never snoop for certain types of accesses:
2341 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2342 * - PPGTT page tables
2343 * - some other special cycles
2345 * As with BDW, we also need to consider the following for GT accesses:
2346 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2347 * so RTL will always use the value corresponding to
2349 * Which means we must set the snoop bit in PAT entry 0
2350 * in order to keep the global status page working.
2352 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2356 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2357 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2358 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2359 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2361 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2362 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2365 static int gen8_gmch_probe(struct drm_device *dev,
2368 phys_addr_t *mappable_base,
2369 unsigned long *mappable_end)
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372 unsigned int gtt_size;
2376 /* TODO: We're not aware of mappable constraints on gen8 yet */
2377 *mappable_base = pci_resource_start(dev->pdev, 2);
2378 *mappable_end = pci_resource_len(dev->pdev, 2);
2380 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2381 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2383 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2385 if (INTEL_INFO(dev)->gen >= 9) {
2386 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2387 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2388 } else if (IS_CHERRYVIEW(dev)) {
2389 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2390 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2392 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2393 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2396 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2398 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2399 chv_setup_private_ppat(dev_priv);
2401 bdw_setup_private_ppat(dev_priv);
2403 ret = ggtt_probe_common(dev, gtt_size);
2405 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2406 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2407 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2408 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2413 static int gen6_gmch_probe(struct drm_device *dev,
2416 phys_addr_t *mappable_base,
2417 unsigned long *mappable_end)
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 unsigned int gtt_size;
2424 *mappable_base = pci_resource_start(dev->pdev, 2);
2425 *mappable_end = pci_resource_len(dev->pdev, 2);
2427 /* 64/512MB is the current min/max we actually know of, but this is just
2428 * a coarse sanity check.
2430 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2431 DRM_ERROR("Unknown GMADR size (%lx)\n",
2432 dev_priv->gtt.mappable_end);
2436 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2437 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2438 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2440 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2442 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2443 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2445 ret = ggtt_probe_common(dev, gtt_size);
2447 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2448 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2449 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2450 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2455 static void gen6_gmch_remove(struct i915_address_space *vm)
2458 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2461 teardown_scratch_page(vm->dev);
2464 static int i915_gmch_probe(struct drm_device *dev,
2467 phys_addr_t *mappable_base,
2468 unsigned long *mappable_end)
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2473 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2475 DRM_ERROR("failed to set up gmch\n");
2479 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2481 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2482 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2483 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2484 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2485 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2487 if (unlikely(dev_priv->gtt.do_idle_maps))
2488 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2493 static void i915_gmch_remove(struct i915_address_space *vm)
2495 intel_gmch_remove();
2498 int i915_gem_gtt_init(struct drm_device *dev)
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501 struct i915_gtt *gtt = &dev_priv->gtt;
2504 if (INTEL_INFO(dev)->gen <= 5) {
2505 gtt->gtt_probe = i915_gmch_probe;
2506 gtt->base.cleanup = i915_gmch_remove;
2507 } else if (INTEL_INFO(dev)->gen < 8) {
2508 gtt->gtt_probe = gen6_gmch_probe;
2509 gtt->base.cleanup = gen6_gmch_remove;
2510 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2511 gtt->base.pte_encode = iris_pte_encode;
2512 else if (IS_HASWELL(dev))
2513 gtt->base.pte_encode = hsw_pte_encode;
2514 else if (IS_VALLEYVIEW(dev))
2515 gtt->base.pte_encode = byt_pte_encode;
2516 else if (INTEL_INFO(dev)->gen >= 7)
2517 gtt->base.pte_encode = ivb_pte_encode;
2519 gtt->base.pte_encode = snb_pte_encode;
2521 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2522 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2525 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
2526 >t->mappable_base, >t->mappable_end);
2530 gtt->base.dev = dev;
2532 /* GMADR is the PCI mmio aperture into the global GTT. */
2533 DRM_INFO("Memory usable by graphics device = %zdM\n",
2534 gtt->base.total >> 20);
2535 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2536 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2537 #ifdef CONFIG_INTEL_IOMMU
2538 if (intel_iommu_gfx_mapped)
2539 DRM_INFO("VT-d active for gfx access\n");
2542 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2543 * user's requested state against the hardware/driver capabilities. We
2544 * do this now so that we can print out any log messages once rather
2545 * than every time we check intel_enable_ppgtt().
2547 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2548 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2553 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 struct drm_i915_gem_object *obj;
2557 struct i915_address_space *vm;
2559 i915_check_and_clear_faults(dev);
2561 /* First fill our portion of the GTT with scratch pages */
2562 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2563 dev_priv->gtt.base.start,
2564 dev_priv->gtt.base.total,
2567 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2568 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2569 &dev_priv->gtt.base);
2573 i915_gem_clflush_object(obj, obj->pin_display);
2574 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2578 if (INTEL_INFO(dev)->gen >= 8) {
2579 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2580 chv_setup_private_ppat(dev_priv);
2582 bdw_setup_private_ppat(dev_priv);
2587 if (USES_PPGTT(dev)) {
2588 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2589 /* TODO: Perhaps it shouldn't be gen6 specific */
2591 struct i915_hw_ppgtt *ppgtt =
2592 container_of(vm, struct i915_hw_ppgtt,
2595 if (i915_is_ggtt(vm))
2596 ppgtt = dev_priv->mm.aliasing_ppgtt;
2598 gen6_write_page_range(dev_priv, &ppgtt->pd,
2599 0, ppgtt->base.total);
2603 i915_ggtt_flush(dev_priv);
2606 static struct i915_vma *
2607 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2608 struct i915_address_space *vm,
2609 const struct i915_ggtt_view *ggtt_view)
2611 struct i915_vma *vma;
2613 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2614 return ERR_PTR(-EINVAL);
2616 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2618 return ERR_PTR(-ENOMEM);
2620 INIT_LIST_HEAD(&vma->vma_link);
2621 INIT_LIST_HEAD(&vma->mm_list);
2622 INIT_LIST_HEAD(&vma->exec_list);
2626 if (i915_is_ggtt(vm))
2627 vma->ggtt_view = *ggtt_view;
2629 list_add_tail(&vma->vma_link, &obj->vma_list);
2630 if (!i915_is_ggtt(vm))
2631 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2637 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2638 struct i915_address_space *vm)
2640 struct i915_vma *vma;
2642 vma = i915_gem_obj_to_vma(obj, vm);
2644 vma = __i915_gem_vma_create(obj, vm,
2645 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2651 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2652 const struct i915_ggtt_view *view)
2654 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2655 struct i915_vma *vma;
2658 return ERR_PTR(-EINVAL);
2660 vma = i915_gem_obj_to_ggtt_view(obj, view);
2666 vma = __i915_gem_vma_create(obj, ggtt, view);
2673 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2674 struct sg_table *st)
2676 unsigned int column, row;
2677 unsigned int src_idx;
2678 struct scatterlist *sg = st->sgl;
2682 for (column = 0; column < width; column++) {
2683 src_idx = width * (height - 1) + column;
2684 for (row = 0; row < height; row++) {
2686 /* We don't need the pages, but need to initialize
2687 * the entries so the sg list can be happily traversed.
2688 * The only thing we need are DMA addresses.
2690 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2691 sg_dma_address(sg) = in[src_idx];
2692 sg_dma_len(sg) = PAGE_SIZE;
2699 static struct sg_table *
2700 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2701 struct drm_i915_gem_object *obj)
2703 struct drm_device *dev = obj->base.dev;
2704 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2705 unsigned long size, pages, rot_pages;
2706 struct sg_page_iter sg_iter;
2708 dma_addr_t *page_addr_list;
2709 struct sg_table *st;
2710 unsigned int tile_pitch, tile_height;
2711 unsigned int width_pages, height_pages;
2714 pages = obj->base.size / PAGE_SIZE;
2716 /* Calculate tiling geometry. */
2717 tile_height = intel_tile_height(dev, rot_info->pixel_format,
2718 rot_info->fb_modifier);
2719 tile_pitch = PAGE_SIZE / tile_height;
2720 width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch);
2721 height_pages = DIV_ROUND_UP(rot_info->height, tile_height);
2722 rot_pages = width_pages * height_pages;
2723 size = rot_pages * PAGE_SIZE;
2725 /* Allocate a temporary list of source pages for random access. */
2726 page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
2727 if (!page_addr_list)
2728 return ERR_PTR(ret);
2730 /* Allocate target SG list. */
2731 st = kmalloc(sizeof(*st), GFP_KERNEL);
2735 ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
2739 /* Populate source page list from the object. */
2741 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2742 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2746 /* Rotate the pages. */
2747 rotate_pages(page_addr_list, width_pages, height_pages, st);
2750 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2751 size, rot_info->pitch, rot_info->height,
2752 rot_info->pixel_format, width_pages, height_pages,
2755 drm_free_large(page_addr_list);
2762 drm_free_large(page_addr_list);
2765 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2766 size, ret, rot_info->pitch, rot_info->height,
2767 rot_info->pixel_format, width_pages, height_pages,
2769 return ERR_PTR(ret);
2772 static struct sg_table *
2773 intel_partial_pages(const struct i915_ggtt_view *view,
2774 struct drm_i915_gem_object *obj)
2776 struct sg_table *st;
2777 struct scatterlist *sg;
2778 struct sg_page_iter obj_sg_iter;
2781 st = kmalloc(sizeof(*st), GFP_KERNEL);
2785 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2791 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2792 view->params.partial.offset)
2794 if (st->nents >= view->params.partial.size)
2797 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2798 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2799 sg_dma_len(sg) = PAGE_SIZE;
2810 return ERR_PTR(ret);
2814 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2818 if (vma->ggtt_view.pages)
2821 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2822 vma->ggtt_view.pages = vma->obj->pages;
2823 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2824 vma->ggtt_view.pages =
2825 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2826 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2827 vma->ggtt_view.pages =
2828 intel_partial_pages(&vma->ggtt_view, vma->obj);
2830 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2831 vma->ggtt_view.type);
2833 if (!vma->ggtt_view.pages) {
2834 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2835 vma->ggtt_view.type);
2837 } else if (IS_ERR(vma->ggtt_view.pages)) {
2838 ret = PTR_ERR(vma->ggtt_view.pages);
2839 vma->ggtt_view.pages = NULL;
2840 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2841 vma->ggtt_view.type, ret);
2848 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2850 * @cache_level: mapping cache level
2851 * @flags: flags like global or local mapping
2853 * DMA addresses are taken from the scatter-gather table of this object (or of
2854 * this VMA in case of non-default GGTT views) and PTE entries set up.
2855 * Note that DMA addresses are also the only part of the SG table we care about.
2857 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2863 if (WARN_ON(flags == 0))
2867 if (flags & PIN_GLOBAL)
2868 bind_flags |= GLOBAL_BIND;
2869 if (flags & PIN_USER)
2870 bind_flags |= LOCAL_BIND;
2872 if (flags & PIN_UPDATE)
2873 bind_flags |= vma->bound;
2875 bind_flags &= ~vma->bound;
2877 if (bind_flags == 0)
2880 if (vma->bound == 0 && vma->vm->allocate_va_range) {
2881 trace_i915_va_alloc(vma->vm,
2884 VM_TO_TRACE_NAME(vma->vm));
2886 ret = vma->vm->allocate_va_range(vma->vm,
2893 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2897 vma->bound |= bind_flags;
2903 * i915_ggtt_view_size - Get the size of a GGTT view.
2904 * @obj: Object the view is of.
2905 * @view: The view in question.
2907 * @return The size of the GGTT view in bytes.
2910 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2911 const struct i915_ggtt_view *view)
2913 if (view->type == I915_GGTT_VIEW_NORMAL ||
2914 view->type == I915_GGTT_VIEW_ROTATED) {
2915 return obj->base.size;
2916 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2917 return view->params.partial.size << PAGE_SHIFT;
2919 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2920 return obj->base.size;