drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 /* PPGTT stuff */
  32 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  33
  34 #define GEN6_PDE_VALID                  (1 << 0)
  35 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  36 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  37
  38 #define GEN6_PTE_VALID                  (1 << 0)
  39 #define GEN6_PTE_UNCACHED               (1 << 1)
  40 #define HSW_PTE_UNCACHED                (0)
  41 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  42 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  43 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  44
  45 static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  46                                       dma_addr_t addr,
  47                                       enum i915_cache_level level)
  48 {
  49         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  50         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  51
  52         switch (level) {
  53         case I915_CACHE_LLC_MLC:
  54                 /* Haswell doesn't set L3 this way */
  55                 if (IS_HASWELL(dev))
  56                         pte |= GEN6_PTE_CACHE_LLC;
  57                 else
  58                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  59                 break;
  60         case I915_CACHE_LLC:
  61                 pte |= GEN6_PTE_CACHE_LLC;
  62                 break;
  63         case I915_CACHE_NONE:
  64                 if (IS_HASWELL(dev))
  65                         pte |= HSW_PTE_UNCACHED;
  66                 else
  67                         pte |= GEN6_PTE_UNCACHED;
  68                 break;
  69         default:
  70                 BUG();
  71         }
  72
  73         return pte;
  74 }
  75
  76 static int gen6_ppgtt_enable(struct drm_device *dev)
  77 {
  78         drm_i915_private_t *dev_priv = dev->dev_private;
  79         uint32_t pd_offset;
  80         struct intel_ring_buffer *ring;
  81         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  82         gen6_gtt_pte_t __iomem *pd_addr;
  83         uint32_t pd_entry;
  84         int i;
  85
  86         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
  87                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
  88         for (i = 0; i < ppgtt->num_pd_entries; i++) {
  89                 dma_addr_t pt_addr;
  90
  91                 pt_addr = ppgtt->pt_dma_addr[i];
  92                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
  93                 pd_entry |= GEN6_PDE_VALID;
  94
  95                 writel(pd_entry, pd_addr + i);
  96         }
  97         readl(pd_addr);
  98
  99         pd_offset = ppgtt->pd_offset;
 100         pd_offset /= 64; /* in cachelines, */
 101         pd_offset <<= 16;
 102
 103         if (INTEL_INFO(dev)->gen == 6) {
 104                 uint32_t ecochk, gab_ctl, ecobits;
 105
 106                 ecobits = I915_READ(GAC_ECO_BITS);
 107                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 108                                          ECOBITS_PPGTT_CACHE64B);
 109
 110                 gab_ctl = I915_READ(GAB_CTL);
 111                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 112
 113                 ecochk = I915_READ(GAM_ECOCHK);
 114                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 115                                        ECOCHK_PPGTT_CACHE64B);
 116                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 117         } else if (INTEL_INFO(dev)->gen >= 7) {
 118                 uint32_t ecochk, ecobits;
 119
 120                 ecobits = I915_READ(GAC_ECO_BITS);
 121                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 122
 123                 ecochk = I915_READ(GAM_ECOCHK);
 124                 if (IS_HASWELL(dev)) {
 125                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 126                 } else {
 127                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 128                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 129                 }
 130                 I915_WRITE(GAM_ECOCHK, ecochk);
 131                 /* GFX_MODE is per-ring on gen7+ */
 132         }
 133
 134         for_each_ring(ring, dev_priv, i) {
 135                 if (INTEL_INFO(dev)->gen >= 7)
 136                         I915_WRITE(RING_MODE_GEN7(ring),
 137                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 138
 139                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 140                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 141         }
 142         return 0;
 143 }
 144
 145 /* PPGTT support for Sandybdrige/Gen6 and later */
 146 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 147                                    unsigned first_entry,
 148                                    unsigned num_entries)
 149 {
 150         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 151         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 152         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 153         unsigned last_pte, i;
 154
 155         scratch_pte = ppgtt->pte_encode(ppgtt->dev,
 156                                         ppgtt->scratch_page_dma_addr,
 157                                         I915_CACHE_LLC);
 158
 159         while (num_entries) {
 160                 last_pte = first_pte + num_entries;
 161                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 162                         last_pte = I915_PPGTT_PT_ENTRIES;
 163
 164                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 165
 166                 for (i = first_pte; i < last_pte; i++)
 167                         pt_vaddr[i] = scratch_pte;
 168
 169                 kunmap_atomic(pt_vaddr);
 170
 171                 num_entries -= last_pte - first_pte;
 172                 first_pte = 0;
 173                 act_pt++;
 174         }
 175 }
 176
 177 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 178                                       struct sg_table *pages,
 179                                       unsigned first_entry,
 180                                       enum i915_cache_level cache_level)
 181 {
 182         gen6_gtt_pte_t *pt_vaddr;
 183         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 184         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 185         struct sg_page_iter sg_iter;
 186
 187         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 188         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 189                 dma_addr_t page_addr;
 190
 191                 page_addr = sg_page_iter_dma_address(&sg_iter);
 192                 pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,
 193                                                       cache_level);
 194                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 195                         kunmap_atomic(pt_vaddr);
 196                         act_pt++;
 197                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 198                         act_pte = 0;
 199
 200                 }
 201         }
 202         kunmap_atomic(pt_vaddr);
 203 }
 204
 205 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 206 {
 207         int i;
 208
 209         if (ppgtt->pt_dma_addr) {
 210                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 211                         pci_unmap_page(ppgtt->dev->pdev,
 212                                        ppgtt->pt_dma_addr[i],
 213                                        4096, PCI_DMA_BIDIRECTIONAL);
 214         }
 215
 216         kfree(ppgtt->pt_dma_addr);
 217         for (i = 0; i < ppgtt->num_pd_entries; i++)
 218                 __free_page(ppgtt->pt_pages[i]);
 219         kfree(ppgtt->pt_pages);
 220         kfree(ppgtt);
 221 }
 222
 223 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 224 {
 225         struct drm_device *dev = ppgtt->dev;
 226         struct drm_i915_private *dev_priv = dev->dev_private;
 227         unsigned first_pd_entry_in_global_pt;
 228         int i;
 229         int ret = -ENOMEM;
 230
 231         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 232          * entries. For aliasing ppgtt support we just steal them at the end for
 233          * now. */
 234         first_pd_entry_in_global_pt =
 235                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 236
 237         ppgtt->pte_encode = gen6_pte_encode;
 238         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 239         ppgtt->enable = gen6_ppgtt_enable;
 240         ppgtt->clear_range = gen6_ppgtt_clear_range;
 241         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 242         ppgtt->cleanup = gen6_ppgtt_cleanup;
 243         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 244                                   GFP_KERNEL);
 245         if (!ppgtt->pt_pages)
 246                 return -ENOMEM;
 247
 248         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 249                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 250                 if (!ppgtt->pt_pages[i])
 251                         goto err_pt_alloc;
 252         }
 253
 254         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 255                                      GFP_KERNEL);
 256         if (!ppgtt->pt_dma_addr)
 257                 goto err_pt_alloc;
 258
 259         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 260                 dma_addr_t pt_addr;
 261
 262                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 263                                        PCI_DMA_BIDIRECTIONAL);
 264
 265                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 266                         ret = -EIO;
 267                         goto err_pd_pin;
 268
 269                 }
 270                 ppgtt->pt_dma_addr[i] = pt_addr;
 271         }
 272
 273         ppgtt->clear_range(ppgtt, 0,
 274                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 275
 276         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 277
 278         return 0;
 279
 280 err_pd_pin:
 281         if (ppgtt->pt_dma_addr) {
 282                 for (i--; i >= 0; i--)
 283                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 284                                        4096, PCI_DMA_BIDIRECTIONAL);
 285         }
 286 err_pt_alloc:
 287         kfree(ppgtt->pt_dma_addr);
 288         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 289                 if (ppgtt->pt_pages[i])
 290                         __free_page(ppgtt->pt_pages[i]);
 291         }
 292         kfree(ppgtt->pt_pages);
 293
 294         return ret;
 295 }
 296
 297 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         struct i915_hw_ppgtt *ppgtt;
 301         int ret;
 302
 303         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 304         if (!ppgtt)
 305                 return -ENOMEM;
 306
 307         ppgtt->dev = dev;
 308         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 309
 310         if (INTEL_INFO(dev)->gen < 8)
 311                 ret = gen6_ppgtt_init(ppgtt);
 312         else
 313                 BUG();
 314
 315         if (ret)
 316                 kfree(ppgtt);
 317         else
 318                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 319
 320         return ret;
 321 }
 322
 323 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 327
 328         if (!ppgtt)
 329                 return;
 330
 331         ppgtt->cleanup(ppgtt);
 332         dev_priv->mm.aliasing_ppgtt = NULL;
 333 }
 334
 335 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 336                             struct drm_i915_gem_object *obj,
 337                             enum i915_cache_level cache_level)
 338 {
 339         ppgtt->insert_entries(ppgtt, obj->pages,
 340                               obj->gtt_space->start >> PAGE_SHIFT,
 341                               cache_level);
 342 }
 343
 344 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 345                               struct drm_i915_gem_object *obj)
 346 {
 347         ppgtt->clear_range(ppgtt,
 348                            obj->gtt_space->start >> PAGE_SHIFT,
 349                            obj->base.size >> PAGE_SHIFT);
 350 }
 351
 352 extern int intel_iommu_gfx_mapped;
 353 /* Certain Gen5 chipsets require require idling the GPU before
 354  * unmapping anything from the GTT when VT-d is enabled.
 355  */
 356 static inline bool needs_idle_maps(struct drm_device *dev)
 357 {
 358 #ifdef CONFIG_INTEL_IOMMU
 359         /* Query intel_iommu to see if we need the workaround. Presumably that
 360          * was loaded first.
 361          */
 362         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 363                 return true;
 364 #endif
 365         return false;
 366 }
 367
 368 static bool do_idling(struct drm_i915_private *dev_priv)
 369 {
 370         bool ret = dev_priv->mm.interruptible;
 371
 372         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 373                 dev_priv->mm.interruptible = false;
 374                 if (i915_gpu_idle(dev_priv->dev)) {
 375                         DRM_ERROR("Couldn't idle GPU\n");
 376                         /* Wait a bit, in hopes it avoids the hang */
 377                         udelay(10);
 378                 }
 379         }
 380
 381         return ret;
 382 }
 383
 384 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 385 {
 386         if (unlikely(dev_priv->gtt.do_idle_maps))
 387                 dev_priv->mm.interruptible = interruptible;
 388 }
 389
 390 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct drm_i915_gem_object *obj;
 394
 395         /* First fill our portion of the GTT with scratch pages */
 396         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 397                                       dev_priv->gtt.total / PAGE_SIZE);
 398
 399         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 400                 i915_gem_clflush_object(obj);
 401                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 402         }
 403
 404         i915_gem_chipset_flush(dev);
 405 }
 406
 407 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 408 {
 409         if (obj->has_dma_mapping)
 410                 return 0;
 411
 412         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 413                         obj->pages->sgl, obj->pages->nents,
 414                         PCI_DMA_BIDIRECTIONAL))
 415                 return -ENOSPC;
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Binds an object into the global gtt with the specified cache level. The object
 422  * will be accessible to the GPU via commands whose operands reference offsets
 423  * within the global GTT as well as accessible by the GPU through the GMADR
 424  * mapped BAR (dev_priv->mm.gtt->gtt).
 425  */
 426 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 427                                      struct sg_table *st,
 428                                      unsigned int first_entry,
 429                                      enum i915_cache_level level)
 430 {
 431         struct drm_i915_private *dev_priv = dev->dev_private;
 432         gen6_gtt_pte_t __iomem *gtt_entries =
 433                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 434         int i = 0;
 435         struct sg_page_iter sg_iter;
 436         dma_addr_t addr;
 437
 438         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 439                 addr = sg_page_iter_dma_address(&sg_iter);
 440                 iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),
 441                           &gtt_entries[i]);
 442                 i++;
 443         }
 444
 445         /* XXX: This serves as a posting read to make sure that the PTE has
 446          * actually been updated. There is some concern that even though
 447          * registers and PTEs are within the same BAR that they are potentially
 448          * of NUMA access patterns. Therefore, even with the way we assume
 449          * hardware should work, we must keep this posting read for paranoia.
 450          */
 451         if (i != 0)
 452                 WARN_ON(readl(&gtt_entries[i-1])
 453                         != dev_priv->gtt.pte_encode(dev, addr, level));
 454
 455         /* This next bit makes the above posting read even more important. We
 456          * want to flush the TLBs only after we're certain all the PTE updates
 457          * have finished.
 458          */
 459         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 460         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 461 }
 462
 463 static void gen6_ggtt_clear_range(struct drm_device *dev,
 464                                   unsigned int first_entry,
 465                                   unsigned int num_entries)
 466 {
 467         struct drm_i915_private *dev_priv = dev->dev_private;
 468         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 469                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 470         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 471         int i;
 472
 473         if (WARN(num_entries > max_entries,
 474                  "First entry = %d; Num entries = %d (max=%d)\n",
 475                  first_entry, num_entries, max_entries))
 476                 num_entries = max_entries;
 477
 478         scratch_pte = dev_priv->gtt.pte_encode(dev,
 479                                                dev_priv->gtt.scratch_page_dma,
 480                                                I915_CACHE_LLC);
 481         for (i = 0; i < num_entries; i++)
 482                 iowrite32(scratch_pte, &gtt_base[i]);
 483         readl(gtt_base);
 484 }
 485
 486
 487 static void i915_ggtt_insert_entries(struct drm_device *dev,
 488                                      struct sg_table *st,
 489                                      unsigned int pg_start,
 490                                      enum i915_cache_level cache_level)
 491 {
 492         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 493                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 494
 495         intel_gtt_insert_sg_entries(st, pg_start, flags);
 496
 497 }
 498
 499 static void i915_ggtt_clear_range(struct drm_device *dev,
 500                                   unsigned int first_entry,
 501                                   unsigned int num_entries)
 502 {
 503         intel_gtt_clear_range(first_entry, num_entries);
 504 }
 505
 506
 507 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 508                               enum i915_cache_level cache_level)
 509 {
 510         struct drm_device *dev = obj->base.dev;
 511         struct drm_i915_private *dev_priv = dev->dev_private;
 512
 513         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 514                                          obj->gtt_space->start >> PAGE_SHIFT,
 515                                          cache_level);
 516
 517         obj->has_global_gtt_mapping = 1;
 518 }
 519
 520 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 521 {
 522         struct drm_device *dev = obj->base.dev;
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524
 525         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 526                                       obj->gtt_space->start >> PAGE_SHIFT,
 527                                       obj->base.size >> PAGE_SHIFT);
 528
 529         obj->has_global_gtt_mapping = 0;
 530 }
 531
 532 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 533 {
 534         struct drm_device *dev = obj->base.dev;
 535         struct drm_i915_private *dev_priv = dev->dev_private;
 536         bool interruptible;
 537
 538         interruptible = do_idling(dev_priv);
 539
 540         if (!obj->has_dma_mapping)
 541                 dma_unmap_sg(&dev->pdev->dev,
 542                              obj->pages->sgl, obj->pages->nents,
 543                              PCI_DMA_BIDIRECTIONAL);
 544
 545         undo_idling(dev_priv, interruptible);
 546 }
 547
 548 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 549                                   unsigned long color,
 550                                   unsigned long *start,
 551                                   unsigned long *end)
 552 {
 553         if (node->color != color)
 554                 *start += 4096;
 555
 556         if (!list_empty(&node->node_list)) {
 557                 node = list_entry(node->node_list.next,
 558                                   struct drm_mm_node,
 559                                   node_list);
 560                 if (node->allocated && node->color != color)
 561                         *end -= 4096;
 562         }
 563 }
 564 void i915_gem_setup_global_gtt(struct drm_device *dev,
 565                                unsigned long start,
 566                                unsigned long mappable_end,
 567                                unsigned long end)
 568 {
 569         /* Let GEM Manage all of the aperture.
 570          *
 571          * However, leave one page at the end still bound to the scratch page.
 572          * There are a number of places where the hardware apparently prefetches
 573          * past the end of the object, and we've seen multiple hangs with the
 574          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 575          * aperture.  One page should be enough to keep any prefetching inside
 576          * of the aperture.
 577          */
 578         drm_i915_private_t *dev_priv = dev->dev_private;
 579         struct drm_mm_node *entry;
 580         struct drm_i915_gem_object *obj;
 581         unsigned long hole_start, hole_end;
 582
 583         BUG_ON(mappable_end > end);
 584
 585         /* Subtract the guard page ... */
 586         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 587         if (!HAS_LLC(dev))
 588                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 589
 590         /* Mark any preallocated objects as occupied */
 591         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 592                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 593                               obj->gtt_offset, obj->base.size);
 594
 595                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 596                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 597                                                      obj->gtt_offset,
 598                                                      obj->base.size,
 599                                                      false);
 600                 obj->has_global_gtt_mapping = 1;
 601         }
 602
 603         dev_priv->gtt.start = start;
 604         dev_priv->gtt.total = end - start;
 605
 606         /* Clear any non-preallocated blocks */
 607         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 608                              hole_start, hole_end) {
 609                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 610                               hole_start, hole_end);
 611                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 612                                               (hole_end-hole_start) / PAGE_SIZE);
 613         }
 614
 615         /* And finally clear the reserved guard page */
 616         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 617 }
 618
 619 static bool
 620 intel_enable_ppgtt(struct drm_device *dev)
 621 {
 622         if (i915_enable_ppgtt >= 0)
 623                 return i915_enable_ppgtt;
 624
 625 #ifdef CONFIG_INTEL_IOMMU
 626         /* Disable ppgtt on SNB if VT-d is on. */
 627         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 628                 return false;
 629 #endif
 630
 631         return true;
 632 }
 633
 634 void i915_gem_init_global_gtt(struct drm_device *dev)
 635 {
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637         unsigned long gtt_size, mappable_size;
 638
 639         gtt_size = dev_priv->gtt.total;
 640         mappable_size = dev_priv->gtt.mappable_end;
 641
 642         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 643                 int ret;
 644
 645                 if (INTEL_INFO(dev)->gen <= 7) {
 646                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 647                          * aperture accordingly when using aliasing ppgtt. */
 648                         gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 649                 }
 650
 651                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 652
 653                 ret = i915_gem_init_aliasing_ppgtt(dev);
 654                 if (!ret)
 655                         return;
 656
 657                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 658                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 659                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 660         }
 661         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 662 }
 663
 664 static int setup_scratch_page(struct drm_device *dev)
 665 {
 666         struct drm_i915_private *dev_priv = dev->dev_private;
 667         struct page *page;
 668         dma_addr_t dma_addr;
 669
 670         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 671         if (page == NULL)
 672                 return -ENOMEM;
 673         get_page(page);
 674         set_pages_uc(page, 1);
 675
 676 #ifdef CONFIG_INTEL_IOMMU
 677         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 678                                 PCI_DMA_BIDIRECTIONAL);
 679         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 680                 return -EINVAL;
 681 #else
 682         dma_addr = page_to_phys(page);
 683 #endif
 684         dev_priv->gtt.scratch_page = page;
 685         dev_priv->gtt.scratch_page_dma = dma_addr;
 686
 687         return 0;
 688 }
 689
 690 static void teardown_scratch_page(struct drm_device *dev)
 691 {
 692         struct drm_i915_private *dev_priv = dev->dev_private;
 693         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 694         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 695                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 696         put_page(dev_priv->gtt.scratch_page);
 697         __free_page(dev_priv->gtt.scratch_page);
 698 }
 699
 700 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 701 {
 702         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 703         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 704         return snb_gmch_ctl << 20;
 705 }
 706
 707 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 708 {
 709         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 710         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 711         return snb_gmch_ctl << 25; /* 32 MB units */
 712 }
 713
 714 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 715 {
 716         static const int stolen_decoder[] = {
 717                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 718         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 719         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 720         return stolen_decoder[snb_gmch_ctl] << 20;
 721 }
 722
 723 static int gen6_gmch_probe(struct drm_device *dev,
 724                            size_t *gtt_total,
 725                            size_t *stolen,
 726                            phys_addr_t *mappable_base,
 727                            unsigned long *mappable_end)
 728 {
 729         struct drm_i915_private *dev_priv = dev->dev_private;
 730         phys_addr_t gtt_bus_addr;
 731         unsigned int gtt_size;
 732         u16 snb_gmch_ctl;
 733         int ret;
 734
 735         *mappable_base = pci_resource_start(dev->pdev, 2);
 736         *mappable_end = pci_resource_len(dev->pdev, 2);
 737
 738         /* 64/512MB is the current min/max we actually know of, but this is just
 739          * a coarse sanity check.
 740          */
 741         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 742                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 743                           dev_priv->gtt.mappable_end);
 744                 return -ENXIO;
 745         }
 746
 747         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 748                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 749         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 750         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 751
 752         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 753                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 754         else
 755                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 756
 757         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 758
 759         /* For Modern GENs the PTEs and register space are split in the BAR */
 760         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 761                 (pci_resource_len(dev->pdev, 0) / 2);
 762
 763         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 764         if (!dev_priv->gtt.gsm) {
 765                 DRM_ERROR("Failed to map the gtt page table\n");
 766                 return -ENOMEM;
 767         }
 768
 769         ret = setup_scratch_page(dev);
 770         if (ret)
 771                 DRM_ERROR("Scratch setup failed\n");
 772
 773         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 774         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 775
 776         return ret;
 777 }
 778
 779 static void gen6_gmch_remove(struct drm_device *dev)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         iounmap(dev_priv->gtt.gsm);
 783         teardown_scratch_page(dev_priv->dev);
 784 }
 785
 786 static int i915_gmch_probe(struct drm_device *dev,
 787                            size_t *gtt_total,
 788                            size_t *stolen,
 789                            phys_addr_t *mappable_base,
 790                            unsigned long *mappable_end)
 791 {
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793         int ret;
 794
 795         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 796         if (!ret) {
 797                 DRM_ERROR("failed to set up gmch\n");
 798                 return -EIO;
 799         }
 800
 801         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 802
 803         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 804         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 805         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 806
 807         return 0;
 808 }
 809
 810 static void i915_gmch_remove(struct drm_device *dev)
 811 {
 812         intel_gmch_remove();
 813 }
 814
 815 int i915_gem_gtt_init(struct drm_device *dev)
 816 {
 817         struct drm_i915_private *dev_priv = dev->dev_private;
 818         struct i915_gtt *gtt = &dev_priv->gtt;
 819         int ret;
 820
 821         if (INTEL_INFO(dev)->gen <= 5) {
 822                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 823                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 824         } else {
 825                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 826                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 827                 dev_priv->gtt.pte_encode = gen6_pte_encode;
 828         }
 829
 830         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 831                                      &dev_priv->gtt.stolen_size,
 832                                      &gtt->mappable_base,
 833                                      &gtt->mappable_end);
 834         if (ret)
 835                 return ret;
 836
 837         /* GMADR is the PCI mmio aperture into the global GTT. */
 838         DRM_INFO("Memory usable by graphics device = %zdM\n",
 839                  dev_priv->gtt.total >> 20);
 840         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 841                          dev_priv->gtt.mappable_end >> 20);
 842         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 843                          dev_priv->gtt.stolen_size >> 20);
 844
 845         return 0;
 846 }