2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
98 const struct i915_ggtt_view i915_ggtt_view_normal;
99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
105 bool has_aliasing_ppgtt;
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
122 if (enable_ppgtt == 1)
125 if (enable_ppgtt == 2 && has_full_ppgtt)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
146 return has_aliasing_ppgtt ? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
155 /* Currently applicable only to VLV */
157 pte_flags |= PTE_READ_ONLY;
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
165 static void ppgtt_unbind_vma(struct i915_vma *vma)
167 vma->vm->clear_range(vma->vm,
173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
181 case I915_CACHE_NONE:
182 pte |= PPAT_UNCACHED_INDEX;
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
188 pte |= PPAT_CACHED_INDEX;
195 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
203 pde |= PPAT_UNCACHED_INDEX;
207 #define gen8_pdpe_encode gen8_pde_encode
208 #define gen8_pml4e_encode gen8_pde_encode
210 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
211 enum i915_cache_level level,
212 bool valid, u32 unused)
214 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
215 pte |= GEN6_PTE_ADDR_ENCODE(addr);
218 case I915_CACHE_L3_LLC:
220 pte |= GEN6_PTE_CACHE_LLC;
222 case I915_CACHE_NONE:
223 pte |= GEN6_PTE_UNCACHED;
232 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
233 enum i915_cache_level level,
234 bool valid, u32 unused)
236 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
237 pte |= GEN6_PTE_ADDR_ENCODE(addr);
240 case I915_CACHE_L3_LLC:
241 pte |= GEN7_PTE_CACHE_L3_LLC;
244 pte |= GEN6_PTE_CACHE_LLC;
246 case I915_CACHE_NONE:
247 pte |= GEN6_PTE_UNCACHED;
256 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
257 enum i915_cache_level level,
258 bool valid, u32 flags)
260 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
261 pte |= GEN6_PTE_ADDR_ENCODE(addr);
263 if (!(flags & PTE_READ_ONLY))
264 pte |= BYT_PTE_WRITEABLE;
266 if (level != I915_CACHE_NONE)
267 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
272 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
273 enum i915_cache_level level,
274 bool valid, u32 unused)
276 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
277 pte |= HSW_PTE_ADDR_ENCODE(addr);
279 if (level != I915_CACHE_NONE)
280 pte |= HSW_WB_LLC_AGE3;
285 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
286 enum i915_cache_level level,
287 bool valid, u32 unused)
289 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
290 pte |= HSW_PTE_ADDR_ENCODE(addr);
293 case I915_CACHE_NONE:
296 pte |= HSW_WT_ELLC_LLC_AGE3;
299 pte |= HSW_WB_ELLC_LLC_AGE3;
306 static int __setup_page_dma(struct drm_device *dev,
307 struct i915_page_dma *p, gfp_t flags)
309 struct device *device = &dev->pdev->dev;
311 p->page = alloc_page(flags);
315 p->daddr = dma_map_page(device,
316 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
318 if (dma_mapping_error(device, p->daddr)) {
319 __free_page(p->page);
326 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
328 return __setup_page_dma(dev, p, GFP_KERNEL);
331 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
333 if (WARN_ON(!p->page))
336 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
337 __free_page(p->page);
338 memset(p, 0, sizeof(*p));
341 static void *kmap_page_dma(struct i915_page_dma *p)
343 return kmap_atomic(p->page);
346 /* We use the flushing unmap only with ppgtt structures:
347 * page directories, page tables and scratch pages.
349 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
351 /* There are only few exceptions for gen >=6. chv and bxt.
352 * And we are not sure about the latter so play safe for now.
354 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
355 drm_clflush_virt_range(vaddr, PAGE_SIZE);
357 kunmap_atomic(vaddr);
360 #define kmap_px(px) kmap_page_dma(px_base(px))
361 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
363 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
364 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
365 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
366 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
368 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
372 uint64_t * const vaddr = kmap_page_dma(p);
374 for (i = 0; i < 512; i++)
377 kunmap_page_dma(dev, vaddr);
380 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
381 const uint32_t val32)
387 fill_page_dma(dev, p, v);
390 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
392 struct i915_page_scratch *sp;
395 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
397 return ERR_PTR(-ENOMEM);
399 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
405 set_pages_uc(px_page(sp), 1);
410 static void free_scratch_page(struct drm_device *dev,
411 struct i915_page_scratch *sp)
413 set_pages_wb(px_page(sp), 1);
419 static struct i915_page_table *alloc_pt(struct drm_device *dev)
421 struct i915_page_table *pt;
422 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
423 GEN8_PTES : GEN6_PTES;
426 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
428 return ERR_PTR(-ENOMEM);
430 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
436 ret = setup_px(dev, pt);
443 kfree(pt->used_ptes);
450 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
453 kfree(pt->used_ptes);
457 static void gen8_initialize_pt(struct i915_address_space *vm,
458 struct i915_page_table *pt)
460 gen8_pte_t scratch_pte;
462 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
463 I915_CACHE_LLC, true);
465 fill_px(vm->dev, pt, scratch_pte);
468 static void gen6_initialize_pt(struct i915_address_space *vm,
469 struct i915_page_table *pt)
471 gen6_pte_t scratch_pte;
473 WARN_ON(px_dma(vm->scratch_page) == 0);
475 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
476 I915_CACHE_LLC, true, 0);
478 fill32_px(vm->dev, pt, scratch_pte);
481 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
483 struct i915_page_directory *pd;
486 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
488 return ERR_PTR(-ENOMEM);
490 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
491 sizeof(*pd->used_pdes), GFP_KERNEL);
495 ret = setup_px(dev, pd);
502 kfree(pd->used_pdes);
509 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
513 kfree(pd->used_pdes);
518 static void gen8_initialize_pd(struct i915_address_space *vm,
519 struct i915_page_directory *pd)
521 gen8_pde_t scratch_pde;
523 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
525 fill_px(vm->dev, pd, scratch_pde);
528 static int __pdp_init(struct drm_device *dev,
529 struct i915_page_directory_pointer *pdp)
531 size_t pdpes = I915_PDPES_PER_PDP(dev);
533 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
534 sizeof(unsigned long),
536 if (!pdp->used_pdpes)
539 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
541 if (!pdp->page_directory) {
542 kfree(pdp->used_pdpes);
543 /* the PDP might be the statically allocated top level. Keep it
544 * as clean as possible */
545 pdp->used_pdpes = NULL;
552 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
554 kfree(pdp->used_pdpes);
555 kfree(pdp->page_directory);
556 pdp->page_directory = NULL;
560 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
562 struct i915_page_directory_pointer *pdp;
565 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
567 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
569 return ERR_PTR(-ENOMEM);
571 ret = __pdp_init(dev, pdp);
575 ret = setup_px(dev, pdp);
589 static void free_pdp(struct drm_device *dev,
590 struct i915_page_directory_pointer *pdp)
593 if (USES_FULL_48BIT_PPGTT(dev)) {
594 cleanup_px(dev, pdp);
599 static void gen8_initialize_pdp(struct i915_address_space *vm,
600 struct i915_page_directory_pointer *pdp)
602 gen8_ppgtt_pdpe_t scratch_pdpe;
604 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
606 fill_px(vm->dev, pdp, scratch_pdpe);
609 static void gen8_initialize_pml4(struct i915_address_space *vm,
610 struct i915_pml4 *pml4)
612 gen8_ppgtt_pml4e_t scratch_pml4e;
614 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
617 fill_px(vm->dev, pml4, scratch_pml4e);
621 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
622 struct i915_page_directory_pointer *pdp,
623 struct i915_page_directory *pd,
626 gen8_ppgtt_pdpe_t *page_directorypo;
628 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
631 page_directorypo = kmap_px(pdp);
632 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
633 kunmap_px(ppgtt, page_directorypo);
637 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
638 struct i915_pml4 *pml4,
639 struct i915_page_directory_pointer *pdp,
642 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
644 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
645 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
646 kunmap_px(ppgtt, pagemap);
649 /* Broadwell Page Directory Pointer Descriptors */
650 static int gen8_write_pdp(struct drm_i915_gem_request *req,
654 struct intel_engine_cs *ring = req->ring;
659 ret = intel_ring_begin(req, 6);
663 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
664 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
665 intel_ring_emit(ring, upper_32_bits(addr));
666 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
667 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
668 intel_ring_emit(ring, lower_32_bits(addr));
669 intel_ring_advance(ring);
674 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
675 struct drm_i915_gem_request *req)
679 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
680 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
682 ret = gen8_write_pdp(req, i, pd_daddr);
690 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
691 struct drm_i915_gem_request *req)
693 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
696 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
697 struct i915_page_directory_pointer *pdp,
700 gen8_pte_t scratch_pte)
702 struct i915_hw_ppgtt *ppgtt =
703 container_of(vm, struct i915_hw_ppgtt, base);
704 gen8_pte_t *pt_vaddr;
705 unsigned pdpe = gen8_pdpe_index(start);
706 unsigned pde = gen8_pde_index(start);
707 unsigned pte = gen8_pte_index(start);
708 unsigned num_entries = length >> PAGE_SHIFT;
709 unsigned last_pte, i;
714 while (num_entries) {
715 struct i915_page_directory *pd;
716 struct i915_page_table *pt;
718 if (WARN_ON(!pdp->page_directory[pdpe]))
721 pd = pdp->page_directory[pdpe];
723 if (WARN_ON(!pd->page_table[pde]))
726 pt = pd->page_table[pde];
728 if (WARN_ON(!px_page(pt)))
731 last_pte = pte + num_entries;
732 if (last_pte > GEN8_PTES)
733 last_pte = GEN8_PTES;
735 pt_vaddr = kmap_px(pt);
737 for (i = pte; i < last_pte; i++) {
738 pt_vaddr[i] = scratch_pte;
742 kunmap_px(ppgtt, pt);
745 if (++pde == I915_PDES) {
746 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
753 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
758 struct i915_hw_ppgtt *ppgtt =
759 container_of(vm, struct i915_hw_ppgtt, base);
760 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
761 I915_CACHE_LLC, use_scratch);
763 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
764 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
767 uint64_t templ4, pml4e;
768 struct i915_page_directory_pointer *pdp;
770 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
771 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
778 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
779 struct i915_page_directory_pointer *pdp,
780 struct sg_page_iter *sg_iter,
782 enum i915_cache_level cache_level)
784 struct i915_hw_ppgtt *ppgtt =
785 container_of(vm, struct i915_hw_ppgtt, base);
786 gen8_pte_t *pt_vaddr;
787 unsigned pdpe = gen8_pdpe_index(start);
788 unsigned pde = gen8_pde_index(start);
789 unsigned pte = gen8_pte_index(start);
793 while (__sg_page_iter_next(sg_iter)) {
794 if (pt_vaddr == NULL) {
795 struct i915_page_directory *pd = pdp->page_directory[pdpe];
796 struct i915_page_table *pt = pd->page_table[pde];
797 pt_vaddr = kmap_px(pt);
801 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
803 if (++pte == GEN8_PTES) {
804 kunmap_px(ppgtt, pt_vaddr);
806 if (++pde == I915_PDES) {
807 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
816 kunmap_px(ppgtt, pt_vaddr);
819 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
820 struct sg_table *pages,
822 enum i915_cache_level cache_level,
825 struct i915_hw_ppgtt *ppgtt =
826 container_of(vm, struct i915_hw_ppgtt, base);
827 struct sg_page_iter sg_iter;
829 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
831 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
832 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
835 struct i915_page_directory_pointer *pdp;
836 uint64_t templ4, pml4e;
837 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
839 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
840 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
846 static void gen8_free_page_tables(struct drm_device *dev,
847 struct i915_page_directory *pd)
854 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
855 if (WARN_ON(!pd->page_table[i]))
858 free_pt(dev, pd->page_table[i]);
859 pd->page_table[i] = NULL;
863 static int gen8_init_scratch(struct i915_address_space *vm)
865 struct drm_device *dev = vm->dev;
867 vm->scratch_page = alloc_scratch_page(dev);
868 if (IS_ERR(vm->scratch_page))
869 return PTR_ERR(vm->scratch_page);
871 vm->scratch_pt = alloc_pt(dev);
872 if (IS_ERR(vm->scratch_pt)) {
873 free_scratch_page(dev, vm->scratch_page);
874 return PTR_ERR(vm->scratch_pt);
877 vm->scratch_pd = alloc_pd(dev);
878 if (IS_ERR(vm->scratch_pd)) {
879 free_pt(dev, vm->scratch_pt);
880 free_scratch_page(dev, vm->scratch_page);
881 return PTR_ERR(vm->scratch_pd);
884 if (USES_FULL_48BIT_PPGTT(dev)) {
885 vm->scratch_pdp = alloc_pdp(dev);
886 if (IS_ERR(vm->scratch_pdp)) {
887 free_pd(dev, vm->scratch_pd);
888 free_pt(dev, vm->scratch_pt);
889 free_scratch_page(dev, vm->scratch_page);
890 return PTR_ERR(vm->scratch_pdp);
894 gen8_initialize_pt(vm, vm->scratch_pt);
895 gen8_initialize_pd(vm, vm->scratch_pd);
896 if (USES_FULL_48BIT_PPGTT(dev))
897 gen8_initialize_pdp(vm, vm->scratch_pdp);
902 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
904 enum vgt_g2v_type msg;
905 struct drm_device *dev = ppgtt->base.dev;
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 unsigned int offset = vgtif_reg(pdp0_lo);
910 if (USES_FULL_48BIT_PPGTT(dev)) {
911 u64 daddr = px_dma(&ppgtt->pml4);
913 I915_WRITE(offset, lower_32_bits(daddr));
914 I915_WRITE(offset + 4, upper_32_bits(daddr));
916 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
917 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
919 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
920 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
922 I915_WRITE(offset, lower_32_bits(daddr));
923 I915_WRITE(offset + 4, upper_32_bits(daddr));
928 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
929 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
932 I915_WRITE(vgtif_reg(g2v_notify), msg);
937 static void gen8_free_scratch(struct i915_address_space *vm)
939 struct drm_device *dev = vm->dev;
941 if (USES_FULL_48BIT_PPGTT(dev))
942 free_pdp(dev, vm->scratch_pdp);
943 free_pd(dev, vm->scratch_pd);
944 free_pt(dev, vm->scratch_pt);
945 free_scratch_page(dev, vm->scratch_page);
948 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
949 struct i915_page_directory_pointer *pdp)
953 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
954 if (WARN_ON(!pdp->page_directory[i]))
957 gen8_free_page_tables(dev, pdp->page_directory[i]);
958 free_pd(dev, pdp->page_directory[i]);
964 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
968 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
969 if (WARN_ON(!ppgtt->pml4.pdps[i]))
972 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
975 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
978 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
980 struct i915_hw_ppgtt *ppgtt =
981 container_of(vm, struct i915_hw_ppgtt, base);
983 if (intel_vgpu_active(vm->dev))
984 gen8_ppgtt_notify_vgt(ppgtt, false);
986 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
987 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
989 gen8_ppgtt_cleanup_4lvl(ppgtt);
991 gen8_free_scratch(vm);
995 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
996 * @vm: Master vm structure.
997 * @pd: Page directory for this address range.
998 * @start: Starting virtual address to begin allocations.
999 * @length: Size of the allocations.
1000 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1001 * caller to free on error.
1003 * Allocate the required number of page tables. Extremely similar to
1004 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1005 * the page directory boundary (instead of the page directory pointer). That
1006 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1007 * possible, and likely that the caller will need to use multiple calls of this
1008 * function to achieve the appropriate allocation.
1010 * Return: 0 if success; negative error code otherwise.
1012 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1013 struct i915_page_directory *pd,
1016 unsigned long *new_pts)
1018 struct drm_device *dev = vm->dev;
1019 struct i915_page_table *pt;
1023 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
1024 /* Don't reallocate page tables */
1025 if (test_bit(pde, pd->used_pdes)) {
1026 /* Scratch is never allocated this way */
1027 WARN_ON(pt == vm->scratch_pt);
1035 gen8_initialize_pt(vm, pt);
1036 pd->page_table[pde] = pt;
1037 __set_bit(pde, new_pts);
1038 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1044 for_each_set_bit(pde, new_pts, I915_PDES)
1045 free_pt(dev, pd->page_table[pde]);
1051 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1052 * @vm: Master vm structure.
1053 * @pdp: Page directory pointer for this address range.
1054 * @start: Starting virtual address to begin allocations.
1055 * @length: Size of the allocations.
1056 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1057 * caller to free on error.
1059 * Allocate the required number of page directories starting at the pde index of
1060 * @start, and ending at the pde index @start + @length. This function will skip
1061 * over already allocated page directories within the range, and only allocate
1062 * new ones, setting the appropriate pointer within the pdp as well as the
1063 * correct position in the bitmap @new_pds.
1065 * The function will only allocate the pages within the range for a give page
1066 * directory pointer. In other words, if @start + @length straddles a virtually
1067 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1068 * required by the caller, This is not currently possible, and the BUG in the
1069 * code will prevent it.
1071 * Return: 0 if success; negative error code otherwise.
1074 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1075 struct i915_page_directory_pointer *pdp,
1078 unsigned long *new_pds)
1080 struct drm_device *dev = vm->dev;
1081 struct i915_page_directory *pd;
1084 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1086 WARN_ON(!bitmap_empty(new_pds, pdpes));
1088 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1089 if (test_bit(pdpe, pdp->used_pdpes))
1096 gen8_initialize_pd(vm, pd);
1097 pdp->page_directory[pdpe] = pd;
1098 __set_bit(pdpe, new_pds);
1099 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1105 for_each_set_bit(pdpe, new_pds, pdpes)
1106 free_pd(dev, pdp->page_directory[pdpe]);
1112 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1113 * @vm: Master vm structure.
1114 * @pml4: Page map level 4 for this address range.
1115 * @start: Starting virtual address to begin allocations.
1116 * @length: Size of the allocations.
1117 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1118 * caller to free on error.
1120 * Allocate the required number of page directory pointers. Extremely similar to
1121 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1122 * The main difference is here we are limited by the pml4 boundary (instead of
1123 * the page directory pointer).
1125 * Return: 0 if success; negative error code otherwise.
1128 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1129 struct i915_pml4 *pml4,
1132 unsigned long *new_pdps)
1134 struct drm_device *dev = vm->dev;
1135 struct i915_page_directory_pointer *pdp;
1139 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1141 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1142 if (!test_bit(pml4e, pml4->used_pml4es)) {
1143 pdp = alloc_pdp(dev);
1147 gen8_initialize_pdp(vm, pdp);
1148 pml4->pdps[pml4e] = pdp;
1149 __set_bit(pml4e, new_pdps);
1150 trace_i915_page_directory_pointer_entry_alloc(vm,
1160 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1161 free_pdp(dev, pml4->pdps[pml4e]);
1167 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1173 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1174 * of these are based on the number of PDPEs in the system.
1177 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1178 unsigned long **new_pts,
1184 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1188 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1199 free_gen8_temp_bitmaps(pds, pts);
1203 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1204 * the page table structures, we mark them dirty so that
1205 * context switching/execlist queuing code takes extra steps
1206 * to ensure that tlbs are flushed.
1208 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1210 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1213 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1214 struct i915_page_directory_pointer *pdp,
1218 struct i915_hw_ppgtt *ppgtt =
1219 container_of(vm, struct i915_hw_ppgtt, base);
1220 unsigned long *new_page_dirs, *new_page_tables;
1221 struct drm_device *dev = vm->dev;
1222 struct i915_page_directory *pd;
1223 const uint64_t orig_start = start;
1224 const uint64_t orig_length = length;
1227 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1230 /* Wrap is never okay since we can only represent 48b, and we don't
1231 * actually use the other side of the canonical address space.
1233 if (WARN_ON(start + length < start))
1236 if (WARN_ON(start + length > vm->total))
1239 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1243 /* Do the allocations first so we can easily bail out */
1244 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1247 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1251 /* For every page directory referenced, allocate page tables */
1252 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1253 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1254 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1260 length = orig_length;
1262 /* Allocations have completed successfully, so set the bitmaps, and do
1264 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1265 gen8_pde_t *const page_directory = kmap_px(pd);
1266 struct i915_page_table *pt;
1267 uint64_t pd_len = length;
1268 uint64_t pd_start = start;
1271 /* Every pd should be allocated, we just did that above. */
1274 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1275 /* Same reasoning as pd */
1278 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1280 /* Set our used ptes within the page table */
1281 bitmap_set(pt->used_ptes,
1282 gen8_pte_index(pd_start),
1283 gen8_pte_count(pd_start, pd_len));
1285 /* Our pde is now pointing to the pagetable, pt */
1286 __set_bit(pde, pd->used_pdes);
1288 /* Map the PDE to the page table */
1289 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1291 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1292 gen8_pte_index(start),
1293 gen8_pte_count(start, length),
1296 /* NB: We haven't yet mapped ptes to pages. At this
1297 * point we're still relying on insert_entries() */
1300 kunmap_px(ppgtt, page_directory);
1301 __set_bit(pdpe, pdp->used_pdpes);
1302 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1305 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1306 mark_tlbs_dirty(ppgtt);
1311 for_each_set_bit(temp, new_page_tables + pdpe *
1312 BITS_TO_LONGS(I915_PDES), I915_PDES)
1313 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1316 for_each_set_bit(pdpe, new_page_dirs, pdpes)
1317 free_pd(dev, pdp->page_directory[pdpe]);
1319 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1320 mark_tlbs_dirty(ppgtt);
1324 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1325 struct i915_pml4 *pml4,
1329 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1330 struct i915_hw_ppgtt *ppgtt =
1331 container_of(vm, struct i915_hw_ppgtt, base);
1332 struct i915_page_directory_pointer *pdp;
1333 uint64_t temp, pml4e;
1336 /* Do the pml4 allocations first, so we don't need to track the newly
1337 * allocated tables below the pdp */
1338 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1340 /* The pagedirectory and pagetable allocations are done in the shared 3
1341 * and 4 level code. Just allocate the pdps.
1343 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1348 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1349 "The allocation has spanned more than 512GB. "
1350 "It is highly likely this is incorrect.");
1352 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1355 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1359 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1362 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1363 GEN8_PML4ES_PER_PML4);
1368 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1369 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1374 static int gen8_alloc_va_range(struct i915_address_space *vm,
1375 uint64_t start, uint64_t length)
1377 struct i915_hw_ppgtt *ppgtt =
1378 container_of(vm, struct i915_hw_ppgtt, base);
1380 if (USES_FULL_48BIT_PPGTT(vm->dev))
1381 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1383 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1386 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1387 uint64_t start, uint64_t length,
1388 gen8_pte_t scratch_pte,
1391 struct i915_page_directory *pd;
1395 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1396 struct i915_page_table *pt;
1397 uint64_t pd_len = length;
1398 uint64_t pd_start = start;
1401 if (!test_bit(pdpe, pdp->used_pdpes))
1404 seq_printf(m, "\tPDPE #%d\n", pdpe);
1405 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1407 gen8_pte_t *pt_vaddr;
1409 if (!test_bit(pde, pd->used_pdes))
1412 pt_vaddr = kmap_px(pt);
1413 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1415 (pdpe << GEN8_PDPE_SHIFT) |
1416 (pde << GEN8_PDE_SHIFT) |
1417 (pte << GEN8_PTE_SHIFT);
1421 for (i = 0; i < 4; i++)
1422 if (pt_vaddr[pte + i] != scratch_pte)
1427 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1428 for (i = 0; i < 4; i++) {
1429 if (pt_vaddr[pte + i] != scratch_pte)
1430 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1432 seq_puts(m, " SCRATCH ");
1436 /* don't use kunmap_px, it could trigger
1437 * an unnecessary flush.
1439 kunmap_atomic(pt_vaddr);
1444 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1446 struct i915_address_space *vm = &ppgtt->base;
1447 uint64_t start = ppgtt->base.start;
1448 uint64_t length = ppgtt->base.total;
1449 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1450 I915_CACHE_LLC, true);
1452 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1453 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1455 uint64_t templ4, pml4e;
1456 struct i915_pml4 *pml4 = &ppgtt->pml4;
1457 struct i915_page_directory_pointer *pdp;
1459 gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
1460 if (!test_bit(pml4e, pml4->used_pml4es))
1463 seq_printf(m, " PML4E #%llu\n", pml4e);
1464 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1469 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1471 unsigned long *new_page_dirs, *new_page_tables;
1472 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1475 /* We allocate temp bitmap for page tables for no gain
1476 * but as this is for init only, lets keep the things simple
1478 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1482 /* Allocate for all pdps regardless of how the ppgtt
1485 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1489 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1491 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1497 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1498 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1499 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1503 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1507 ret = gen8_init_scratch(&ppgtt->base);
1511 ppgtt->base.start = 0;
1512 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1513 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1514 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1515 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1516 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1517 ppgtt->base.bind_vma = ppgtt_bind_vma;
1518 ppgtt->debug_dump = gen8_dump_ppgtt;
1520 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1521 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1525 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1527 ppgtt->base.total = 1ULL << 48;
1528 ppgtt->switch_mm = gen8_48b_mm_switch;
1530 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1534 ppgtt->base.total = 1ULL << 32;
1535 ppgtt->switch_mm = gen8_legacy_mm_switch;
1536 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1540 if (intel_vgpu_active(ppgtt->base.dev)) {
1541 ret = gen8_preallocate_top_level_pdps(ppgtt);
1547 if (intel_vgpu_active(ppgtt->base.dev))
1548 gen8_ppgtt_notify_vgt(ppgtt, true);
1553 gen8_free_scratch(&ppgtt->base);
1557 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1559 struct i915_address_space *vm = &ppgtt->base;
1560 struct i915_page_table *unused;
1561 gen6_pte_t scratch_pte;
1563 uint32_t pte, pde, temp;
1564 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1566 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1567 I915_CACHE_LLC, true, 0);
1569 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1571 gen6_pte_t *pt_vaddr;
1572 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1573 pd_entry = readl(ppgtt->pd_addr + pde);
1574 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1576 if (pd_entry != expected)
1577 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1581 seq_printf(m, "\tPDE: %x\n", pd_entry);
1583 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1585 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1587 (pde * PAGE_SIZE * GEN6_PTES) +
1591 for (i = 0; i < 4; i++)
1592 if (pt_vaddr[pte + i] != scratch_pte)
1597 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1598 for (i = 0; i < 4; i++) {
1599 if (pt_vaddr[pte + i] != scratch_pte)
1600 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1602 seq_puts(m, " SCRATCH ");
1606 kunmap_px(ppgtt, pt_vaddr);
1610 /* Write pde (index) from the page directory @pd to the page table @pt */
1611 static void gen6_write_pde(struct i915_page_directory *pd,
1612 const int pde, struct i915_page_table *pt)
1614 /* Caller needs to make sure the write completes if necessary */
1615 struct i915_hw_ppgtt *ppgtt =
1616 container_of(pd, struct i915_hw_ppgtt, pd);
1619 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1620 pd_entry |= GEN6_PDE_VALID;
1622 writel(pd_entry, ppgtt->pd_addr + pde);
1625 /* Write all the page tables found in the ppgtt structure to incrementing page
1627 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1628 struct i915_page_directory *pd,
1629 uint32_t start, uint32_t length)
1631 struct i915_page_table *pt;
1634 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1635 gen6_write_pde(pd, pde, pt);
1637 /* Make sure write is complete before other code can use this page
1638 * table. Also require for WC mapped PTEs */
1639 readl(dev_priv->gtt.gsm);
1642 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1644 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1646 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1649 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1650 struct drm_i915_gem_request *req)
1652 struct intel_engine_cs *ring = req->ring;
1655 /* NB: TLBs must be flushed and invalidated before a switch */
1656 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1660 ret = intel_ring_begin(req, 6);
1664 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1665 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1666 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1667 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1668 intel_ring_emit(ring, get_pd_offset(ppgtt));
1669 intel_ring_emit(ring, MI_NOOP);
1670 intel_ring_advance(ring);
1675 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1676 struct drm_i915_gem_request *req)
1678 struct intel_engine_cs *ring = req->ring;
1679 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1681 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1682 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1686 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1687 struct drm_i915_gem_request *req)
1689 struct intel_engine_cs *ring = req->ring;
1692 /* NB: TLBs must be flushed and invalidated before a switch */
1693 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1697 ret = intel_ring_begin(req, 6);
1701 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1702 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1703 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1704 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1705 intel_ring_emit(ring, get_pd_offset(ppgtt));
1706 intel_ring_emit(ring, MI_NOOP);
1707 intel_ring_advance(ring);
1709 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1710 if (ring->id != RCS) {
1711 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1719 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1720 struct drm_i915_gem_request *req)
1722 struct intel_engine_cs *ring = req->ring;
1723 struct drm_device *dev = ppgtt->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1727 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1728 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1730 POSTING_READ(RING_PP_DIR_DCLV(ring));
1735 static void gen8_ppgtt_enable(struct drm_device *dev)
1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 struct intel_engine_cs *ring;
1741 for_each_ring(ring, dev_priv, j) {
1742 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1743 I915_WRITE(RING_MODE_GEN7(ring),
1744 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1748 static void gen7_ppgtt_enable(struct drm_device *dev)
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 struct intel_engine_cs *ring;
1752 uint32_t ecochk, ecobits;
1755 ecobits = I915_READ(GAC_ECO_BITS);
1756 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1758 ecochk = I915_READ(GAM_ECOCHK);
1759 if (IS_HASWELL(dev)) {
1760 ecochk |= ECOCHK_PPGTT_WB_HSW;
1762 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1763 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1765 I915_WRITE(GAM_ECOCHK, ecochk);
1767 for_each_ring(ring, dev_priv, i) {
1768 /* GFX_MODE is per-ring on gen7+ */
1769 I915_WRITE(RING_MODE_GEN7(ring),
1770 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1774 static void gen6_ppgtt_enable(struct drm_device *dev)
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 uint32_t ecochk, gab_ctl, ecobits;
1779 ecobits = I915_READ(GAC_ECO_BITS);
1780 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1781 ECOBITS_PPGTT_CACHE64B);
1783 gab_ctl = I915_READ(GAB_CTL);
1784 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1786 ecochk = I915_READ(GAM_ECOCHK);
1787 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1789 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1792 /* PPGTT support for Sandybdrige/Gen6 and later */
1793 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1798 struct i915_hw_ppgtt *ppgtt =
1799 container_of(vm, struct i915_hw_ppgtt, base);
1800 gen6_pte_t *pt_vaddr, scratch_pte;
1801 unsigned first_entry = start >> PAGE_SHIFT;
1802 unsigned num_entries = length >> PAGE_SHIFT;
1803 unsigned act_pt = first_entry / GEN6_PTES;
1804 unsigned first_pte = first_entry % GEN6_PTES;
1805 unsigned last_pte, i;
1807 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1808 I915_CACHE_LLC, true, 0);
1810 while (num_entries) {
1811 last_pte = first_pte + num_entries;
1812 if (last_pte > GEN6_PTES)
1813 last_pte = GEN6_PTES;
1815 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1817 for (i = first_pte; i < last_pte; i++)
1818 pt_vaddr[i] = scratch_pte;
1820 kunmap_px(ppgtt, pt_vaddr);
1822 num_entries -= last_pte - first_pte;
1828 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1829 struct sg_table *pages,
1831 enum i915_cache_level cache_level, u32 flags)
1833 struct i915_hw_ppgtt *ppgtt =
1834 container_of(vm, struct i915_hw_ppgtt, base);
1835 gen6_pte_t *pt_vaddr;
1836 unsigned first_entry = start >> PAGE_SHIFT;
1837 unsigned act_pt = first_entry / GEN6_PTES;
1838 unsigned act_pte = first_entry % GEN6_PTES;
1839 struct sg_page_iter sg_iter;
1842 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1843 if (pt_vaddr == NULL)
1844 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1847 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1848 cache_level, true, flags);
1850 if (++act_pte == GEN6_PTES) {
1851 kunmap_px(ppgtt, pt_vaddr);
1858 kunmap_px(ppgtt, pt_vaddr);
1861 static int gen6_alloc_va_range(struct i915_address_space *vm,
1862 uint64_t start_in, uint64_t length_in)
1864 DECLARE_BITMAP(new_page_tables, I915_PDES);
1865 struct drm_device *dev = vm->dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 struct i915_hw_ppgtt *ppgtt =
1868 container_of(vm, struct i915_hw_ppgtt, base);
1869 struct i915_page_table *pt;
1870 uint32_t start, length, start_save, length_save;
1874 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1877 start = start_save = start_in;
1878 length = length_save = length_in;
1880 bitmap_zero(new_page_tables, I915_PDES);
1882 /* The allocation is done in two stages so that we can bail out with
1883 * minimal amount of pain. The first stage finds new page tables that
1884 * need allocation. The second stage marks use ptes within the page
1887 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1888 if (pt != vm->scratch_pt) {
1889 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1893 /* We've already allocated a page table */
1894 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1902 gen6_initialize_pt(vm, pt);
1904 ppgtt->pd.page_table[pde] = pt;
1905 __set_bit(pde, new_page_tables);
1906 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1910 length = length_save;
1912 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1913 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1915 bitmap_zero(tmp_bitmap, GEN6_PTES);
1916 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1917 gen6_pte_count(start, length));
1919 if (__test_and_clear_bit(pde, new_page_tables))
1920 gen6_write_pde(&ppgtt->pd, pde, pt);
1922 trace_i915_page_table_entry_map(vm, pde, pt,
1923 gen6_pte_index(start),
1924 gen6_pte_count(start, length),
1926 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1930 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1932 /* Make sure write is complete before other code can use this page
1933 * table. Also require for WC mapped PTEs */
1934 readl(dev_priv->gtt.gsm);
1936 mark_tlbs_dirty(ppgtt);
1940 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1941 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1943 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1944 free_pt(vm->dev, pt);
1947 mark_tlbs_dirty(ppgtt);
1951 static int gen6_init_scratch(struct i915_address_space *vm)
1953 struct drm_device *dev = vm->dev;
1955 vm->scratch_page = alloc_scratch_page(dev);
1956 if (IS_ERR(vm->scratch_page))
1957 return PTR_ERR(vm->scratch_page);
1959 vm->scratch_pt = alloc_pt(dev);
1960 if (IS_ERR(vm->scratch_pt)) {
1961 free_scratch_page(dev, vm->scratch_page);
1962 return PTR_ERR(vm->scratch_pt);
1965 gen6_initialize_pt(vm, vm->scratch_pt);
1970 static void gen6_free_scratch(struct i915_address_space *vm)
1972 struct drm_device *dev = vm->dev;
1974 free_pt(dev, vm->scratch_pt);
1975 free_scratch_page(dev, vm->scratch_page);
1978 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1980 struct i915_hw_ppgtt *ppgtt =
1981 container_of(vm, struct i915_hw_ppgtt, base);
1982 struct i915_page_table *pt;
1985 drm_mm_remove_node(&ppgtt->node);
1987 gen6_for_all_pdes(pt, ppgtt, pde) {
1988 if (pt != vm->scratch_pt)
1989 free_pt(ppgtt->base.dev, pt);
1992 gen6_free_scratch(vm);
1995 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1997 struct i915_address_space *vm = &ppgtt->base;
1998 struct drm_device *dev = ppgtt->base.dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 bool retried = false;
2003 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2004 * allocator works in address space sizes, so it's multiplied by page
2005 * size. We allocate at the top of the GTT to avoid fragmentation.
2007 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
2009 ret = gen6_init_scratch(vm);
2014 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
2015 &ppgtt->node, GEN6_PD_SIZE,
2017 0, dev_priv->gtt.base.total,
2019 if (ret == -ENOSPC && !retried) {
2020 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
2021 GEN6_PD_SIZE, GEN6_PD_ALIGN,
2023 0, dev_priv->gtt.base.total,
2036 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
2037 DRM_DEBUG("Forced to use aperture for PDEs\n");
2042 gen6_free_scratch(vm);
2046 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2048 return gen6_ppgtt_allocate_page_directories(ppgtt);
2051 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2052 uint64_t start, uint64_t length)
2054 struct i915_page_table *unused;
2057 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
2058 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2061 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2063 struct drm_device *dev = ppgtt->base.dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2067 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
2069 ppgtt->switch_mm = gen6_mm_switch;
2070 } else if (IS_HASWELL(dev)) {
2071 ppgtt->switch_mm = hsw_mm_switch;
2072 } else if (IS_GEN7(dev)) {
2073 ppgtt->switch_mm = gen7_mm_switch;
2077 if (intel_vgpu_active(dev))
2078 ppgtt->switch_mm = vgpu_mm_switch;
2080 ret = gen6_ppgtt_alloc(ppgtt);
2084 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2085 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2086 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2087 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2088 ppgtt->base.bind_vma = ppgtt_bind_vma;
2089 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2090 ppgtt->base.start = 0;
2091 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2092 ppgtt->debug_dump = gen6_dump_ppgtt;
2094 ppgtt->pd.base.ggtt_offset =
2095 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2097 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
2098 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2100 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2102 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2104 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2105 ppgtt->node.size >> 20,
2106 ppgtt->node.start / PAGE_SIZE);
2108 DRM_DEBUG("Adding PPGTT at offset %x\n",
2109 ppgtt->pd.base.ggtt_offset << 10);
2114 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2116 ppgtt->base.dev = dev;
2118 if (INTEL_INFO(dev)->gen < 8)
2119 return gen6_ppgtt_init(ppgtt);
2121 return gen8_ppgtt_init(ppgtt);
2124 static void i915_address_space_init(struct i915_address_space *vm,
2125 struct drm_i915_private *dev_priv)
2127 drm_mm_init(&vm->mm, vm->start, vm->total);
2128 vm->dev = dev_priv->dev;
2129 INIT_LIST_HEAD(&vm->active_list);
2130 INIT_LIST_HEAD(&vm->inactive_list);
2131 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2134 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2139 ret = __hw_ppgtt_init(dev, ppgtt);
2141 kref_init(&ppgtt->ref);
2142 i915_address_space_init(&ppgtt->base, dev_priv);
2148 int i915_ppgtt_init_hw(struct drm_device *dev)
2150 /* In the case of execlists, PPGTT is enabled by the context descriptor
2151 * and the PDPs are contained within the context itself. We don't
2152 * need to do anything here. */
2153 if (i915.enable_execlists)
2156 if (!USES_PPGTT(dev))
2160 gen6_ppgtt_enable(dev);
2161 else if (IS_GEN7(dev))
2162 gen7_ppgtt_enable(dev);
2163 else if (INTEL_INFO(dev)->gen >= 8)
2164 gen8_ppgtt_enable(dev);
2166 MISSING_CASE(INTEL_INFO(dev)->gen);
2171 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
2173 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
2174 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2176 if (i915.enable_execlists)
2182 return ppgtt->switch_mm(ppgtt, req);
2185 struct i915_hw_ppgtt *
2186 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2188 struct i915_hw_ppgtt *ppgtt;
2191 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2193 return ERR_PTR(-ENOMEM);
2195 ret = i915_ppgtt_init(dev, ppgtt);
2198 return ERR_PTR(ret);
2201 ppgtt->file_priv = fpriv;
2203 trace_i915_ppgtt_create(&ppgtt->base);
2208 void i915_ppgtt_release(struct kref *kref)
2210 struct i915_hw_ppgtt *ppgtt =
2211 container_of(kref, struct i915_hw_ppgtt, ref);
2213 trace_i915_ppgtt_release(&ppgtt->base);
2215 /* vmas should already be unbound */
2216 WARN_ON(!list_empty(&ppgtt->base.active_list));
2217 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2219 list_del(&ppgtt->base.global_link);
2220 drm_mm_takedown(&ppgtt->base.mm);
2222 ppgtt->base.cleanup(&ppgtt->base);
2226 extern int intel_iommu_gfx_mapped;
2227 /* Certain Gen5 chipsets require require idling the GPU before
2228 * unmapping anything from the GTT when VT-d is enabled.
2230 static bool needs_idle_maps(struct drm_device *dev)
2232 #ifdef CONFIG_INTEL_IOMMU
2233 /* Query intel_iommu to see if we need the workaround. Presumably that
2236 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2242 static bool do_idling(struct drm_i915_private *dev_priv)
2244 bool ret = dev_priv->mm.interruptible;
2246 if (unlikely(dev_priv->gtt.do_idle_maps)) {
2247 dev_priv->mm.interruptible = false;
2248 if (i915_gpu_idle(dev_priv->dev)) {
2249 DRM_ERROR("Couldn't idle GPU\n");
2250 /* Wait a bit, in hopes it avoids the hang */
2258 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2260 if (unlikely(dev_priv->gtt.do_idle_maps))
2261 dev_priv->mm.interruptible = interruptible;
2264 void i915_check_and_clear_faults(struct drm_device *dev)
2266 struct drm_i915_private *dev_priv = dev->dev_private;
2267 struct intel_engine_cs *ring;
2270 if (INTEL_INFO(dev)->gen < 6)
2273 for_each_ring(ring, dev_priv, i) {
2275 fault_reg = I915_READ(RING_FAULT_REG(ring));
2276 if (fault_reg & RING_FAULT_VALID) {
2277 DRM_DEBUG_DRIVER("Unexpected fault\n"
2279 "\tAddress space: %s\n"
2282 fault_reg & PAGE_MASK,
2283 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2284 RING_FAULT_SRCID(fault_reg),
2285 RING_FAULT_FAULT_TYPE(fault_reg));
2286 I915_WRITE(RING_FAULT_REG(ring),
2287 fault_reg & ~RING_FAULT_VALID);
2290 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
2293 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2295 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2296 intel_gtt_chipset_flush();
2298 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2299 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2303 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2307 /* Don't bother messing with faults pre GEN6 as we have little
2308 * documentation supporting that it's a good idea.
2310 if (INTEL_INFO(dev)->gen < 6)
2313 i915_check_and_clear_faults(dev);
2315 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2316 dev_priv->gtt.base.start,
2317 dev_priv->gtt.base.total,
2320 i915_ggtt_flush(dev_priv);
2323 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2325 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2326 obj->pages->sgl, obj->pages->nents,
2327 PCI_DMA_BIDIRECTIONAL))
2333 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2338 iowrite32((u32)pte, addr);
2339 iowrite32(pte >> 32, addr + 4);
2343 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2344 struct sg_table *st,
2346 enum i915_cache_level level, u32 unused)
2348 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2349 unsigned first_entry = start >> PAGE_SHIFT;
2350 gen8_pte_t __iomem *gtt_entries =
2351 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2353 struct sg_page_iter sg_iter;
2354 dma_addr_t addr = 0; /* shut up gcc */
2356 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2357 addr = sg_dma_address(sg_iter.sg) +
2358 (sg_iter.sg_pgoffset << PAGE_SHIFT);
2359 gen8_set_pte(>t_entries[i],
2360 gen8_pte_encode(addr, level, true));
2365 * XXX: This serves as a posting read to make sure that the PTE has
2366 * actually been updated. There is some concern that even though
2367 * registers and PTEs are within the same BAR that they are potentially
2368 * of NUMA access patterns. Therefore, even with the way we assume
2369 * hardware should work, we must keep this posting read for paranoia.
2372 WARN_ON(readq(>t_entries[i-1])
2373 != gen8_pte_encode(addr, level, true));
2375 /* This next bit makes the above posting read even more important. We
2376 * want to flush the TLBs only after we're certain all the PTE updates
2379 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2380 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2384 * Binds an object into the global gtt with the specified cache level. The object
2385 * will be accessible to the GPU via commands whose operands reference offsets
2386 * within the global GTT as well as accessible by the GPU through the GMADR
2387 * mapped BAR (dev_priv->mm.gtt->gtt).
2389 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2390 struct sg_table *st,
2392 enum i915_cache_level level, u32 flags)
2394 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2395 unsigned first_entry = start >> PAGE_SHIFT;
2396 gen6_pte_t __iomem *gtt_entries =
2397 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2399 struct sg_page_iter sg_iter;
2400 dma_addr_t addr = 0;
2402 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2403 addr = sg_page_iter_dma_address(&sg_iter);
2404 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
2408 /* XXX: This serves as a posting read to make sure that the PTE has
2409 * actually been updated. There is some concern that even though
2410 * registers and PTEs are within the same BAR that they are potentially
2411 * of NUMA access patterns. Therefore, even with the way we assume
2412 * hardware should work, we must keep this posting read for paranoia.
2415 unsigned long gtt = readl(>t_entries[i-1]);
2416 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2419 /* This next bit makes the above posting read even more important. We
2420 * want to flush the TLBs only after we're certain all the PTE updates
2423 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2424 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2427 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2432 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2433 unsigned first_entry = start >> PAGE_SHIFT;
2434 unsigned num_entries = length >> PAGE_SHIFT;
2435 gen8_pte_t scratch_pte, __iomem *gtt_base =
2436 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2437 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2440 if (WARN(num_entries > max_entries,
2441 "First entry = %d; Num entries = %d (max=%d)\n",
2442 first_entry, num_entries, max_entries))
2443 num_entries = max_entries;
2445 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2448 for (i = 0; i < num_entries; i++)
2449 gen8_set_pte(>t_base[i], scratch_pte);
2453 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2458 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2459 unsigned first_entry = start >> PAGE_SHIFT;
2460 unsigned num_entries = length >> PAGE_SHIFT;
2461 gen6_pte_t scratch_pte, __iomem *gtt_base =
2462 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2463 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2466 if (WARN(num_entries > max_entries,
2467 "First entry = %d; Num entries = %d (max=%d)\n",
2468 first_entry, num_entries, max_entries))
2469 num_entries = max_entries;
2471 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2472 I915_CACHE_LLC, use_scratch, 0);
2474 for (i = 0; i < num_entries; i++)
2475 iowrite32(scratch_pte, >t_base[i]);
2479 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2480 struct sg_table *pages,
2482 enum i915_cache_level cache_level, u32 unused)
2484 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2485 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2487 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2491 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2496 unsigned first_entry = start >> PAGE_SHIFT;
2497 unsigned num_entries = length >> PAGE_SHIFT;
2498 intel_gtt_clear_range(first_entry, num_entries);
2501 static int ggtt_bind_vma(struct i915_vma *vma,
2502 enum i915_cache_level cache_level,
2505 struct drm_device *dev = vma->vm->dev;
2506 struct drm_i915_private *dev_priv = dev->dev_private;
2507 struct drm_i915_gem_object *obj = vma->obj;
2508 struct sg_table *pages = obj->pages;
2512 ret = i915_get_ggtt_vma_pages(vma);
2515 pages = vma->ggtt_view.pages;
2517 /* Currently applicable only to VLV */
2519 pte_flags |= PTE_READ_ONLY;
2522 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
2523 vma->vm->insert_entries(vma->vm, pages,
2525 cache_level, pte_flags);
2527 /* Note the inconsistency here is due to absence of the
2528 * aliasing ppgtt on gen4 and earlier. Though we always
2529 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2530 * without the appgtt, we cannot honour that request and so
2531 * must substitute it with a global binding. Since we do this
2532 * behind the upper layers back, we need to explicitly set
2533 * the bound flag ourselves.
2535 vma->bound |= GLOBAL_BIND;
2539 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
2540 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2541 appgtt->base.insert_entries(&appgtt->base, pages,
2543 cache_level, pte_flags);
2549 static void ggtt_unbind_vma(struct i915_vma *vma)
2551 struct drm_device *dev = vma->vm->dev;
2552 struct drm_i915_private *dev_priv = dev->dev_private;
2553 struct drm_i915_gem_object *obj = vma->obj;
2554 const uint64_t size = min_t(uint64_t,
2558 if (vma->bound & GLOBAL_BIND) {
2559 vma->vm->clear_range(vma->vm,
2565 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2566 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2568 appgtt->base.clear_range(&appgtt->base,
2575 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2577 struct drm_device *dev = obj->base.dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2581 interruptible = do_idling(dev_priv);
2583 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2584 PCI_DMA_BIDIRECTIONAL);
2586 undo_idling(dev_priv, interruptible);
2589 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2590 unsigned long color,
2594 if (node->color != color)
2597 if (!list_empty(&node->node_list)) {
2598 node = list_entry(node->node_list.next,
2601 if (node->allocated && node->color != color)
2606 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2611 /* Let GEM Manage all of the aperture.
2613 * However, leave one page at the end still bound to the scratch page.
2614 * There are a number of places where the hardware apparently prefetches
2615 * past the end of the object, and we've seen multiple hangs with the
2616 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2617 * aperture. One page should be enough to keep any prefetching inside
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2622 struct drm_mm_node *entry;
2623 struct drm_i915_gem_object *obj;
2624 unsigned long hole_start, hole_end;
2627 BUG_ON(mappable_end > end);
2629 ggtt_vm->start = start;
2631 /* Subtract the guard page before address space initialization to
2632 * shrink the range used by drm_mm */
2633 ggtt_vm->total = end - start - PAGE_SIZE;
2634 i915_address_space_init(ggtt_vm, dev_priv);
2635 ggtt_vm->total += PAGE_SIZE;
2637 if (intel_vgpu_active(dev)) {
2638 ret = intel_vgt_balloon(dev);
2644 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
2646 /* Mark any preallocated objects as occupied */
2647 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2648 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2650 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2651 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2653 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2654 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2656 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2659 vma->bound |= GLOBAL_BIND;
2662 /* Clear any non-preallocated blocks */
2663 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2664 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2665 hole_start, hole_end);
2666 ggtt_vm->clear_range(ggtt_vm, hole_start,
2667 hole_end - hole_start, true);
2670 /* And finally clear the reserved guard page */
2671 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2673 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2674 struct i915_hw_ppgtt *ppgtt;
2676 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2680 ret = __hw_ppgtt_init(dev, ppgtt);
2682 ppgtt->base.cleanup(&ppgtt->base);
2687 if (ppgtt->base.allocate_va_range)
2688 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2691 ppgtt->base.cleanup(&ppgtt->base);
2696 ppgtt->base.clear_range(&ppgtt->base,
2701 dev_priv->mm.aliasing_ppgtt = ppgtt;
2707 void i915_gem_init_global_gtt(struct drm_device *dev)
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 u64 gtt_size, mappable_size;
2712 gtt_size = dev_priv->gtt.base.total;
2713 mappable_size = dev_priv->gtt.mappable_end;
2715 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2718 void i915_global_gtt_cleanup(struct drm_device *dev)
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct i915_address_space *vm = &dev_priv->gtt.base;
2723 if (dev_priv->mm.aliasing_ppgtt) {
2724 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2726 ppgtt->base.cleanup(&ppgtt->base);
2729 if (drm_mm_initialized(&vm->mm)) {
2730 if (intel_vgpu_active(dev))
2731 intel_vgt_deballoon();
2733 drm_mm_takedown(&vm->mm);
2734 list_del(&vm->global_link);
2740 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2742 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2743 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2744 return snb_gmch_ctl << 20;
2747 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2749 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2750 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2752 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2754 #ifdef CONFIG_X86_32
2755 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2756 if (bdw_gmch_ctl > 4)
2760 return bdw_gmch_ctl << 20;
2763 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2765 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2766 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2769 return 1 << (20 + gmch_ctrl);
2774 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2776 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2777 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2778 return snb_gmch_ctl << 25; /* 32 MB units */
2781 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2783 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2784 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2785 return bdw_gmch_ctl << 25; /* 32 MB units */
2788 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2790 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2791 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2794 * 0x0 to 0x10: 32MB increments starting at 0MB
2795 * 0x11 to 0x16: 4MB increments starting at 8MB
2796 * 0x17 to 0x1d: 4MB increments start at 36MB
2798 if (gmch_ctrl < 0x11)
2799 return gmch_ctrl << 25;
2800 else if (gmch_ctrl < 0x17)
2801 return (gmch_ctrl - 0x11 + 2) << 22;
2803 return (gmch_ctrl - 0x17 + 9) << 22;
2806 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2808 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2809 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2811 if (gen9_gmch_ctl < 0xf0)
2812 return gen9_gmch_ctl << 25; /* 32 MB units */
2814 /* 4MB increments starting at 0xf0 for 4MB */
2815 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2818 static int ggtt_probe_common(struct drm_device *dev,
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct i915_page_scratch *scratch_page;
2823 phys_addr_t gtt_phys_addr;
2825 /* For Modern GENs the PTEs and register space are split in the BAR */
2826 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2827 (pci_resource_len(dev->pdev, 0) / 2);
2830 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2831 * dropped. For WC mappings in general we have 64 byte burst writes
2832 * when the WC buffer is flushed, so we can't use it, but have to
2833 * resort to an uncached mapping. The WC issue is easily caught by the
2834 * readback check when writing GTT PTE entries.
2836 if (IS_BROXTON(dev))
2837 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2839 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2840 if (!dev_priv->gtt.gsm) {
2841 DRM_ERROR("Failed to map the gtt page table\n");
2845 scratch_page = alloc_scratch_page(dev);
2846 if (IS_ERR(scratch_page)) {
2847 DRM_ERROR("Scratch setup failed\n");
2848 /* iounmap will also get called at remove, but meh */
2849 iounmap(dev_priv->gtt.gsm);
2850 return PTR_ERR(scratch_page);
2853 dev_priv->gtt.base.scratch_page = scratch_page;
2858 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2859 * bits. When using advanced contexts each context stores its own PAT, but
2860 * writing this data shouldn't be harmful even in those cases. */
2861 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2865 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2866 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2867 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2868 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2869 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2870 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2871 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2872 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2874 if (!USES_PPGTT(dev_priv->dev))
2875 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2876 * so RTL will always use the value corresponding to
2878 * So let's disable cache for GGTT to avoid screen corruptions.
2879 * MOCS still can be used though.
2880 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2881 * before this patch, i.e. the same uncached + snooping access
2882 * like on gen6/7 seems to be in effect.
2883 * - So this just fixes blitter/render access. Again it looks
2884 * like it's not just uncached access, but uncached + snooping.
2885 * So we can still hold onto all our assumptions wrt cpu
2886 * clflushing on LLC machines.
2888 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2890 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2891 * write would work. */
2892 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2893 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2896 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2901 * Map WB on BDW to snooped on CHV.
2903 * Only the snoop bit has meaning for CHV, the rest is
2906 * The hardware will never snoop for certain types of accesses:
2907 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2908 * - PPGTT page tables
2909 * - some other special cycles
2911 * As with BDW, we also need to consider the following for GT accesses:
2912 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2913 * so RTL will always use the value corresponding to
2915 * Which means we must set the snoop bit in PAT entry 0
2916 * in order to keep the global status page working.
2918 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2922 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2923 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2924 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2925 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2927 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2928 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2931 static int gen8_gmch_probe(struct drm_device *dev,
2934 phys_addr_t *mappable_base,
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2942 /* TODO: We're not aware of mappable constraints on gen8 yet */
2943 *mappable_base = pci_resource_start(dev->pdev, 2);
2944 *mappable_end = pci_resource_len(dev->pdev, 2);
2946 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2947 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2949 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2951 if (INTEL_INFO(dev)->gen >= 9) {
2952 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2953 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2954 } else if (IS_CHERRYVIEW(dev)) {
2955 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2956 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2958 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2959 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2962 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2964 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2965 chv_setup_private_ppat(dev_priv);
2967 bdw_setup_private_ppat(dev_priv);
2969 ret = ggtt_probe_common(dev, gtt_size);
2971 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2972 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2973 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2974 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2979 static int gen6_gmch_probe(struct drm_device *dev,
2982 phys_addr_t *mappable_base,
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 unsigned int gtt_size;
2990 *mappable_base = pci_resource_start(dev->pdev, 2);
2991 *mappable_end = pci_resource_len(dev->pdev, 2);
2993 /* 64/512MB is the current min/max we actually know of, but this is just
2994 * a coarse sanity check.
2996 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2997 DRM_ERROR("Unknown GMADR size (%llx)\n",
2998 dev_priv->gtt.mappable_end);
3002 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3003 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3004 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3006 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
3008 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
3009 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3011 ret = ggtt_probe_common(dev, gtt_size);
3013 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
3014 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
3015 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3016 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3021 static void gen6_gmch_remove(struct i915_address_space *vm)
3024 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
3027 free_scratch_page(vm->dev, vm->scratch_page);
3030 static int i915_gmch_probe(struct drm_device *dev,
3033 phys_addr_t *mappable_base,
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3039 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3041 DRM_ERROR("failed to set up gmch\n");
3045 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
3047 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
3048 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
3049 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
3050 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3051 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3053 if (unlikely(dev_priv->gtt.do_idle_maps))
3054 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3059 static void i915_gmch_remove(struct i915_address_space *vm)
3061 intel_gmch_remove();
3064 int i915_gem_gtt_init(struct drm_device *dev)
3066 struct drm_i915_private *dev_priv = dev->dev_private;
3067 struct i915_gtt *gtt = &dev_priv->gtt;
3070 if (INTEL_INFO(dev)->gen <= 5) {
3071 gtt->gtt_probe = i915_gmch_probe;
3072 gtt->base.cleanup = i915_gmch_remove;
3073 } else if (INTEL_INFO(dev)->gen < 8) {
3074 gtt->gtt_probe = gen6_gmch_probe;
3075 gtt->base.cleanup = gen6_gmch_remove;
3076 if (IS_HASWELL(dev) && dev_priv->ellc_size)
3077 gtt->base.pte_encode = iris_pte_encode;
3078 else if (IS_HASWELL(dev))
3079 gtt->base.pte_encode = hsw_pte_encode;
3080 else if (IS_VALLEYVIEW(dev))
3081 gtt->base.pte_encode = byt_pte_encode;
3082 else if (INTEL_INFO(dev)->gen >= 7)
3083 gtt->base.pte_encode = ivb_pte_encode;
3085 gtt->base.pte_encode = snb_pte_encode;
3087 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
3088 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
3091 gtt->base.dev = dev;
3093 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
3094 >t->mappable_base, >t->mappable_end);
3098 /* GMADR is the PCI mmio aperture into the global GTT. */
3099 DRM_INFO("Memory usable by graphics device = %lluM\n",
3100 gtt->base.total >> 20);
3101 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
3102 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
3103 #ifdef CONFIG_INTEL_IOMMU
3104 if (intel_iommu_gfx_mapped)
3105 DRM_INFO("VT-d active for gfx access\n");
3108 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3109 * user's requested state against the hardware/driver capabilities. We
3110 * do this now so that we can print out any log messages once rather
3111 * than every time we check intel_enable_ppgtt().
3113 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3114 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
3119 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3121 struct drm_i915_private *dev_priv = dev->dev_private;
3122 struct drm_i915_gem_object *obj;
3123 struct i915_address_space *vm;
3124 struct i915_vma *vma;
3127 i915_check_and_clear_faults(dev);
3129 /* First fill our portion of the GTT with scratch pages */
3130 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
3131 dev_priv->gtt.base.start,
3132 dev_priv->gtt.base.total,
3135 /* Cache flush objects bound into GGTT and rebind them. */
3136 vm = &dev_priv->gtt.base;
3137 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3139 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3143 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3150 i915_gem_clflush_object(obj, obj->pin_display);
3153 if (INTEL_INFO(dev)->gen >= 8) {
3154 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3155 chv_setup_private_ppat(dev_priv);
3157 bdw_setup_private_ppat(dev_priv);
3162 if (USES_PPGTT(dev)) {
3163 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3164 /* TODO: Perhaps it shouldn't be gen6 specific */
3166 struct i915_hw_ppgtt *ppgtt =
3167 container_of(vm, struct i915_hw_ppgtt,
3170 if (i915_is_ggtt(vm))
3171 ppgtt = dev_priv->mm.aliasing_ppgtt;
3173 gen6_write_page_range(dev_priv, &ppgtt->pd,
3174 0, ppgtt->base.total);
3178 i915_ggtt_flush(dev_priv);
3181 static struct i915_vma *
3182 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3183 struct i915_address_space *vm,
3184 const struct i915_ggtt_view *ggtt_view)
3186 struct i915_vma *vma;
3188 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3189 return ERR_PTR(-EINVAL);
3191 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3193 return ERR_PTR(-ENOMEM);
3195 INIT_LIST_HEAD(&vma->vma_link);
3196 INIT_LIST_HEAD(&vma->mm_list);
3197 INIT_LIST_HEAD(&vma->exec_list);
3201 if (i915_is_ggtt(vm))
3202 vma->ggtt_view = *ggtt_view;
3204 list_add_tail(&vma->vma_link, &obj->vma_list);
3205 if (!i915_is_ggtt(vm))
3206 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3212 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3213 struct i915_address_space *vm)
3215 struct i915_vma *vma;
3217 vma = i915_gem_obj_to_vma(obj, vm);
3219 vma = __i915_gem_vma_create(obj, vm,
3220 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3226 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3227 const struct i915_ggtt_view *view)
3229 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
3230 struct i915_vma *vma;
3233 return ERR_PTR(-EINVAL);
3235 vma = i915_gem_obj_to_ggtt_view(obj, view);
3241 vma = __i915_gem_vma_create(obj, ggtt, view);
3247 static struct scatterlist *
3248 rotate_pages(dma_addr_t *in, unsigned int offset,
3249 unsigned int width, unsigned int height,
3250 struct sg_table *st, struct scatterlist *sg)
3252 unsigned int column, row;
3253 unsigned int src_idx;
3260 for (column = 0; column < width; column++) {
3261 src_idx = width * (height - 1) + column;
3262 for (row = 0; row < height; row++) {
3264 /* We don't need the pages, but need to initialize
3265 * the entries so the sg list can be happily traversed.
3266 * The only thing we need are DMA addresses.
3268 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3269 sg_dma_address(sg) = in[offset + src_idx];
3270 sg_dma_len(sg) = PAGE_SIZE;
3279 static struct sg_table *
3280 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
3281 struct drm_i915_gem_object *obj)
3283 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
3284 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
3285 unsigned int size_pages_uv;
3286 struct sg_page_iter sg_iter;
3288 dma_addr_t *page_addr_list;
3289 struct sg_table *st;
3290 unsigned int uv_start_page;
3291 struct scatterlist *sg;
3294 /* Allocate a temporary list of source pages for random access. */
3295 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3296 sizeof(dma_addr_t));
3297 if (!page_addr_list)
3298 return ERR_PTR(ret);
3300 /* Account for UV plane with NV12. */
3301 if (rot_info->pixel_format == DRM_FORMAT_NV12)
3302 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
3306 /* Allocate target SG list. */
3307 st = kmalloc(sizeof(*st), GFP_KERNEL);
3311 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3315 /* Populate source page list from the object. */
3317 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3318 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3322 /* Rotate the pages. */
3323 sg = rotate_pages(page_addr_list, 0,
3324 rot_info->width_pages, rot_info->height_pages,
3327 /* Append the UV plane if NV12. */
3328 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3329 uv_start_page = size_pages;
3331 /* Check for tile-row un-alignment. */
3332 if (offset_in_page(rot_info->uv_offset))
3335 rotate_pages(page_addr_list, uv_start_page,
3336 rot_info->width_pages_uv,
3337 rot_info->height_pages_uv,
3342 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3343 obj->base.size, rot_info->pitch, rot_info->height,
3344 rot_info->pixel_format, rot_info->width_pages,
3345 rot_info->height_pages, size_pages + size_pages_uv,
3348 drm_free_large(page_addr_list);
3355 drm_free_large(page_addr_list);
3358 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3359 obj->base.size, ret, rot_info->pitch, rot_info->height,
3360 rot_info->pixel_format, rot_info->width_pages,
3361 rot_info->height_pages, size_pages + size_pages_uv,
3363 return ERR_PTR(ret);
3366 static struct sg_table *
3367 intel_partial_pages(const struct i915_ggtt_view *view,
3368 struct drm_i915_gem_object *obj)
3370 struct sg_table *st;
3371 struct scatterlist *sg;
3372 struct sg_page_iter obj_sg_iter;
3375 st = kmalloc(sizeof(*st), GFP_KERNEL);
3379 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3385 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3386 view->params.partial.offset)
3388 if (st->nents >= view->params.partial.size)
3391 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3392 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3393 sg_dma_len(sg) = PAGE_SIZE;
3404 return ERR_PTR(ret);
3408 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3412 if (vma->ggtt_view.pages)
3415 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3416 vma->ggtt_view.pages = vma->obj->pages;
3417 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3418 vma->ggtt_view.pages =
3419 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
3420 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3421 vma->ggtt_view.pages =
3422 intel_partial_pages(&vma->ggtt_view, vma->obj);
3424 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3425 vma->ggtt_view.type);
3427 if (!vma->ggtt_view.pages) {
3428 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3429 vma->ggtt_view.type);
3431 } else if (IS_ERR(vma->ggtt_view.pages)) {
3432 ret = PTR_ERR(vma->ggtt_view.pages);
3433 vma->ggtt_view.pages = NULL;
3434 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3435 vma->ggtt_view.type, ret);
3442 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3444 * @cache_level: mapping cache level
3445 * @flags: flags like global or local mapping
3447 * DMA addresses are taken from the scatter-gather table of this object (or of
3448 * this VMA in case of non-default GGTT views) and PTE entries set up.
3449 * Note that DMA addresses are also the only part of the SG table we care about.
3451 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3457 if (WARN_ON(flags == 0))
3461 if (flags & PIN_GLOBAL)
3462 bind_flags |= GLOBAL_BIND;
3463 if (flags & PIN_USER)
3464 bind_flags |= LOCAL_BIND;
3466 if (flags & PIN_UPDATE)
3467 bind_flags |= vma->bound;
3469 bind_flags &= ~vma->bound;
3471 if (bind_flags == 0)
3474 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3475 trace_i915_va_alloc(vma->vm,
3478 VM_TO_TRACE_NAME(vma->vm));
3480 /* XXX: i915_vma_pin() will fix this +- hack */
3482 ret = vma->vm->allocate_va_range(vma->vm,
3490 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3494 vma->bound |= bind_flags;
3500 * i915_ggtt_view_size - Get the size of a GGTT view.
3501 * @obj: Object the view is of.
3502 * @view: The view in question.
3504 * @return The size of the GGTT view in bytes.
3507 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3508 const struct i915_ggtt_view *view)
3510 if (view->type == I915_GGTT_VIEW_NORMAL) {
3511 return obj->base.size;
3512 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3513 return view->rotation_info.size;
3514 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3515 return view->params.partial.size << PAGE_SHIFT;
3517 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3518 return obj->base.size;