2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
98 const struct i915_ggtt_view i915_ggtt_view_normal;
99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
105 bool has_aliasing_ppgtt;
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
122 if (enable_ppgtt == 1)
125 if (enable_ppgtt == 2 && has_full_ppgtt)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
146 return has_aliasing_ppgtt ? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
155 /* Currently applicable only to VLV */
157 pte_flags |= PTE_READ_ONLY;
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
165 static void ppgtt_unbind_vma(struct i915_vma *vma)
167 vma->vm->clear_range(vma->vm,
173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
181 case I915_CACHE_NONE:
182 pte |= PPAT_UNCACHED_INDEX;
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
188 pte |= PPAT_CACHED_INDEX;
195 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
203 pde |= PPAT_UNCACHED_INDEX;
207 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
208 enum i915_cache_level level,
209 bool valid, u32 unused)
211 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
212 pte |= GEN6_PTE_ADDR_ENCODE(addr);
215 case I915_CACHE_L3_LLC:
217 pte |= GEN6_PTE_CACHE_LLC;
219 case I915_CACHE_NONE:
220 pte |= GEN6_PTE_UNCACHED;
229 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
230 enum i915_cache_level level,
231 bool valid, u32 unused)
233 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
234 pte |= GEN6_PTE_ADDR_ENCODE(addr);
237 case I915_CACHE_L3_LLC:
238 pte |= GEN7_PTE_CACHE_L3_LLC;
241 pte |= GEN6_PTE_CACHE_LLC;
243 case I915_CACHE_NONE:
244 pte |= GEN6_PTE_UNCACHED;
253 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
254 enum i915_cache_level level,
255 bool valid, u32 flags)
257 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
258 pte |= GEN6_PTE_ADDR_ENCODE(addr);
260 if (!(flags & PTE_READ_ONLY))
261 pte |= BYT_PTE_WRITEABLE;
263 if (level != I915_CACHE_NONE)
264 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
269 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
270 enum i915_cache_level level,
271 bool valid, u32 unused)
273 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
274 pte |= HSW_PTE_ADDR_ENCODE(addr);
276 if (level != I915_CACHE_NONE)
277 pte |= HSW_WB_LLC_AGE3;
282 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
283 enum i915_cache_level level,
284 bool valid, u32 unused)
286 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
287 pte |= HSW_PTE_ADDR_ENCODE(addr);
290 case I915_CACHE_NONE:
293 pte |= HSW_WT_ELLC_LLC_AGE3;
296 pte |= HSW_WB_ELLC_LLC_AGE3;
303 static int __setup_page_dma(struct drm_device *dev,
304 struct i915_page_dma *p, gfp_t flags)
306 struct device *device = &dev->pdev->dev;
308 p->page = alloc_page(flags);
312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
323 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
325 return __setup_page_dma(dev, p, GFP_KERNEL);
328 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
330 if (WARN_ON(!p->page))
333 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
334 __free_page(p->page);
335 memset(p, 0, sizeof(*p));
338 static void *kmap_page_dma(struct i915_page_dma *p)
340 return kmap_atomic(p->page);
343 /* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
346 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
351 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
352 drm_clflush_virt_range(vaddr, PAGE_SIZE);
354 kunmap_atomic(vaddr);
357 #define kmap_px(px) kmap_page_dma(px_base(px))
358 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
360 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
365 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
369 uint64_t * const vaddr = kmap_page_dma(p);
371 for (i = 0; i < 512; i++)
374 kunmap_page_dma(dev, vaddr);
377 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
378 const uint32_t val32)
384 fill_page_dma(dev, p, v);
387 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
389 struct i915_page_scratch *sp;
392 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
394 return ERR_PTR(-ENOMEM);
396 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
402 set_pages_uc(px_page(sp), 1);
407 static void free_scratch_page(struct drm_device *dev,
408 struct i915_page_scratch *sp)
410 set_pages_wb(px_page(sp), 1);
416 static struct i915_page_table *alloc_pt(struct drm_device *dev)
418 struct i915_page_table *pt;
419 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
420 GEN8_PTES : GEN6_PTES;
423 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
425 return ERR_PTR(-ENOMEM);
427 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
433 ret = setup_px(dev, pt);
440 kfree(pt->used_ptes);
447 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
450 kfree(pt->used_ptes);
454 static void gen8_initialize_pt(struct i915_address_space *vm,
455 struct i915_page_table *pt)
457 gen8_pte_t scratch_pte;
459 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
460 I915_CACHE_LLC, true);
462 fill_px(vm->dev, pt, scratch_pte);
465 static void gen6_initialize_pt(struct i915_address_space *vm,
466 struct i915_page_table *pt)
468 gen6_pte_t scratch_pte;
470 WARN_ON(px_dma(vm->scratch_page) == 0);
472 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
473 I915_CACHE_LLC, true, 0);
475 fill32_px(vm->dev, pt, scratch_pte);
478 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
480 struct i915_page_directory *pd;
483 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
485 return ERR_PTR(-ENOMEM);
487 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
488 sizeof(*pd->used_pdes), GFP_KERNEL);
492 ret = setup_px(dev, pd);
499 kfree(pd->used_pdes);
506 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
510 kfree(pd->used_pdes);
515 static void gen8_initialize_pd(struct i915_address_space *vm,
516 struct i915_page_directory *pd)
518 gen8_pde_t scratch_pde;
520 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
522 fill_px(vm->dev, pd, scratch_pde);
525 /* Broadwell Page Directory Pointer Descriptors */
526 static int gen8_write_pdp(struct drm_i915_gem_request *req,
530 struct intel_engine_cs *ring = req->ring;
535 ret = intel_ring_begin(req, 6);
539 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
540 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
541 intel_ring_emit(ring, upper_32_bits(addr));
542 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
543 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
544 intel_ring_emit(ring, lower_32_bits(addr));
545 intel_ring_advance(ring);
550 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
551 struct drm_i915_gem_request *req)
555 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
556 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
558 ret = gen8_write_pdp(req, i, pd_daddr);
566 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
571 struct i915_hw_ppgtt *ppgtt =
572 container_of(vm, struct i915_hw_ppgtt, base);
573 gen8_pte_t *pt_vaddr, scratch_pte;
574 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
575 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
576 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
577 unsigned num_entries = length >> PAGE_SHIFT;
578 unsigned last_pte, i;
580 scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page),
581 I915_CACHE_LLC, use_scratch);
583 while (num_entries) {
584 struct i915_page_directory *pd;
585 struct i915_page_table *pt;
587 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
590 pd = ppgtt->pdp.page_directory[pdpe];
592 if (WARN_ON(!pd->page_table[pde]))
595 pt = pd->page_table[pde];
597 if (WARN_ON(!px_page(pt)))
600 last_pte = pte + num_entries;
601 if (last_pte > GEN8_PTES)
602 last_pte = GEN8_PTES;
604 pt_vaddr = kmap_px(pt);
606 for (i = pte; i < last_pte; i++) {
607 pt_vaddr[i] = scratch_pte;
611 kunmap_px(ppgtt, pt);
614 if (++pde == I915_PDES) {
621 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
622 struct sg_table *pages,
624 enum i915_cache_level cache_level, u32 unused)
626 struct i915_hw_ppgtt *ppgtt =
627 container_of(vm, struct i915_hw_ppgtt, base);
628 gen8_pte_t *pt_vaddr;
629 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
630 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
631 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
632 struct sg_page_iter sg_iter;
636 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
637 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
640 if (pt_vaddr == NULL) {
641 struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
642 struct i915_page_table *pt = pd->page_table[pde];
643 pt_vaddr = kmap_px(pt);
647 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
649 if (++pte == GEN8_PTES) {
650 kunmap_px(ppgtt, pt_vaddr);
652 if (++pde == I915_PDES) {
661 kunmap_px(ppgtt, pt_vaddr);
664 static void gen8_free_page_tables(struct drm_device *dev,
665 struct i915_page_directory *pd)
672 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
673 if (WARN_ON(!pd->page_table[i]))
676 free_pt(dev, pd->page_table[i]);
677 pd->page_table[i] = NULL;
681 static int gen8_init_scratch(struct i915_address_space *vm)
683 struct drm_device *dev = vm->dev;
685 vm->scratch_page = alloc_scratch_page(dev);
686 if (IS_ERR(vm->scratch_page))
687 return PTR_ERR(vm->scratch_page);
689 vm->scratch_pt = alloc_pt(dev);
690 if (IS_ERR(vm->scratch_pt)) {
691 free_scratch_page(dev, vm->scratch_page);
692 return PTR_ERR(vm->scratch_pt);
695 vm->scratch_pd = alloc_pd(dev);
696 if (IS_ERR(vm->scratch_pd)) {
697 free_pt(dev, vm->scratch_pt);
698 free_scratch_page(dev, vm->scratch_page);
699 return PTR_ERR(vm->scratch_pd);
702 gen8_initialize_pt(vm, vm->scratch_pt);
703 gen8_initialize_pd(vm, vm->scratch_pd);
708 static void gen8_free_scratch(struct i915_address_space *vm)
710 struct drm_device *dev = vm->dev;
712 free_pd(dev, vm->scratch_pd);
713 free_pt(dev, vm->scratch_pt);
714 free_scratch_page(dev, vm->scratch_page);
717 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
719 struct i915_hw_ppgtt *ppgtt =
720 container_of(vm, struct i915_hw_ppgtt, base);
723 for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
724 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
727 gen8_free_page_tables(ppgtt->base.dev,
728 ppgtt->pdp.page_directory[i]);
729 free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]);
732 gen8_free_scratch(vm);
736 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
737 * @ppgtt: Master ppgtt structure.
738 * @pd: Page directory for this address range.
739 * @start: Starting virtual address to begin allocations.
740 * @length Size of the allocations.
741 * @new_pts: Bitmap set by function with new allocations. Likely used by the
742 * caller to free on error.
744 * Allocate the required number of page tables. Extremely similar to
745 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
746 * the page directory boundary (instead of the page directory pointer). That
747 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
748 * possible, and likely that the caller will need to use multiple calls of this
749 * function to achieve the appropriate allocation.
751 * Return: 0 if success; negative error code otherwise.
753 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
754 struct i915_page_directory *pd,
757 unsigned long *new_pts)
759 struct drm_device *dev = ppgtt->base.dev;
760 struct i915_page_table *pt;
764 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
765 /* Don't reallocate page tables */
767 /* Scratch is never allocated this way */
768 WARN_ON(pt == ppgtt->base.scratch_pt);
776 gen8_initialize_pt(&ppgtt->base, pt);
777 pd->page_table[pde] = pt;
778 __set_bit(pde, new_pts);
784 for_each_set_bit(pde, new_pts, I915_PDES)
785 free_pt(dev, pd->page_table[pde]);
791 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
792 * @ppgtt: Master ppgtt structure.
793 * @pdp: Page directory pointer for this address range.
794 * @start: Starting virtual address to begin allocations.
795 * @length Size of the allocations.
796 * @new_pds Bitmap set by function with new allocations. Likely used by the
797 * caller to free on error.
799 * Allocate the required number of page directories starting at the pde index of
800 * @start, and ending at the pde index @start + @length. This function will skip
801 * over already allocated page directories within the range, and only allocate
802 * new ones, setting the appropriate pointer within the pdp as well as the
803 * correct position in the bitmap @new_pds.
805 * The function will only allocate the pages within the range for a give page
806 * directory pointer. In other words, if @start + @length straddles a virtually
807 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
808 * required by the caller, This is not currently possible, and the BUG in the
809 * code will prevent it.
811 * Return: 0 if success; negative error code otherwise.
813 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
814 struct i915_page_directory_pointer *pdp,
817 unsigned long *new_pds)
819 struct drm_device *dev = ppgtt->base.dev;
820 struct i915_page_directory *pd;
824 WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
826 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
834 gen8_initialize_pd(&ppgtt->base, pd);
835 pdp->page_directory[pdpe] = pd;
836 __set_bit(pdpe, new_pds);
842 for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
843 free_pd(dev, pdp->page_directory[pdpe]);
849 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
853 for (i = 0; i < GEN8_LEGACY_PDPES; i++)
859 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
860 * of these are based on the number of PDPEs in the system.
863 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
864 unsigned long ***new_pts)
870 pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
874 pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
880 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
881 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
882 sizeof(unsigned long), GFP_KERNEL);
893 free_gen8_temp_bitmaps(pds, pts);
897 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
898 * the page table structures, we mark them dirty so that
899 * context switching/execlist queuing code takes extra steps
900 * to ensure that tlbs are flushed.
902 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
904 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
907 static int gen8_alloc_va_range(struct i915_address_space *vm,
911 struct i915_hw_ppgtt *ppgtt =
912 container_of(vm, struct i915_hw_ppgtt, base);
913 unsigned long *new_page_dirs, **new_page_tables;
914 struct i915_page_directory *pd;
915 const uint64_t orig_start = start;
916 const uint64_t orig_length = length;
921 /* Wrap is never okay since we can only represent 48b, and we don't
922 * actually use the other side of the canonical address space.
924 if (WARN_ON(start + length < start))
927 if (WARN_ON(start + length > ppgtt->base.total))
930 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
934 /* Do the allocations first so we can easily bail out */
935 ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
938 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
942 /* For every page directory referenced, allocate page tables */
943 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
944 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
945 new_page_tables[pdpe]);
951 length = orig_length;
953 /* Allocations have completed successfully, so set the bitmaps, and do
955 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
956 gen8_pde_t *const page_directory = kmap_px(pd);
957 struct i915_page_table *pt;
958 uint64_t pd_len = length;
959 uint64_t pd_start = start;
962 /* Every pd should be allocated, we just did that above. */
965 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
966 /* Same reasoning as pd */
969 WARN_ON(!gen8_pte_count(pd_start, pd_len));
971 /* Set our used ptes within the page table */
972 bitmap_set(pt->used_ptes,
973 gen8_pte_index(pd_start),
974 gen8_pte_count(pd_start, pd_len));
976 /* Our pde is now pointing to the pagetable, pt */
977 __set_bit(pde, pd->used_pdes);
979 /* Map the PDE to the page table */
980 page_directory[pde] = gen8_pde_encode(px_dma(pt),
983 /* NB: We haven't yet mapped ptes to pages. At this
984 * point we're still relying on insert_entries() */
987 kunmap_px(ppgtt, page_directory);
989 __set_bit(pdpe, ppgtt->pdp.used_pdpes);
992 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
993 mark_tlbs_dirty(ppgtt);
998 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
999 free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]);
1002 for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
1003 free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]);
1005 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1006 mark_tlbs_dirty(ppgtt);
1011 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1012 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1013 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1017 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1021 ret = gen8_init_scratch(&ppgtt->base);
1025 ppgtt->base.start = 0;
1026 ppgtt->base.total = 1ULL << 32;
1027 if (IS_ENABLED(CONFIG_X86_32))
1028 /* While we have a proliferation of size_t variables
1029 * we cannot represent the full ppgtt size on 32bit,
1030 * so limit it to the same size as the GGTT (currently
1033 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
1034 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1035 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1036 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1037 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1038 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1039 ppgtt->base.bind_vma = ppgtt_bind_vma;
1041 ppgtt->switch_mm = gen8_mm_switch;
1046 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1048 struct i915_address_space *vm = &ppgtt->base;
1049 struct i915_page_table *unused;
1050 gen6_pte_t scratch_pte;
1052 uint32_t pte, pde, temp;
1053 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1055 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1056 I915_CACHE_LLC, true, 0);
1058 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1060 gen6_pte_t *pt_vaddr;
1061 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1062 pd_entry = readl(ppgtt->pd_addr + pde);
1063 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1065 if (pd_entry != expected)
1066 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1070 seq_printf(m, "\tPDE: %x\n", pd_entry);
1072 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1074 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1076 (pde * PAGE_SIZE * GEN6_PTES) +
1080 for (i = 0; i < 4; i++)
1081 if (pt_vaddr[pte + i] != scratch_pte)
1086 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1087 for (i = 0; i < 4; i++) {
1088 if (pt_vaddr[pte + i] != scratch_pte)
1089 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1091 seq_puts(m, " SCRATCH ");
1095 kunmap_px(ppgtt, pt_vaddr);
1099 /* Write pde (index) from the page directory @pd to the page table @pt */
1100 static void gen6_write_pde(struct i915_page_directory *pd,
1101 const int pde, struct i915_page_table *pt)
1103 /* Caller needs to make sure the write completes if necessary */
1104 struct i915_hw_ppgtt *ppgtt =
1105 container_of(pd, struct i915_hw_ppgtt, pd);
1108 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1109 pd_entry |= GEN6_PDE_VALID;
1111 writel(pd_entry, ppgtt->pd_addr + pde);
1114 /* Write all the page tables found in the ppgtt structure to incrementing page
1116 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1117 struct i915_page_directory *pd,
1118 uint32_t start, uint32_t length)
1120 struct i915_page_table *pt;
1123 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1124 gen6_write_pde(pd, pde, pt);
1126 /* Make sure write is complete before other code can use this page
1127 * table. Also require for WC mapped PTEs */
1128 readl(dev_priv->gtt.gsm);
1131 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1133 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1135 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1138 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1139 struct drm_i915_gem_request *req)
1141 struct intel_engine_cs *ring = req->ring;
1144 /* NB: TLBs must be flushed and invalidated before a switch */
1145 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1149 ret = intel_ring_begin(req, 6);
1153 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1154 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1155 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1156 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1157 intel_ring_emit(ring, get_pd_offset(ppgtt));
1158 intel_ring_emit(ring, MI_NOOP);
1159 intel_ring_advance(ring);
1164 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1165 struct drm_i915_gem_request *req)
1167 struct intel_engine_cs *ring = req->ring;
1168 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1170 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1171 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1175 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1176 struct drm_i915_gem_request *req)
1178 struct intel_engine_cs *ring = req->ring;
1181 /* NB: TLBs must be flushed and invalidated before a switch */
1182 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1186 ret = intel_ring_begin(req, 6);
1190 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1191 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1192 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1193 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1194 intel_ring_emit(ring, get_pd_offset(ppgtt));
1195 intel_ring_emit(ring, MI_NOOP);
1196 intel_ring_advance(ring);
1198 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1199 if (ring->id != RCS) {
1200 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1208 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1209 struct drm_i915_gem_request *req)
1211 struct intel_engine_cs *ring = req->ring;
1212 struct drm_device *dev = ppgtt->base.dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1216 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1217 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1219 POSTING_READ(RING_PP_DIR_DCLV(ring));
1224 static void gen8_ppgtt_enable(struct drm_device *dev)
1226 struct drm_i915_private *dev_priv = dev->dev_private;
1227 struct intel_engine_cs *ring;
1230 for_each_ring(ring, dev_priv, j) {
1231 I915_WRITE(RING_MODE_GEN7(ring),
1232 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1236 static void gen7_ppgtt_enable(struct drm_device *dev)
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 struct intel_engine_cs *ring;
1240 uint32_t ecochk, ecobits;
1243 ecobits = I915_READ(GAC_ECO_BITS);
1244 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1246 ecochk = I915_READ(GAM_ECOCHK);
1247 if (IS_HASWELL(dev)) {
1248 ecochk |= ECOCHK_PPGTT_WB_HSW;
1250 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1251 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1253 I915_WRITE(GAM_ECOCHK, ecochk);
1255 for_each_ring(ring, dev_priv, i) {
1256 /* GFX_MODE is per-ring on gen7+ */
1257 I915_WRITE(RING_MODE_GEN7(ring),
1258 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1262 static void gen6_ppgtt_enable(struct drm_device *dev)
1264 struct drm_i915_private *dev_priv = dev->dev_private;
1265 uint32_t ecochk, gab_ctl, ecobits;
1267 ecobits = I915_READ(GAC_ECO_BITS);
1268 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1269 ECOBITS_PPGTT_CACHE64B);
1271 gab_ctl = I915_READ(GAB_CTL);
1272 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1274 ecochk = I915_READ(GAM_ECOCHK);
1275 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1277 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1280 /* PPGTT support for Sandybdrige/Gen6 and later */
1281 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1286 struct i915_hw_ppgtt *ppgtt =
1287 container_of(vm, struct i915_hw_ppgtt, base);
1288 gen6_pte_t *pt_vaddr, scratch_pte;
1289 unsigned first_entry = start >> PAGE_SHIFT;
1290 unsigned num_entries = length >> PAGE_SHIFT;
1291 unsigned act_pt = first_entry / GEN6_PTES;
1292 unsigned first_pte = first_entry % GEN6_PTES;
1293 unsigned last_pte, i;
1295 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1296 I915_CACHE_LLC, true, 0);
1298 while (num_entries) {
1299 last_pte = first_pte + num_entries;
1300 if (last_pte > GEN6_PTES)
1301 last_pte = GEN6_PTES;
1303 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1305 for (i = first_pte; i < last_pte; i++)
1306 pt_vaddr[i] = scratch_pte;
1308 kunmap_px(ppgtt, pt_vaddr);
1310 num_entries -= last_pte - first_pte;
1316 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1317 struct sg_table *pages,
1319 enum i915_cache_level cache_level, u32 flags)
1321 struct i915_hw_ppgtt *ppgtt =
1322 container_of(vm, struct i915_hw_ppgtt, base);
1323 gen6_pte_t *pt_vaddr;
1324 unsigned first_entry = start >> PAGE_SHIFT;
1325 unsigned act_pt = first_entry / GEN6_PTES;
1326 unsigned act_pte = first_entry % GEN6_PTES;
1327 struct sg_page_iter sg_iter;
1330 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1331 if (pt_vaddr == NULL)
1332 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1335 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1336 cache_level, true, flags);
1338 if (++act_pte == GEN6_PTES) {
1339 kunmap_px(ppgtt, pt_vaddr);
1346 kunmap_px(ppgtt, pt_vaddr);
1349 static int gen6_alloc_va_range(struct i915_address_space *vm,
1350 uint64_t start_in, uint64_t length_in)
1352 DECLARE_BITMAP(new_page_tables, I915_PDES);
1353 struct drm_device *dev = vm->dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 struct i915_hw_ppgtt *ppgtt =
1356 container_of(vm, struct i915_hw_ppgtt, base);
1357 struct i915_page_table *pt;
1358 uint32_t start, length, start_save, length_save;
1362 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1365 start = start_save = start_in;
1366 length = length_save = length_in;
1368 bitmap_zero(new_page_tables, I915_PDES);
1370 /* The allocation is done in two stages so that we can bail out with
1371 * minimal amount of pain. The first stage finds new page tables that
1372 * need allocation. The second stage marks use ptes within the page
1375 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1376 if (pt != vm->scratch_pt) {
1377 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1381 /* We've already allocated a page table */
1382 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1390 gen6_initialize_pt(vm, pt);
1392 ppgtt->pd.page_table[pde] = pt;
1393 __set_bit(pde, new_page_tables);
1394 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1398 length = length_save;
1400 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1401 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1403 bitmap_zero(tmp_bitmap, GEN6_PTES);
1404 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1405 gen6_pte_count(start, length));
1407 if (__test_and_clear_bit(pde, new_page_tables))
1408 gen6_write_pde(&ppgtt->pd, pde, pt);
1410 trace_i915_page_table_entry_map(vm, pde, pt,
1411 gen6_pte_index(start),
1412 gen6_pte_count(start, length),
1414 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1418 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1420 /* Make sure write is complete before other code can use this page
1421 * table. Also require for WC mapped PTEs */
1422 readl(dev_priv->gtt.gsm);
1424 mark_tlbs_dirty(ppgtt);
1428 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1429 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1431 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1432 free_pt(vm->dev, pt);
1435 mark_tlbs_dirty(ppgtt);
1439 static int gen6_init_scratch(struct i915_address_space *vm)
1441 struct drm_device *dev = vm->dev;
1443 vm->scratch_page = alloc_scratch_page(dev);
1444 if (IS_ERR(vm->scratch_page))
1445 return PTR_ERR(vm->scratch_page);
1447 vm->scratch_pt = alloc_pt(dev);
1448 if (IS_ERR(vm->scratch_pt)) {
1449 free_scratch_page(dev, vm->scratch_page);
1450 return PTR_ERR(vm->scratch_pt);
1453 gen6_initialize_pt(vm, vm->scratch_pt);
1458 static void gen6_free_scratch(struct i915_address_space *vm)
1460 struct drm_device *dev = vm->dev;
1462 free_pt(dev, vm->scratch_pt);
1463 free_scratch_page(dev, vm->scratch_page);
1466 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1468 struct i915_hw_ppgtt *ppgtt =
1469 container_of(vm, struct i915_hw_ppgtt, base);
1470 struct i915_page_table *pt;
1473 drm_mm_remove_node(&ppgtt->node);
1475 gen6_for_all_pdes(pt, ppgtt, pde) {
1476 if (pt != vm->scratch_pt)
1477 free_pt(ppgtt->base.dev, pt);
1480 gen6_free_scratch(vm);
1483 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1485 struct i915_address_space *vm = &ppgtt->base;
1486 struct drm_device *dev = ppgtt->base.dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 bool retried = false;
1491 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1492 * allocator works in address space sizes, so it's multiplied by page
1493 * size. We allocate at the top of the GTT to avoid fragmentation.
1495 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1497 ret = gen6_init_scratch(vm);
1502 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1503 &ppgtt->node, GEN6_PD_SIZE,
1505 0, dev_priv->gtt.base.total,
1507 if (ret == -ENOSPC && !retried) {
1508 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1509 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1511 0, dev_priv->gtt.base.total,
1524 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1525 DRM_DEBUG("Forced to use aperture for PDEs\n");
1530 gen6_free_scratch(vm);
1534 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1536 return gen6_ppgtt_allocate_page_directories(ppgtt);
1539 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1540 uint64_t start, uint64_t length)
1542 struct i915_page_table *unused;
1545 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1546 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
1549 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1551 struct drm_device *dev = ppgtt->base.dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1555 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1557 ppgtt->switch_mm = gen6_mm_switch;
1558 } else if (IS_HASWELL(dev)) {
1559 ppgtt->switch_mm = hsw_mm_switch;
1560 } else if (IS_GEN7(dev)) {
1561 ppgtt->switch_mm = gen7_mm_switch;
1565 if (intel_vgpu_active(dev))
1566 ppgtt->switch_mm = vgpu_mm_switch;
1568 ret = gen6_ppgtt_alloc(ppgtt);
1572 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1573 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1574 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1575 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1576 ppgtt->base.bind_vma = ppgtt_bind_vma;
1577 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1578 ppgtt->base.start = 0;
1579 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1580 ppgtt->debug_dump = gen6_dump_ppgtt;
1582 ppgtt->pd.base.ggtt_offset =
1583 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1585 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1586 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
1588 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1590 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1592 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1593 ppgtt->node.size >> 20,
1594 ppgtt->node.start / PAGE_SIZE);
1596 DRM_DEBUG("Adding PPGTT at offset %x\n",
1597 ppgtt->pd.base.ggtt_offset << 10);
1602 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1604 ppgtt->base.dev = dev;
1606 if (INTEL_INFO(dev)->gen < 8)
1607 return gen6_ppgtt_init(ppgtt);
1609 return gen8_ppgtt_init(ppgtt);
1612 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1617 ret = __hw_ppgtt_init(dev, ppgtt);
1619 kref_init(&ppgtt->ref);
1620 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1622 i915_init_vm(dev_priv, &ppgtt->base);
1628 int i915_ppgtt_init_hw(struct drm_device *dev)
1630 /* In the case of execlists, PPGTT is enabled by the context descriptor
1631 * and the PDPs are contained within the context itself. We don't
1632 * need to do anything here. */
1633 if (i915.enable_execlists)
1636 if (!USES_PPGTT(dev))
1640 gen6_ppgtt_enable(dev);
1641 else if (IS_GEN7(dev))
1642 gen7_ppgtt_enable(dev);
1643 else if (INTEL_INFO(dev)->gen >= 8)
1644 gen8_ppgtt_enable(dev);
1646 MISSING_CASE(INTEL_INFO(dev)->gen);
1651 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
1653 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
1654 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1656 if (i915.enable_execlists)
1662 return ppgtt->switch_mm(ppgtt, req);
1665 struct i915_hw_ppgtt *
1666 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1668 struct i915_hw_ppgtt *ppgtt;
1671 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1673 return ERR_PTR(-ENOMEM);
1675 ret = i915_ppgtt_init(dev, ppgtt);
1678 return ERR_PTR(ret);
1681 ppgtt->file_priv = fpriv;
1683 trace_i915_ppgtt_create(&ppgtt->base);
1688 void i915_ppgtt_release(struct kref *kref)
1690 struct i915_hw_ppgtt *ppgtt =
1691 container_of(kref, struct i915_hw_ppgtt, ref);
1693 trace_i915_ppgtt_release(&ppgtt->base);
1695 /* vmas should already be unbound */
1696 WARN_ON(!list_empty(&ppgtt->base.active_list));
1697 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1699 list_del(&ppgtt->base.global_link);
1700 drm_mm_takedown(&ppgtt->base.mm);
1702 ppgtt->base.cleanup(&ppgtt->base);
1706 extern int intel_iommu_gfx_mapped;
1707 /* Certain Gen5 chipsets require require idling the GPU before
1708 * unmapping anything from the GTT when VT-d is enabled.
1710 static bool needs_idle_maps(struct drm_device *dev)
1712 #ifdef CONFIG_INTEL_IOMMU
1713 /* Query intel_iommu to see if we need the workaround. Presumably that
1716 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1722 static bool do_idling(struct drm_i915_private *dev_priv)
1724 bool ret = dev_priv->mm.interruptible;
1726 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1727 dev_priv->mm.interruptible = false;
1728 if (i915_gpu_idle(dev_priv->dev)) {
1729 DRM_ERROR("Couldn't idle GPU\n");
1730 /* Wait a bit, in hopes it avoids the hang */
1738 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1740 if (unlikely(dev_priv->gtt.do_idle_maps))
1741 dev_priv->mm.interruptible = interruptible;
1744 void i915_check_and_clear_faults(struct drm_device *dev)
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_engine_cs *ring;
1750 if (INTEL_INFO(dev)->gen < 6)
1753 for_each_ring(ring, dev_priv, i) {
1755 fault_reg = I915_READ(RING_FAULT_REG(ring));
1756 if (fault_reg & RING_FAULT_VALID) {
1757 DRM_DEBUG_DRIVER("Unexpected fault\n"
1759 "\tAddress space: %s\n"
1762 fault_reg & PAGE_MASK,
1763 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1764 RING_FAULT_SRCID(fault_reg),
1765 RING_FAULT_FAULT_TYPE(fault_reg));
1766 I915_WRITE(RING_FAULT_REG(ring),
1767 fault_reg & ~RING_FAULT_VALID);
1770 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1773 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1775 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1776 intel_gtt_chipset_flush();
1778 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1779 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1783 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1787 /* Don't bother messing with faults pre GEN6 as we have little
1788 * documentation supporting that it's a good idea.
1790 if (INTEL_INFO(dev)->gen < 6)
1793 i915_check_and_clear_faults(dev);
1795 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1796 dev_priv->gtt.base.start,
1797 dev_priv->gtt.base.total,
1800 i915_ggtt_flush(dev_priv);
1803 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1805 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1806 obj->pages->sgl, obj->pages->nents,
1807 PCI_DMA_BIDIRECTIONAL))
1813 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1818 iowrite32((u32)pte, addr);
1819 iowrite32(pte >> 32, addr + 4);
1823 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1824 struct sg_table *st,
1826 enum i915_cache_level level, u32 unused)
1828 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1829 unsigned first_entry = start >> PAGE_SHIFT;
1830 gen8_pte_t __iomem *gtt_entries =
1831 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1833 struct sg_page_iter sg_iter;
1834 dma_addr_t addr = 0; /* shut up gcc */
1836 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1837 addr = sg_dma_address(sg_iter.sg) +
1838 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1839 gen8_set_pte(>t_entries[i],
1840 gen8_pte_encode(addr, level, true));
1845 * XXX: This serves as a posting read to make sure that the PTE has
1846 * actually been updated. There is some concern that even though
1847 * registers and PTEs are within the same BAR that they are potentially
1848 * of NUMA access patterns. Therefore, even with the way we assume
1849 * hardware should work, we must keep this posting read for paranoia.
1852 WARN_ON(readq(>t_entries[i-1])
1853 != gen8_pte_encode(addr, level, true));
1855 /* This next bit makes the above posting read even more important. We
1856 * want to flush the TLBs only after we're certain all the PTE updates
1859 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1860 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1864 * Binds an object into the global gtt with the specified cache level. The object
1865 * will be accessible to the GPU via commands whose operands reference offsets
1866 * within the global GTT as well as accessible by the GPU through the GMADR
1867 * mapped BAR (dev_priv->mm.gtt->gtt).
1869 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1870 struct sg_table *st,
1872 enum i915_cache_level level, u32 flags)
1874 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1875 unsigned first_entry = start >> PAGE_SHIFT;
1876 gen6_pte_t __iomem *gtt_entries =
1877 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1879 struct sg_page_iter sg_iter;
1880 dma_addr_t addr = 0;
1882 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1883 addr = sg_page_iter_dma_address(&sg_iter);
1884 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
1888 /* XXX: This serves as a posting read to make sure that the PTE has
1889 * actually been updated. There is some concern that even though
1890 * registers and PTEs are within the same BAR that they are potentially
1891 * of NUMA access patterns. Therefore, even with the way we assume
1892 * hardware should work, we must keep this posting read for paranoia.
1895 unsigned long gtt = readl(>t_entries[i-1]);
1896 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1899 /* This next bit makes the above posting read even more important. We
1900 * want to flush the TLBs only after we're certain all the PTE updates
1903 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1904 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1907 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1912 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1913 unsigned first_entry = start >> PAGE_SHIFT;
1914 unsigned num_entries = length >> PAGE_SHIFT;
1915 gen8_pte_t scratch_pte, __iomem *gtt_base =
1916 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1917 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1920 if (WARN(num_entries > max_entries,
1921 "First entry = %d; Num entries = %d (max=%d)\n",
1922 first_entry, num_entries, max_entries))
1923 num_entries = max_entries;
1925 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1928 for (i = 0; i < num_entries; i++)
1929 gen8_set_pte(>t_base[i], scratch_pte);
1933 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1938 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1939 unsigned first_entry = start >> PAGE_SHIFT;
1940 unsigned num_entries = length >> PAGE_SHIFT;
1941 gen6_pte_t scratch_pte, __iomem *gtt_base =
1942 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1943 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1946 if (WARN(num_entries > max_entries,
1947 "First entry = %d; Num entries = %d (max=%d)\n",
1948 first_entry, num_entries, max_entries))
1949 num_entries = max_entries;
1951 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1952 I915_CACHE_LLC, use_scratch, 0);
1954 for (i = 0; i < num_entries; i++)
1955 iowrite32(scratch_pte, >t_base[i]);
1959 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1960 struct sg_table *pages,
1962 enum i915_cache_level cache_level, u32 unused)
1964 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1965 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1967 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1971 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1976 unsigned first_entry = start >> PAGE_SHIFT;
1977 unsigned num_entries = length >> PAGE_SHIFT;
1978 intel_gtt_clear_range(first_entry, num_entries);
1981 static int ggtt_bind_vma(struct i915_vma *vma,
1982 enum i915_cache_level cache_level,
1985 struct drm_device *dev = vma->vm->dev;
1986 struct drm_i915_private *dev_priv = dev->dev_private;
1987 struct drm_i915_gem_object *obj = vma->obj;
1988 struct sg_table *pages = obj->pages;
1992 ret = i915_get_ggtt_vma_pages(vma);
1995 pages = vma->ggtt_view.pages;
1997 /* Currently applicable only to VLV */
1999 pte_flags |= PTE_READ_ONLY;
2002 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
2003 vma->vm->insert_entries(vma->vm, pages,
2005 cache_level, pte_flags);
2007 /* Note the inconsistency here is due to absence of the
2008 * aliasing ppgtt on gen4 and earlier. Though we always
2009 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2010 * without the appgtt, we cannot honour that request and so
2011 * must substitute it with a global binding. Since we do this
2012 * behind the upper layers back, we need to explicitly set
2013 * the bound flag ourselves.
2015 vma->bound |= GLOBAL_BIND;
2019 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
2020 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2021 appgtt->base.insert_entries(&appgtt->base, pages,
2023 cache_level, pte_flags);
2029 static void ggtt_unbind_vma(struct i915_vma *vma)
2031 struct drm_device *dev = vma->vm->dev;
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033 struct drm_i915_gem_object *obj = vma->obj;
2034 const uint64_t size = min_t(uint64_t,
2038 if (vma->bound & GLOBAL_BIND) {
2039 vma->vm->clear_range(vma->vm,
2045 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2046 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2048 appgtt->base.clear_range(&appgtt->base,
2055 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2057 struct drm_device *dev = obj->base.dev;
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2061 interruptible = do_idling(dev_priv);
2063 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2064 PCI_DMA_BIDIRECTIONAL);
2066 undo_idling(dev_priv, interruptible);
2069 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2070 unsigned long color,
2074 if (node->color != color)
2077 if (!list_empty(&node->node_list)) {
2078 node = list_entry(node->node_list.next,
2081 if (node->allocated && node->color != color)
2086 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2087 unsigned long start,
2088 unsigned long mappable_end,
2091 /* Let GEM Manage all of the aperture.
2093 * However, leave one page at the end still bound to the scratch page.
2094 * There are a number of places where the hardware apparently prefetches
2095 * past the end of the object, and we've seen multiple hangs with the
2096 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2097 * aperture. One page should be enough to keep any prefetching inside
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2102 struct drm_mm_node *entry;
2103 struct drm_i915_gem_object *obj;
2104 unsigned long hole_start, hole_end;
2107 BUG_ON(mappable_end > end);
2109 /* Subtract the guard page ... */
2110 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2112 dev_priv->gtt.base.start = start;
2113 dev_priv->gtt.base.total = end - start;
2115 if (intel_vgpu_active(dev)) {
2116 ret = intel_vgt_balloon(dev);
2122 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2124 /* Mark any preallocated objects as occupied */
2125 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2126 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2128 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2129 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2131 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2132 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2134 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2137 vma->bound |= GLOBAL_BIND;
2140 /* Clear any non-preallocated blocks */
2141 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2142 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2143 hole_start, hole_end);
2144 ggtt_vm->clear_range(ggtt_vm, hole_start,
2145 hole_end - hole_start, true);
2148 /* And finally clear the reserved guard page */
2149 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2151 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2152 struct i915_hw_ppgtt *ppgtt;
2154 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2158 ret = __hw_ppgtt_init(dev, ppgtt);
2160 ppgtt->base.cleanup(&ppgtt->base);
2165 if (ppgtt->base.allocate_va_range)
2166 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2169 ppgtt->base.cleanup(&ppgtt->base);
2174 ppgtt->base.clear_range(&ppgtt->base,
2179 dev_priv->mm.aliasing_ppgtt = ppgtt;
2185 void i915_gem_init_global_gtt(struct drm_device *dev)
2187 struct drm_i915_private *dev_priv = dev->dev_private;
2188 u64 gtt_size, mappable_size;
2190 gtt_size = dev_priv->gtt.base.total;
2191 mappable_size = dev_priv->gtt.mappable_end;
2193 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2196 void i915_global_gtt_cleanup(struct drm_device *dev)
2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 struct i915_address_space *vm = &dev_priv->gtt.base;
2201 if (dev_priv->mm.aliasing_ppgtt) {
2202 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2204 ppgtt->base.cleanup(&ppgtt->base);
2207 if (drm_mm_initialized(&vm->mm)) {
2208 if (intel_vgpu_active(dev))
2209 intel_vgt_deballoon();
2211 drm_mm_takedown(&vm->mm);
2212 list_del(&vm->global_link);
2218 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2220 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2221 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2222 return snb_gmch_ctl << 20;
2225 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2227 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2228 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2230 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2232 #ifdef CONFIG_X86_32
2233 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2234 if (bdw_gmch_ctl > 4)
2238 return bdw_gmch_ctl << 20;
2241 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2243 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2244 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2247 return 1 << (20 + gmch_ctrl);
2252 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2254 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2255 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2256 return snb_gmch_ctl << 25; /* 32 MB units */
2259 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2261 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2262 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2263 return bdw_gmch_ctl << 25; /* 32 MB units */
2266 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2268 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2269 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2272 * 0x0 to 0x10: 32MB increments starting at 0MB
2273 * 0x11 to 0x16: 4MB increments starting at 8MB
2274 * 0x17 to 0x1d: 4MB increments start at 36MB
2276 if (gmch_ctrl < 0x11)
2277 return gmch_ctrl << 25;
2278 else if (gmch_ctrl < 0x17)
2279 return (gmch_ctrl - 0x11 + 2) << 22;
2281 return (gmch_ctrl - 0x17 + 9) << 22;
2284 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2286 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2287 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2289 if (gen9_gmch_ctl < 0xf0)
2290 return gen9_gmch_ctl << 25; /* 32 MB units */
2292 /* 4MB increments starting at 0xf0 for 4MB */
2293 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2296 static int ggtt_probe_common(struct drm_device *dev,
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 struct i915_page_scratch *scratch_page;
2301 phys_addr_t gtt_phys_addr;
2303 /* For Modern GENs the PTEs and register space are split in the BAR */
2304 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2305 (pci_resource_len(dev->pdev, 0) / 2);
2308 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2309 * dropped. For WC mappings in general we have 64 byte burst writes
2310 * when the WC buffer is flushed, so we can't use it, but have to
2311 * resort to an uncached mapping. The WC issue is easily caught by the
2312 * readback check when writing GTT PTE entries.
2314 if (IS_BROXTON(dev))
2315 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2317 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2318 if (!dev_priv->gtt.gsm) {
2319 DRM_ERROR("Failed to map the gtt page table\n");
2323 scratch_page = alloc_scratch_page(dev);
2324 if (IS_ERR(scratch_page)) {
2325 DRM_ERROR("Scratch setup failed\n");
2326 /* iounmap will also get called at remove, but meh */
2327 iounmap(dev_priv->gtt.gsm);
2328 return PTR_ERR(scratch_page);
2331 dev_priv->gtt.base.scratch_page = scratch_page;
2336 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2337 * bits. When using advanced contexts each context stores its own PAT, but
2338 * writing this data shouldn't be harmful even in those cases. */
2339 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2343 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2344 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2345 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2346 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2347 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2348 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2349 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2350 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2352 if (!USES_PPGTT(dev_priv->dev))
2353 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2354 * so RTL will always use the value corresponding to
2356 * So let's disable cache for GGTT to avoid screen corruptions.
2357 * MOCS still can be used though.
2358 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2359 * before this patch, i.e. the same uncached + snooping access
2360 * like on gen6/7 seems to be in effect.
2361 * - So this just fixes blitter/render access. Again it looks
2362 * like it's not just uncached access, but uncached + snooping.
2363 * So we can still hold onto all our assumptions wrt cpu
2364 * clflushing on LLC machines.
2366 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2368 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2369 * write would work. */
2370 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2371 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2374 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2379 * Map WB on BDW to snooped on CHV.
2381 * Only the snoop bit has meaning for CHV, the rest is
2384 * The hardware will never snoop for certain types of accesses:
2385 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2386 * - PPGTT page tables
2387 * - some other special cycles
2389 * As with BDW, we also need to consider the following for GT accesses:
2390 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2391 * so RTL will always use the value corresponding to
2393 * Which means we must set the snoop bit in PAT entry 0
2394 * in order to keep the global status page working.
2396 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2400 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2401 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2402 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2403 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2405 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2406 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2409 static int gen8_gmch_probe(struct drm_device *dev,
2412 phys_addr_t *mappable_base,
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2420 /* TODO: We're not aware of mappable constraints on gen8 yet */
2421 *mappable_base = pci_resource_start(dev->pdev, 2);
2422 *mappable_end = pci_resource_len(dev->pdev, 2);
2424 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2425 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2427 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2429 if (INTEL_INFO(dev)->gen >= 9) {
2430 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2431 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2432 } else if (IS_CHERRYVIEW(dev)) {
2433 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2434 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2436 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2437 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2440 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2442 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2443 chv_setup_private_ppat(dev_priv);
2445 bdw_setup_private_ppat(dev_priv);
2447 ret = ggtt_probe_common(dev, gtt_size);
2449 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2450 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2451 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2452 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2457 static int gen6_gmch_probe(struct drm_device *dev,
2460 phys_addr_t *mappable_base,
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 unsigned int gtt_size;
2468 *mappable_base = pci_resource_start(dev->pdev, 2);
2469 *mappable_end = pci_resource_len(dev->pdev, 2);
2471 /* 64/512MB is the current min/max we actually know of, but this is just
2472 * a coarse sanity check.
2474 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2475 DRM_ERROR("Unknown GMADR size (%llx)\n",
2476 dev_priv->gtt.mappable_end);
2480 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2481 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2482 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2484 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2486 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2487 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2489 ret = ggtt_probe_common(dev, gtt_size);
2491 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2492 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2493 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2494 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2499 static void gen6_gmch_remove(struct i915_address_space *vm)
2502 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2505 free_scratch_page(vm->dev, vm->scratch_page);
2508 static int i915_gmch_probe(struct drm_device *dev,
2511 phys_addr_t *mappable_base,
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2517 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2519 DRM_ERROR("failed to set up gmch\n");
2523 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2525 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2526 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2527 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2528 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2529 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2531 if (unlikely(dev_priv->gtt.do_idle_maps))
2532 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2537 static void i915_gmch_remove(struct i915_address_space *vm)
2539 intel_gmch_remove();
2542 int i915_gem_gtt_init(struct drm_device *dev)
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct i915_gtt *gtt = &dev_priv->gtt;
2548 if (INTEL_INFO(dev)->gen <= 5) {
2549 gtt->gtt_probe = i915_gmch_probe;
2550 gtt->base.cleanup = i915_gmch_remove;
2551 } else if (INTEL_INFO(dev)->gen < 8) {
2552 gtt->gtt_probe = gen6_gmch_probe;
2553 gtt->base.cleanup = gen6_gmch_remove;
2554 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2555 gtt->base.pte_encode = iris_pte_encode;
2556 else if (IS_HASWELL(dev))
2557 gtt->base.pte_encode = hsw_pte_encode;
2558 else if (IS_VALLEYVIEW(dev))
2559 gtt->base.pte_encode = byt_pte_encode;
2560 else if (INTEL_INFO(dev)->gen >= 7)
2561 gtt->base.pte_encode = ivb_pte_encode;
2563 gtt->base.pte_encode = snb_pte_encode;
2565 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2566 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2569 gtt->base.dev = dev;
2571 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
2572 >t->mappable_base, >t->mappable_end);
2576 /* GMADR is the PCI mmio aperture into the global GTT. */
2577 DRM_INFO("Memory usable by graphics device = %lluM\n",
2578 gtt->base.total >> 20);
2579 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
2580 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2581 #ifdef CONFIG_INTEL_IOMMU
2582 if (intel_iommu_gfx_mapped)
2583 DRM_INFO("VT-d active for gfx access\n");
2586 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2587 * user's requested state against the hardware/driver capabilities. We
2588 * do this now so that we can print out any log messages once rather
2589 * than every time we check intel_enable_ppgtt().
2591 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2592 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2597 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct drm_i915_gem_object *obj;
2601 struct i915_address_space *vm;
2602 struct i915_vma *vma;
2605 i915_check_and_clear_faults(dev);
2607 /* First fill our portion of the GTT with scratch pages */
2608 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2609 dev_priv->gtt.base.start,
2610 dev_priv->gtt.base.total,
2613 /* Cache flush objects bound into GGTT and rebind them. */
2614 vm = &dev_priv->gtt.base;
2615 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2617 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2621 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2628 i915_gem_clflush_object(obj, obj->pin_display);
2631 if (INTEL_INFO(dev)->gen >= 8) {
2632 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2633 chv_setup_private_ppat(dev_priv);
2635 bdw_setup_private_ppat(dev_priv);
2640 if (USES_PPGTT(dev)) {
2641 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2642 /* TODO: Perhaps it shouldn't be gen6 specific */
2644 struct i915_hw_ppgtt *ppgtt =
2645 container_of(vm, struct i915_hw_ppgtt,
2648 if (i915_is_ggtt(vm))
2649 ppgtt = dev_priv->mm.aliasing_ppgtt;
2651 gen6_write_page_range(dev_priv, &ppgtt->pd,
2652 0, ppgtt->base.total);
2656 i915_ggtt_flush(dev_priv);
2659 static struct i915_vma *
2660 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2661 struct i915_address_space *vm,
2662 const struct i915_ggtt_view *ggtt_view)
2664 struct i915_vma *vma;
2666 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2667 return ERR_PTR(-EINVAL);
2669 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2671 return ERR_PTR(-ENOMEM);
2673 INIT_LIST_HEAD(&vma->vma_link);
2674 INIT_LIST_HEAD(&vma->mm_list);
2675 INIT_LIST_HEAD(&vma->exec_list);
2679 if (i915_is_ggtt(vm))
2680 vma->ggtt_view = *ggtt_view;
2682 list_add_tail(&vma->vma_link, &obj->vma_list);
2683 if (!i915_is_ggtt(vm))
2684 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2690 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2691 struct i915_address_space *vm)
2693 struct i915_vma *vma;
2695 vma = i915_gem_obj_to_vma(obj, vm);
2697 vma = __i915_gem_vma_create(obj, vm,
2698 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2704 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2705 const struct i915_ggtt_view *view)
2707 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2708 struct i915_vma *vma;
2711 return ERR_PTR(-EINVAL);
2713 vma = i915_gem_obj_to_ggtt_view(obj, view);
2719 vma = __i915_gem_vma_create(obj, ggtt, view);
2726 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2727 struct sg_table *st)
2729 unsigned int column, row;
2730 unsigned int src_idx;
2731 struct scatterlist *sg = st->sgl;
2735 for (column = 0; column < width; column++) {
2736 src_idx = width * (height - 1) + column;
2737 for (row = 0; row < height; row++) {
2739 /* We don't need the pages, but need to initialize
2740 * the entries so the sg list can be happily traversed.
2741 * The only thing we need are DMA addresses.
2743 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2744 sg_dma_address(sg) = in[src_idx];
2745 sg_dma_len(sg) = PAGE_SIZE;
2752 static struct sg_table *
2753 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2754 struct drm_i915_gem_object *obj)
2756 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2757 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
2758 struct sg_page_iter sg_iter;
2760 dma_addr_t *page_addr_list;
2761 struct sg_table *st;
2764 /* Allocate a temporary list of source pages for random access. */
2765 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2766 sizeof(dma_addr_t));
2767 if (!page_addr_list)
2768 return ERR_PTR(ret);
2770 /* Allocate target SG list. */
2771 st = kmalloc(sizeof(*st), GFP_KERNEL);
2775 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
2779 /* Populate source page list from the object. */
2781 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2782 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2786 /* Rotate the pages. */
2787 rotate_pages(page_addr_list,
2788 rot_info->width_pages, rot_info->height_pages,
2792 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2793 obj->base.size, rot_info->pitch, rot_info->height,
2794 rot_info->pixel_format, rot_info->width_pages,
2795 rot_info->height_pages, size_pages);
2797 drm_free_large(page_addr_list);
2804 drm_free_large(page_addr_list);
2807 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2808 obj->base.size, ret, rot_info->pitch, rot_info->height,
2809 rot_info->pixel_format, rot_info->width_pages,
2810 rot_info->height_pages, size_pages);
2811 return ERR_PTR(ret);
2814 static struct sg_table *
2815 intel_partial_pages(const struct i915_ggtt_view *view,
2816 struct drm_i915_gem_object *obj)
2818 struct sg_table *st;
2819 struct scatterlist *sg;
2820 struct sg_page_iter obj_sg_iter;
2823 st = kmalloc(sizeof(*st), GFP_KERNEL);
2827 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2833 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2834 view->params.partial.offset)
2836 if (st->nents >= view->params.partial.size)
2839 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2840 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2841 sg_dma_len(sg) = PAGE_SIZE;
2852 return ERR_PTR(ret);
2856 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2860 if (vma->ggtt_view.pages)
2863 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2864 vma->ggtt_view.pages = vma->obj->pages;
2865 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2866 vma->ggtt_view.pages =
2867 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2868 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2869 vma->ggtt_view.pages =
2870 intel_partial_pages(&vma->ggtt_view, vma->obj);
2872 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2873 vma->ggtt_view.type);
2875 if (!vma->ggtt_view.pages) {
2876 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2877 vma->ggtt_view.type);
2879 } else if (IS_ERR(vma->ggtt_view.pages)) {
2880 ret = PTR_ERR(vma->ggtt_view.pages);
2881 vma->ggtt_view.pages = NULL;
2882 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2883 vma->ggtt_view.type, ret);
2890 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2892 * @cache_level: mapping cache level
2893 * @flags: flags like global or local mapping
2895 * DMA addresses are taken from the scatter-gather table of this object (or of
2896 * this VMA in case of non-default GGTT views) and PTE entries set up.
2897 * Note that DMA addresses are also the only part of the SG table we care about.
2899 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2905 if (WARN_ON(flags == 0))
2909 if (flags & PIN_GLOBAL)
2910 bind_flags |= GLOBAL_BIND;
2911 if (flags & PIN_USER)
2912 bind_flags |= LOCAL_BIND;
2914 if (flags & PIN_UPDATE)
2915 bind_flags |= vma->bound;
2917 bind_flags &= ~vma->bound;
2919 if (bind_flags == 0)
2922 if (vma->bound == 0 && vma->vm->allocate_va_range) {
2923 trace_i915_va_alloc(vma->vm,
2926 VM_TO_TRACE_NAME(vma->vm));
2928 /* XXX: i915_vma_pin() will fix this +- hack */
2930 ret = vma->vm->allocate_va_range(vma->vm,
2938 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2942 vma->bound |= bind_flags;
2948 * i915_ggtt_view_size - Get the size of a GGTT view.
2949 * @obj: Object the view is of.
2950 * @view: The view in question.
2952 * @return The size of the GGTT view in bytes.
2955 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2956 const struct i915_ggtt_view *view)
2958 if (view->type == I915_GGTT_VIEW_NORMAL) {
2959 return obj->base.size;
2960 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
2961 return view->rotation_info.size;
2962 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2963 return view->params.partial.size << PAGE_SHIFT;
2965 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2966 return obj->base.size;