drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_trace.h"
  31 #include "intel_drv.h"
  32
  33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
  34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
  35
  36 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
  37 {
  38         bool has_aliasing_ppgtt;
  39         bool has_full_ppgtt;
  40
  41         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
  42         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
  43         if (IS_GEN8(dev))
  44                 has_full_ppgtt = false; /* XXX why? */
  45
  46         if (enable_ppgtt == 0 || !has_aliasing_ppgtt)
  47                 return 0;
  48
  49         if (enable_ppgtt == 1)
  50                 return 1;
  51
  52         if (enable_ppgtt == 2 && has_full_ppgtt)
  53                 return 2;
  54
  55 #ifdef CONFIG_INTEL_IOMMU
  56         /* Disable ppgtt on SNB if VT-d is on. */
  57         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
  58                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
  59                 return 0;
  60         }
  61 #endif
  62
  63         /* Early VLV doesn't have this */
  64         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
  65             dev->pdev->revision < 0xb) {
  66                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
  67                 return 0;
  68         }
  69
  70         return has_aliasing_ppgtt ? 1 : 0;
  71 }
  72
  73
  74 static void ppgtt_bind_vma(struct i915_vma *vma,
  75                            enum i915_cache_level cache_level,
  76                            u32 flags);
  77 static void ppgtt_unbind_vma(struct i915_vma *vma);
  78
  79 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  80                                              enum i915_cache_level level,
  81                                              bool valid)
  82 {
  83         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  84         pte |= addr;
  85
  86         switch (level) {
  87         case I915_CACHE_NONE:
  88                 pte |= PPAT_UNCACHED_INDEX;
  89                 break;
  90         case I915_CACHE_WT:
  91                 pte |= PPAT_DISPLAY_ELLC_INDEX;
  92                 break;
  93         default:
  94                 pte |= PPAT_CACHED_INDEX;
  95                 break;
  96         }
  97
  98         return pte;
  99 }
 100
 101 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
 102                                              dma_addr_t addr,
 103                                              enum i915_cache_level level)
 104 {
 105         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 106         pde |= addr;
 107         if (level != I915_CACHE_NONE)
 108                 pde |= PPAT_CACHED_PDE_INDEX;
 109         else
 110                 pde |= PPAT_UNCACHED_INDEX;
 111         return pde;
 112 }
 113
 114 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 115                                      enum i915_cache_level level,
 116                                      bool valid, u32 unused)
 117 {
 118         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 119         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 120
 121         switch (level) {
 122         case I915_CACHE_L3_LLC:
 123         case I915_CACHE_LLC:
 124                 pte |= GEN6_PTE_CACHE_LLC;
 125                 break;
 126         case I915_CACHE_NONE:
 127                 pte |= GEN6_PTE_UNCACHED;
 128                 break;
 129         default:
 130                 WARN_ON(1);
 131         }
 132
 133         return pte;
 134 }
 135
 136 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 137                                      enum i915_cache_level level,
 138                                      bool valid, u32 unused)
 139 {
 140         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 141         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 142
 143         switch (level) {
 144         case I915_CACHE_L3_LLC:
 145                 pte |= GEN7_PTE_CACHE_L3_LLC;
 146                 break;
 147         case I915_CACHE_LLC:
 148                 pte |= GEN6_PTE_CACHE_LLC;
 149                 break;
 150         case I915_CACHE_NONE:
 151                 pte |= GEN6_PTE_UNCACHED;
 152                 break;
 153         default:
 154                 WARN_ON(1);
 155         }
 156
 157         return pte;
 158 }
 159
 160 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 161                                      enum i915_cache_level level,
 162                                      bool valid, u32 flags)
 163 {
 164         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 165         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 166
 167         if (!(flags & PTE_READ_ONLY))
 168                 pte |= BYT_PTE_WRITEABLE;
 169
 170         if (level != I915_CACHE_NONE)
 171                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 172
 173         return pte;
 174 }
 175
 176 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 177                                      enum i915_cache_level level,
 178                                      bool valid, u32 unused)
 179 {
 180         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 181         pte |= HSW_PTE_ADDR_ENCODE(addr);
 182
 183         if (level != I915_CACHE_NONE)
 184                 pte |= HSW_WB_LLC_AGE3;
 185
 186         return pte;
 187 }
 188
 189 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 190                                       enum i915_cache_level level,
 191                                       bool valid, u32 unused)
 192 {
 193         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 194         pte |= HSW_PTE_ADDR_ENCODE(addr);
 195
 196         switch (level) {
 197         case I915_CACHE_NONE:
 198                 break;
 199         case I915_CACHE_WT:
 200                 pte |= HSW_WT_ELLC_LLC_AGE3;
 201                 break;
 202         default:
 203                 pte |= HSW_WB_ELLC_LLC_AGE3;
 204                 break;
 205         }
 206
 207         return pte;
 208 }
 209
 210 /* Broadwell Page Directory Pointer Descriptors */
 211 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
 212                            uint64_t val)
 213 {
 214         int ret;
 215
 216         BUG_ON(entry >= 4);
 217
 218         ret = intel_ring_begin(ring, 6);
 219         if (ret)
 220                 return ret;
 221
 222         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 223         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 224         intel_ring_emit(ring, (u32)(val >> 32));
 225         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 226         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 227         intel_ring_emit(ring, (u32)(val));
 228         intel_ring_advance(ring);
 229
 230         return 0;
 231 }
 232
 233 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 234                           struct intel_engine_cs *ring)
 235 {
 236         int i, ret;
 237
 238         /* bit of a hack to find the actual last used pd */
 239         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 240
 241         for (i = used_pd - 1; i >= 0; i--) {
 242                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 243                 ret = gen8_write_pdp(ring, i, addr);
 244                 if (ret)
 245                         return ret;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 252                                    uint64_t start,
 253                                    uint64_t length,
 254                                    bool use_scratch)
 255 {
 256         struct i915_hw_ppgtt *ppgtt =
 257                 container_of(vm, struct i915_hw_ppgtt, base);
 258         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 259         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 260         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 261         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 262         unsigned num_entries = length >> PAGE_SHIFT;
 263         unsigned last_pte, i;
 264
 265         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 266                                       I915_CACHE_LLC, use_scratch);
 267
 268         while (num_entries) {
 269                 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
 270
 271                 last_pte = pte + num_entries;
 272                 if (last_pte > GEN8_PTES_PER_PAGE)
 273                         last_pte = GEN8_PTES_PER_PAGE;
 274
 275                 pt_vaddr = kmap_atomic(page_table);
 276
 277                 for (i = pte; i < last_pte; i++) {
 278                         pt_vaddr[i] = scratch_pte;
 279                         num_entries--;
 280                 }
 281
 282                 if (!HAS_LLC(ppgtt->base.dev))
 283                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 284                 kunmap_atomic(pt_vaddr);
 285
 286                 pte = 0;
 287                 if (++pde == GEN8_PDES_PER_PAGE) {
 288                         pdpe++;
 289                         pde = 0;
 290                 }
 291         }
 292 }
 293
 294 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 295                                       struct sg_table *pages,
 296                                       uint64_t start,
 297                                       enum i915_cache_level cache_level, u32 unused)
 298 {
 299         struct i915_hw_ppgtt *ppgtt =
 300                 container_of(vm, struct i915_hw_ppgtt, base);
 301         gen8_gtt_pte_t *pt_vaddr;
 302         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 303         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 304         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 305         struct sg_page_iter sg_iter;
 306
 307         pt_vaddr = NULL;
 308
 309         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 310                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
 311                         break;
 312
 313                 if (pt_vaddr == NULL)
 314                         pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
 315
 316                 pt_vaddr[pte] =
 317                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 318                                         cache_level, true);
 319                 if (++pte == GEN8_PTES_PER_PAGE) {
 320                         if (!HAS_LLC(ppgtt->base.dev))
 321                                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 322                         kunmap_atomic(pt_vaddr);
 323                         pt_vaddr = NULL;
 324                         if (++pde == GEN8_PDES_PER_PAGE) {
 325                                 pdpe++;
 326                                 pde = 0;
 327                         }
 328                         pte = 0;
 329                 }
 330         }
 331         if (pt_vaddr) {
 332                 if (!HAS_LLC(ppgtt->base.dev))
 333                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 334                 kunmap_atomic(pt_vaddr);
 335         }
 336 }
 337
 338 static void gen8_free_page_tables(struct page **pt_pages)
 339 {
 340         int i;
 341
 342         if (pt_pages == NULL)
 343                 return;
 344
 345         for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
 346                 if (pt_pages[i])
 347                         __free_pages(pt_pages[i], 0);
 348 }
 349
 350 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
 351 {
 352         int i;
 353
 354         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 355                 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
 356                 kfree(ppgtt->gen8_pt_pages[i]);
 357                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 358         }
 359
 360         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 361 }
 362
 363 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 364 {
 365         struct pci_dev *hwdev = ppgtt->base.dev->pdev;
 366         int i, j;
 367
 368         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 369                 /* TODO: In the future we'll support sparse mappings, so this
 370                  * will have to change. */
 371                 if (!ppgtt->pd_dma_addr[i])
 372                         continue;
 373
 374                 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
 375                                PCI_DMA_BIDIRECTIONAL);
 376
 377                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 378                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 379                         if (addr)
 380                                 pci_unmap_page(hwdev, addr, PAGE_SIZE,
 381                                                PCI_DMA_BIDIRECTIONAL);
 382                 }
 383         }
 384 }
 385
 386 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 387 {
 388         struct i915_hw_ppgtt *ppgtt =
 389                 container_of(vm, struct i915_hw_ppgtt, base);
 390
 391         gen8_ppgtt_unmap_pages(ppgtt);
 392         gen8_ppgtt_free(ppgtt);
 393 }
 394
 395 static struct page **__gen8_alloc_page_tables(void)
 396 {
 397         struct page **pt_pages;
 398         int i;
 399
 400         pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
 401         if (!pt_pages)
 402                 return ERR_PTR(-ENOMEM);
 403
 404         for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
 405                 pt_pages[i] = alloc_page(GFP_KERNEL);
 406                 if (!pt_pages[i])
 407                         goto bail;
 408         }
 409
 410         return pt_pages;
 411
 412 bail:
 413         gen8_free_page_tables(pt_pages);
 414         kfree(pt_pages);
 415         return ERR_PTR(-ENOMEM);
 416 }
 417
 418 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
 419                                            const int max_pdp)
 420 {
 421         struct page **pt_pages[GEN8_LEGACY_PDPS];
 422         int i, ret;
 423
 424         for (i = 0; i < max_pdp; i++) {
 425                 pt_pages[i] = __gen8_alloc_page_tables();
 426                 if (IS_ERR(pt_pages[i])) {
 427                         ret = PTR_ERR(pt_pages[i]);
 428                         goto unwind_out;
 429                 }
 430         }
 431
 432         /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
 433          * "atomic" - for cleanup purposes.
 434          */
 435         for (i = 0; i < max_pdp; i++)
 436                 ppgtt->gen8_pt_pages[i] = pt_pages[i];
 437
 438         return 0;
 439
 440 unwind_out:
 441         while (i--) {
 442                 gen8_free_page_tables(pt_pages[i]);
 443                 kfree(pt_pages[i]);
 444         }
 445
 446         return ret;
 447 }
 448
 449 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
 450 {
 451         int i;
 452
 453         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 454                 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
 455                                                      sizeof(dma_addr_t),
 456                                                      GFP_KERNEL);
 457                 if (!ppgtt->gen8_pt_dma_addr[i])
 458                         return -ENOMEM;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
 465                                                 const int max_pdp)
 466 {
 467         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 468         if (!ppgtt->pd_pages)
 469                 return -ENOMEM;
 470
 471         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 472         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 473
 474         return 0;
 475 }
 476
 477 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
 478                             const int max_pdp)
 479 {
 480         int ret;
 481
 482         ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
 483         if (ret)
 484                 return ret;
 485
 486         ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
 487         if (ret) {
 488                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 489                 return ret;
 490         }
 491
 492         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 493
 494         ret = gen8_ppgtt_allocate_dma(ppgtt);
 495         if (ret)
 496                 gen8_ppgtt_free(ppgtt);
 497
 498         return ret;
 499 }
 500
 501 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
 502                                              const int pd)
 503 {
 504         dma_addr_t pd_addr;
 505         int ret;
 506
 507         pd_addr = pci_map_page(ppgtt->base.dev->pdev,
 508                                &ppgtt->pd_pages[pd], 0,
 509                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 510
 511         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
 512         if (ret)
 513                 return ret;
 514
 515         ppgtt->pd_dma_addr[pd] = pd_addr;
 516
 517         return 0;
 518 }
 519
 520 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
 521                                         const int pd,
 522                                         const int pt)
 523 {
 524         dma_addr_t pt_addr;
 525         struct page *p;
 526         int ret;
 527
 528         p = ppgtt->gen8_pt_pages[pd][pt];
 529         pt_addr = pci_map_page(ppgtt->base.dev->pdev,
 530                                p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 531         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
 532         if (ret)
 533                 return ret;
 534
 535         ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
 536
 537         return 0;
 538 }
 539
 540 /**
 541  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 542  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 543  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 544  * space.
 545  *
 546  * FIXME: split allocation into smaller pieces. For now we only ever do this
 547  * once, but with full PPGTT, the multiple contiguous allocations will be bad.
 548  * TODO: Do something with the size parameter
 549  */
 550 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 551 {
 552         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 553         const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 554         int i, j, ret;
 555
 556         if (size % (1<<30))
 557                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 558
 559         /* 1. Do all our allocations for page directories and page tables. */
 560         ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
 561         if (ret)
 562                 return ret;
 563
 564         /*
 565          * 2. Create DMA mappings for the page directories and page tables.
 566          */
 567         for (i = 0; i < max_pdp; i++) {
 568                 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
 569                 if (ret)
 570                         goto bail;
 571
 572                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 573                         ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
 574                         if (ret)
 575                                 goto bail;
 576                 }
 577         }
 578
 579         /*
 580          * 3. Map all the page directory entires to point to the page tables
 581          * we've allocated.
 582          *
 583          * For now, the PPGTT helper functions all require that the PDEs are
 584          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 585          * will never need to touch the PDEs again.
 586          */
 587         for (i = 0; i < max_pdp; i++) {
 588                 gen8_ppgtt_pde_t *pd_vaddr;
 589                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 590                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 591                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 592                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 593                                                       I915_CACHE_LLC);
 594                 }
 595                 if (!HAS_LLC(ppgtt->base.dev))
 596                         drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
 597                 kunmap_atomic(pd_vaddr);
 598         }
 599
 600         ppgtt->switch_mm = gen8_mm_switch;
 601         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 602         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 603         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 604         ppgtt->base.start = 0;
 605         ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 606
 607         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
 608
 609         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 610                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 611         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 612                          ppgtt->num_pd_entries,
 613                          (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
 614         return 0;
 615
 616 bail:
 617         gen8_ppgtt_unmap_pages(ppgtt);
 618         gen8_ppgtt_free(ppgtt);
 619         return ret;
 620 }
 621
 622 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 623 {
 624         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 625         struct i915_address_space *vm = &ppgtt->base;
 626         gen6_gtt_pte_t __iomem *pd_addr;
 627         gen6_gtt_pte_t scratch_pte;
 628         uint32_t pd_entry;
 629         int pte, pde;
 630
 631         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 632
 633         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
 634                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 635
 636         seq_printf(m, "  VM %p (pd_offset %x-%x):\n", vm,
 637                    ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
 638         for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
 639                 u32 expected;
 640                 gen6_gtt_pte_t *pt_vaddr;
 641                 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
 642                 pd_entry = readl(pd_addr + pde);
 643                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 644
 645                 if (pd_entry != expected)
 646                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 647                                    pde,
 648                                    pd_entry,
 649                                    expected);
 650                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 651
 652                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
 653                 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
 654                         unsigned long va =
 655                                 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
 656                                 (pte * PAGE_SIZE);
 657                         int i;
 658                         bool found = false;
 659                         for (i = 0; i < 4; i++)
 660                                 if (pt_vaddr[pte + i] != scratch_pte)
 661                                         found = true;
 662                         if (!found)
 663                                 continue;
 664
 665                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
 666                         for (i = 0; i < 4; i++) {
 667                                 if (pt_vaddr[pte + i] != scratch_pte)
 668                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
 669                                 else
 670                                         seq_puts(m, "  SCRATCH ");
 671                         }
 672                         seq_puts(m, "\n");
 673                 }
 674                 kunmap_atomic(pt_vaddr);
 675         }
 676 }
 677
 678 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 679 {
 680         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 681         gen6_gtt_pte_t __iomem *pd_addr;
 682         uint32_t pd_entry;
 683         int i;
 684
 685         WARN_ON(ppgtt->pd_offset & 0x3f);
 686         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 687                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 688         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 689                 dma_addr_t pt_addr;
 690
 691                 pt_addr = ppgtt->pt_dma_addr[i];
 692                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 693                 pd_entry |= GEN6_PDE_VALID;
 694
 695                 writel(pd_entry, pd_addr + i);
 696         }
 697         readl(pd_addr);
 698 }
 699
 700 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 701 {
 702         BUG_ON(ppgtt->pd_offset & 0x3f);
 703
 704         return (ppgtt->pd_offset / 64) << 16;
 705 }
 706
 707 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 708                          struct intel_engine_cs *ring)
 709 {
 710         int ret;
 711
 712         /* NB: TLBs must be flushed and invalidated before a switch */
 713         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 714         if (ret)
 715                 return ret;
 716
 717         ret = intel_ring_begin(ring, 6);
 718         if (ret)
 719                 return ret;
 720
 721         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 722         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 723         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 724         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 725         intel_ring_emit(ring, get_pd_offset(ppgtt));
 726         intel_ring_emit(ring, MI_NOOP);
 727         intel_ring_advance(ring);
 728
 729         return 0;
 730 }
 731
 732 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 733                           struct intel_engine_cs *ring)
 734 {
 735         int ret;
 736
 737         /* NB: TLBs must be flushed and invalidated before a switch */
 738         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 739         if (ret)
 740                 return ret;
 741
 742         ret = intel_ring_begin(ring, 6);
 743         if (ret)
 744                 return ret;
 745
 746         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 747         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 748         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 749         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 750         intel_ring_emit(ring, get_pd_offset(ppgtt));
 751         intel_ring_emit(ring, MI_NOOP);
 752         intel_ring_advance(ring);
 753
 754         /* XXX: RCS is the only one to auto invalidate the TLBs? */
 755         if (ring->id != RCS) {
 756                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 757                 if (ret)
 758                         return ret;
 759         }
 760
 761         return 0;
 762 }
 763
 764 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 765                           struct intel_engine_cs *ring)
 766 {
 767         struct drm_device *dev = ppgtt->base.dev;
 768         struct drm_i915_private *dev_priv = dev->dev_private;
 769
 770
 771         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 772         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 773
 774         POSTING_READ(RING_PP_DIR_DCLV(ring));
 775
 776         return 0;
 777 }
 778
 779 static void gen8_ppgtt_enable(struct drm_device *dev)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         struct intel_engine_cs *ring;
 783         int j;
 784
 785         for_each_ring(ring, dev_priv, j) {
 786                 I915_WRITE(RING_MODE_GEN7(ring),
 787                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 788         }
 789 }
 790
 791 static void gen7_ppgtt_enable(struct drm_device *dev)
 792 {
 793         struct drm_i915_private *dev_priv = dev->dev_private;
 794         struct intel_engine_cs *ring;
 795         uint32_t ecochk, ecobits;
 796         int i;
 797
 798         ecobits = I915_READ(GAC_ECO_BITS);
 799         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 800
 801         ecochk = I915_READ(GAM_ECOCHK);
 802         if (IS_HASWELL(dev)) {
 803                 ecochk |= ECOCHK_PPGTT_WB_HSW;
 804         } else {
 805                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
 806                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 807         }
 808         I915_WRITE(GAM_ECOCHK, ecochk);
 809
 810         for_each_ring(ring, dev_priv, i) {
 811                 /* GFX_MODE is per-ring on gen7+ */
 812                 I915_WRITE(RING_MODE_GEN7(ring),
 813                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 814         }
 815 }
 816
 817 static void gen6_ppgtt_enable(struct drm_device *dev)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         uint32_t ecochk, gab_ctl, ecobits;
 821
 822         ecobits = I915_READ(GAC_ECO_BITS);
 823         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 824                    ECOBITS_PPGTT_CACHE64B);
 825
 826         gab_ctl = I915_READ(GAB_CTL);
 827         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 828
 829         ecochk = I915_READ(GAM_ECOCHK);
 830         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 831
 832         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 833 }
 834
 835 /* PPGTT support for Sandybdrige/Gen6 and later */
 836 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 837                                    uint64_t start,
 838                                    uint64_t length,
 839                                    bool use_scratch)
 840 {
 841         struct i915_hw_ppgtt *ppgtt =
 842                 container_of(vm, struct i915_hw_ppgtt, base);
 843         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 844         unsigned first_entry = start >> PAGE_SHIFT;
 845         unsigned num_entries = length >> PAGE_SHIFT;
 846         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 847         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 848         unsigned last_pte, i;
 849
 850         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 851
 852         while (num_entries) {
 853                 last_pte = first_pte + num_entries;
 854                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 855                         last_pte = I915_PPGTT_PT_ENTRIES;
 856
 857                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 858
 859                 for (i = first_pte; i < last_pte; i++)
 860                         pt_vaddr[i] = scratch_pte;
 861
 862                 kunmap_atomic(pt_vaddr);
 863
 864                 num_entries -= last_pte - first_pte;
 865                 first_pte = 0;
 866                 act_pt++;
 867         }
 868 }
 869
 870 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 871                                       struct sg_table *pages,
 872                                       uint64_t start,
 873                                       enum i915_cache_level cache_level, u32 flags)
 874 {
 875         struct i915_hw_ppgtt *ppgtt =
 876                 container_of(vm, struct i915_hw_ppgtt, base);
 877         gen6_gtt_pte_t *pt_vaddr;
 878         unsigned first_entry = start >> PAGE_SHIFT;
 879         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 880         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 881         struct sg_page_iter sg_iter;
 882
 883         pt_vaddr = NULL;
 884         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 885                 if (pt_vaddr == NULL)
 886                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 887
 888                 pt_vaddr[act_pte] =
 889                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
 890                                        cache_level, true, flags);
 891
 892                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 893                         kunmap_atomic(pt_vaddr);
 894                         pt_vaddr = NULL;
 895                         act_pt++;
 896                         act_pte = 0;
 897                 }
 898         }
 899         if (pt_vaddr)
 900                 kunmap_atomic(pt_vaddr);
 901 }
 902
 903 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 904 {
 905         int i;
 906
 907         if (ppgtt->pt_dma_addr) {
 908                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 909                         pci_unmap_page(ppgtt->base.dev->pdev,
 910                                        ppgtt->pt_dma_addr[i],
 911                                        4096, PCI_DMA_BIDIRECTIONAL);
 912         }
 913 }
 914
 915 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
 916 {
 917         int i;
 918
 919         kfree(ppgtt->pt_dma_addr);
 920         for (i = 0; i < ppgtt->num_pd_entries; i++)
 921                 __free_page(ppgtt->pt_pages[i]);
 922         kfree(ppgtt->pt_pages);
 923 }
 924
 925 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 926 {
 927         struct i915_hw_ppgtt *ppgtt =
 928                 container_of(vm, struct i915_hw_ppgtt, base);
 929
 930         drm_mm_remove_node(&ppgtt->node);
 931
 932         gen6_ppgtt_unmap_pages(ppgtt);
 933         gen6_ppgtt_free(ppgtt);
 934 }
 935
 936 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
 937 {
 938         struct drm_device *dev = ppgtt->base.dev;
 939         struct drm_i915_private *dev_priv = dev->dev_private;
 940         bool retried = false;
 941         int ret;
 942
 943         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 944          * allocator works in address space sizes, so it's multiplied by page
 945          * size. We allocate at the top of the GTT to avoid fragmentation.
 946          */
 947         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
 948 alloc:
 949         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
 950                                                   &ppgtt->node, GEN6_PD_SIZE,
 951                                                   GEN6_PD_ALIGN, 0,
 952                                                   0, dev_priv->gtt.base.total,
 953                                                   DRM_MM_TOPDOWN);
 954         if (ret == -ENOSPC && !retried) {
 955                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
 956                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
 957                                                I915_CACHE_NONE,
 958                                                0, dev_priv->gtt.base.total,
 959                                                0);
 960                 if (ret)
 961                         return ret;
 962
 963                 retried = true;
 964                 goto alloc;
 965         }
 966
 967         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
 968                 DRM_DEBUG("Forced to use aperture for PDEs\n");
 969
 970         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 971         return ret;
 972 }
 973
 974 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
 975 {
 976         int i;
 977
 978         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
 979                                   GFP_KERNEL);
 980
 981         if (!ppgtt->pt_pages)
 982                 return -ENOMEM;
 983
 984         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 985                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 986                 if (!ppgtt->pt_pages[i]) {
 987                         gen6_ppgtt_free(ppgtt);
 988                         return -ENOMEM;
 989                 }
 990         }
 991
 992         return 0;
 993 }
 994
 995 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
 996 {
 997         int ret;
 998
 999         ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1000         if (ret)
1001                 return ret;
1002
1003         ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1004         if (ret) {
1005                 drm_mm_remove_node(&ppgtt->node);
1006                 return ret;
1007         }
1008
1009         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1010                                      GFP_KERNEL);
1011         if (!ppgtt->pt_dma_addr) {
1012                 drm_mm_remove_node(&ppgtt->node);
1013                 gen6_ppgtt_free(ppgtt);
1014                 return -ENOMEM;
1015         }
1016
1017         return 0;
1018 }
1019
1020 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1021 {
1022         struct drm_device *dev = ppgtt->base.dev;
1023         int i;
1024
1025         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1026                 dma_addr_t pt_addr;
1027
1028                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1029                                        PCI_DMA_BIDIRECTIONAL);
1030
1031                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1032                         gen6_ppgtt_unmap_pages(ppgtt);
1033                         return -EIO;
1034                 }
1035
1036                 ppgtt->pt_dma_addr[i] = pt_addr;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1043 {
1044         struct drm_device *dev = ppgtt->base.dev;
1045         struct drm_i915_private *dev_priv = dev->dev_private;
1046         int ret;
1047
1048         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1049         if (IS_GEN6(dev)) {
1050                 ppgtt->switch_mm = gen6_mm_switch;
1051         } else if (IS_HASWELL(dev)) {
1052                 ppgtt->switch_mm = hsw_mm_switch;
1053         } else if (IS_GEN7(dev)) {
1054                 ppgtt->switch_mm = gen7_mm_switch;
1055         } else
1056                 BUG();
1057
1058         ret = gen6_ppgtt_alloc(ppgtt);
1059         if (ret)
1060                 return ret;
1061
1062         ret = gen6_ppgtt_setup_page_tables(ppgtt);
1063         if (ret) {
1064                 gen6_ppgtt_free(ppgtt);
1065                 return ret;
1066         }
1067
1068         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1069         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1070         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1071         ppgtt->base.start = 0;
1072         ppgtt->base.total =  ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1073         ppgtt->debug_dump = gen6_dump_ppgtt;
1074
1075         ppgtt->pd_offset =
1076                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1077
1078         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1079
1080         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1081                          ppgtt->node.size >> 20,
1082                          ppgtt->node.start / PAGE_SIZE);
1083
1084         gen6_write_pdes(ppgtt);
1085         DRM_DEBUG("Adding PPGTT at offset %x\n",
1086                   ppgtt->pd_offset << 10);
1087
1088         return 0;
1089 }
1090
1091 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1092 {
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094
1095         ppgtt->base.dev = dev;
1096         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1097
1098         if (INTEL_INFO(dev)->gen < 8)
1099                 return gen6_ppgtt_init(ppgtt);
1100         else if (IS_GEN8(dev) || IS_GEN9(dev))
1101                 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1102         else
1103                 BUG();
1104 }
1105 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1106 {
1107         struct drm_i915_private *dev_priv = dev->dev_private;
1108         int ret = 0;
1109
1110         ret = __hw_ppgtt_init(dev, ppgtt);
1111         if (ret == 0) {
1112                 kref_init(&ppgtt->ref);
1113                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1114                             ppgtt->base.total);
1115                 i915_init_vm(dev_priv, &ppgtt->base);
1116         }
1117
1118         return ret;
1119 }
1120
1121 int i915_ppgtt_init_hw(struct drm_device *dev)
1122 {
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124         struct intel_engine_cs *ring;
1125         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1126         int i, ret = 0;
1127
1128         /* In the case of execlists, PPGTT is enabled by the context descriptor
1129          * and the PDPs are contained within the context itself.  We don't
1130          * need to do anything here. */
1131         if (i915.enable_execlists)
1132                 return 0;
1133
1134         if (!USES_PPGTT(dev))
1135                 return 0;
1136
1137         if (IS_GEN6(dev))
1138                 gen6_ppgtt_enable(dev);
1139         else if (IS_GEN7(dev))
1140                 gen7_ppgtt_enable(dev);
1141         else if (INTEL_INFO(dev)->gen >= 8)
1142                 gen8_ppgtt_enable(dev);
1143         else
1144                 WARN_ON(1);
1145
1146         if (ppgtt) {
1147                 for_each_ring(ring, dev_priv, i) {
1148                         ret = ppgtt->switch_mm(ppgtt, ring);
1149                         if (ret != 0)
1150                                 return ret;
1151                 }
1152         }
1153
1154         return ret;
1155 }
1156 struct i915_hw_ppgtt *
1157 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1158 {
1159         struct i915_hw_ppgtt *ppgtt;
1160         int ret;
1161
1162         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1163         if (!ppgtt)
1164                 return ERR_PTR(-ENOMEM);
1165
1166         ret = i915_ppgtt_init(dev, ppgtt);
1167         if (ret) {
1168                 kfree(ppgtt);
1169                 return ERR_PTR(ret);
1170         }
1171
1172         ppgtt->file_priv = fpriv;
1173
1174         trace_i915_ppgtt_create(&ppgtt->base);
1175
1176         return ppgtt;
1177 }
1178
1179 void  i915_ppgtt_release(struct kref *kref)
1180 {
1181         struct i915_hw_ppgtt *ppgtt =
1182                 container_of(kref, struct i915_hw_ppgtt, ref);
1183
1184         trace_i915_ppgtt_release(&ppgtt->base);
1185
1186         /* vmas should already be unbound */
1187         WARN_ON(!list_empty(&ppgtt->base.active_list));
1188         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1189
1190         list_del(&ppgtt->base.global_link);
1191         drm_mm_takedown(&ppgtt->base.mm);
1192
1193         ppgtt->base.cleanup(&ppgtt->base);
1194         kfree(ppgtt);
1195 }
1196
1197 static void
1198 ppgtt_bind_vma(struct i915_vma *vma,
1199                enum i915_cache_level cache_level,
1200                u32 flags)
1201 {
1202         /* Currently applicable only to VLV */
1203         if (vma->obj->gt_ro)
1204                 flags |= PTE_READ_ONLY;
1205
1206         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1207                                 cache_level, flags);
1208 }
1209
1210 static void ppgtt_unbind_vma(struct i915_vma *vma)
1211 {
1212         vma->vm->clear_range(vma->vm,
1213                              vma->node.start,
1214                              vma->obj->base.size,
1215                              true);
1216 }
1217
1218 extern int intel_iommu_gfx_mapped;
1219 /* Certain Gen5 chipsets require require idling the GPU before
1220  * unmapping anything from the GTT when VT-d is enabled.
1221  */
1222 static inline bool needs_idle_maps(struct drm_device *dev)
1223 {
1224 #ifdef CONFIG_INTEL_IOMMU
1225         /* Query intel_iommu to see if we need the workaround. Presumably that
1226          * was loaded first.
1227          */
1228         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1229                 return true;
1230 #endif
1231         return false;
1232 }
1233
1234 static bool do_idling(struct drm_i915_private *dev_priv)
1235 {
1236         bool ret = dev_priv->mm.interruptible;
1237
1238         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1239                 dev_priv->mm.interruptible = false;
1240                 if (i915_gpu_idle(dev_priv->dev)) {
1241                         DRM_ERROR("Couldn't idle GPU\n");
1242                         /* Wait a bit, in hopes it avoids the hang */
1243                         udelay(10);
1244                 }
1245         }
1246
1247         return ret;
1248 }
1249
1250 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1251 {
1252         if (unlikely(dev_priv->gtt.do_idle_maps))
1253                 dev_priv->mm.interruptible = interruptible;
1254 }
1255
1256 void i915_check_and_clear_faults(struct drm_device *dev)
1257 {
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         struct intel_engine_cs *ring;
1260         int i;
1261
1262         if (INTEL_INFO(dev)->gen < 6)
1263                 return;
1264
1265         for_each_ring(ring, dev_priv, i) {
1266                 u32 fault_reg;
1267                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1268                 if (fault_reg & RING_FAULT_VALID) {
1269                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1270                                          "\tAddr: 0x%08lx\n"
1271                                          "\tAddress space: %s\n"
1272                                          "\tSource ID: %d\n"
1273                                          "\tType: %d\n",
1274                                          fault_reg & PAGE_MASK,
1275                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1276                                          RING_FAULT_SRCID(fault_reg),
1277                                          RING_FAULT_FAULT_TYPE(fault_reg));
1278                         I915_WRITE(RING_FAULT_REG(ring),
1279                                    fault_reg & ~RING_FAULT_VALID);
1280                 }
1281         }
1282         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1283 }
1284
1285 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1286 {
1287         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1288                 intel_gtt_chipset_flush();
1289         } else {
1290                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1291                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1292         }
1293 }
1294
1295 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1296 {
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298
1299         /* Don't bother messing with faults pre GEN6 as we have little
1300          * documentation supporting that it's a good idea.
1301          */
1302         if (INTEL_INFO(dev)->gen < 6)
1303                 return;
1304
1305         i915_check_and_clear_faults(dev);
1306
1307         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1308                                        dev_priv->gtt.base.start,
1309                                        dev_priv->gtt.base.total,
1310                                        true);
1311
1312         i915_ggtt_flush(dev_priv);
1313 }
1314
1315 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1316 {
1317         struct drm_i915_private *dev_priv = dev->dev_private;
1318         struct drm_i915_gem_object *obj;
1319         struct i915_address_space *vm;
1320
1321         i915_check_and_clear_faults(dev);
1322
1323         /* First fill our portion of the GTT with scratch pages */
1324         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1325                                        dev_priv->gtt.base.start,
1326                                        dev_priv->gtt.base.total,
1327                                        true);
1328
1329         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1330                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1331                                                            &dev_priv->gtt.base);
1332                 if (!vma)
1333                         continue;
1334
1335                 i915_gem_clflush_object(obj, obj->pin_display);
1336                 /* The bind_vma code tries to be smart about tracking mappings.
1337                  * Unfortunately above, we've just wiped out the mappings
1338                  * without telling our object about it. So we need to fake it.
1339                  */
1340                 vma->bound &= ~GLOBAL_BIND;
1341                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1342         }
1343
1344
1345         if (INTEL_INFO(dev)->gen >= 8) {
1346                 if (IS_CHERRYVIEW(dev))
1347                         chv_setup_private_ppat(dev_priv);
1348                 else
1349                         bdw_setup_private_ppat(dev_priv);
1350
1351                 return;
1352         }
1353
1354         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1355                 /* TODO: Perhaps it shouldn't be gen6 specific */
1356                 if (i915_is_ggtt(vm)) {
1357                         if (dev_priv->mm.aliasing_ppgtt)
1358                                 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1359                         continue;
1360                 }
1361
1362                 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1363         }
1364
1365         i915_ggtt_flush(dev_priv);
1366 }
1367
1368 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1369 {
1370         if (obj->has_dma_mapping)
1371                 return 0;
1372
1373         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1374                         obj->pages->sgl, obj->pages->nents,
1375                         PCI_DMA_BIDIRECTIONAL))
1376                 return -ENOSPC;
1377
1378         return 0;
1379 }
1380
1381 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1382 {
1383 #ifdef writeq
1384         writeq(pte, addr);
1385 #else
1386         iowrite32((u32)pte, addr);
1387         iowrite32(pte >> 32, addr + 4);
1388 #endif
1389 }
1390
1391 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1392                                      struct sg_table *st,
1393                                      uint64_t start,
1394                                      enum i915_cache_level level, u32 unused)
1395 {
1396         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1397         unsigned first_entry = start >> PAGE_SHIFT;
1398         gen8_gtt_pte_t __iomem *gtt_entries =
1399                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1400         int i = 0;
1401         struct sg_page_iter sg_iter;
1402         dma_addr_t addr = 0; /* shut up gcc */
1403
1404         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1405                 addr = sg_dma_address(sg_iter.sg) +
1406                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1407                 gen8_set_pte(&gtt_entries[i],
1408                              gen8_pte_encode(addr, level, true));
1409                 i++;
1410         }
1411
1412         /*
1413          * XXX: This serves as a posting read to make sure that the PTE has
1414          * actually been updated. There is some concern that even though
1415          * registers and PTEs are within the same BAR that they are potentially
1416          * of NUMA access patterns. Therefore, even with the way we assume
1417          * hardware should work, we must keep this posting read for paranoia.
1418          */
1419         if (i != 0)
1420                 WARN_ON(readq(&gtt_entries[i-1])
1421                         != gen8_pte_encode(addr, level, true));
1422
1423         /* This next bit makes the above posting read even more important. We
1424          * want to flush the TLBs only after we're certain all the PTE updates
1425          * have finished.
1426          */
1427         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1428         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1429 }
1430
1431 /*
1432  * Binds an object into the global gtt with the specified cache level. The object
1433  * will be accessible to the GPU via commands whose operands reference offsets
1434  * within the global GTT as well as accessible by the GPU through the GMADR
1435  * mapped BAR (dev_priv->mm.gtt->gtt).
1436  */
1437 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1438                                      struct sg_table *st,
1439                                      uint64_t start,
1440                                      enum i915_cache_level level, u32 flags)
1441 {
1442         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1443         unsigned first_entry = start >> PAGE_SHIFT;
1444         gen6_gtt_pte_t __iomem *gtt_entries =
1445                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1446         int i = 0;
1447         struct sg_page_iter sg_iter;
1448         dma_addr_t addr = 0;
1449
1450         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1451                 addr = sg_page_iter_dma_address(&sg_iter);
1452                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1453                 i++;
1454         }
1455
1456         /* XXX: This serves as a posting read to make sure that the PTE has
1457          * actually been updated. There is some concern that even though
1458          * registers and PTEs are within the same BAR that they are potentially
1459          * of NUMA access patterns. Therefore, even with the way we assume
1460          * hardware should work, we must keep this posting read for paranoia.
1461          */
1462         if (i != 0) {
1463                 unsigned long gtt = readl(&gtt_entries[i-1]);
1464                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1465         }
1466
1467         /* This next bit makes the above posting read even more important. We
1468          * want to flush the TLBs only after we're certain all the PTE updates
1469          * have finished.
1470          */
1471         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1472         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1473 }
1474
1475 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1476                                   uint64_t start,
1477                                   uint64_t length,
1478                                   bool use_scratch)
1479 {
1480         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1481         unsigned first_entry = start >> PAGE_SHIFT;
1482         unsigned num_entries = length >> PAGE_SHIFT;
1483         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1484                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1485         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1486         int i;
1487
1488         if (WARN(num_entries > max_entries,
1489                  "First entry = %d; Num entries = %d (max=%d)\n",
1490                  first_entry, num_entries, max_entries))
1491                 num_entries = max_entries;
1492
1493         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1494                                       I915_CACHE_LLC,
1495                                       use_scratch);
1496         for (i = 0; i < num_entries; i++)
1497                 gen8_set_pte(&gtt_base[i], scratch_pte);
1498         readl(gtt_base);
1499 }
1500
1501 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1502                                   uint64_t start,
1503                                   uint64_t length,
1504                                   bool use_scratch)
1505 {
1506         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1507         unsigned first_entry = start >> PAGE_SHIFT;
1508         unsigned num_entries = length >> PAGE_SHIFT;
1509         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1510                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1511         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1512         int i;
1513
1514         if (WARN(num_entries > max_entries,
1515                  "First entry = %d; Num entries = %d (max=%d)\n",
1516                  first_entry, num_entries, max_entries))
1517                 num_entries = max_entries;
1518
1519         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1520
1521         for (i = 0; i < num_entries; i++)
1522                 iowrite32(scratch_pte, &gtt_base[i]);
1523         readl(gtt_base);
1524 }
1525
1526
1527 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1528                                enum i915_cache_level cache_level,
1529                                u32 unused)
1530 {
1531         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1532         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1533                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1534
1535         BUG_ON(!i915_is_ggtt(vma->vm));
1536         intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1537         vma->bound = GLOBAL_BIND;
1538 }
1539
1540 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1541                                   uint64_t start,
1542                                   uint64_t length,
1543                                   bool unused)
1544 {
1545         unsigned first_entry = start >> PAGE_SHIFT;
1546         unsigned num_entries = length >> PAGE_SHIFT;
1547         intel_gtt_clear_range(first_entry, num_entries);
1548 }
1549
1550 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1551 {
1552         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1553         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1554
1555         BUG_ON(!i915_is_ggtt(vma->vm));
1556         vma->bound = 0;
1557         intel_gtt_clear_range(first, size);
1558 }
1559
1560 static void ggtt_bind_vma(struct i915_vma *vma,
1561                           enum i915_cache_level cache_level,
1562                           u32 flags)
1563 {
1564         struct drm_device *dev = vma->vm->dev;
1565         struct drm_i915_private *dev_priv = dev->dev_private;
1566         struct drm_i915_gem_object *obj = vma->obj;
1567
1568         /* Currently applicable only to VLV */
1569         if (obj->gt_ro)
1570                 flags |= PTE_READ_ONLY;
1571
1572         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1573          * or we have a global mapping already but the cacheability flags have
1574          * changed, set the global PTEs.
1575          *
1576          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1577          * instead if none of the above hold true.
1578          *
1579          * NB: A global mapping should only be needed for special regions like
1580          * "gtt mappable", SNB errata, or if specified via special execbuf
1581          * flags. At all other times, the GPU will use the aliasing PPGTT.
1582          */
1583         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1584                 if (!(vma->bound & GLOBAL_BIND) ||
1585                     (cache_level != obj->cache_level)) {
1586                         vma->vm->insert_entries(vma->vm, obj->pages,
1587                                                 vma->node.start,
1588                                                 cache_level, flags);
1589                         vma->bound |= GLOBAL_BIND;
1590                 }
1591         }
1592
1593         if (dev_priv->mm.aliasing_ppgtt &&
1594             (!(vma->bound & LOCAL_BIND) ||
1595              (cache_level != obj->cache_level))) {
1596                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1597                 appgtt->base.insert_entries(&appgtt->base,
1598                                             vma->obj->pages,
1599                                             vma->node.start,
1600                                             cache_level, flags);
1601                 vma->bound |= LOCAL_BIND;
1602         }
1603 }
1604
1605 static void ggtt_unbind_vma(struct i915_vma *vma)
1606 {
1607         struct drm_device *dev = vma->vm->dev;
1608         struct drm_i915_private *dev_priv = dev->dev_private;
1609         struct drm_i915_gem_object *obj = vma->obj;
1610
1611         if (vma->bound & GLOBAL_BIND) {
1612                 vma->vm->clear_range(vma->vm,
1613                                      vma->node.start,
1614                                      obj->base.size,
1615                                      true);
1616                 vma->bound &= ~GLOBAL_BIND;
1617         }
1618
1619         if (vma->bound & LOCAL_BIND) {
1620                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1621                 appgtt->base.clear_range(&appgtt->base,
1622                                          vma->node.start,
1623                                          obj->base.size,
1624                                          true);
1625                 vma->bound &= ~LOCAL_BIND;
1626         }
1627 }
1628
1629 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1630 {
1631         struct drm_device *dev = obj->base.dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633         bool interruptible;
1634
1635         interruptible = do_idling(dev_priv);
1636
1637         if (!obj->has_dma_mapping)
1638                 dma_unmap_sg(&dev->pdev->dev,
1639                              obj->pages->sgl, obj->pages->nents,
1640                              PCI_DMA_BIDIRECTIONAL);
1641
1642         undo_idling(dev_priv, interruptible);
1643 }
1644
1645 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1646                                   unsigned long color,
1647                                   unsigned long *start,
1648                                   unsigned long *end)
1649 {
1650         if (node->color != color)
1651                 *start += 4096;
1652
1653         if (!list_empty(&node->node_list)) {
1654                 node = list_entry(node->node_list.next,
1655                                   struct drm_mm_node,
1656                                   node_list);
1657                 if (node->allocated && node->color != color)
1658                         *end -= 4096;
1659         }
1660 }
1661
1662 int i915_gem_setup_global_gtt(struct drm_device *dev,
1663                               unsigned long start,
1664                               unsigned long mappable_end,
1665                               unsigned long end)
1666 {
1667         /* Let GEM Manage all of the aperture.
1668          *
1669          * However, leave one page at the end still bound to the scratch page.
1670          * There are a number of places where the hardware apparently prefetches
1671          * past the end of the object, and we've seen multiple hangs with the
1672          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1673          * aperture.  One page should be enough to keep any prefetching inside
1674          * of the aperture.
1675          */
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1678         struct drm_mm_node *entry;
1679         struct drm_i915_gem_object *obj;
1680         unsigned long hole_start, hole_end;
1681         int ret;
1682
1683         BUG_ON(mappable_end > end);
1684
1685         /* Subtract the guard page ... */
1686         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1687         if (!HAS_LLC(dev))
1688                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1689
1690         /* Mark any preallocated objects as occupied */
1691         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1692                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1693
1694                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1695                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1696
1697                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1698                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1699                 if (ret) {
1700                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1701                         return ret;
1702                 }
1703                 vma->bound |= GLOBAL_BIND;
1704         }
1705
1706         dev_priv->gtt.base.start = start;
1707         dev_priv->gtt.base.total = end - start;
1708
1709         /* Clear any non-preallocated blocks */
1710         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1711                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1712                               hole_start, hole_end);
1713                 ggtt_vm->clear_range(ggtt_vm, hole_start,
1714                                      hole_end - hole_start, true);
1715         }
1716
1717         /* And finally clear the reserved guard page */
1718         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1719
1720         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1721                 struct i915_hw_ppgtt *ppgtt;
1722
1723                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1724                 if (!ppgtt)
1725                         return -ENOMEM;
1726
1727                 ret = __hw_ppgtt_init(dev, ppgtt);
1728                 if (ret != 0)
1729                         return ret;
1730
1731                 dev_priv->mm.aliasing_ppgtt = ppgtt;
1732         }
1733
1734         return 0;
1735 }
1736
1737 void i915_gem_init_global_gtt(struct drm_device *dev)
1738 {
1739         struct drm_i915_private *dev_priv = dev->dev_private;
1740         unsigned long gtt_size, mappable_size;
1741
1742         gtt_size = dev_priv->gtt.base.total;
1743         mappable_size = dev_priv->gtt.mappable_end;
1744
1745         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1746 }
1747
1748 void i915_global_gtt_cleanup(struct drm_device *dev)
1749 {
1750         struct drm_i915_private *dev_priv = dev->dev_private;
1751         struct i915_address_space *vm = &dev_priv->gtt.base;
1752
1753         if (dev_priv->mm.aliasing_ppgtt) {
1754                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1755
1756                 ppgtt->base.cleanup(&ppgtt->base);
1757         }
1758
1759         if (drm_mm_initialized(&vm->mm)) {
1760                 drm_mm_takedown(&vm->mm);
1761                 list_del(&vm->global_link);
1762         }
1763
1764         vm->cleanup(vm);
1765 }
1766
1767 static int setup_scratch_page(struct drm_device *dev)
1768 {
1769         struct drm_i915_private *dev_priv = dev->dev_private;
1770         struct page *page;
1771         dma_addr_t dma_addr;
1772
1773         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1774         if (page == NULL)
1775                 return -ENOMEM;
1776         set_pages_uc(page, 1);
1777
1778 #ifdef CONFIG_INTEL_IOMMU
1779         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1780                                 PCI_DMA_BIDIRECTIONAL);
1781         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1782                 return -EINVAL;
1783 #else
1784         dma_addr = page_to_phys(page);
1785 #endif
1786         dev_priv->gtt.base.scratch.page = page;
1787         dev_priv->gtt.base.scratch.addr = dma_addr;
1788
1789         return 0;
1790 }
1791
1792 static void teardown_scratch_page(struct drm_device *dev)
1793 {
1794         struct drm_i915_private *dev_priv = dev->dev_private;
1795         struct page *page = dev_priv->gtt.base.scratch.page;
1796
1797         set_pages_wb(page, 1);
1798         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1799                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1800         __free_page(page);
1801 }
1802
1803 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1804 {
1805         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1806         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1807         return snb_gmch_ctl << 20;
1808 }
1809
1810 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1811 {
1812         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1813         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1814         if (bdw_gmch_ctl)
1815                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1816
1817 #ifdef CONFIG_X86_32
1818         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1819         if (bdw_gmch_ctl > 4)
1820                 bdw_gmch_ctl = 4;
1821 #endif
1822
1823         return bdw_gmch_ctl << 20;
1824 }
1825
1826 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1827 {
1828         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1829         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1830
1831         if (gmch_ctrl)
1832                 return 1 << (20 + gmch_ctrl);
1833
1834         return 0;
1835 }
1836
1837 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1838 {
1839         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1840         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1841         return snb_gmch_ctl << 25; /* 32 MB units */
1842 }
1843
1844 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1845 {
1846         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1847         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1848         return bdw_gmch_ctl << 25; /* 32 MB units */
1849 }
1850
1851 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1852 {
1853         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1854         gmch_ctrl &= SNB_GMCH_GMS_MASK;
1855
1856         /*
1857          * 0x0  to 0x10: 32MB increments starting at 0MB
1858          * 0x11 to 0x16: 4MB increments starting at 8MB
1859          * 0x17 to 0x1d: 4MB increments start at 36MB
1860          */
1861         if (gmch_ctrl < 0x11)
1862                 return gmch_ctrl << 25;
1863         else if (gmch_ctrl < 0x17)
1864                 return (gmch_ctrl - 0x11 + 2) << 22;
1865         else
1866                 return (gmch_ctrl - 0x17 + 9) << 22;
1867 }
1868
1869 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
1870 {
1871         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1872         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
1873
1874         if (gen9_gmch_ctl < 0xf0)
1875                 return gen9_gmch_ctl << 25; /* 32 MB units */
1876         else
1877                 /* 4MB increments starting at 0xf0 for 4MB */
1878                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
1879 }
1880
1881 static int ggtt_probe_common(struct drm_device *dev,
1882                              size_t gtt_size)
1883 {
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         phys_addr_t gtt_phys_addr;
1886         int ret;
1887
1888         /* For Modern GENs the PTEs and register space are split in the BAR */
1889         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1890                 (pci_resource_len(dev->pdev, 0) / 2);
1891
1892         dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1893         if (!dev_priv->gtt.gsm) {
1894                 DRM_ERROR("Failed to map the gtt page table\n");
1895                 return -ENOMEM;
1896         }
1897
1898         ret = setup_scratch_page(dev);
1899         if (ret) {
1900                 DRM_ERROR("Scratch setup failed\n");
1901                 /* iounmap will also get called at remove, but meh */
1902                 iounmap(dev_priv->gtt.gsm);
1903         }
1904
1905         return ret;
1906 }
1907
1908 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1909  * bits. When using advanced contexts each context stores its own PAT, but
1910  * writing this data shouldn't be harmful even in those cases. */
1911 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1912 {
1913         uint64_t pat;
1914
1915         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1916               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1917               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1918               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1919               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1920               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1921               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1922               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1923
1924         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1925          * write would work. */
1926         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1927         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1928 }
1929
1930 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1931 {
1932         uint64_t pat;
1933
1934         /*
1935          * Map WB on BDW to snooped on CHV.
1936          *
1937          * Only the snoop bit has meaning for CHV, the rest is
1938          * ignored.
1939          *
1940          * Note that the harware enforces snooping for all page
1941          * table accesses. The snoop bit is actually ignored for
1942          * PDEs.
1943          */
1944         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1945               GEN8_PPAT(1, 0) |
1946               GEN8_PPAT(2, 0) |
1947               GEN8_PPAT(3, 0) |
1948               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1949               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1950               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1951               GEN8_PPAT(7, CHV_PPAT_SNOOP);
1952
1953         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1954         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1955 }
1956
1957 static int gen8_gmch_probe(struct drm_device *dev,
1958                            size_t *gtt_total,
1959                            size_t *stolen,
1960                            phys_addr_t *mappable_base,
1961                            unsigned long *mappable_end)
1962 {
1963         struct drm_i915_private *dev_priv = dev->dev_private;
1964         unsigned int gtt_size;
1965         u16 snb_gmch_ctl;
1966         int ret;
1967
1968         /* TODO: We're not aware of mappable constraints on gen8 yet */
1969         *mappable_base = pci_resource_start(dev->pdev, 2);
1970         *mappable_end = pci_resource_len(dev->pdev, 2);
1971
1972         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1973                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1974
1975         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1976
1977         if (INTEL_INFO(dev)->gen >= 9) {
1978                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
1979                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1980         } else if (IS_CHERRYVIEW(dev)) {
1981                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1982                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1983         } else {
1984                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1985                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1986         }
1987
1988         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1989
1990         if (IS_CHERRYVIEW(dev))
1991                 chv_setup_private_ppat(dev_priv);
1992         else
1993                 bdw_setup_private_ppat(dev_priv);
1994
1995         ret = ggtt_probe_common(dev, gtt_size);
1996
1997         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1998         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1999
2000         return ret;
2001 }
2002
2003 static int gen6_gmch_probe(struct drm_device *dev,
2004                            size_t *gtt_total,
2005                            size_t *stolen,
2006                            phys_addr_t *mappable_base,
2007                            unsigned long *mappable_end)
2008 {
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         unsigned int gtt_size;
2011         u16 snb_gmch_ctl;
2012         int ret;
2013
2014         *mappable_base = pci_resource_start(dev->pdev, 2);
2015         *mappable_end = pci_resource_len(dev->pdev, 2);
2016
2017         /* 64/512MB is the current min/max we actually know of, but this is just
2018          * a coarse sanity check.
2019          */
2020         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2021                 DRM_ERROR("Unknown GMADR size (%lx)\n",
2022                           dev_priv->gtt.mappable_end);
2023                 return -ENXIO;
2024         }
2025
2026         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2027                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2028         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2029
2030         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2031
2032         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2033         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2034
2035         ret = ggtt_probe_common(dev, gtt_size);
2036
2037         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2038         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2039
2040         return ret;
2041 }
2042
2043 static void gen6_gmch_remove(struct i915_address_space *vm)
2044 {
2045
2046         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2047
2048         iounmap(gtt->gsm);
2049         teardown_scratch_page(vm->dev);
2050 }
2051
2052 static int i915_gmch_probe(struct drm_device *dev,
2053                            size_t *gtt_total,
2054                            size_t *stolen,
2055                            phys_addr_t *mappable_base,
2056                            unsigned long *mappable_end)
2057 {
2058         struct drm_i915_private *dev_priv = dev->dev_private;
2059         int ret;
2060
2061         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2062         if (!ret) {
2063                 DRM_ERROR("failed to set up gmch\n");
2064                 return -EIO;
2065         }
2066
2067         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2068
2069         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2070         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2071
2072         if (unlikely(dev_priv->gtt.do_idle_maps))
2073                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2074
2075         return 0;
2076 }
2077
2078 static void i915_gmch_remove(struct i915_address_space *vm)
2079 {
2080         intel_gmch_remove();
2081 }
2082
2083 int i915_gem_gtt_init(struct drm_device *dev)
2084 {
2085         struct drm_i915_private *dev_priv = dev->dev_private;
2086         struct i915_gtt *gtt = &dev_priv->gtt;
2087         int ret;
2088
2089         if (INTEL_INFO(dev)->gen <= 5) {
2090                 gtt->gtt_probe = i915_gmch_probe;
2091                 gtt->base.cleanup = i915_gmch_remove;
2092         } else if (INTEL_INFO(dev)->gen < 8) {
2093                 gtt->gtt_probe = gen6_gmch_probe;
2094                 gtt->base.cleanup = gen6_gmch_remove;
2095                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2096                         gtt->base.pte_encode = iris_pte_encode;
2097                 else if (IS_HASWELL(dev))
2098                         gtt->base.pte_encode = hsw_pte_encode;
2099                 else if (IS_VALLEYVIEW(dev))
2100                         gtt->base.pte_encode = byt_pte_encode;
2101                 else if (INTEL_INFO(dev)->gen >= 7)
2102                         gtt->base.pte_encode = ivb_pte_encode;
2103                 else
2104                         gtt->base.pte_encode = snb_pte_encode;
2105         } else {
2106                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2107                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2108         }
2109
2110         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2111                              &gtt->mappable_base, &gtt->mappable_end);
2112         if (ret)
2113                 return ret;
2114
2115         gtt->base.dev = dev;
2116
2117         /* GMADR is the PCI mmio aperture into the global GTT. */
2118         DRM_INFO("Memory usable by graphics device = %zdM\n",
2119                  gtt->base.total >> 20);
2120         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2121         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2122 #ifdef CONFIG_INTEL_IOMMU
2123         if (intel_iommu_gfx_mapped)
2124                 DRM_INFO("VT-d active for gfx access\n");
2125 #endif
2126         /*
2127          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2128          * user's requested state against the hardware/driver capabilities.  We
2129          * do this now so that we can print out any log messages once rather
2130          * than every time we check intel_enable_ppgtt().
2131          */
2132         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2133         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2134
2135         return 0;
2136 }
2137
2138 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2139                                               struct i915_address_space *vm)
2140 {
2141         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2142         if (vma == NULL)
2143                 return ERR_PTR(-ENOMEM);
2144
2145         INIT_LIST_HEAD(&vma->vma_link);
2146         INIT_LIST_HEAD(&vma->mm_list);
2147         INIT_LIST_HEAD(&vma->exec_list);
2148         vma->vm = vm;
2149         vma->obj = obj;
2150
2151         switch (INTEL_INFO(vm->dev)->gen) {
2152         case 9:
2153         case 8:
2154         case 7:
2155         case 6:
2156                 if (i915_is_ggtt(vm)) {
2157                         vma->unbind_vma = ggtt_unbind_vma;
2158                         vma->bind_vma = ggtt_bind_vma;
2159                 } else {
2160                         vma->unbind_vma = ppgtt_unbind_vma;
2161                         vma->bind_vma = ppgtt_bind_vma;
2162                 }
2163                 break;
2164         case 5:
2165         case 4:
2166         case 3:
2167         case 2:
2168                 BUG_ON(!i915_is_ggtt(vm));
2169                 vma->unbind_vma = i915_ggtt_unbind_vma;
2170                 vma->bind_vma = i915_ggtt_bind_vma;
2171                 break;
2172         default:
2173                 BUG();
2174         }
2175
2176         /* Keep GGTT vmas first to make debug easier */
2177         if (i915_is_ggtt(vm))
2178                 list_add(&vma->vma_link, &obj->vma_list);
2179         else {
2180                 list_add_tail(&vma->vma_link, &obj->vma_list);
2181                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2182         }
2183
2184         return vma;
2185 }
2186
2187 struct i915_vma *
2188 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2189                                   struct i915_address_space *vm)
2190 {
2191         struct i915_vma *vma;
2192
2193         vma = i915_gem_obj_to_vma(obj, vm);
2194         if (!vma)
2195                 vma = __i915_gem_vma_create(obj, vm);
2196
2197         return vma;
2198 }