2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_trace.h"
31 #include "intel_drv.h"
33 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
36 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
38 bool has_aliasing_ppgtt;
41 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
42 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
44 has_full_ppgtt = false; /* XXX why? */
46 if (enable_ppgtt == 0 || !has_aliasing_ppgtt)
49 if (enable_ppgtt == 1)
52 if (enable_ppgtt == 2 && has_full_ppgtt)
55 #ifdef CONFIG_INTEL_IOMMU
56 /* Disable ppgtt on SNB if VT-d is on. */
57 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
58 DRM_INFO("Disabling PPGTT because VT-d is on\n");
63 /* Early VLV doesn't have this */
64 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
65 dev->pdev->revision < 0xb) {
66 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
70 return has_aliasing_ppgtt ? 1 : 0;
74 static void ppgtt_bind_vma(struct i915_vma *vma,
75 enum i915_cache_level cache_level,
77 static void ppgtt_unbind_vma(struct i915_vma *vma);
79 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
80 enum i915_cache_level level,
83 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
88 pte |= PPAT_UNCACHED_INDEX;
91 pte |= PPAT_DISPLAY_ELLC_INDEX;
94 pte |= PPAT_CACHED_INDEX;
101 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
103 enum i915_cache_level level)
105 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
107 if (level != I915_CACHE_NONE)
108 pde |= PPAT_CACHED_PDE_INDEX;
110 pde |= PPAT_UNCACHED_INDEX;
114 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
115 enum i915_cache_level level,
116 bool valid, u32 unused)
118 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
119 pte |= GEN6_PTE_ADDR_ENCODE(addr);
122 case I915_CACHE_L3_LLC:
124 pte |= GEN6_PTE_CACHE_LLC;
126 case I915_CACHE_NONE:
127 pte |= GEN6_PTE_UNCACHED;
136 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
137 enum i915_cache_level level,
138 bool valid, u32 unused)
140 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
141 pte |= GEN6_PTE_ADDR_ENCODE(addr);
144 case I915_CACHE_L3_LLC:
145 pte |= GEN7_PTE_CACHE_L3_LLC;
148 pte |= GEN6_PTE_CACHE_LLC;
150 case I915_CACHE_NONE:
151 pte |= GEN6_PTE_UNCACHED;
160 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
161 enum i915_cache_level level,
162 bool valid, u32 flags)
164 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
165 pte |= GEN6_PTE_ADDR_ENCODE(addr);
167 /* Mark the page as writeable. Other platforms don't have a
168 * setting for read-only/writable, so this matches that behavior.
170 if (!(flags & PTE_READ_ONLY))
171 pte |= BYT_PTE_WRITEABLE;
173 if (level != I915_CACHE_NONE)
174 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
179 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
180 enum i915_cache_level level,
181 bool valid, u32 unused)
183 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
184 pte |= HSW_PTE_ADDR_ENCODE(addr);
186 if (level != I915_CACHE_NONE)
187 pte |= HSW_WB_LLC_AGE3;
192 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
193 enum i915_cache_level level,
194 bool valid, u32 unused)
196 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
197 pte |= HSW_PTE_ADDR_ENCODE(addr);
200 case I915_CACHE_NONE:
203 pte |= HSW_WT_ELLC_LLC_AGE3;
206 pte |= HSW_WB_ELLC_LLC_AGE3;
213 /* Broadwell Page Directory Pointer Descriptors */
214 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
221 ret = intel_ring_begin(ring, 6);
225 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
226 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
227 intel_ring_emit(ring, (u32)(val >> 32));
228 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
229 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
230 intel_ring_emit(ring, (u32)(val));
231 intel_ring_advance(ring);
236 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
237 struct intel_engine_cs *ring)
241 /* bit of a hack to find the actual last used pd */
242 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
244 for (i = used_pd - 1; i >= 0; i--) {
245 dma_addr_t addr = ppgtt->pd_dma_addr[i];
246 ret = gen8_write_pdp(ring, i, addr);
254 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
259 struct i915_hw_ppgtt *ppgtt =
260 container_of(vm, struct i915_hw_ppgtt, base);
261 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
262 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
263 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
264 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
265 unsigned num_entries = length >> PAGE_SHIFT;
266 unsigned last_pte, i;
268 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
269 I915_CACHE_LLC, use_scratch);
271 while (num_entries) {
272 struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
274 last_pte = pte + num_entries;
275 if (last_pte > GEN8_PTES_PER_PAGE)
276 last_pte = GEN8_PTES_PER_PAGE;
278 pt_vaddr = kmap_atomic(page_table);
280 for (i = pte; i < last_pte; i++) {
281 pt_vaddr[i] = scratch_pte;
285 if (!HAS_LLC(ppgtt->base.dev))
286 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
287 kunmap_atomic(pt_vaddr);
290 if (++pde == GEN8_PDES_PER_PAGE) {
297 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
298 struct sg_table *pages,
300 enum i915_cache_level cache_level, u32 unused)
302 struct i915_hw_ppgtt *ppgtt =
303 container_of(vm, struct i915_hw_ppgtt, base);
304 gen8_gtt_pte_t *pt_vaddr;
305 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
306 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
307 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
308 struct sg_page_iter sg_iter;
312 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
313 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
316 if (pt_vaddr == NULL)
317 pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
320 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
322 if (++pte == GEN8_PTES_PER_PAGE) {
323 if (!HAS_LLC(ppgtt->base.dev))
324 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
325 kunmap_atomic(pt_vaddr);
327 if (++pde == GEN8_PDES_PER_PAGE) {
335 if (!HAS_LLC(ppgtt->base.dev))
336 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
337 kunmap_atomic(pt_vaddr);
341 static void gen8_free_page_tables(struct page **pt_pages)
345 if (pt_pages == NULL)
348 for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
350 __free_pages(pt_pages[i], 0);
353 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
357 for (i = 0; i < ppgtt->num_pd_pages; i++) {
358 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
359 kfree(ppgtt->gen8_pt_pages[i]);
360 kfree(ppgtt->gen8_pt_dma_addr[i]);
363 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
366 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
368 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
371 for (i = 0; i < ppgtt->num_pd_pages; i++) {
372 /* TODO: In the future we'll support sparse mappings, so this
373 * will have to change. */
374 if (!ppgtt->pd_dma_addr[i])
377 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
378 PCI_DMA_BIDIRECTIONAL);
380 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
381 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
383 pci_unmap_page(hwdev, addr, PAGE_SIZE,
384 PCI_DMA_BIDIRECTIONAL);
389 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
391 struct i915_hw_ppgtt *ppgtt =
392 container_of(vm, struct i915_hw_ppgtt, base);
394 gen8_ppgtt_unmap_pages(ppgtt);
395 gen8_ppgtt_free(ppgtt);
398 static struct page **__gen8_alloc_page_tables(void)
400 struct page **pt_pages;
403 pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
405 return ERR_PTR(-ENOMEM);
407 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
408 pt_pages[i] = alloc_page(GFP_KERNEL);
416 gen8_free_page_tables(pt_pages);
418 return ERR_PTR(-ENOMEM);
421 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
424 struct page **pt_pages[GEN8_LEGACY_PDPS];
427 for (i = 0; i < max_pdp; i++) {
428 pt_pages[i] = __gen8_alloc_page_tables();
429 if (IS_ERR(pt_pages[i])) {
430 ret = PTR_ERR(pt_pages[i]);
435 /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
436 * "atomic" - for cleanup purposes.
438 for (i = 0; i < max_pdp; i++)
439 ppgtt->gen8_pt_pages[i] = pt_pages[i];
445 gen8_free_page_tables(pt_pages[i]);
452 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
456 for (i = 0; i < ppgtt->num_pd_pages; i++) {
457 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
460 if (!ppgtt->gen8_pt_dma_addr[i])
467 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
470 ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
471 if (!ppgtt->pd_pages)
474 ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
475 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
480 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
485 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
489 ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
491 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
495 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
497 ret = gen8_ppgtt_allocate_dma(ppgtt);
499 gen8_ppgtt_free(ppgtt);
504 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
510 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
511 &ppgtt->pd_pages[pd], 0,
512 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
514 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
518 ppgtt->pd_dma_addr[pd] = pd_addr;
523 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
531 p = ppgtt->gen8_pt_pages[pd][pt];
532 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
533 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
534 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
538 ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
544 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
545 * with a net effect resembling a 2-level page table in normal x86 terms. Each
546 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
549 * FIXME: split allocation into smaller pieces. For now we only ever do this
550 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
551 * TODO: Do something with the size parameter
553 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
555 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
556 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
560 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
562 /* 1. Do all our allocations for page directories and page tables. */
563 ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
568 * 2. Create DMA mappings for the page directories and page tables.
570 for (i = 0; i < max_pdp; i++) {
571 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
575 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
576 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
583 * 3. Map all the page directory entires to point to the page tables
586 * For now, the PPGTT helper functions all require that the PDEs are
587 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
588 * will never need to touch the PDEs again.
590 for (i = 0; i < max_pdp; i++) {
591 gen8_ppgtt_pde_t *pd_vaddr;
592 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
593 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
594 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
595 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
598 if (!HAS_LLC(ppgtt->base.dev))
599 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
600 kunmap_atomic(pd_vaddr);
603 ppgtt->switch_mm = gen8_mm_switch;
604 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
605 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
606 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
607 ppgtt->base.start = 0;
608 ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
610 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
612 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
613 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
614 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
615 ppgtt->num_pd_entries,
616 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
620 gen8_ppgtt_unmap_pages(ppgtt);
621 gen8_ppgtt_free(ppgtt);
625 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
627 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
628 struct i915_address_space *vm = &ppgtt->base;
629 gen6_gtt_pte_t __iomem *pd_addr;
630 gen6_gtt_pte_t scratch_pte;
634 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
636 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
637 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
639 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
640 ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
641 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
643 gen6_gtt_pte_t *pt_vaddr;
644 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
645 pd_entry = readl(pd_addr + pde);
646 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
648 if (pd_entry != expected)
649 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
653 seq_printf(m, "\tPDE: %x\n", pd_entry);
655 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
656 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
658 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
662 for (i = 0; i < 4; i++)
663 if (pt_vaddr[pte + i] != scratch_pte)
668 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
669 for (i = 0; i < 4; i++) {
670 if (pt_vaddr[pte + i] != scratch_pte)
671 seq_printf(m, " %08x", pt_vaddr[pte + i]);
673 seq_puts(m, " SCRATCH ");
677 kunmap_atomic(pt_vaddr);
681 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
683 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
684 gen6_gtt_pte_t __iomem *pd_addr;
688 WARN_ON(ppgtt->pd_offset & 0x3f);
689 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
690 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
691 for (i = 0; i < ppgtt->num_pd_entries; i++) {
694 pt_addr = ppgtt->pt_dma_addr[i];
695 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
696 pd_entry |= GEN6_PDE_VALID;
698 writel(pd_entry, pd_addr + i);
703 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
705 BUG_ON(ppgtt->pd_offset & 0x3f);
707 return (ppgtt->pd_offset / 64) << 16;
710 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
711 struct intel_engine_cs *ring)
715 /* NB: TLBs must be flushed and invalidated before a switch */
716 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
720 ret = intel_ring_begin(ring, 6);
724 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
725 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
726 intel_ring_emit(ring, PP_DIR_DCLV_2G);
727 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
728 intel_ring_emit(ring, get_pd_offset(ppgtt));
729 intel_ring_emit(ring, MI_NOOP);
730 intel_ring_advance(ring);
735 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
736 struct intel_engine_cs *ring)
740 /* NB: TLBs must be flushed and invalidated before a switch */
741 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
745 ret = intel_ring_begin(ring, 6);
749 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
750 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
751 intel_ring_emit(ring, PP_DIR_DCLV_2G);
752 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
753 intel_ring_emit(ring, get_pd_offset(ppgtt));
754 intel_ring_emit(ring, MI_NOOP);
755 intel_ring_advance(ring);
757 /* XXX: RCS is the only one to auto invalidate the TLBs? */
758 if (ring->id != RCS) {
759 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
767 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
768 struct intel_engine_cs *ring)
770 struct drm_device *dev = ppgtt->base.dev;
771 struct drm_i915_private *dev_priv = dev->dev_private;
774 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
775 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
777 POSTING_READ(RING_PP_DIR_DCLV(ring));
782 static void gen8_ppgtt_enable(struct drm_device *dev)
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 struct intel_engine_cs *ring;
788 for_each_ring(ring, dev_priv, j) {
789 I915_WRITE(RING_MODE_GEN7(ring),
790 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
794 static void gen7_ppgtt_enable(struct drm_device *dev)
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct intel_engine_cs *ring;
798 uint32_t ecochk, ecobits;
801 ecobits = I915_READ(GAC_ECO_BITS);
802 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
804 ecochk = I915_READ(GAM_ECOCHK);
805 if (IS_HASWELL(dev)) {
806 ecochk |= ECOCHK_PPGTT_WB_HSW;
808 ecochk |= ECOCHK_PPGTT_LLC_IVB;
809 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
811 I915_WRITE(GAM_ECOCHK, ecochk);
813 for_each_ring(ring, dev_priv, i) {
814 /* GFX_MODE is per-ring on gen7+ */
815 I915_WRITE(RING_MODE_GEN7(ring),
816 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
820 static void gen6_ppgtt_enable(struct drm_device *dev)
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t ecochk, gab_ctl, ecobits;
825 ecobits = I915_READ(GAC_ECO_BITS);
826 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
827 ECOBITS_PPGTT_CACHE64B);
829 gab_ctl = I915_READ(GAB_CTL);
830 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
832 ecochk = I915_READ(GAM_ECOCHK);
833 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
835 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
838 /* PPGTT support for Sandybdrige/Gen6 and later */
839 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
844 struct i915_hw_ppgtt *ppgtt =
845 container_of(vm, struct i915_hw_ppgtt, base);
846 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
847 unsigned first_entry = start >> PAGE_SHIFT;
848 unsigned num_entries = length >> PAGE_SHIFT;
849 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
850 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
851 unsigned last_pte, i;
853 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
855 while (num_entries) {
856 last_pte = first_pte + num_entries;
857 if (last_pte > I915_PPGTT_PT_ENTRIES)
858 last_pte = I915_PPGTT_PT_ENTRIES;
860 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
862 for (i = first_pte; i < last_pte; i++)
863 pt_vaddr[i] = scratch_pte;
865 kunmap_atomic(pt_vaddr);
867 num_entries -= last_pte - first_pte;
873 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
874 struct sg_table *pages,
876 enum i915_cache_level cache_level, u32 flags)
878 struct i915_hw_ppgtt *ppgtt =
879 container_of(vm, struct i915_hw_ppgtt, base);
880 gen6_gtt_pte_t *pt_vaddr;
881 unsigned first_entry = start >> PAGE_SHIFT;
882 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
883 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
884 struct sg_page_iter sg_iter;
887 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
888 if (pt_vaddr == NULL)
889 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
892 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
893 cache_level, true, flags);
895 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
896 kunmap_atomic(pt_vaddr);
903 kunmap_atomic(pt_vaddr);
906 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
910 if (ppgtt->pt_dma_addr) {
911 for (i = 0; i < ppgtt->num_pd_entries; i++)
912 pci_unmap_page(ppgtt->base.dev->pdev,
913 ppgtt->pt_dma_addr[i],
914 4096, PCI_DMA_BIDIRECTIONAL);
918 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
922 kfree(ppgtt->pt_dma_addr);
923 for (i = 0; i < ppgtt->num_pd_entries; i++)
924 __free_page(ppgtt->pt_pages[i]);
925 kfree(ppgtt->pt_pages);
928 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
930 struct i915_hw_ppgtt *ppgtt =
931 container_of(vm, struct i915_hw_ppgtt, base);
933 drm_mm_remove_node(&ppgtt->node);
935 gen6_ppgtt_unmap_pages(ppgtt);
936 gen6_ppgtt_free(ppgtt);
939 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
941 struct drm_device *dev = ppgtt->base.dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
943 bool retried = false;
946 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
947 * allocator works in address space sizes, so it's multiplied by page
948 * size. We allocate at the top of the GTT to avoid fragmentation.
950 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
952 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
953 &ppgtt->node, GEN6_PD_SIZE,
955 0, dev_priv->gtt.base.total,
957 if (ret == -ENOSPC && !retried) {
958 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
959 GEN6_PD_SIZE, GEN6_PD_ALIGN,
961 0, dev_priv->gtt.base.total,
970 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
971 DRM_DEBUG("Forced to use aperture for PDEs\n");
973 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
977 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
981 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
984 if (!ppgtt->pt_pages)
987 for (i = 0; i < ppgtt->num_pd_entries; i++) {
988 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
989 if (!ppgtt->pt_pages[i]) {
990 gen6_ppgtt_free(ppgtt);
998 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1002 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1006 ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1008 drm_mm_remove_node(&ppgtt->node);
1012 ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1014 if (!ppgtt->pt_dma_addr) {
1015 drm_mm_remove_node(&ppgtt->node);
1016 gen6_ppgtt_free(ppgtt);
1023 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1025 struct drm_device *dev = ppgtt->base.dev;
1028 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1031 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1032 PCI_DMA_BIDIRECTIONAL);
1034 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1035 gen6_ppgtt_unmap_pages(ppgtt);
1039 ppgtt->pt_dma_addr[i] = pt_addr;
1045 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1047 struct drm_device *dev = ppgtt->base.dev;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1051 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1053 ppgtt->switch_mm = gen6_mm_switch;
1054 } else if (IS_HASWELL(dev)) {
1055 ppgtt->switch_mm = hsw_mm_switch;
1056 } else if (IS_GEN7(dev)) {
1057 ppgtt->switch_mm = gen7_mm_switch;
1061 ret = gen6_ppgtt_alloc(ppgtt);
1065 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1067 gen6_ppgtt_free(ppgtt);
1071 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1072 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1073 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1074 ppgtt->base.start = 0;
1075 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1076 ppgtt->debug_dump = gen6_dump_ppgtt;
1079 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1081 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1083 DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1084 ppgtt->node.size >> 20,
1085 ppgtt->node.start / PAGE_SIZE);
1087 gen6_write_pdes(ppgtt);
1088 DRM_DEBUG("Adding PPGTT at offset %x\n",
1089 ppgtt->pd_offset << 10);
1094 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1098 ppgtt->base.dev = dev;
1099 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1101 if (INTEL_INFO(dev)->gen < 8)
1102 return gen6_ppgtt_init(ppgtt);
1103 else if (IS_GEN8(dev) || IS_GEN9(dev))
1104 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1108 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1113 ret = __hw_ppgtt_init(dev, ppgtt);
1115 kref_init(&ppgtt->ref);
1116 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1118 i915_init_vm(dev_priv, &ppgtt->base);
1124 int i915_ppgtt_init_hw(struct drm_device *dev)
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127 struct intel_engine_cs *ring;
1128 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1131 /* In the case of execlists, PPGTT is enabled by the context descriptor
1132 * and the PDPs are contained within the context itself. We don't
1133 * need to do anything here. */
1134 if (i915.enable_execlists)
1137 if (!USES_PPGTT(dev))
1141 gen6_ppgtt_enable(dev);
1142 else if (IS_GEN7(dev))
1143 gen7_ppgtt_enable(dev);
1144 else if (INTEL_INFO(dev)->gen >= 8)
1145 gen8_ppgtt_enable(dev);
1150 for_each_ring(ring, dev_priv, i) {
1151 ret = ppgtt->switch_mm(ppgtt, ring);
1159 struct i915_hw_ppgtt *
1160 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1162 struct i915_hw_ppgtt *ppgtt;
1165 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1167 return ERR_PTR(-ENOMEM);
1169 ret = i915_ppgtt_init(dev, ppgtt);
1172 return ERR_PTR(ret);
1175 ppgtt->file_priv = fpriv;
1180 void i915_ppgtt_release(struct kref *kref)
1182 struct i915_hw_ppgtt *ppgtt =
1183 container_of(kref, struct i915_hw_ppgtt, ref);
1185 /* vmas should already be unbound */
1186 WARN_ON(!list_empty(&ppgtt->base.active_list));
1187 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1189 list_del(&ppgtt->base.global_link);
1190 drm_mm_takedown(&ppgtt->base.mm);
1192 ppgtt->base.cleanup(&ppgtt->base);
1197 ppgtt_bind_vma(struct i915_vma *vma,
1198 enum i915_cache_level cache_level,
1201 /* Currently applicable only to VLV */
1202 if (vma->obj->gt_ro)
1203 flags |= PTE_READ_ONLY;
1205 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1206 cache_level, flags);
1209 static void ppgtt_unbind_vma(struct i915_vma *vma)
1211 vma->vm->clear_range(vma->vm,
1213 vma->obj->base.size,
1217 extern int intel_iommu_gfx_mapped;
1218 /* Certain Gen5 chipsets require require idling the GPU before
1219 * unmapping anything from the GTT when VT-d is enabled.
1221 static inline bool needs_idle_maps(struct drm_device *dev)
1223 #ifdef CONFIG_INTEL_IOMMU
1224 /* Query intel_iommu to see if we need the workaround. Presumably that
1227 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1233 static bool do_idling(struct drm_i915_private *dev_priv)
1235 bool ret = dev_priv->mm.interruptible;
1237 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1238 dev_priv->mm.interruptible = false;
1239 if (i915_gpu_idle(dev_priv->dev)) {
1240 DRM_ERROR("Couldn't idle GPU\n");
1241 /* Wait a bit, in hopes it avoids the hang */
1249 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1251 if (unlikely(dev_priv->gtt.do_idle_maps))
1252 dev_priv->mm.interruptible = interruptible;
1255 void i915_check_and_clear_faults(struct drm_device *dev)
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 struct intel_engine_cs *ring;
1261 if (INTEL_INFO(dev)->gen < 6)
1264 for_each_ring(ring, dev_priv, i) {
1266 fault_reg = I915_READ(RING_FAULT_REG(ring));
1267 if (fault_reg & RING_FAULT_VALID) {
1268 DRM_DEBUG_DRIVER("Unexpected fault\n"
1270 "\tAddress space: %s\n"
1273 fault_reg & PAGE_MASK,
1274 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1275 RING_FAULT_SRCID(fault_reg),
1276 RING_FAULT_FAULT_TYPE(fault_reg));
1277 I915_WRITE(RING_FAULT_REG(ring),
1278 fault_reg & ~RING_FAULT_VALID);
1281 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1284 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1286 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1287 intel_gtt_chipset_flush();
1289 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1290 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1294 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1298 /* Don't bother messing with faults pre GEN6 as we have little
1299 * documentation supporting that it's a good idea.
1301 if (INTEL_INFO(dev)->gen < 6)
1304 i915_check_and_clear_faults(dev);
1306 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1307 dev_priv->gtt.base.start,
1308 dev_priv->gtt.base.total,
1311 i915_ggtt_flush(dev_priv);
1314 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 struct drm_i915_gem_object *obj;
1318 struct i915_address_space *vm;
1320 i915_check_and_clear_faults(dev);
1322 /* First fill our portion of the GTT with scratch pages */
1323 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1324 dev_priv->gtt.base.start,
1325 dev_priv->gtt.base.total,
1328 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1329 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1330 &dev_priv->gtt.base);
1334 i915_gem_clflush_object(obj, obj->pin_display);
1335 /* The bind_vma code tries to be smart about tracking mappings.
1336 * Unfortunately above, we've just wiped out the mappings
1337 * without telling our object about it. So we need to fake it.
1339 vma->bound &= ~GLOBAL_BIND;
1340 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1344 if (INTEL_INFO(dev)->gen >= 8) {
1345 if (IS_CHERRYVIEW(dev))
1346 chv_setup_private_ppat(dev_priv);
1348 bdw_setup_private_ppat(dev_priv);
1353 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1354 /* TODO: Perhaps it shouldn't be gen6 specific */
1355 if (i915_is_ggtt(vm)) {
1356 if (dev_priv->mm.aliasing_ppgtt)
1357 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1361 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1364 i915_ggtt_flush(dev_priv);
1367 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1369 if (obj->has_dma_mapping)
1372 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1373 obj->pages->sgl, obj->pages->nents,
1374 PCI_DMA_BIDIRECTIONAL))
1380 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1385 iowrite32((u32)pte, addr);
1386 iowrite32(pte >> 32, addr + 4);
1390 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1391 struct sg_table *st,
1393 enum i915_cache_level level, u32 unused)
1395 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1396 unsigned first_entry = start >> PAGE_SHIFT;
1397 gen8_gtt_pte_t __iomem *gtt_entries =
1398 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1400 struct sg_page_iter sg_iter;
1401 dma_addr_t addr = 0; /* shut up gcc */
1403 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1404 addr = sg_dma_address(sg_iter.sg) +
1405 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1406 gen8_set_pte(>t_entries[i],
1407 gen8_pte_encode(addr, level, true));
1412 * XXX: This serves as a posting read to make sure that the PTE has
1413 * actually been updated. There is some concern that even though
1414 * registers and PTEs are within the same BAR that they are potentially
1415 * of NUMA access patterns. Therefore, even with the way we assume
1416 * hardware should work, we must keep this posting read for paranoia.
1419 WARN_ON(readq(>t_entries[i-1])
1420 != gen8_pte_encode(addr, level, true));
1422 /* This next bit makes the above posting read even more important. We
1423 * want to flush the TLBs only after we're certain all the PTE updates
1426 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1427 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1431 * Binds an object into the global gtt with the specified cache level. The object
1432 * will be accessible to the GPU via commands whose operands reference offsets
1433 * within the global GTT as well as accessible by the GPU through the GMADR
1434 * mapped BAR (dev_priv->mm.gtt->gtt).
1436 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1437 struct sg_table *st,
1439 enum i915_cache_level level, u32 flags)
1441 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1442 unsigned first_entry = start >> PAGE_SHIFT;
1443 gen6_gtt_pte_t __iomem *gtt_entries =
1444 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1446 struct sg_page_iter sg_iter;
1447 dma_addr_t addr = 0;
1449 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1450 addr = sg_page_iter_dma_address(&sg_iter);
1451 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
1455 /* XXX: This serves as a posting read to make sure that the PTE has
1456 * actually been updated. There is some concern that even though
1457 * registers and PTEs are within the same BAR that they are potentially
1458 * of NUMA access patterns. Therefore, even with the way we assume
1459 * hardware should work, we must keep this posting read for paranoia.
1462 unsigned long gtt = readl(>t_entries[i-1]);
1463 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1466 /* This next bit makes the above posting read even more important. We
1467 * want to flush the TLBs only after we're certain all the PTE updates
1470 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1471 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1474 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1479 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1480 unsigned first_entry = start >> PAGE_SHIFT;
1481 unsigned num_entries = length >> PAGE_SHIFT;
1482 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1483 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1484 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1487 if (WARN(num_entries > max_entries,
1488 "First entry = %d; Num entries = %d (max=%d)\n",
1489 first_entry, num_entries, max_entries))
1490 num_entries = max_entries;
1492 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1495 for (i = 0; i < num_entries; i++)
1496 gen8_set_pte(>t_base[i], scratch_pte);
1500 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1505 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1506 unsigned first_entry = start >> PAGE_SHIFT;
1507 unsigned num_entries = length >> PAGE_SHIFT;
1508 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1509 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1510 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1513 if (WARN(num_entries > max_entries,
1514 "First entry = %d; Num entries = %d (max=%d)\n",
1515 first_entry, num_entries, max_entries))
1516 num_entries = max_entries;
1518 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1520 for (i = 0; i < num_entries; i++)
1521 iowrite32(scratch_pte, >t_base[i]);
1526 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1527 enum i915_cache_level cache_level,
1530 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1531 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1532 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1534 BUG_ON(!i915_is_ggtt(vma->vm));
1535 intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1536 vma->bound = GLOBAL_BIND;
1539 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1544 unsigned first_entry = start >> PAGE_SHIFT;
1545 unsigned num_entries = length >> PAGE_SHIFT;
1546 intel_gtt_clear_range(first_entry, num_entries);
1549 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1551 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1552 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1554 BUG_ON(!i915_is_ggtt(vma->vm));
1556 intel_gtt_clear_range(first, size);
1559 static void ggtt_bind_vma(struct i915_vma *vma,
1560 enum i915_cache_level cache_level,
1563 struct drm_device *dev = vma->vm->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 struct drm_i915_gem_object *obj = vma->obj;
1567 /* Currently applicable only to VLV */
1569 flags |= PTE_READ_ONLY;
1571 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1572 * or we have a global mapping already but the cacheability flags have
1573 * changed, set the global PTEs.
1575 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1576 * instead if none of the above hold true.
1578 * NB: A global mapping should only be needed for special regions like
1579 * "gtt mappable", SNB errata, or if specified via special execbuf
1580 * flags. At all other times, the GPU will use the aliasing PPGTT.
1582 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1583 if (!(vma->bound & GLOBAL_BIND) ||
1584 (cache_level != obj->cache_level)) {
1585 vma->vm->insert_entries(vma->vm, obj->pages,
1587 cache_level, flags);
1588 vma->bound |= GLOBAL_BIND;
1592 if (dev_priv->mm.aliasing_ppgtt &&
1593 (!(vma->bound & LOCAL_BIND) ||
1594 (cache_level != obj->cache_level))) {
1595 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1596 appgtt->base.insert_entries(&appgtt->base,
1599 cache_level, flags);
1600 vma->bound |= LOCAL_BIND;
1604 static void ggtt_unbind_vma(struct i915_vma *vma)
1606 struct drm_device *dev = vma->vm->dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 struct drm_i915_gem_object *obj = vma->obj;
1610 if (vma->bound & GLOBAL_BIND) {
1611 vma->vm->clear_range(vma->vm,
1615 vma->bound &= ~GLOBAL_BIND;
1618 if (vma->bound & LOCAL_BIND) {
1619 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1620 appgtt->base.clear_range(&appgtt->base,
1624 vma->bound &= ~LOCAL_BIND;
1628 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1630 struct drm_device *dev = obj->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1634 interruptible = do_idling(dev_priv);
1636 if (!obj->has_dma_mapping)
1637 dma_unmap_sg(&dev->pdev->dev,
1638 obj->pages->sgl, obj->pages->nents,
1639 PCI_DMA_BIDIRECTIONAL);
1641 undo_idling(dev_priv, interruptible);
1644 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1645 unsigned long color,
1646 unsigned long *start,
1649 if (node->color != color)
1652 if (!list_empty(&node->node_list)) {
1653 node = list_entry(node->node_list.next,
1656 if (node->allocated && node->color != color)
1661 int i915_gem_setup_global_gtt(struct drm_device *dev,
1662 unsigned long start,
1663 unsigned long mappable_end,
1666 /* Let GEM Manage all of the aperture.
1668 * However, leave one page at the end still bound to the scratch page.
1669 * There are a number of places where the hardware apparently prefetches
1670 * past the end of the object, and we've seen multiple hangs with the
1671 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1672 * aperture. One page should be enough to keep any prefetching inside
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1677 struct drm_mm_node *entry;
1678 struct drm_i915_gem_object *obj;
1679 unsigned long hole_start, hole_end;
1682 BUG_ON(mappable_end > end);
1684 /* Subtract the guard page ... */
1685 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1687 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1689 /* Mark any preallocated objects as occupied */
1690 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1691 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1693 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1694 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1696 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1697 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1699 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1702 vma->bound |= GLOBAL_BIND;
1705 dev_priv->gtt.base.start = start;
1706 dev_priv->gtt.base.total = end - start;
1708 /* Clear any non-preallocated blocks */
1709 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1710 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1711 hole_start, hole_end);
1712 ggtt_vm->clear_range(ggtt_vm, hole_start,
1713 hole_end - hole_start, true);
1716 /* And finally clear the reserved guard page */
1717 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1719 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1720 struct i915_hw_ppgtt *ppgtt;
1722 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1726 ret = __hw_ppgtt_init(dev, ppgtt);
1730 dev_priv->mm.aliasing_ppgtt = ppgtt;
1736 void i915_gem_init_global_gtt(struct drm_device *dev)
1738 struct drm_i915_private *dev_priv = dev->dev_private;
1739 unsigned long gtt_size, mappable_size;
1741 gtt_size = dev_priv->gtt.base.total;
1742 mappable_size = dev_priv->gtt.mappable_end;
1744 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1747 void i915_global_gtt_cleanup(struct drm_device *dev)
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 struct i915_address_space *vm = &dev_priv->gtt.base;
1752 if (dev_priv->mm.aliasing_ppgtt) {
1753 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1755 ppgtt->base.cleanup(&ppgtt->base);
1758 if (drm_mm_initialized(&vm->mm)) {
1759 drm_mm_takedown(&vm->mm);
1760 list_del(&vm->global_link);
1766 static int setup_scratch_page(struct drm_device *dev)
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1770 dma_addr_t dma_addr;
1772 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1775 set_pages_uc(page, 1);
1777 #ifdef CONFIG_INTEL_IOMMU
1778 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1779 PCI_DMA_BIDIRECTIONAL);
1780 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1783 dma_addr = page_to_phys(page);
1785 dev_priv->gtt.base.scratch.page = page;
1786 dev_priv->gtt.base.scratch.addr = dma_addr;
1791 static void teardown_scratch_page(struct drm_device *dev)
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 struct page *page = dev_priv->gtt.base.scratch.page;
1796 set_pages_wb(page, 1);
1797 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1798 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1802 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1804 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1805 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1806 return snb_gmch_ctl << 20;
1809 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1811 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1812 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1814 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1816 #ifdef CONFIG_X86_32
1817 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1818 if (bdw_gmch_ctl > 4)
1822 return bdw_gmch_ctl << 20;
1825 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1827 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1828 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1831 return 1 << (20 + gmch_ctrl);
1836 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1838 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1839 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1840 return snb_gmch_ctl << 25; /* 32 MB units */
1843 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1845 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1846 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1847 return bdw_gmch_ctl << 25; /* 32 MB units */
1850 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1852 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1853 gmch_ctrl &= SNB_GMCH_GMS_MASK;
1856 * 0x0 to 0x10: 32MB increments starting at 0MB
1857 * 0x11 to 0x16: 4MB increments starting at 8MB
1858 * 0x17 to 0x1d: 4MB increments start at 36MB
1860 if (gmch_ctrl < 0x11)
1861 return gmch_ctrl << 25;
1862 else if (gmch_ctrl < 0x17)
1863 return (gmch_ctrl - 0x11 + 2) << 22;
1865 return (gmch_ctrl - 0x17 + 9) << 22;
1868 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
1870 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1871 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
1873 if (gen9_gmch_ctl < 0xf0)
1874 return gen9_gmch_ctl << 25; /* 32 MB units */
1876 /* 4MB increments starting at 0xf0 for 4MB */
1877 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
1880 static int ggtt_probe_common(struct drm_device *dev,
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 phys_addr_t gtt_phys_addr;
1887 /* For Modern GENs the PTEs and register space are split in the BAR */
1888 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1889 (pci_resource_len(dev->pdev, 0) / 2);
1891 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1892 if (!dev_priv->gtt.gsm) {
1893 DRM_ERROR("Failed to map the gtt page table\n");
1897 ret = setup_scratch_page(dev);
1899 DRM_ERROR("Scratch setup failed\n");
1900 /* iounmap will also get called at remove, but meh */
1901 iounmap(dev_priv->gtt.gsm);
1907 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1908 * bits. When using advanced contexts each context stores its own PAT, but
1909 * writing this data shouldn't be harmful even in those cases. */
1910 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1914 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
1915 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1916 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1917 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
1918 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1919 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1920 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1921 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1923 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1924 * write would work. */
1925 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1926 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1929 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1934 * Map WB on BDW to snooped on CHV.
1936 * Only the snoop bit has meaning for CHV, the rest is
1939 * Note that the harware enforces snooping for all page
1940 * table accesses. The snoop bit is actually ignored for
1943 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1947 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1948 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1949 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1950 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1952 I915_WRITE(GEN8_PRIVATE_PAT, pat);
1953 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1956 static int gen8_gmch_probe(struct drm_device *dev,
1959 phys_addr_t *mappable_base,
1960 unsigned long *mappable_end)
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 unsigned int gtt_size;
1967 /* TODO: We're not aware of mappable constraints on gen8 yet */
1968 *mappable_base = pci_resource_start(dev->pdev, 2);
1969 *mappable_end = pci_resource_len(dev->pdev, 2);
1971 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1972 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1974 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1976 if (INTEL_INFO(dev)->gen >= 9) {
1977 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
1978 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1979 } else if (IS_CHERRYVIEW(dev)) {
1980 *stolen = chv_get_stolen_size(snb_gmch_ctl);
1981 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
1983 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1984 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1987 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1989 if (IS_CHERRYVIEW(dev))
1990 chv_setup_private_ppat(dev_priv);
1992 bdw_setup_private_ppat(dev_priv);
1994 ret = ggtt_probe_common(dev, gtt_size);
1996 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1997 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2002 static int gen6_gmch_probe(struct drm_device *dev,
2005 phys_addr_t *mappable_base,
2006 unsigned long *mappable_end)
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 unsigned int gtt_size;
2013 *mappable_base = pci_resource_start(dev->pdev, 2);
2014 *mappable_end = pci_resource_len(dev->pdev, 2);
2016 /* 64/512MB is the current min/max we actually know of, but this is just
2017 * a coarse sanity check.
2019 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2020 DRM_ERROR("Unknown GMADR size (%lx)\n",
2021 dev_priv->gtt.mappable_end);
2025 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2026 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2027 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2029 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2031 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2032 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2034 ret = ggtt_probe_common(dev, gtt_size);
2036 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2037 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2042 static void gen6_gmch_remove(struct i915_address_space *vm)
2045 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2048 teardown_scratch_page(vm->dev);
2051 static int i915_gmch_probe(struct drm_device *dev,
2054 phys_addr_t *mappable_base,
2055 unsigned long *mappable_end)
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2060 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2062 DRM_ERROR("failed to set up gmch\n");
2066 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2068 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2069 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2071 if (unlikely(dev_priv->gtt.do_idle_maps))
2072 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2077 static void i915_gmch_remove(struct i915_address_space *vm)
2079 intel_gmch_remove();
2082 int i915_gem_gtt_init(struct drm_device *dev)
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct i915_gtt *gtt = &dev_priv->gtt;
2088 if (INTEL_INFO(dev)->gen <= 5) {
2089 gtt->gtt_probe = i915_gmch_probe;
2090 gtt->base.cleanup = i915_gmch_remove;
2091 } else if (INTEL_INFO(dev)->gen < 8) {
2092 gtt->gtt_probe = gen6_gmch_probe;
2093 gtt->base.cleanup = gen6_gmch_remove;
2094 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2095 gtt->base.pte_encode = iris_pte_encode;
2096 else if (IS_HASWELL(dev))
2097 gtt->base.pte_encode = hsw_pte_encode;
2098 else if (IS_VALLEYVIEW(dev))
2099 gtt->base.pte_encode = byt_pte_encode;
2100 else if (INTEL_INFO(dev)->gen >= 7)
2101 gtt->base.pte_encode = ivb_pte_encode;
2103 gtt->base.pte_encode = snb_pte_encode;
2105 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2106 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2109 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
2110 >t->mappable_base, >t->mappable_end);
2114 gtt->base.dev = dev;
2116 /* GMADR is the PCI mmio aperture into the global GTT. */
2117 DRM_INFO("Memory usable by graphics device = %zdM\n",
2118 gtt->base.total >> 20);
2119 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2120 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2121 #ifdef CONFIG_INTEL_IOMMU
2122 if (intel_iommu_gfx_mapped)
2123 DRM_INFO("VT-d active for gfx access\n");
2126 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2127 * user's requested state against the hardware/driver capabilities. We
2128 * do this now so that we can print out any log messages once rather
2129 * than every time we check intel_enable_ppgtt().
2131 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2132 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2137 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2138 struct i915_address_space *vm)
2140 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2142 return ERR_PTR(-ENOMEM);
2144 INIT_LIST_HEAD(&vma->vma_link);
2145 INIT_LIST_HEAD(&vma->mm_list);
2146 INIT_LIST_HEAD(&vma->exec_list);
2150 switch (INTEL_INFO(vm->dev)->gen) {
2155 if (i915_is_ggtt(vm)) {
2156 vma->unbind_vma = ggtt_unbind_vma;
2157 vma->bind_vma = ggtt_bind_vma;
2159 vma->unbind_vma = ppgtt_unbind_vma;
2160 vma->bind_vma = ppgtt_bind_vma;
2167 BUG_ON(!i915_is_ggtt(vm));
2168 vma->unbind_vma = i915_ggtt_unbind_vma;
2169 vma->bind_vma = i915_ggtt_bind_vma;
2175 /* Keep GGTT vmas first to make debug easier */
2176 if (i915_is_ggtt(vm))
2177 list_add(&vma->vma_link, &obj->vma_list);
2179 list_add_tail(&vma->vma_link, &obj->vma_list);
2180 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2187 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2188 struct i915_address_space *vm)
2190 struct i915_vma *vma;
2192 vma = i915_gem_obj_to_vma(obj, vm);
2194 vma = __i915_gem_vma_create(obj, vm);