2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
98 const struct i915_ggtt_view i915_ggtt_view_normal;
99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
105 bool has_aliasing_ppgtt;
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
122 if (enable_ppgtt == 1)
125 if (enable_ppgtt == 2 && has_full_ppgtt)
128 #ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
136 /* Early VLV doesn't have this */
137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
146 return has_aliasing_ppgtt ? 1 : 0;
149 static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
155 /* Currently applicable only to VLV */
157 pte_flags |= PTE_READ_ONLY;
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
165 static void ppgtt_unbind_vma(struct i915_vma *vma)
167 vma->vm->clear_range(vma->vm,
173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
181 case I915_CACHE_NONE:
182 pte |= PPAT_UNCACHED_INDEX;
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
188 pte |= PPAT_CACHED_INDEX;
195 static gen8_pde_t gen8_pde_encode(struct drm_device *dev,
197 enum i915_cache_level level)
199 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
201 if (level != I915_CACHE_NONE)
202 pde |= PPAT_CACHED_PDE_INDEX;
204 pde |= PPAT_UNCACHED_INDEX;
208 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
209 enum i915_cache_level level,
210 bool valid, u32 unused)
212 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
213 pte |= GEN6_PTE_ADDR_ENCODE(addr);
216 case I915_CACHE_L3_LLC:
218 pte |= GEN6_PTE_CACHE_LLC;
220 case I915_CACHE_NONE:
221 pte |= GEN6_PTE_UNCACHED;
230 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
231 enum i915_cache_level level,
232 bool valid, u32 unused)
234 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
235 pte |= GEN6_PTE_ADDR_ENCODE(addr);
238 case I915_CACHE_L3_LLC:
239 pte |= GEN7_PTE_CACHE_L3_LLC;
242 pte |= GEN6_PTE_CACHE_LLC;
244 case I915_CACHE_NONE:
245 pte |= GEN6_PTE_UNCACHED;
254 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
255 enum i915_cache_level level,
256 bool valid, u32 flags)
258 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
259 pte |= GEN6_PTE_ADDR_ENCODE(addr);
261 if (!(flags & PTE_READ_ONLY))
262 pte |= BYT_PTE_WRITEABLE;
264 if (level != I915_CACHE_NONE)
265 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
270 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
271 enum i915_cache_level level,
272 bool valid, u32 unused)
274 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
275 pte |= HSW_PTE_ADDR_ENCODE(addr);
277 if (level != I915_CACHE_NONE)
278 pte |= HSW_WB_LLC_AGE3;
283 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
284 enum i915_cache_level level,
285 bool valid, u32 unused)
287 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
288 pte |= HSW_PTE_ADDR_ENCODE(addr);
291 case I915_CACHE_NONE:
294 pte |= HSW_WT_ELLC_LLC_AGE3;
297 pte |= HSW_WB_ELLC_LLC_AGE3;
304 #define i915_dma_unmap_single(px, dev) \
305 __i915_dma_unmap_single((px)->daddr, dev)
307 static void __i915_dma_unmap_single(dma_addr_t daddr,
308 struct drm_device *dev)
310 struct device *device = &dev->pdev->dev;
312 dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
316 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
317 * @px: Page table/dir/etc to get a DMA map for
320 * Page table allocations are unified across all gens. They always require a
321 * single 4k allocation, as well as a DMA mapping. If we keep the structs
322 * symmetric here, the simple macro covers us for every page table type.
324 * Return: 0 if success.
326 #define i915_dma_map_single(px, dev) \
327 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
329 static int i915_dma_map_page_single(struct page *page,
330 struct drm_device *dev,
333 struct device *device = &dev->pdev->dev;
335 *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
336 if (dma_mapping_error(device, *daddr))
342 static void unmap_and_free_pt(struct i915_page_table *pt,
343 struct drm_device *dev)
345 if (WARN_ON(!pt->page))
348 i915_dma_unmap_single(pt, dev);
349 __free_page(pt->page);
350 kfree(pt->used_ptes);
354 static void gen8_initialize_pt(struct i915_address_space *vm,
355 struct i915_page_table *pt)
357 gen8_pte_t *pt_vaddr, scratch_pte;
360 pt_vaddr = kmap_atomic(pt->page);
361 scratch_pte = gen8_pte_encode(vm->scratch.addr,
362 I915_CACHE_LLC, true);
364 for (i = 0; i < GEN8_PTES; i++)
365 pt_vaddr[i] = scratch_pte;
367 if (!HAS_LLC(vm->dev))
368 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
369 kunmap_atomic(pt_vaddr);
372 static struct i915_page_table *alloc_pt_single(struct drm_device *dev)
374 struct i915_page_table *pt;
375 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
376 GEN8_PTES : GEN6_PTES;
379 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
381 return ERR_PTR(-ENOMEM);
383 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
389 pt->page = alloc_page(GFP_KERNEL);
393 ret = i915_dma_map_single(pt, dev);
400 __free_page(pt->page);
402 kfree(pt->used_ptes);
409 static void unmap_and_free_pd(struct i915_page_directory *pd,
410 struct drm_device *dev)
413 i915_dma_unmap_single(pd, dev);
414 __free_page(pd->page);
415 kfree(pd->used_pdes);
420 static struct i915_page_directory *alloc_pd_single(struct drm_device *dev)
422 struct i915_page_directory *pd;
425 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
427 return ERR_PTR(-ENOMEM);
429 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
430 sizeof(*pd->used_pdes), GFP_KERNEL);
434 pd->page = alloc_page(GFP_KERNEL);
438 ret = i915_dma_map_single(pd, dev);
445 __free_page(pd->page);
447 kfree(pd->used_pdes);
454 /* Broadwell Page Directory Pointer Descriptors */
455 static int gen8_write_pdp(struct intel_engine_cs *ring,
463 ret = intel_ring_begin(ring, 6);
467 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
468 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
469 intel_ring_emit(ring, upper_32_bits(addr));
470 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
471 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
472 intel_ring_emit(ring, lower_32_bits(addr));
473 intel_ring_advance(ring);
478 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
479 struct intel_engine_cs *ring)
483 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
484 struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
485 dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr;
486 /* The page directory might be NULL, but we need to clear out
487 * whatever the previous context might have used. */
488 ret = gen8_write_pdp(ring, i, pd_daddr);
496 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
501 struct i915_hw_ppgtt *ppgtt =
502 container_of(vm, struct i915_hw_ppgtt, base);
503 gen8_pte_t *pt_vaddr, scratch_pte;
504 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
505 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
506 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
507 unsigned num_entries = length >> PAGE_SHIFT;
508 unsigned last_pte, i;
510 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
511 I915_CACHE_LLC, use_scratch);
513 while (num_entries) {
514 struct i915_page_directory *pd;
515 struct i915_page_table *pt;
516 struct page *page_table;
518 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
521 pd = ppgtt->pdp.page_directory[pdpe];
523 if (WARN_ON(!pd->page_table[pde]))
526 pt = pd->page_table[pde];
528 if (WARN_ON(!pt->page))
531 page_table = pt->page;
533 last_pte = pte + num_entries;
534 if (last_pte > GEN8_PTES)
535 last_pte = GEN8_PTES;
537 pt_vaddr = kmap_atomic(page_table);
539 for (i = pte; i < last_pte; i++) {
540 pt_vaddr[i] = scratch_pte;
544 if (!HAS_LLC(ppgtt->base.dev))
545 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
546 kunmap_atomic(pt_vaddr);
549 if (++pde == I915_PDES) {
556 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
557 struct sg_table *pages,
559 enum i915_cache_level cache_level, u32 unused)
561 struct i915_hw_ppgtt *ppgtt =
562 container_of(vm, struct i915_hw_ppgtt, base);
563 gen8_pte_t *pt_vaddr;
564 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
565 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
566 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
567 struct sg_page_iter sg_iter;
571 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
572 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
575 if (pt_vaddr == NULL) {
576 struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
577 struct i915_page_table *pt = pd->page_table[pde];
578 struct page *page_table = pt->page;
580 pt_vaddr = kmap_atomic(page_table);
584 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
586 if (++pte == GEN8_PTES) {
587 if (!HAS_LLC(ppgtt->base.dev))
588 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
589 kunmap_atomic(pt_vaddr);
591 if (++pde == I915_PDES) {
599 if (!HAS_LLC(ppgtt->base.dev))
600 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
601 kunmap_atomic(pt_vaddr);
605 static void __gen8_do_map_pt(gen8_pde_t * const pde,
606 struct i915_page_table *pt,
607 struct drm_device *dev)
610 gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC);
614 static void gen8_initialize_pd(struct i915_address_space *vm,
615 struct i915_page_directory *pd)
617 struct i915_hw_ppgtt *ppgtt =
618 container_of(vm, struct i915_hw_ppgtt, base);
619 gen8_pde_t *page_directory;
620 struct i915_page_table *pt;
623 page_directory = kmap_atomic(pd->page);
624 pt = ppgtt->scratch_pt;
625 for (i = 0; i < I915_PDES; i++)
626 /* Map the PDE to the page table */
627 __gen8_do_map_pt(page_directory + i, pt, vm->dev);
629 if (!HAS_LLC(vm->dev))
630 drm_clflush_virt_range(page_directory, PAGE_SIZE);
631 kunmap_atomic(page_directory);
634 static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
641 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
642 if (WARN_ON(!pd->page_table[i]))
645 unmap_and_free_pt(pd->page_table[i], dev);
646 pd->page_table[i] = NULL;
650 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
652 struct i915_hw_ppgtt *ppgtt =
653 container_of(vm, struct i915_hw_ppgtt, base);
656 for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
657 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
660 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
661 unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
664 unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev);
665 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
669 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
670 * @ppgtt: Master ppgtt structure.
671 * @pd: Page directory for this address range.
672 * @start: Starting virtual address to begin allocations.
673 * @length Size of the allocations.
674 * @new_pts: Bitmap set by function with new allocations. Likely used by the
675 * caller to free on error.
677 * Allocate the required number of page tables. Extremely similar to
678 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
679 * the page directory boundary (instead of the page directory pointer). That
680 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
681 * possible, and likely that the caller will need to use multiple calls of this
682 * function to achieve the appropriate allocation.
684 * Return: 0 if success; negative error code otherwise.
686 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
687 struct i915_page_directory *pd,
690 unsigned long *new_pts)
692 struct drm_device *dev = ppgtt->base.dev;
693 struct i915_page_table *pt;
697 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
698 /* Don't reallocate page tables */
700 /* Scratch is never allocated this way */
701 WARN_ON(pt == ppgtt->scratch_pt);
705 pt = alloc_pt_single(dev);
709 gen8_initialize_pt(&ppgtt->base, pt);
710 pd->page_table[pde] = pt;
711 set_bit(pde, new_pts);
717 for_each_set_bit(pde, new_pts, I915_PDES)
718 unmap_and_free_pt(pd->page_table[pde], dev);
724 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
725 * @ppgtt: Master ppgtt structure.
726 * @pdp: Page directory pointer for this address range.
727 * @start: Starting virtual address to begin allocations.
728 * @length Size of the allocations.
729 * @new_pds Bitmap set by function with new allocations. Likely used by the
730 * caller to free on error.
732 * Allocate the required number of page directories starting at the pde index of
733 * @start, and ending at the pde index @start + @length. This function will skip
734 * over already allocated page directories within the range, and only allocate
735 * new ones, setting the appropriate pointer within the pdp as well as the
736 * correct position in the bitmap @new_pds.
738 * The function will only allocate the pages within the range for a give page
739 * directory pointer. In other words, if @start + @length straddles a virtually
740 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
741 * required by the caller, This is not currently possible, and the BUG in the
742 * code will prevent it.
744 * Return: 0 if success; negative error code otherwise.
746 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
747 struct i915_page_directory_pointer *pdp,
750 unsigned long *new_pds)
752 struct drm_device *dev = ppgtt->base.dev;
753 struct i915_page_directory *pd;
757 WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
759 /* FIXME: upper bound must not overflow 32 bits */
760 WARN_ON((start + length) > (1ULL << 32));
762 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
766 pd = alloc_pd_single(dev);
770 gen8_initialize_pd(&ppgtt->base, pd);
771 pdp->page_directory[pdpe] = pd;
772 set_bit(pdpe, new_pds);
778 for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
779 unmap_and_free_pd(pdp->page_directory[pdpe], dev);
785 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
789 for (i = 0; i < GEN8_LEGACY_PDPES; i++)
795 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
796 * of these are based on the number of PDPEs in the system.
799 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
800 unsigned long ***new_pts)
806 pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
810 pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
816 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
817 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
818 sizeof(unsigned long), GFP_KERNEL);
829 free_gen8_temp_bitmaps(pds, pts);
833 static int gen8_alloc_va_range(struct i915_address_space *vm,
837 struct i915_hw_ppgtt *ppgtt =
838 container_of(vm, struct i915_hw_ppgtt, base);
839 unsigned long *new_page_dirs, **new_page_tables;
840 struct i915_page_directory *pd;
841 const uint64_t orig_start = start;
842 const uint64_t orig_length = length;
847 /* Wrap is never okay since we can only represent 48b, and we don't
848 * actually use the other side of the canonical address space.
850 if (WARN_ON(start + length < start))
853 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
857 /* Do the allocations first so we can easily bail out */
858 ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
861 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
865 /* For every page directory referenced, allocate page tables */
866 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
867 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
868 new_page_tables[pdpe]);
874 length = orig_length;
876 /* Allocations have completed successfully, so set the bitmaps, and do
878 gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
879 gen8_pde_t *const page_directory = kmap_atomic(pd->page);
880 struct i915_page_table *pt;
881 uint64_t pd_len = gen8_clamp_pd(start, length);
882 uint64_t pd_start = start;
885 /* Every pd should be allocated, we just did that above. */
888 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
889 /* Same reasoning as pd */
892 WARN_ON(!gen8_pte_count(pd_start, pd_len));
894 /* Set our used ptes within the page table */
895 bitmap_set(pt->used_ptes,
896 gen8_pte_index(pd_start),
897 gen8_pte_count(pd_start, pd_len));
899 /* Our pde is now pointing to the pagetable, pt */
900 set_bit(pde, pd->used_pdes);
902 /* Map the PDE to the page table */
903 __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
905 /* NB: We haven't yet mapped ptes to pages. At this
906 * point we're still relying on insert_entries() */
909 if (!HAS_LLC(vm->dev))
910 drm_clflush_virt_range(page_directory, PAGE_SIZE);
912 kunmap_atomic(page_directory);
914 set_bit(pdpe, ppgtt->pdp.used_pdpes);
917 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
922 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
923 unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev);
926 for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
927 unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev);
929 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
934 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
935 * with a net effect resembling a 2-level page table in normal x86 terms. Each
936 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
940 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
942 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
943 if (IS_ERR(ppgtt->scratch_pt))
944 return PTR_ERR(ppgtt->scratch_pt);
946 ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev);
947 if (IS_ERR(ppgtt->scratch_pd))
948 return PTR_ERR(ppgtt->scratch_pd);
950 gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
951 gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
953 ppgtt->base.start = 0;
954 ppgtt->base.total = 1ULL << 32;
955 if (IS_ENABLED(CONFIG_X86_32))
956 /* While we have a proliferation of size_t variables
957 * we cannot represent the full ppgtt size on 32bit,
958 * so limit it to the same size as the GGTT (currently
961 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
962 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
963 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
964 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
965 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
966 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
967 ppgtt->base.bind_vma = ppgtt_bind_vma;
969 ppgtt->switch_mm = gen8_mm_switch;
974 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
976 struct i915_address_space *vm = &ppgtt->base;
977 struct i915_page_table *unused;
978 gen6_pte_t scratch_pte;
980 uint32_t pte, pde, temp;
981 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
983 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
985 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
987 gen6_pte_t *pt_vaddr;
988 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
989 pd_entry = readl(ppgtt->pd_addr + pde);
990 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
992 if (pd_entry != expected)
993 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
997 seq_printf(m, "\tPDE: %x\n", pd_entry);
999 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
1000 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1002 (pde * PAGE_SIZE * GEN6_PTES) +
1006 for (i = 0; i < 4; i++)
1007 if (pt_vaddr[pte + i] != scratch_pte)
1012 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1013 for (i = 0; i < 4; i++) {
1014 if (pt_vaddr[pte + i] != scratch_pte)
1015 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1017 seq_puts(m, " SCRATCH ");
1021 kunmap_atomic(pt_vaddr);
1025 /* Write pde (index) from the page directory @pd to the page table @pt */
1026 static void gen6_write_pde(struct i915_page_directory *pd,
1027 const int pde, struct i915_page_table *pt)
1029 /* Caller needs to make sure the write completes if necessary */
1030 struct i915_hw_ppgtt *ppgtt =
1031 container_of(pd, struct i915_hw_ppgtt, pd);
1034 pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr);
1035 pd_entry |= GEN6_PDE_VALID;
1037 writel(pd_entry, ppgtt->pd_addr + pde);
1040 /* Write all the page tables found in the ppgtt structure to incrementing page
1042 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1043 struct i915_page_directory *pd,
1044 uint32_t start, uint32_t length)
1046 struct i915_page_table *pt;
1049 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1050 gen6_write_pde(pd, pde, pt);
1052 /* Make sure write is complete before other code can use this page
1053 * table. Also require for WC mapped PTEs */
1054 readl(dev_priv->gtt.gsm);
1057 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1059 BUG_ON(ppgtt->pd.pd_offset & 0x3f);
1061 return (ppgtt->pd.pd_offset / 64) << 16;
1064 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1065 struct intel_engine_cs *ring)
1069 /* NB: TLBs must be flushed and invalidated before a switch */
1070 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1074 ret = intel_ring_begin(ring, 6);
1078 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1079 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1080 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1081 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1082 intel_ring_emit(ring, get_pd_offset(ppgtt));
1083 intel_ring_emit(ring, MI_NOOP);
1084 intel_ring_advance(ring);
1089 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1090 struct intel_engine_cs *ring)
1092 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1094 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1095 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1099 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1100 struct intel_engine_cs *ring)
1104 /* NB: TLBs must be flushed and invalidated before a switch */
1105 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1109 ret = intel_ring_begin(ring, 6);
1113 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1114 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1115 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1116 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1117 intel_ring_emit(ring, get_pd_offset(ppgtt));
1118 intel_ring_emit(ring, MI_NOOP);
1119 intel_ring_advance(ring);
1121 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1122 if (ring->id != RCS) {
1123 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1131 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1132 struct intel_engine_cs *ring)
1134 struct drm_device *dev = ppgtt->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1138 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1139 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1141 POSTING_READ(RING_PP_DIR_DCLV(ring));
1146 static void gen8_ppgtt_enable(struct drm_device *dev)
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 struct intel_engine_cs *ring;
1152 for_each_ring(ring, dev_priv, j) {
1153 I915_WRITE(RING_MODE_GEN7(ring),
1154 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1158 static void gen7_ppgtt_enable(struct drm_device *dev)
1160 struct drm_i915_private *dev_priv = dev->dev_private;
1161 struct intel_engine_cs *ring;
1162 uint32_t ecochk, ecobits;
1165 ecobits = I915_READ(GAC_ECO_BITS);
1166 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1168 ecochk = I915_READ(GAM_ECOCHK);
1169 if (IS_HASWELL(dev)) {
1170 ecochk |= ECOCHK_PPGTT_WB_HSW;
1172 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1173 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1175 I915_WRITE(GAM_ECOCHK, ecochk);
1177 for_each_ring(ring, dev_priv, i) {
1178 /* GFX_MODE is per-ring on gen7+ */
1179 I915_WRITE(RING_MODE_GEN7(ring),
1180 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1184 static void gen6_ppgtt_enable(struct drm_device *dev)
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 uint32_t ecochk, gab_ctl, ecobits;
1189 ecobits = I915_READ(GAC_ECO_BITS);
1190 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1191 ECOBITS_PPGTT_CACHE64B);
1193 gab_ctl = I915_READ(GAB_CTL);
1194 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1196 ecochk = I915_READ(GAM_ECOCHK);
1197 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1199 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1202 /* PPGTT support for Sandybdrige/Gen6 and later */
1203 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1208 struct i915_hw_ppgtt *ppgtt =
1209 container_of(vm, struct i915_hw_ppgtt, base);
1210 gen6_pte_t *pt_vaddr, scratch_pte;
1211 unsigned first_entry = start >> PAGE_SHIFT;
1212 unsigned num_entries = length >> PAGE_SHIFT;
1213 unsigned act_pt = first_entry / GEN6_PTES;
1214 unsigned first_pte = first_entry % GEN6_PTES;
1215 unsigned last_pte, i;
1217 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1219 while (num_entries) {
1220 last_pte = first_pte + num_entries;
1221 if (last_pte > GEN6_PTES)
1222 last_pte = GEN6_PTES;
1224 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1226 for (i = first_pte; i < last_pte; i++)
1227 pt_vaddr[i] = scratch_pte;
1229 kunmap_atomic(pt_vaddr);
1231 num_entries -= last_pte - first_pte;
1237 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1238 struct sg_table *pages,
1240 enum i915_cache_level cache_level, u32 flags)
1242 struct i915_hw_ppgtt *ppgtt =
1243 container_of(vm, struct i915_hw_ppgtt, base);
1244 gen6_pte_t *pt_vaddr;
1245 unsigned first_entry = start >> PAGE_SHIFT;
1246 unsigned act_pt = first_entry / GEN6_PTES;
1247 unsigned act_pte = first_entry % GEN6_PTES;
1248 struct sg_page_iter sg_iter;
1251 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1252 if (pt_vaddr == NULL)
1253 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1256 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1257 cache_level, true, flags);
1259 if (++act_pte == GEN6_PTES) {
1260 kunmap_atomic(pt_vaddr);
1267 kunmap_atomic(pt_vaddr);
1270 /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1271 * are switching between contexts with the same LRCA, we also must do a force
1274 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1276 /* If current vm != vm, */
1277 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1280 static void gen6_initialize_pt(struct i915_address_space *vm,
1281 struct i915_page_table *pt)
1283 gen6_pte_t *pt_vaddr, scratch_pte;
1286 WARN_ON(vm->scratch.addr == 0);
1288 scratch_pte = vm->pte_encode(vm->scratch.addr,
1289 I915_CACHE_LLC, true, 0);
1291 pt_vaddr = kmap_atomic(pt->page);
1293 for (i = 0; i < GEN6_PTES; i++)
1294 pt_vaddr[i] = scratch_pte;
1296 kunmap_atomic(pt_vaddr);
1299 static int gen6_alloc_va_range(struct i915_address_space *vm,
1300 uint64_t start, uint64_t length)
1302 DECLARE_BITMAP(new_page_tables, I915_PDES);
1303 struct drm_device *dev = vm->dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct i915_hw_ppgtt *ppgtt =
1306 container_of(vm, struct i915_hw_ppgtt, base);
1307 struct i915_page_table *pt;
1308 const uint32_t start_save = start, length_save = length;
1312 WARN_ON(upper_32_bits(start));
1314 bitmap_zero(new_page_tables, I915_PDES);
1316 /* The allocation is done in two stages so that we can bail out with
1317 * minimal amount of pain. The first stage finds new page tables that
1318 * need allocation. The second stage marks use ptes within the page
1321 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1322 if (pt != ppgtt->scratch_pt) {
1323 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1327 /* We've already allocated a page table */
1328 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1330 pt = alloc_pt_single(dev);
1336 gen6_initialize_pt(vm, pt);
1338 ppgtt->pd.page_table[pde] = pt;
1339 set_bit(pde, new_page_tables);
1340 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1344 length = length_save;
1346 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1347 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1349 bitmap_zero(tmp_bitmap, GEN6_PTES);
1350 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1351 gen6_pte_count(start, length));
1353 if (test_and_clear_bit(pde, new_page_tables))
1354 gen6_write_pde(&ppgtt->pd, pde, pt);
1356 trace_i915_page_table_entry_map(vm, pde, pt,
1357 gen6_pte_index(start),
1358 gen6_pte_count(start, length),
1360 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1364 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1366 /* Make sure write is complete before other code can use this page
1367 * table. Also require for WC mapped PTEs */
1368 readl(dev_priv->gtt.gsm);
1370 mark_tlbs_dirty(ppgtt);
1374 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1375 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1377 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1378 unmap_and_free_pt(pt, vm->dev);
1381 mark_tlbs_dirty(ppgtt);
1385 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1387 struct i915_hw_ppgtt *ppgtt =
1388 container_of(vm, struct i915_hw_ppgtt, base);
1389 struct i915_page_table *pt;
1393 drm_mm_remove_node(&ppgtt->node);
1395 gen6_for_all_pdes(pt, ppgtt, pde) {
1396 if (pt != ppgtt->scratch_pt)
1397 unmap_and_free_pt(pt, ppgtt->base.dev);
1400 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1401 unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev);
1404 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1406 struct drm_device *dev = ppgtt->base.dev;
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 bool retried = false;
1411 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1412 * allocator works in address space sizes, so it's multiplied by page
1413 * size. We allocate at the top of the GTT to avoid fragmentation.
1415 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1416 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
1417 if (IS_ERR(ppgtt->scratch_pt))
1418 return PTR_ERR(ppgtt->scratch_pt);
1420 gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1423 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1424 &ppgtt->node, GEN6_PD_SIZE,
1426 0, dev_priv->gtt.base.total,
1428 if (ret == -ENOSPC && !retried) {
1429 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1430 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1432 0, dev_priv->gtt.base.total,
1445 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1446 DRM_DEBUG("Forced to use aperture for PDEs\n");
1451 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
1455 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1457 return gen6_ppgtt_allocate_page_directories(ppgtt);
1460 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1461 uint64_t start, uint64_t length)
1463 struct i915_page_table *unused;
1466 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1467 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1470 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1472 struct drm_device *dev = ppgtt->base.dev;
1473 struct drm_i915_private *dev_priv = dev->dev_private;
1476 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1478 ppgtt->switch_mm = gen6_mm_switch;
1479 } else if (IS_HASWELL(dev)) {
1480 ppgtt->switch_mm = hsw_mm_switch;
1481 } else if (IS_GEN7(dev)) {
1482 ppgtt->switch_mm = gen7_mm_switch;
1486 if (intel_vgpu_active(dev))
1487 ppgtt->switch_mm = vgpu_mm_switch;
1489 ret = gen6_ppgtt_alloc(ppgtt);
1493 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1494 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1495 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1496 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1497 ppgtt->base.bind_vma = ppgtt_bind_vma;
1498 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1499 ppgtt->base.start = 0;
1500 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1501 ppgtt->debug_dump = gen6_dump_ppgtt;
1503 ppgtt->pd.pd_offset =
1504 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1506 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1507 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
1509 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1511 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1513 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1514 ppgtt->node.size >> 20,
1515 ppgtt->node.start / PAGE_SIZE);
1517 DRM_DEBUG("Adding PPGTT at offset %x\n",
1518 ppgtt->pd.pd_offset << 10);
1523 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1527 ppgtt->base.dev = dev;
1528 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1530 if (INTEL_INFO(dev)->gen < 8)
1531 return gen6_ppgtt_init(ppgtt);
1533 return gen8_ppgtt_init(ppgtt);
1535 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1540 ret = __hw_ppgtt_init(dev, ppgtt);
1542 kref_init(&ppgtt->ref);
1543 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1545 i915_init_vm(dev_priv, &ppgtt->base);
1551 int i915_ppgtt_init_hw(struct drm_device *dev)
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 struct intel_engine_cs *ring;
1555 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1558 /* In the case of execlists, PPGTT is enabled by the context descriptor
1559 * and the PDPs are contained within the context itself. We don't
1560 * need to do anything here. */
1561 if (i915.enable_execlists)
1564 if (!USES_PPGTT(dev))
1568 gen6_ppgtt_enable(dev);
1569 else if (IS_GEN7(dev))
1570 gen7_ppgtt_enable(dev);
1571 else if (INTEL_INFO(dev)->gen >= 8)
1572 gen8_ppgtt_enable(dev);
1574 MISSING_CASE(INTEL_INFO(dev)->gen);
1577 for_each_ring(ring, dev_priv, i) {
1578 ret = ppgtt->switch_mm(ppgtt, ring);
1586 struct i915_hw_ppgtt *
1587 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1589 struct i915_hw_ppgtt *ppgtt;
1592 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1594 return ERR_PTR(-ENOMEM);
1596 ret = i915_ppgtt_init(dev, ppgtt);
1599 return ERR_PTR(ret);
1602 ppgtt->file_priv = fpriv;
1604 trace_i915_ppgtt_create(&ppgtt->base);
1609 void i915_ppgtt_release(struct kref *kref)
1611 struct i915_hw_ppgtt *ppgtt =
1612 container_of(kref, struct i915_hw_ppgtt, ref);
1614 trace_i915_ppgtt_release(&ppgtt->base);
1616 /* vmas should already be unbound */
1617 WARN_ON(!list_empty(&ppgtt->base.active_list));
1618 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1620 list_del(&ppgtt->base.global_link);
1621 drm_mm_takedown(&ppgtt->base.mm);
1623 ppgtt->base.cleanup(&ppgtt->base);
1627 extern int intel_iommu_gfx_mapped;
1628 /* Certain Gen5 chipsets require require idling the GPU before
1629 * unmapping anything from the GTT when VT-d is enabled.
1631 static bool needs_idle_maps(struct drm_device *dev)
1633 #ifdef CONFIG_INTEL_IOMMU
1634 /* Query intel_iommu to see if we need the workaround. Presumably that
1637 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1643 static bool do_idling(struct drm_i915_private *dev_priv)
1645 bool ret = dev_priv->mm.interruptible;
1647 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1648 dev_priv->mm.interruptible = false;
1649 if (i915_gpu_idle(dev_priv->dev)) {
1650 DRM_ERROR("Couldn't idle GPU\n");
1651 /* Wait a bit, in hopes it avoids the hang */
1659 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1661 if (unlikely(dev_priv->gtt.do_idle_maps))
1662 dev_priv->mm.interruptible = interruptible;
1665 void i915_check_and_clear_faults(struct drm_device *dev)
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1668 struct intel_engine_cs *ring;
1671 if (INTEL_INFO(dev)->gen < 6)
1674 for_each_ring(ring, dev_priv, i) {
1676 fault_reg = I915_READ(RING_FAULT_REG(ring));
1677 if (fault_reg & RING_FAULT_VALID) {
1678 DRM_DEBUG_DRIVER("Unexpected fault\n"
1680 "\tAddress space: %s\n"
1683 fault_reg & PAGE_MASK,
1684 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1685 RING_FAULT_SRCID(fault_reg),
1686 RING_FAULT_FAULT_TYPE(fault_reg));
1687 I915_WRITE(RING_FAULT_REG(ring),
1688 fault_reg & ~RING_FAULT_VALID);
1691 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1694 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1696 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1697 intel_gtt_chipset_flush();
1699 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1700 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1704 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1708 /* Don't bother messing with faults pre GEN6 as we have little
1709 * documentation supporting that it's a good idea.
1711 if (INTEL_INFO(dev)->gen < 6)
1714 i915_check_and_clear_faults(dev);
1716 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1717 dev_priv->gtt.base.start,
1718 dev_priv->gtt.base.total,
1721 i915_ggtt_flush(dev_priv);
1724 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1726 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1727 obj->pages->sgl, obj->pages->nents,
1728 PCI_DMA_BIDIRECTIONAL))
1734 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1739 iowrite32((u32)pte, addr);
1740 iowrite32(pte >> 32, addr + 4);
1744 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1745 struct sg_table *st,
1747 enum i915_cache_level level, u32 unused)
1749 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1750 unsigned first_entry = start >> PAGE_SHIFT;
1751 gen8_pte_t __iomem *gtt_entries =
1752 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1754 struct sg_page_iter sg_iter;
1755 dma_addr_t addr = 0; /* shut up gcc */
1757 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1758 addr = sg_dma_address(sg_iter.sg) +
1759 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1760 gen8_set_pte(>t_entries[i],
1761 gen8_pte_encode(addr, level, true));
1766 * XXX: This serves as a posting read to make sure that the PTE has
1767 * actually been updated. There is some concern that even though
1768 * registers and PTEs are within the same BAR that they are potentially
1769 * of NUMA access patterns. Therefore, even with the way we assume
1770 * hardware should work, we must keep this posting read for paranoia.
1773 WARN_ON(readq(>t_entries[i-1])
1774 != gen8_pte_encode(addr, level, true));
1776 /* This next bit makes the above posting read even more important. We
1777 * want to flush the TLBs only after we're certain all the PTE updates
1780 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1781 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1785 * Binds an object into the global gtt with the specified cache level. The object
1786 * will be accessible to the GPU via commands whose operands reference offsets
1787 * within the global GTT as well as accessible by the GPU through the GMADR
1788 * mapped BAR (dev_priv->mm.gtt->gtt).
1790 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1791 struct sg_table *st,
1793 enum i915_cache_level level, u32 flags)
1795 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1796 unsigned first_entry = start >> PAGE_SHIFT;
1797 gen6_pte_t __iomem *gtt_entries =
1798 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1800 struct sg_page_iter sg_iter;
1801 dma_addr_t addr = 0;
1803 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1804 addr = sg_page_iter_dma_address(&sg_iter);
1805 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
1809 /* XXX: This serves as a posting read to make sure that the PTE has
1810 * actually been updated. There is some concern that even though
1811 * registers and PTEs are within the same BAR that they are potentially
1812 * of NUMA access patterns. Therefore, even with the way we assume
1813 * hardware should work, we must keep this posting read for paranoia.
1816 unsigned long gtt = readl(>t_entries[i-1]);
1817 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1820 /* This next bit makes the above posting read even more important. We
1821 * want to flush the TLBs only after we're certain all the PTE updates
1824 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1825 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1828 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1833 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1834 unsigned first_entry = start >> PAGE_SHIFT;
1835 unsigned num_entries = length >> PAGE_SHIFT;
1836 gen8_pte_t scratch_pte, __iomem *gtt_base =
1837 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1838 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1841 if (WARN(num_entries > max_entries,
1842 "First entry = %d; Num entries = %d (max=%d)\n",
1843 first_entry, num_entries, max_entries))
1844 num_entries = max_entries;
1846 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1849 for (i = 0; i < num_entries; i++)
1850 gen8_set_pte(>t_base[i], scratch_pte);
1854 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1859 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1860 unsigned first_entry = start >> PAGE_SHIFT;
1861 unsigned num_entries = length >> PAGE_SHIFT;
1862 gen6_pte_t scratch_pte, __iomem *gtt_base =
1863 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1864 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1867 if (WARN(num_entries > max_entries,
1868 "First entry = %d; Num entries = %d (max=%d)\n",
1869 first_entry, num_entries, max_entries))
1870 num_entries = max_entries;
1872 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1874 for (i = 0; i < num_entries; i++)
1875 iowrite32(scratch_pte, >t_base[i]);
1879 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1880 struct sg_table *pages,
1882 enum i915_cache_level cache_level, u32 unused)
1884 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1885 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1887 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1891 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1896 unsigned first_entry = start >> PAGE_SHIFT;
1897 unsigned num_entries = length >> PAGE_SHIFT;
1898 intel_gtt_clear_range(first_entry, num_entries);
1901 static int ggtt_bind_vma(struct i915_vma *vma,
1902 enum i915_cache_level cache_level,
1905 struct drm_device *dev = vma->vm->dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct drm_i915_gem_object *obj = vma->obj;
1908 struct sg_table *pages = obj->pages;
1912 ret = i915_get_ggtt_vma_pages(vma);
1915 pages = vma->ggtt_view.pages;
1917 /* Currently applicable only to VLV */
1919 pte_flags |= PTE_READ_ONLY;
1922 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1923 vma->vm->insert_entries(vma->vm, pages,
1925 cache_level, pte_flags);
1928 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1929 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1930 appgtt->base.insert_entries(&appgtt->base, pages,
1932 cache_level, pte_flags);
1938 static void ggtt_unbind_vma(struct i915_vma *vma)
1940 struct drm_device *dev = vma->vm->dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct drm_i915_gem_object *obj = vma->obj;
1943 const uint64_t size = min_t(uint64_t,
1947 if (vma->bound & GLOBAL_BIND) {
1948 vma->vm->clear_range(vma->vm,
1954 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1955 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1957 appgtt->base.clear_range(&appgtt->base,
1964 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1966 struct drm_device *dev = obj->base.dev;
1967 struct drm_i915_private *dev_priv = dev->dev_private;
1970 interruptible = do_idling(dev_priv);
1972 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
1973 PCI_DMA_BIDIRECTIONAL);
1975 undo_idling(dev_priv, interruptible);
1978 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1979 unsigned long color,
1983 if (node->color != color)
1986 if (!list_empty(&node->node_list)) {
1987 node = list_entry(node->node_list.next,
1990 if (node->allocated && node->color != color)
1995 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1996 unsigned long start,
1997 unsigned long mappable_end,
2000 /* Let GEM Manage all of the aperture.
2002 * However, leave one page at the end still bound to the scratch page.
2003 * There are a number of places where the hardware apparently prefetches
2004 * past the end of the object, and we've seen multiple hangs with the
2005 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2006 * aperture. One page should be enough to keep any prefetching inside
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2011 struct drm_mm_node *entry;
2012 struct drm_i915_gem_object *obj;
2013 unsigned long hole_start, hole_end;
2016 BUG_ON(mappable_end > end);
2018 /* Subtract the guard page ... */
2019 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2021 dev_priv->gtt.base.start = start;
2022 dev_priv->gtt.base.total = end - start;
2024 if (intel_vgpu_active(dev)) {
2025 ret = intel_vgt_balloon(dev);
2031 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2033 /* Mark any preallocated objects as occupied */
2034 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2035 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2037 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2038 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2040 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2041 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2043 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2046 vma->bound |= GLOBAL_BIND;
2049 /* Clear any non-preallocated blocks */
2050 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2051 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2052 hole_start, hole_end);
2053 ggtt_vm->clear_range(ggtt_vm, hole_start,
2054 hole_end - hole_start, true);
2057 /* And finally clear the reserved guard page */
2058 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2060 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2061 struct i915_hw_ppgtt *ppgtt;
2063 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2067 ret = __hw_ppgtt_init(dev, ppgtt);
2069 ppgtt->base.cleanup(&ppgtt->base);
2074 if (ppgtt->base.allocate_va_range)
2075 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2078 ppgtt->base.cleanup(&ppgtt->base);
2083 ppgtt->base.clear_range(&ppgtt->base,
2088 dev_priv->mm.aliasing_ppgtt = ppgtt;
2094 void i915_gem_init_global_gtt(struct drm_device *dev)
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 unsigned long gtt_size, mappable_size;
2099 gtt_size = dev_priv->gtt.base.total;
2100 mappable_size = dev_priv->gtt.mappable_end;
2102 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2105 void i915_global_gtt_cleanup(struct drm_device *dev)
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct i915_address_space *vm = &dev_priv->gtt.base;
2110 if (dev_priv->mm.aliasing_ppgtt) {
2111 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2113 ppgtt->base.cleanup(&ppgtt->base);
2116 if (drm_mm_initialized(&vm->mm)) {
2117 if (intel_vgpu_active(dev))
2118 intel_vgt_deballoon();
2120 drm_mm_takedown(&vm->mm);
2121 list_del(&vm->global_link);
2127 static int setup_scratch_page(struct drm_device *dev)
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2131 dma_addr_t dma_addr;
2133 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2136 set_pages_uc(page, 1);
2138 #ifdef CONFIG_INTEL_IOMMU
2139 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2140 PCI_DMA_BIDIRECTIONAL);
2141 if (pci_dma_mapping_error(dev->pdev, dma_addr))
2144 dma_addr = page_to_phys(page);
2146 dev_priv->gtt.base.scratch.page = page;
2147 dev_priv->gtt.base.scratch.addr = dma_addr;
2152 static void teardown_scratch_page(struct drm_device *dev)
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 struct page *page = dev_priv->gtt.base.scratch.page;
2157 set_pages_wb(page, 1);
2158 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
2159 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
2163 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2165 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2166 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2167 return snb_gmch_ctl << 20;
2170 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2172 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2173 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2175 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2177 #ifdef CONFIG_X86_32
2178 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2179 if (bdw_gmch_ctl > 4)
2183 return bdw_gmch_ctl << 20;
2186 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2188 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2189 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2192 return 1 << (20 + gmch_ctrl);
2197 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2199 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2200 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2201 return snb_gmch_ctl << 25; /* 32 MB units */
2204 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2206 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2207 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2208 return bdw_gmch_ctl << 25; /* 32 MB units */
2211 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2213 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2214 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2217 * 0x0 to 0x10: 32MB increments starting at 0MB
2218 * 0x11 to 0x16: 4MB increments starting at 8MB
2219 * 0x17 to 0x1d: 4MB increments start at 36MB
2221 if (gmch_ctrl < 0x11)
2222 return gmch_ctrl << 25;
2223 else if (gmch_ctrl < 0x17)
2224 return (gmch_ctrl - 0x11 + 2) << 22;
2226 return (gmch_ctrl - 0x17 + 9) << 22;
2229 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2231 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2232 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2234 if (gen9_gmch_ctl < 0xf0)
2235 return gen9_gmch_ctl << 25; /* 32 MB units */
2237 /* 4MB increments starting at 0xf0 for 4MB */
2238 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2241 static int ggtt_probe_common(struct drm_device *dev,
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 phys_addr_t gtt_phys_addr;
2248 /* For Modern GENs the PTEs and register space are split in the BAR */
2249 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2250 (pci_resource_len(dev->pdev, 0) / 2);
2253 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2254 * dropped. For WC mappings in general we have 64 byte burst writes
2255 * when the WC buffer is flushed, so we can't use it, but have to
2256 * resort to an uncached mapping. The WC issue is easily caught by the
2257 * readback check when writing GTT PTE entries.
2259 if (IS_BROXTON(dev))
2260 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2262 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2263 if (!dev_priv->gtt.gsm) {
2264 DRM_ERROR("Failed to map the gtt page table\n");
2268 ret = setup_scratch_page(dev);
2270 DRM_ERROR("Scratch setup failed\n");
2271 /* iounmap will also get called at remove, but meh */
2272 iounmap(dev_priv->gtt.gsm);
2278 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2279 * bits. When using advanced contexts each context stores its own PAT, but
2280 * writing this data shouldn't be harmful even in those cases. */
2281 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2285 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2286 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2287 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2288 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2289 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2290 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2291 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2292 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2294 if (!USES_PPGTT(dev_priv->dev))
2295 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2296 * so RTL will always use the value corresponding to
2298 * So let's disable cache for GGTT to avoid screen corruptions.
2299 * MOCS still can be used though.
2300 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2301 * before this patch, i.e. the same uncached + snooping access
2302 * like on gen6/7 seems to be in effect.
2303 * - So this just fixes blitter/render access. Again it looks
2304 * like it's not just uncached access, but uncached + snooping.
2305 * So we can still hold onto all our assumptions wrt cpu
2306 * clflushing on LLC machines.
2308 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2310 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2311 * write would work. */
2312 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2313 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2316 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2321 * Map WB on BDW to snooped on CHV.
2323 * Only the snoop bit has meaning for CHV, the rest is
2326 * The hardware will never snoop for certain types of accesses:
2327 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2328 * - PPGTT page tables
2329 * - some other special cycles
2331 * As with BDW, we also need to consider the following for GT accesses:
2332 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2333 * so RTL will always use the value corresponding to
2335 * Which means we must set the snoop bit in PAT entry 0
2336 * in order to keep the global status page working.
2338 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2342 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2343 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2344 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2345 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2347 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2348 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2351 static int gen8_gmch_probe(struct drm_device *dev,
2354 phys_addr_t *mappable_base,
2355 unsigned long *mappable_end)
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358 unsigned int gtt_size;
2362 /* TODO: We're not aware of mappable constraints on gen8 yet */
2363 *mappable_base = pci_resource_start(dev->pdev, 2);
2364 *mappable_end = pci_resource_len(dev->pdev, 2);
2366 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2367 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2369 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2371 if (INTEL_INFO(dev)->gen >= 9) {
2372 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2373 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2374 } else if (IS_CHERRYVIEW(dev)) {
2375 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2376 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2378 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2379 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2382 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2384 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2385 chv_setup_private_ppat(dev_priv);
2387 bdw_setup_private_ppat(dev_priv);
2389 ret = ggtt_probe_common(dev, gtt_size);
2391 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2392 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2393 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2394 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2399 static int gen6_gmch_probe(struct drm_device *dev,
2402 phys_addr_t *mappable_base,
2403 unsigned long *mappable_end)
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 unsigned int gtt_size;
2410 *mappable_base = pci_resource_start(dev->pdev, 2);
2411 *mappable_end = pci_resource_len(dev->pdev, 2);
2413 /* 64/512MB is the current min/max we actually know of, but this is just
2414 * a coarse sanity check.
2416 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2417 DRM_ERROR("Unknown GMADR size (%lx)\n",
2418 dev_priv->gtt.mappable_end);
2422 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2423 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2424 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2426 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2428 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2429 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2431 ret = ggtt_probe_common(dev, gtt_size);
2433 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2434 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2435 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2436 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2441 static void gen6_gmch_remove(struct i915_address_space *vm)
2444 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2447 teardown_scratch_page(vm->dev);
2450 static int i915_gmch_probe(struct drm_device *dev,
2453 phys_addr_t *mappable_base,
2454 unsigned long *mappable_end)
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2459 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2461 DRM_ERROR("failed to set up gmch\n");
2465 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2467 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2468 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2469 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2470 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2471 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2473 if (unlikely(dev_priv->gtt.do_idle_maps))
2474 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2479 static void i915_gmch_remove(struct i915_address_space *vm)
2481 intel_gmch_remove();
2484 int i915_gem_gtt_init(struct drm_device *dev)
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487 struct i915_gtt *gtt = &dev_priv->gtt;
2490 if (INTEL_INFO(dev)->gen <= 5) {
2491 gtt->gtt_probe = i915_gmch_probe;
2492 gtt->base.cleanup = i915_gmch_remove;
2493 } else if (INTEL_INFO(dev)->gen < 8) {
2494 gtt->gtt_probe = gen6_gmch_probe;
2495 gtt->base.cleanup = gen6_gmch_remove;
2496 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2497 gtt->base.pte_encode = iris_pte_encode;
2498 else if (IS_HASWELL(dev))
2499 gtt->base.pte_encode = hsw_pte_encode;
2500 else if (IS_VALLEYVIEW(dev))
2501 gtt->base.pte_encode = byt_pte_encode;
2502 else if (INTEL_INFO(dev)->gen >= 7)
2503 gtt->base.pte_encode = ivb_pte_encode;
2505 gtt->base.pte_encode = snb_pte_encode;
2507 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2508 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2511 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
2512 >t->mappable_base, >t->mappable_end);
2516 gtt->base.dev = dev;
2518 /* GMADR is the PCI mmio aperture into the global GTT. */
2519 DRM_INFO("Memory usable by graphics device = %zdM\n",
2520 gtt->base.total >> 20);
2521 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2522 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2523 #ifdef CONFIG_INTEL_IOMMU
2524 if (intel_iommu_gfx_mapped)
2525 DRM_INFO("VT-d active for gfx access\n");
2528 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2529 * user's requested state against the hardware/driver capabilities. We
2530 * do this now so that we can print out any log messages once rather
2531 * than every time we check intel_enable_ppgtt().
2533 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2534 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2539 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct drm_i915_gem_object *obj;
2543 struct i915_address_space *vm;
2544 struct i915_vma *vma;
2547 i915_check_and_clear_faults(dev);
2549 /* First fill our portion of the GTT with scratch pages */
2550 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2551 dev_priv->gtt.base.start,
2552 dev_priv->gtt.base.total,
2555 /* Cache flush objects bound into GGTT and rebind them. */
2556 vm = &dev_priv->gtt.base;
2557 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2559 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2563 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2570 i915_gem_clflush_object(obj, obj->pin_display);
2573 if (INTEL_INFO(dev)->gen >= 8) {
2574 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2575 chv_setup_private_ppat(dev_priv);
2577 bdw_setup_private_ppat(dev_priv);
2582 if (USES_PPGTT(dev)) {
2583 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2584 /* TODO: Perhaps it shouldn't be gen6 specific */
2586 struct i915_hw_ppgtt *ppgtt =
2587 container_of(vm, struct i915_hw_ppgtt,
2590 if (i915_is_ggtt(vm))
2591 ppgtt = dev_priv->mm.aliasing_ppgtt;
2593 gen6_write_page_range(dev_priv, &ppgtt->pd,
2594 0, ppgtt->base.total);
2598 i915_ggtt_flush(dev_priv);
2601 static struct i915_vma *
2602 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2603 struct i915_address_space *vm,
2604 const struct i915_ggtt_view *ggtt_view)
2606 struct i915_vma *vma;
2608 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2609 return ERR_PTR(-EINVAL);
2611 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2613 return ERR_PTR(-ENOMEM);
2615 INIT_LIST_HEAD(&vma->vma_link);
2616 INIT_LIST_HEAD(&vma->mm_list);
2617 INIT_LIST_HEAD(&vma->exec_list);
2621 if (i915_is_ggtt(vm))
2622 vma->ggtt_view = *ggtt_view;
2624 list_add_tail(&vma->vma_link, &obj->vma_list);
2625 if (!i915_is_ggtt(vm))
2626 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2632 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2633 struct i915_address_space *vm)
2635 struct i915_vma *vma;
2637 vma = i915_gem_obj_to_vma(obj, vm);
2639 vma = __i915_gem_vma_create(obj, vm,
2640 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2646 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2647 const struct i915_ggtt_view *view)
2649 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2650 struct i915_vma *vma;
2653 return ERR_PTR(-EINVAL);
2655 vma = i915_gem_obj_to_ggtt_view(obj, view);
2661 vma = __i915_gem_vma_create(obj, ggtt, view);
2668 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2669 struct sg_table *st)
2671 unsigned int column, row;
2672 unsigned int src_idx;
2673 struct scatterlist *sg = st->sgl;
2677 for (column = 0; column < width; column++) {
2678 src_idx = width * (height - 1) + column;
2679 for (row = 0; row < height; row++) {
2681 /* We don't need the pages, but need to initialize
2682 * the entries so the sg list can be happily traversed.
2683 * The only thing we need are DMA addresses.
2685 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2686 sg_dma_address(sg) = in[src_idx];
2687 sg_dma_len(sg) = PAGE_SIZE;
2694 static struct sg_table *
2695 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2696 struct drm_i915_gem_object *obj)
2698 struct drm_device *dev = obj->base.dev;
2699 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2700 unsigned long size, pages, rot_pages;
2701 struct sg_page_iter sg_iter;
2703 dma_addr_t *page_addr_list;
2704 struct sg_table *st;
2705 unsigned int tile_pitch, tile_height;
2706 unsigned int width_pages, height_pages;
2709 pages = obj->base.size / PAGE_SIZE;
2711 /* Calculate tiling geometry. */
2712 tile_height = intel_tile_height(dev, rot_info->pixel_format,
2713 rot_info->fb_modifier);
2714 tile_pitch = PAGE_SIZE / tile_height;
2715 width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch);
2716 height_pages = DIV_ROUND_UP(rot_info->height, tile_height);
2717 rot_pages = width_pages * height_pages;
2718 size = rot_pages * PAGE_SIZE;
2720 /* Allocate a temporary list of source pages for random access. */
2721 page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
2722 if (!page_addr_list)
2723 return ERR_PTR(ret);
2725 /* Allocate target SG list. */
2726 st = kmalloc(sizeof(*st), GFP_KERNEL);
2730 ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
2734 /* Populate source page list from the object. */
2736 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2737 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2741 /* Rotate the pages. */
2742 rotate_pages(page_addr_list, width_pages, height_pages, st);
2745 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2746 size, rot_info->pitch, rot_info->height,
2747 rot_info->pixel_format, width_pages, height_pages,
2750 drm_free_large(page_addr_list);
2757 drm_free_large(page_addr_list);
2760 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2761 size, ret, rot_info->pitch, rot_info->height,
2762 rot_info->pixel_format, width_pages, height_pages,
2764 return ERR_PTR(ret);
2767 static struct sg_table *
2768 intel_partial_pages(const struct i915_ggtt_view *view,
2769 struct drm_i915_gem_object *obj)
2771 struct sg_table *st;
2772 struct scatterlist *sg;
2773 struct sg_page_iter obj_sg_iter;
2776 st = kmalloc(sizeof(*st), GFP_KERNEL);
2780 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2786 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2787 view->params.partial.offset)
2789 if (st->nents >= view->params.partial.size)
2792 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2793 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2794 sg_dma_len(sg) = PAGE_SIZE;
2805 return ERR_PTR(ret);
2809 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2813 if (vma->ggtt_view.pages)
2816 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2817 vma->ggtt_view.pages = vma->obj->pages;
2818 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2819 vma->ggtt_view.pages =
2820 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2821 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2822 vma->ggtt_view.pages =
2823 intel_partial_pages(&vma->ggtt_view, vma->obj);
2825 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2826 vma->ggtt_view.type);
2828 if (!vma->ggtt_view.pages) {
2829 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2830 vma->ggtt_view.type);
2832 } else if (IS_ERR(vma->ggtt_view.pages)) {
2833 ret = PTR_ERR(vma->ggtt_view.pages);
2834 vma->ggtt_view.pages = NULL;
2835 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2836 vma->ggtt_view.type, ret);
2843 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2845 * @cache_level: mapping cache level
2846 * @flags: flags like global or local mapping
2848 * DMA addresses are taken from the scatter-gather table of this object (or of
2849 * this VMA in case of non-default GGTT views) and PTE entries set up.
2850 * Note that DMA addresses are also the only part of the SG table we care about.
2852 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2858 if (WARN_ON(flags == 0))
2862 if (flags & PIN_GLOBAL)
2863 bind_flags |= GLOBAL_BIND;
2864 if (flags & PIN_USER)
2865 bind_flags |= LOCAL_BIND;
2867 if (flags & PIN_UPDATE)
2868 bind_flags |= vma->bound;
2870 bind_flags &= ~vma->bound;
2872 if (bind_flags == 0)
2875 if (vma->bound == 0 && vma->vm->allocate_va_range) {
2876 trace_i915_va_alloc(vma->vm,
2879 VM_TO_TRACE_NAME(vma->vm));
2881 ret = vma->vm->allocate_va_range(vma->vm,
2888 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2892 vma->bound |= bind_flags;
2898 * i915_ggtt_view_size - Get the size of a GGTT view.
2899 * @obj: Object the view is of.
2900 * @view: The view in question.
2902 * @return The size of the GGTT view in bytes.
2905 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2906 const struct i915_ggtt_view *view)
2908 if (view->type == I915_GGTT_VIEW_NORMAL ||
2909 view->type == I915_GGTT_VIEW_ROTATED) {
2910 return obj->base.size;
2911 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2912 return view->params.partial.size << PAGE_SHIFT;
2914 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2915 return obj->base.size;