2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
73 u32 val = I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val);
78 static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
80 struct drm_i915_private *dev_priv = guc_to_i915(guc);
85 if (WARN_ON(len < 1 || len > 15))
88 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
89 spin_lock(&dev_priv->guc.host2guc_lock);
91 dev_priv->guc.action_count += 1;
92 dev_priv->guc.action_cmd = data[0];
94 for (i = 0; i < len; i++)
95 I915_WRITE(SOFT_SCRATCH(i), data[i]);
97 POSTING_READ(SOFT_SCRATCH(i - 1));
99 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
101 /* No HOST2GUC command should take longer than 10ms */
102 ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
103 if (status != GUC2HOST_STATUS_SUCCESS) {
105 * Either the GuC explicitly returned an error (which
106 * we convert to -EIO here) or no response at all was
107 * received within the timeout limit (-ETIMEDOUT)
109 if (ret != -ETIMEDOUT)
112 DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
113 "status=0x%08X response=0x%08X\n",
114 data[0], ret, status,
115 I915_READ(SOFT_SCRATCH(15)));
117 dev_priv->guc.action_fail += 1;
118 dev_priv->guc.action_err = ret;
120 dev_priv->guc.action_status = status;
122 spin_unlock(&dev_priv->guc.host2guc_lock);
123 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
129 * Tell the GuC to allocate or deallocate a specific doorbell
132 static int host2guc_allocate_doorbell(struct intel_guc *guc,
133 struct i915_guc_client *client)
137 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
138 data[1] = client->ctx_index;
140 return host2guc_action(guc, data, 2);
143 static int host2guc_release_doorbell(struct intel_guc *guc,
144 struct i915_guc_client *client)
148 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
149 data[1] = client->ctx_index;
151 return host2guc_action(guc, data, 2);
154 static int host2guc_sample_forcewake(struct intel_guc *guc,
155 struct i915_guc_client *client)
157 struct drm_i915_private *dev_priv = guc_to_i915(guc);
160 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
161 data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
163 return host2guc_action(guc, data, 2);
167 * Initialise, update, or clear doorbell data shared with the GuC
169 * These functions modify shared data and so need access to the mapped
170 * client object which contains the page being used for the doorbell
173 static void guc_init_doorbell(struct intel_guc *guc,
174 struct i915_guc_client *client)
176 struct guc_doorbell_info *doorbell;
179 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
180 doorbell = base + client->doorbell_offset;
182 doorbell->db_status = 1;
183 doorbell->cookie = 0;
188 static int guc_ring_doorbell(struct i915_guc_client *gc)
190 struct guc_process_desc *desc;
191 union guc_doorbell_qw db_cmp, db_exc, db_ret;
192 union guc_doorbell_qw *db;
194 int attempt = 2, ret = -EAGAIN;
196 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
197 desc = base + gc->proc_desc_offset;
199 /* Update the tail so it is visible to GuC */
200 desc->tail = gc->wq_tail;
203 db_cmp.db_status = GUC_DOORBELL_ENABLED;
204 db_cmp.cookie = gc->cookie;
206 /* cookie to be updated */
207 db_exc.db_status = GUC_DOORBELL_ENABLED;
208 db_exc.cookie = gc->cookie + 1;
209 if (db_exc.cookie == 0)
212 /* pointer of current doorbell cacheline */
213 db = base + gc->doorbell_offset;
216 /* lets ring the doorbell */
217 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
218 db_cmp.value_qw, db_exc.value_qw);
220 /* if the exchange was successfully executed */
221 if (db_ret.value_qw == db_cmp.value_qw) {
222 /* db was successfully rung */
223 gc->cookie = db_exc.cookie;
228 /* XXX: doorbell was lost and need to acquire it again */
229 if (db_ret.db_status == GUC_DOORBELL_DISABLED)
232 DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
233 db_cmp.cookie, db_ret.cookie);
235 /* update the cookie to newly read cookie from GuC */
236 db_cmp.cookie = db_ret.cookie;
237 db_exc.cookie = db_ret.cookie + 1;
238 if (db_exc.cookie == 0)
246 static void guc_disable_doorbell(struct intel_guc *guc,
247 struct i915_guc_client *client)
249 struct drm_i915_private *dev_priv = guc_to_i915(guc);
250 struct guc_doorbell_info *doorbell;
252 int drbreg = GEN8_DRBREGL(client->doorbell_id);
255 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
256 doorbell = base + client->doorbell_offset;
258 doorbell->db_status = 0;
262 I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID);
264 value = I915_READ(drbreg);
265 WARN_ON((value & GEN8_DRB_VALID) != 0);
267 I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0);
268 I915_WRITE(drbreg, 0);
270 /* XXX: wait for any interrupts */
271 /* XXX: wait for workqueue to drain */
275 * Select, assign and relase doorbell cachelines
277 * These functions track which doorbell cachelines are in use.
278 * The data they manipulate is protected by the host2guc lock.
281 static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
283 const uint32_t cacheline_size = cache_line_size();
286 spin_lock(&guc->host2guc_lock);
288 /* Doorbell uses a single cache line within a page */
289 offset = offset_in_page(guc->db_cacheline);
291 /* Moving to next cache line to reduce contention */
292 guc->db_cacheline += cacheline_size;
294 spin_unlock(&guc->host2guc_lock);
296 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
297 offset, guc->db_cacheline, cacheline_size);
302 static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority)
305 * The bitmap is split into two halves; the first half is used for
306 * normal priority contexts, the second half for high-priority ones.
307 * Note that logically higher priorities are numerically less than
308 * normal ones, so the test below means "is it high-priority?"
310 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
311 const uint16_t half = GUC_MAX_DOORBELLS / 2;
312 const uint16_t start = hi_pri ? half : 0;
313 const uint16_t end = start + half;
316 spin_lock(&guc->host2guc_lock);
317 id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
319 id = GUC_INVALID_DOORBELL_ID;
321 bitmap_set(guc->doorbell_bitmap, id, 1);
322 spin_unlock(&guc->host2guc_lock);
324 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
325 hi_pri ? "high" : "normal", id);
330 static void release_doorbell(struct intel_guc *guc, uint16_t id)
332 spin_lock(&guc->host2guc_lock);
333 bitmap_clear(guc->doorbell_bitmap, id, 1);
334 spin_unlock(&guc->host2guc_lock);
338 * Initialise the process descriptor shared with the GuC firmware.
340 static void guc_init_proc_desc(struct intel_guc *guc,
341 struct i915_guc_client *client)
343 struct guc_process_desc *desc;
346 base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
347 desc = base + client->proc_desc_offset;
349 memset(desc, 0, sizeof(*desc));
352 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
353 * space for ring3 clients (set them as in mmap_ioctl) or kernel
354 * space for kernel clients (map on demand instead? May make debug
355 * easier to have it mapped).
357 desc->wq_base_addr = 0;
358 desc->db_base_addr = 0;
360 desc->context_id = client->ctx_index;
361 desc->wq_size_bytes = client->wq_size;
362 desc->wq_status = WQ_STATUS_ACTIVE;
363 desc->priority = client->priority;
369 * Initialise/clear the context descriptor shared with the GuC firmware.
371 * This descriptor tells the GuC where (in GGTT space) to find the important
372 * data structures relating to this client (doorbell, process descriptor,
376 static void guc_init_ctx_desc(struct intel_guc *guc,
377 struct i915_guc_client *client)
379 struct intel_context *ctx = client->owner;
380 struct guc_context_desc desc;
384 memset(&desc, 0, sizeof(desc));
386 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
387 desc.context_id = client->ctx_index;
388 desc.priority = client->priority;
389 desc.db_id = client->doorbell_id;
391 for (i = 0; i < I915_NUM_RINGS; i++) {
392 struct guc_execlist_context *lrc = &desc.lrc[i];
393 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
394 struct intel_engine_cs *ring;
395 struct drm_i915_gem_object *obj;
398 /* TODO: We have a design issue to be solved here. Only when we
399 * receive the first batch, we know which engine is used by the
400 * user. But here GuC expects the lrc and ring to be pinned. It
401 * is not an issue for default context, which is the only one
402 * for now who owns a GuC client. But for future owner of GuC
403 * client, need to make sure lrc is pinned prior to enter here.
405 obj = ctx->engine[i].state;
407 break; /* XXX: continue? */
409 ring = ringbuf->ring;
410 ctx_desc = intel_lr_context_descriptor(ctx, ring);
411 lrc->context_desc = (u32)ctx_desc;
413 /* The state page is after PPHWSP */
414 lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
415 LRC_STATE_PN * PAGE_SIZE;
416 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
417 (ring->id << GUC_ELC_ENGINE_OFFSET);
421 lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
422 lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
423 lrc->ring_next_free_location = lrc->ring_begin;
424 lrc->ring_current_tail_pointer_value = 0;
426 desc.engines_used |= (1 << ring->id);
429 WARN_ON(desc.engines_used == 0);
432 * The CPU address is only needed at certain points, so kmap_atomic on
433 * demand instead of storing it in the ctx descriptor.
434 * XXX: May make debug easier to have it mapped
436 desc.db_trigger_cpu = 0;
437 desc.db_trigger_uk = client->doorbell_offset +
438 i915_gem_obj_ggtt_offset(client->client_obj);
439 desc.db_trigger_phy = client->doorbell_offset +
440 sg_dma_address(client->client_obj->pages->sgl);
442 desc.process_desc = client->proc_desc_offset +
443 i915_gem_obj_ggtt_offset(client->client_obj);
445 desc.wq_addr = client->wq_offset +
446 i915_gem_obj_ggtt_offset(client->client_obj);
448 desc.wq_size = client->wq_size;
451 * XXX: Take LRCs from an existing intel_context if this is not an
452 * IsKMDCreatedContext client
454 desc.desc_private = (uintptr_t)client;
456 /* Pool context is pinned already */
457 sg = guc->ctx_pool_obj->pages;
458 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
459 sizeof(desc) * client->ctx_index);
462 static void guc_fini_ctx_desc(struct intel_guc *guc,
463 struct i915_guc_client *client)
465 struct guc_context_desc desc;
468 memset(&desc, 0, sizeof(desc));
470 sg = guc->ctx_pool_obj->pages;
471 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
472 sizeof(desc) * client->ctx_index);
475 /* Get valid workqueue item and return it back to offset */
476 static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
478 struct guc_process_desc *desc;
480 u32 size = sizeof(struct guc_wq_item);
481 int ret = 0, timeout_counter = 200;
483 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
484 desc = base + gc->proc_desc_offset;
486 while (timeout_counter-- > 0) {
487 ret = wait_for_atomic(CIRC_SPACE(gc->wq_tail, desc->head,
488 gc->wq_size) >= size, 1);
491 *offset = gc->wq_tail;
493 /* advance the tail for next workqueue item */
495 gc->wq_tail &= gc->wq_size - 1;
497 /* this will break the loop */
507 static int guc_add_workqueue_item(struct i915_guc_client *gc,
508 struct drm_i915_gem_request *rq)
510 enum intel_ring_id ring_id = rq->ring->id;
511 struct guc_wq_item *wqi;
513 u32 tail, wq_len, wq_off = 0;
516 ret = guc_get_workqueue_space(gc, &wq_off);
520 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
521 * should not have the case where structure wqi is across page, neither
522 * wrapped to the beginning. This simplifies the implementation below.
524 * XXX: if not the case, we need save data to a temp wqi and copy it to
525 * workqueue buffer dw by dw.
527 WARN_ON(sizeof(struct guc_wq_item) != 16);
530 /* wq starts from the page after doorbell / process_desc */
531 base = kmap_atomic(i915_gem_object_get_page(gc->client_obj,
532 (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT));
533 wq_off &= PAGE_SIZE - 1;
534 wqi = (struct guc_wq_item *)((char *)base + wq_off);
536 /* len does not include the header */
537 wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1;
538 wqi->header = WQ_TYPE_INORDER |
539 (wq_len << WQ_LEN_SHIFT) |
540 (ring_id << WQ_TARGET_SHIFT) |
543 /* The GuC wants only the low-order word of the context descriptor */
544 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring);
546 /* The GuC firmware wants the tail index in QWords, not bytes */
547 tail = rq->ringbuf->tail >> 3;
548 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
549 wqi->fence_id = 0; /*XXX: what fence to be here */
556 #define CTX_RING_BUFFER_START 0x08
558 /* Update the ringbuffer pointer in a saved context image */
559 static void lr_context_update(struct drm_i915_gem_request *rq)
561 enum intel_ring_id ring_id = rq->ring->id;
562 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring_id].state;
563 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
568 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
569 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
571 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
572 reg_state = kmap_atomic(page);
574 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
576 kunmap_atomic(reg_state);
580 * i915_guc_submit() - Submit commands through GuC
581 * @client: the guc client where commands will go through
582 * @ctx: LRC where commands come from
583 * @ring: HW engine that will excute the commands
585 * Return: 0 if succeed
587 int i915_guc_submit(struct i915_guc_client *client,
588 struct drm_i915_gem_request *rq)
590 struct intel_guc *guc = client->guc;
591 enum intel_ring_id ring_id = rq->ring->id;
595 /* Need this because of the deferred pin ctx and ring */
596 /* Shall we move this right after ring is pinned? */
597 lr_context_update(rq);
599 spin_lock_irqsave(&client->wq_lock, flags);
601 q_ret = guc_add_workqueue_item(client, rq);
603 b_ret = guc_ring_doorbell(client);
605 client->submissions[ring_id] += 1;
608 client->retcode = q_ret;
611 client->retcode = q_ret = b_ret;
615 spin_unlock_irqrestore(&client->wq_lock, flags);
617 spin_lock(&guc->host2guc_lock);
618 guc->submissions[ring_id] += 1;
619 guc->last_seqno[ring_id] = rq->seqno;
620 spin_unlock(&guc->host2guc_lock);
626 * Everything below here is concerned with setup & teardown, and is
627 * therefore not part of the somewhat time-critical batch-submission
628 * path of i915_guc_submit() above.
632 * gem_allocate_guc_obj() - Allocate gem object for GuC usage
634 * @size: size of object
636 * This is a wrapper to create a gem obj. In order to use it inside GuC, the
637 * object needs to be pinned lifetime. Also we must pin it to gtt space other
638 * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
640 * Return: A drm_i915_gem_object if successful, otherwise NULL.
642 static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 struct drm_i915_gem_object *obj;
648 obj = i915_gem_alloc_object(dev, size);
652 if (i915_gem_object_get_pages(obj)) {
653 drm_gem_object_unreference(&obj->base);
657 if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
658 PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) {
659 drm_gem_object_unreference(&obj->base);
663 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
664 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
670 * gem_release_guc_obj() - Release gem object allocated for GuC usage
671 * @obj: gem obj to be released
673 static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
678 if (i915_gem_obj_is_pinned(obj))
679 i915_gem_object_ggtt_unpin(obj);
681 drm_gem_object_unreference(&obj->base);
684 static void guc_client_free(struct drm_device *dev,
685 struct i915_guc_client *client)
687 struct drm_i915_private *dev_priv = dev->dev_private;
688 struct intel_guc *guc = &dev_priv->guc;
693 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) {
695 * First disable the doorbell, then tell the GuC we've
696 * finished with it, finally deallocate it in our bitmap
698 guc_disable_doorbell(guc, client);
699 host2guc_release_doorbell(guc, client);
700 release_doorbell(guc, client->doorbell_id);
704 * XXX: wait for any outstanding submissions before freeing memory.
705 * Be sure to drop any locks
708 gem_release_guc_obj(client->client_obj);
710 if (client->ctx_index != GUC_INVALID_CTX_ID) {
711 guc_fini_ctx_desc(guc, client);
712 ida_simple_remove(&guc->ctx_ids, client->ctx_index);
719 * guc_client_alloc() - Allocate an i915_guc_client
721 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
722 * The kernel client to replace ExecList submission is created with
723 * NORMAL priority. Priority of a client for scheduler can be HIGH,
724 * while a preemption context can use CRITICAL.
725 * @ctx the context to own the client (we use the default render context)
727 * Return: An i915_guc_client object if success.
729 static struct i915_guc_client *guc_client_alloc(struct drm_device *dev,
731 struct intel_context *ctx)
733 struct i915_guc_client *client;
734 struct drm_i915_private *dev_priv = dev->dev_private;
735 struct intel_guc *guc = &dev_priv->guc;
736 struct drm_i915_gem_object *obj;
738 client = kzalloc(sizeof(*client), GFP_KERNEL);
742 client->doorbell_id = GUC_INVALID_DOORBELL_ID;
743 client->priority = priority;
747 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
748 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
749 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
750 client->ctx_index = GUC_INVALID_CTX_ID;
754 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
755 obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE);
759 client->client_obj = obj;
760 client->wq_offset = GUC_DB_SIZE;
761 client->wq_size = GUC_WQ_SIZE;
762 spin_lock_init(&client->wq_lock);
764 client->doorbell_offset = select_doorbell_cacheline(guc);
767 * Since the doorbell only requires a single cacheline, we can save
768 * space by putting the application process descriptor in the same
769 * page. Use the half of the page that doesn't include the doorbell.
771 if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
772 client->proc_desc_offset = 0;
774 client->proc_desc_offset = (GUC_DB_SIZE / 2);
776 client->doorbell_id = assign_doorbell(guc, client->priority);
777 if (client->doorbell_id == GUC_INVALID_DOORBELL_ID)
778 /* XXX: evict a doorbell instead */
781 guc_init_proc_desc(guc, client);
782 guc_init_ctx_desc(guc, client);
783 guc_init_doorbell(guc, client);
785 /* XXX: Any cache flushes needed? General domain mgmt calls? */
787 if (host2guc_allocate_doorbell(guc, client))
790 DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
791 priority, client, client->ctx_index, client->doorbell_id);
796 DRM_ERROR("FAILED to create priority %u GuC client!\n", priority);
798 guc_client_free(dev, client);
802 static void guc_create_log(struct intel_guc *guc)
804 struct drm_i915_private *dev_priv = guc_to_i915(guc);
805 struct drm_i915_gem_object *obj;
806 unsigned long offset;
807 uint32_t size, flags;
809 if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
812 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
813 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
815 /* The first page is to save log buffer state. Allocate one
816 * extra page for others in case for overlap */
817 size = (1 + GUC_LOG_DPC_PAGES + 1 +
818 GUC_LOG_ISR_PAGES + 1 +
819 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
823 obj = gem_allocate_guc_obj(dev_priv->dev, size);
825 /* logging will be off */
826 i915.guc_log_level = -1;
833 /* each allocated unit is a page */
834 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
835 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
836 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
837 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
839 offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */
840 guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
844 * Set up the memory resources to be shared with the GuC. At this point,
845 * we require just one object that can be mapped through the GGTT.
847 int i915_guc_submission_init(struct drm_device *dev)
849 struct drm_i915_private *dev_priv = dev->dev_private;
850 const size_t ctxsize = sizeof(struct guc_context_desc);
851 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
852 const size_t gemsize = round_up(poolsize, PAGE_SIZE);
853 struct intel_guc *guc = &dev_priv->guc;
855 if (!i915.enable_guc_submission)
856 return 0; /* not enabled */
858 if (guc->ctx_pool_obj)
859 return 0; /* already allocated */
861 guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize);
862 if (!guc->ctx_pool_obj)
865 spin_lock_init(&dev_priv->guc.host2guc_lock);
867 ida_init(&guc->ctx_ids);
874 int i915_guc_submission_enable(struct drm_device *dev)
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 struct intel_guc *guc = &dev_priv->guc;
878 struct intel_context *ctx = dev_priv->ring[RCS].default_context;
879 struct i915_guc_client *client;
881 /* client for execbuf submission */
882 client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx);
884 DRM_ERROR("Failed to create execbuf guc_client\n");
888 guc->execbuf_client = client;
890 host2guc_sample_forcewake(guc, client);
895 void i915_guc_submission_disable(struct drm_device *dev)
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 struct intel_guc *guc = &dev_priv->guc;
900 guc_client_free(dev, guc->execbuf_client);
901 guc->execbuf_client = NULL;
904 void i915_guc_submission_fini(struct drm_device *dev)
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 struct intel_guc *guc = &dev_priv->guc;
909 gem_release_guc_obj(dev_priv->guc.log_obj);
912 if (guc->ctx_pool_obj)
913 ida_destroy(&guc->ctx_ids);
914 gem_release_guc_obj(guc->ctx_pool_obj);
915 guc->ctx_pool_obj = NULL;