drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 /* For display hotplug interrupt */
  40 static void
  41 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  42 {
  43         if ((dev_priv->irq_mask & mask) != 0) {
  44                 dev_priv->irq_mask &= ~mask;
  45                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  46                 POSTING_READ(DEIMR);
  47         }
  48 }
  49
  50 static inline void
  51 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  52 {
  53         if ((dev_priv->irq_mask & mask) != mask) {
  54                 dev_priv->irq_mask |= mask;
  55                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  56                 POSTING_READ(DEIMR);
  57         }
  58 }
  59
  60 void
  61 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  62 {
  63         u32 reg = PIPESTAT(pipe);
  64         u32 pipestat = I915_READ(reg) & 0x7fff0000;
  65
  66         if ((pipestat & mask) == mask)
  67                 return;
  68
  69         /* Enable the interrupt, clear any pending status */
  70         pipestat |= mask | (mask >> 16);
  71         I915_WRITE(reg, pipestat);
  72         POSTING_READ(reg);
  73 }
  74
  75 void
  76 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  77 {
  78         u32 reg = PIPESTAT(pipe);
  79         u32 pipestat = I915_READ(reg) & 0x7fff0000;
  80
  81         if ((pipestat & mask) == 0)
  82                 return;
  83
  84         pipestat &= ~mask;
  85         I915_WRITE(reg, pipestat);
  86         POSTING_READ(reg);
  87 }
  88
  89 /**
  90  * intel_enable_asle - enable ASLE interrupt for OpRegion
  91  */
  92 void intel_enable_asle(struct drm_device *dev)
  93 {
  94         drm_i915_private_t *dev_priv = dev->dev_private;
  95         unsigned long irqflags;
  96
  97         /* FIXME: opregion/asle for VLV */
  98         if (IS_VALLEYVIEW(dev))
  99                 return;
 100
 101         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 102
 103         if (HAS_PCH_SPLIT(dev))
 104                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 105         else {
 106                 i915_enable_pipestat(dev_priv, 1,
 107                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 108                 if (INTEL_INFO(dev)->gen >= 4)
 109                         i915_enable_pipestat(dev_priv, 0,
 110                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 111         }
 112
 113         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 114 }
 115
 116 /**
 117  * i915_pipe_enabled - check if a pipe is enabled
 118  * @dev: DRM device
 119  * @pipe: pipe to check
 120  *
 121  * Reading certain registers when the pipe is disabled can hang the chip.
 122  * Use this routine to make sure the PLL is running and the pipe is active
 123  * before reading such registers if unsure.
 124  */
 125 static int
 126 i915_pipe_enabled(struct drm_device *dev, int pipe)
 127 {
 128         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 129         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 130                                                                       pipe);
 131
 132         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 133 }
 134
 135 /* Called from drm generic code, passed a 'crtc', which
 136  * we use as a pipe index
 137  */
 138 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 139 {
 140         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 141         unsigned long high_frame;
 142         unsigned long low_frame;
 143         u32 high1, high2, low;
 144
 145         if (!i915_pipe_enabled(dev, pipe)) {
 146                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 147                                 "pipe %c\n", pipe_name(pipe));
 148                 return 0;
 149         }
 150
 151         high_frame = PIPEFRAME(pipe);
 152         low_frame = PIPEFRAMEPIXEL(pipe);
 153
 154         /*
 155          * High & low register fields aren't synchronized, so make sure
 156          * we get a low value that's stable across two reads of the high
 157          * register.
 158          */
 159         do {
 160                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 161                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 162                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 163         } while (high1 != high2);
 164
 165         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 166         low >>= PIPE_FRAME_LOW_SHIFT;
 167         return (high1 << 8) | low;
 168 }
 169
 170 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 171 {
 172         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 173         int reg = PIPE_FRMCOUNT_GM45(pipe);
 174
 175         if (!i915_pipe_enabled(dev, pipe)) {
 176                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 177                                  "pipe %c\n", pipe_name(pipe));
 178                 return 0;
 179         }
 180
 181         return I915_READ(reg);
 182 }
 183
 184 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 185                              int *vpos, int *hpos)
 186 {
 187         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 188         u32 vbl = 0, position = 0;
 189         int vbl_start, vbl_end, htotal, vtotal;
 190         bool in_vbl = true;
 191         int ret = 0;
 192         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 193                                                                       pipe);
 194
 195         if (!i915_pipe_enabled(dev, pipe)) {
 196                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 197                                  "pipe %c\n", pipe_name(pipe));
 198                 return 0;
 199         }
 200
 201         /* Get vtotal. */
 202         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 203
 204         if (INTEL_INFO(dev)->gen >= 4) {
 205                 /* No obvious pixelcount register. Only query vertical
 206                  * scanout position from Display scan line register.
 207                  */
 208                 position = I915_READ(PIPEDSL(pipe));
 209
 210                 /* Decode into vertical scanout position. Don't have
 211                  * horizontal scanout position.
 212                  */
 213                 *vpos = position & 0x1fff;
 214                 *hpos = 0;
 215         } else {
 216                 /* Have access to pixelcount since start of frame.
 217                  * We can split this into vertical and horizontal
 218                  * scanout position.
 219                  */
 220                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 221
 222                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 223                 *vpos = position / htotal;
 224                 *hpos = position - (*vpos * htotal);
 225         }
 226
 227         /* Query vblank area. */
 228         vbl = I915_READ(VBLANK(cpu_transcoder));
 229
 230         /* Test position against vblank region. */
 231         vbl_start = vbl & 0x1fff;
 232         vbl_end = (vbl >> 16) & 0x1fff;
 233
 234         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 235                 in_vbl = false;
 236
 237         /* Inside "upper part" of vblank area? Apply corrective offset: */
 238         if (in_vbl && (*vpos >= vbl_start))
 239                 *vpos = *vpos - vtotal;
 240
 241         /* Readouts valid? */
 242         if (vbl > 0)
 243                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 244
 245         /* In vblank? */
 246         if (in_vbl)
 247                 ret |= DRM_SCANOUTPOS_INVBL;
 248
 249         return ret;
 250 }
 251
 252 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 253                               int *max_error,
 254                               struct timeval *vblank_time,
 255                               unsigned flags)
 256 {
 257         struct drm_crtc *crtc;
 258
 259         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         /* Get drm_crtc to timestamp: */
 265         crtc = intel_get_crtc_for_pipe(dev, pipe);
 266         if (crtc == NULL) {
 267                 DRM_ERROR("Invalid crtc %d\n", pipe);
 268                 return -EINVAL;
 269         }
 270
 271         if (!crtc->enabled) {
 272                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 273                 return -EBUSY;
 274         }
 275
 276         /* Helper routine in DRM core does all the work: */
 277         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 278                                                      vblank_time, flags,
 279                                                      crtc);
 280 }
 281
 282 /*
 283  * Handle hotplug events outside the interrupt handler proper.
 284  */
 285 static void i915_hotplug_work_func(struct work_struct *work)
 286 {
 287         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 288                                                     hotplug_work);
 289         struct drm_device *dev = dev_priv->dev;
 290         struct drm_mode_config *mode_config = &dev->mode_config;
 291         struct intel_encoder *encoder;
 292
 293         /* HPD irq before everything is fully set up. */
 294         if (!dev_priv->enable_hotplug_processing)
 295                 return;
 296
 297         mutex_lock(&mode_config->mutex);
 298         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 299
 300         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 301                 if (encoder->hot_plug)
 302                         encoder->hot_plug(encoder);
 303
 304         mutex_unlock(&mode_config->mutex);
 305
 306         /* Just fire off a uevent and let userspace tell us what to do */
 307         drm_helper_hpd_irq_event(dev);
 308 }
 309
 310 static void ironlake_handle_rps_change(struct drm_device *dev)
 311 {
 312         drm_i915_private_t *dev_priv = dev->dev_private;
 313         u32 busy_up, busy_down, max_avg, min_avg;
 314         u8 new_delay;
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&mchdev_lock, flags);
 318
 319         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 320
 321         new_delay = dev_priv->ips.cur_delay;
 322
 323         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 324         busy_up = I915_READ(RCPREVBSYTUPAVG);
 325         busy_down = I915_READ(RCPREVBSYTDNAVG);
 326         max_avg = I915_READ(RCBMAXAVG);
 327         min_avg = I915_READ(RCBMINAVG);
 328
 329         /* Handle RCS change request from hw */
 330         if (busy_up > max_avg) {
 331                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 332                         new_delay = dev_priv->ips.cur_delay - 1;
 333                 if (new_delay < dev_priv->ips.max_delay)
 334                         new_delay = dev_priv->ips.max_delay;
 335         } else if (busy_down < min_avg) {
 336                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 337                         new_delay = dev_priv->ips.cur_delay + 1;
 338                 if (new_delay > dev_priv->ips.min_delay)
 339                         new_delay = dev_priv->ips.min_delay;
 340         }
 341
 342         if (ironlake_set_drps(dev, new_delay))
 343                 dev_priv->ips.cur_delay = new_delay;
 344
 345         spin_unlock_irqrestore(&mchdev_lock, flags);
 346
 347         return;
 348 }
 349
 350 static void notify_ring(struct drm_device *dev,
 351                         struct intel_ring_buffer *ring)
 352 {
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354
 355         if (ring->obj == NULL)
 356                 return;
 357
 358         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 359
 360         wake_up_all(&ring->irq_queue);
 361         if (i915_enable_hangcheck) {
 362                 dev_priv->gpu_error.hangcheck_count = 0;
 363                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 364                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 365         }
 366 }
 367
 368 static void gen6_pm_rps_work(struct work_struct *work)
 369 {
 370         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 371                                                     rps.work);
 372         u32 pm_iir, pm_imr;
 373         u8 new_delay;
 374
 375         spin_lock_irq(&dev_priv->rps.lock);
 376         pm_iir = dev_priv->rps.pm_iir;
 377         dev_priv->rps.pm_iir = 0;
 378         pm_imr = I915_READ(GEN6_PMIMR);
 379         I915_WRITE(GEN6_PMIMR, 0);
 380         spin_unlock_irq(&dev_priv->rps.lock);
 381
 382         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 383                 return;
 384
 385         mutex_lock(&dev_priv->rps.hw_lock);
 386
 387         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 388                 new_delay = dev_priv->rps.cur_delay + 1;
 389         else
 390                 new_delay = dev_priv->rps.cur_delay - 1;
 391
 392         /* sysfs frequency interfaces may have snuck in while servicing the
 393          * interrupt
 394          */
 395         if (!(new_delay > dev_priv->rps.max_delay ||
 396               new_delay < dev_priv->rps.min_delay)) {
 397                 gen6_set_rps(dev_priv->dev, new_delay);
 398         }
 399
 400         mutex_unlock(&dev_priv->rps.hw_lock);
 401 }
 402
 403
 404 /**
 405  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 406  * occurred.
 407  * @work: workqueue struct
 408  *
 409  * Doesn't actually do anything except notify userspace. As a consequence of
 410  * this event, userspace should try to remap the bad rows since statistically
 411  * it is likely the same row is more likely to go bad again.
 412  */
 413 static void ivybridge_parity_work(struct work_struct *work)
 414 {
 415         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 416                                                     l3_parity.error_work);
 417         u32 error_status, row, bank, subbank;
 418         char *parity_event[5];
 419         uint32_t misccpctl;
 420         unsigned long flags;
 421
 422         /* We must turn off DOP level clock gating to access the L3 registers.
 423          * In order to prevent a get/put style interface, acquire struct mutex
 424          * any time we access those registers.
 425          */
 426         mutex_lock(&dev_priv->dev->struct_mutex);
 427
 428         misccpctl = I915_READ(GEN7_MISCCPCTL);
 429         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 430         POSTING_READ(GEN7_MISCCPCTL);
 431
 432         error_status = I915_READ(GEN7_L3CDERRST1);
 433         row = GEN7_PARITY_ERROR_ROW(error_status);
 434         bank = GEN7_PARITY_ERROR_BANK(error_status);
 435         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 436
 437         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 438                                     GEN7_L3CDERRST1_ENABLE);
 439         POSTING_READ(GEN7_L3CDERRST1);
 440
 441         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 442
 443         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 444         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 445         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 446         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 447
 448         mutex_unlock(&dev_priv->dev->struct_mutex);
 449
 450         parity_event[0] = "L3_PARITY_ERROR=1";
 451         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 452         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 453         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 454         parity_event[4] = NULL;
 455
 456         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 457                            KOBJ_CHANGE, parity_event);
 458
 459         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 460                   row, bank, subbank);
 461
 462         kfree(parity_event[3]);
 463         kfree(parity_event[2]);
 464         kfree(parity_event[1]);
 465 }
 466
 467 static void ivybridge_handle_parity_error(struct drm_device *dev)
 468 {
 469         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 470         unsigned long flags;
 471
 472         if (!HAS_L3_GPU_CACHE(dev))
 473                 return;
 474
 475         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 476         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 477         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 478         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 479
 480         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 481 }
 482
 483 static void snb_gt_irq_handler(struct drm_device *dev,
 484                                struct drm_i915_private *dev_priv,
 485                                u32 gt_iir)
 486 {
 487
 488         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 489                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 490                 notify_ring(dev, &dev_priv->ring[RCS]);
 491         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 492                 notify_ring(dev, &dev_priv->ring[VCS]);
 493         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 494                 notify_ring(dev, &dev_priv->ring[BCS]);
 495
 496         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 497                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 498                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 499                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 500                 i915_handle_error(dev, false);
 501         }
 502
 503         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 504                 ivybridge_handle_parity_error(dev);
 505 }
 506
 507 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 508                                 u32 pm_iir)
 509 {
 510         unsigned long flags;
 511
 512         /*
 513          * IIR bits should never already be set because IMR should
 514          * prevent an interrupt from being shown in IIR. The warning
 515          * displays a case where we've unsafely cleared
 516          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 517          * type is not a problem, it displays a problem in the logic.
 518          *
 519          * The mask bit in IMR is cleared by dev_priv->rps.work.
 520          */
 521
 522         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 523         dev_priv->rps.pm_iir |= pm_iir;
 524         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 525         POSTING_READ(GEN6_PMIMR);
 526         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 527
 528         queue_work(dev_priv->wq, &dev_priv->rps.work);
 529 }
 530
 531 static void gmbus_irq_handler(struct drm_device *dev)
 532 {
 533         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 534
 535         wake_up_all(&dev_priv->gmbus_wait_queue);
 536 }
 537
 538 static void dp_aux_irq_handler(struct drm_device *dev)
 539 {
 540         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 541
 542         wake_up_all(&dev_priv->gmbus_wait_queue);
 543 }
 544
 545 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 546 {
 547         struct drm_device *dev = (struct drm_device *) arg;
 548         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 549         u32 iir, gt_iir, pm_iir;
 550         irqreturn_t ret = IRQ_NONE;
 551         unsigned long irqflags;
 552         int pipe;
 553         u32 pipe_stats[I915_MAX_PIPES];
 554
 555         atomic_inc(&dev_priv->irq_received);
 556
 557         while (true) {
 558                 iir = I915_READ(VLV_IIR);
 559                 gt_iir = I915_READ(GTIIR);
 560                 pm_iir = I915_READ(GEN6_PMIIR);
 561
 562                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 563                         goto out;
 564
 565                 ret = IRQ_HANDLED;
 566
 567                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 568
 569                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 570                 for_each_pipe(pipe) {
 571                         int reg = PIPESTAT(pipe);
 572                         pipe_stats[pipe] = I915_READ(reg);
 573
 574                         /*
 575                          * Clear the PIPE*STAT regs before the IIR
 576                          */
 577                         if (pipe_stats[pipe] & 0x8000ffff) {
 578                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 579                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 580                                                          pipe_name(pipe));
 581                                 I915_WRITE(reg, pipe_stats[pipe]);
 582                         }
 583                 }
 584                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 585
 586                 for_each_pipe(pipe) {
 587                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 588                                 drm_handle_vblank(dev, pipe);
 589
 590                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 591                                 intel_prepare_page_flip(dev, pipe);
 592                                 intel_finish_page_flip(dev, pipe);
 593                         }
 594                 }
 595
 596                 /* Consume port.  Then clear IIR or we'll miss events */
 597                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 598                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 599
 600                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 601                                          hotplug_status);
 602                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 603                                 queue_work(dev_priv->wq,
 604                                            &dev_priv->hotplug_work);
 605
 606                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 607                         I915_READ(PORT_HOTPLUG_STAT);
 608                 }
 609
 610                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 611                         gmbus_irq_handler(dev);
 612
 613                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 614                         gen6_queue_rps_work(dev_priv, pm_iir);
 615
 616                 I915_WRITE(GTIIR, gt_iir);
 617                 I915_WRITE(GEN6_PMIIR, pm_iir);
 618                 I915_WRITE(VLV_IIR, iir);
 619         }
 620
 621 out:
 622         return ret;
 623 }
 624
 625 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 626 {
 627         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 628         int pipe;
 629
 630         if (pch_iir & SDE_HOTPLUG_MASK)
 631                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 632
 633         if (pch_iir & SDE_AUDIO_POWER_MASK)
 634                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 635                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 636                                  SDE_AUDIO_POWER_SHIFT);
 637
 638         if (pch_iir & SDE_AUX_MASK)
 639                 dp_aux_irq_handler(dev);
 640
 641         if (pch_iir & SDE_GMBUS)
 642                 gmbus_irq_handler(dev);
 643
 644         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 645                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 646
 647         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 648                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 649
 650         if (pch_iir & SDE_POISON)
 651                 DRM_ERROR("PCH poison interrupt\n");
 652
 653         if (pch_iir & SDE_FDI_MASK)
 654                 for_each_pipe(pipe)
 655                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 656                                          pipe_name(pipe),
 657                                          I915_READ(FDI_RX_IIR(pipe)));
 658
 659         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 660                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 661
 662         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 663                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 664
 665         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 666                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 667         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 668                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 669 }
 670
 671 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 672 {
 673         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 674         int pipe;
 675
 676         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 677                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 678
 679         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 680                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 681                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 682                                  SDE_AUDIO_POWER_SHIFT_CPT);
 683
 684         if (pch_iir & SDE_AUX_MASK_CPT)
 685                 dp_aux_irq_handler(dev);
 686
 687         if (pch_iir & SDE_GMBUS_CPT)
 688                 gmbus_irq_handler(dev);
 689
 690         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 691                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 692
 693         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 694                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 695
 696         if (pch_iir & SDE_FDI_MASK_CPT)
 697                 for_each_pipe(pipe)
 698                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 699                                          pipe_name(pipe),
 700                                          I915_READ(FDI_RX_IIR(pipe)));
 701 }
 702
 703 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 704 {
 705         struct drm_device *dev = (struct drm_device *) arg;
 706         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 707         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 708         irqreturn_t ret = IRQ_NONE;
 709         int i;
 710
 711         atomic_inc(&dev_priv->irq_received);
 712
 713         /* disable master interrupt before clearing iir  */
 714         de_ier = I915_READ(DEIER);
 715         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 716
 717         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 718          * interrupts will will be stored on its back queue, and then we'll be
 719          * able to process them after we restore SDEIER (as soon as we restore
 720          * it, we'll get an interrupt if SDEIIR still has something to process
 721          * due to its back queue). */
 722         sde_ier = I915_READ(SDEIER);
 723         I915_WRITE(SDEIER, 0);
 724         POSTING_READ(SDEIER);
 725
 726         gt_iir = I915_READ(GTIIR);
 727         if (gt_iir) {
 728                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 729                 I915_WRITE(GTIIR, gt_iir);
 730                 ret = IRQ_HANDLED;
 731         }
 732
 733         de_iir = I915_READ(DEIIR);
 734         if (de_iir) {
 735                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 736                         dp_aux_irq_handler(dev);
 737
 738                 if (de_iir & DE_GSE_IVB)
 739                         intel_opregion_gse_intr(dev);
 740
 741                 for (i = 0; i < 3; i++) {
 742                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 743                                 drm_handle_vblank(dev, i);
 744                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 745                                 intel_prepare_page_flip(dev, i);
 746                                 intel_finish_page_flip_plane(dev, i);
 747                         }
 748                 }
 749
 750                 /* check event from PCH */
 751                 if (de_iir & DE_PCH_EVENT_IVB) {
 752                         u32 pch_iir = I915_READ(SDEIIR);
 753
 754                         cpt_irq_handler(dev, pch_iir);
 755
 756                         /* clear PCH hotplug event before clear CPU irq */
 757                         I915_WRITE(SDEIIR, pch_iir);
 758                 }
 759
 760                 I915_WRITE(DEIIR, de_iir);
 761                 ret = IRQ_HANDLED;
 762         }
 763
 764         pm_iir = I915_READ(GEN6_PMIIR);
 765         if (pm_iir) {
 766                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 767                         gen6_queue_rps_work(dev_priv, pm_iir);
 768                 I915_WRITE(GEN6_PMIIR, pm_iir);
 769                 ret = IRQ_HANDLED;
 770         }
 771
 772         I915_WRITE(DEIER, de_ier);
 773         POSTING_READ(DEIER);
 774         I915_WRITE(SDEIER, sde_ier);
 775         POSTING_READ(SDEIER);
 776
 777         return ret;
 778 }
 779
 780 static void ilk_gt_irq_handler(struct drm_device *dev,
 781                                struct drm_i915_private *dev_priv,
 782                                u32 gt_iir)
 783 {
 784         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 785                 notify_ring(dev, &dev_priv->ring[RCS]);
 786         if (gt_iir & GT_BSD_USER_INTERRUPT)
 787                 notify_ring(dev, &dev_priv->ring[VCS]);
 788 }
 789
 790 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 791 {
 792         struct drm_device *dev = (struct drm_device *) arg;
 793         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 794         int ret = IRQ_NONE;
 795         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 796
 797         atomic_inc(&dev_priv->irq_received);
 798
 799         /* disable master interrupt before clearing iir  */
 800         de_ier = I915_READ(DEIER);
 801         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 802         POSTING_READ(DEIER);
 803
 804         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 805          * interrupts will will be stored on its back queue, and then we'll be
 806          * able to process them after we restore SDEIER (as soon as we restore
 807          * it, we'll get an interrupt if SDEIIR still has something to process
 808          * due to its back queue). */
 809         sde_ier = I915_READ(SDEIER);
 810         I915_WRITE(SDEIER, 0);
 811         POSTING_READ(SDEIER);
 812
 813         de_iir = I915_READ(DEIIR);
 814         gt_iir = I915_READ(GTIIR);
 815         pm_iir = I915_READ(GEN6_PMIIR);
 816
 817         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 818                 goto done;
 819
 820         ret = IRQ_HANDLED;
 821
 822         if (IS_GEN5(dev))
 823                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 824         else
 825                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 826
 827         if (de_iir & DE_AUX_CHANNEL_A)
 828                 dp_aux_irq_handler(dev);
 829
 830         if (de_iir & DE_GSE)
 831                 intel_opregion_gse_intr(dev);
 832
 833         if (de_iir & DE_PIPEA_VBLANK)
 834                 drm_handle_vblank(dev, 0);
 835
 836         if (de_iir & DE_PIPEB_VBLANK)
 837                 drm_handle_vblank(dev, 1);
 838
 839         if (de_iir & DE_PLANEA_FLIP_DONE) {
 840                 intel_prepare_page_flip(dev, 0);
 841                 intel_finish_page_flip_plane(dev, 0);
 842         }
 843
 844         if (de_iir & DE_PLANEB_FLIP_DONE) {
 845                 intel_prepare_page_flip(dev, 1);
 846                 intel_finish_page_flip_plane(dev, 1);
 847         }
 848
 849         /* check event from PCH */
 850         if (de_iir & DE_PCH_EVENT) {
 851                 u32 pch_iir = I915_READ(SDEIIR);
 852
 853                 if (HAS_PCH_CPT(dev))
 854                         cpt_irq_handler(dev, pch_iir);
 855                 else
 856                         ibx_irq_handler(dev, pch_iir);
 857
 858                 /* should clear PCH hotplug event before clear CPU irq */
 859                 I915_WRITE(SDEIIR, pch_iir);
 860         }
 861
 862         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 863                 ironlake_handle_rps_change(dev);
 864
 865         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 866                 gen6_queue_rps_work(dev_priv, pm_iir);
 867
 868         I915_WRITE(GTIIR, gt_iir);
 869         I915_WRITE(DEIIR, de_iir);
 870         I915_WRITE(GEN6_PMIIR, pm_iir);
 871
 872 done:
 873         I915_WRITE(DEIER, de_ier);
 874         POSTING_READ(DEIER);
 875         I915_WRITE(SDEIER, sde_ier);
 876         POSTING_READ(SDEIER);
 877
 878         return ret;
 879 }
 880
 881 /**
 882  * i915_error_work_func - do process context error handling work
 883  * @work: work struct
 884  *
 885  * Fire an error uevent so userspace can see that a hang or error
 886  * was detected.
 887  */
 888 static void i915_error_work_func(struct work_struct *work)
 889 {
 890         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
 891                                                     work);
 892         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
 893                                                     gpu_error);
 894         struct drm_device *dev = dev_priv->dev;
 895         struct intel_ring_buffer *ring;
 896         char *error_event[] = { "ERROR=1", NULL };
 897         char *reset_event[] = { "RESET=1", NULL };
 898         char *reset_done_event[] = { "ERROR=0", NULL };
 899         int i, ret;
 900
 901         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 902
 903         /*
 904          * Note that there's only one work item which does gpu resets, so we
 905          * need not worry about concurrent gpu resets potentially incrementing
 906          * error->reset_counter twice. We only need to take care of another
 907          * racing irq/hangcheck declaring the gpu dead for a second time. A
 908          * quick check for that is good enough: schedule_work ensures the
 909          * correct ordering between hang detection and this work item, and since
 910          * the reset in-progress bit is only ever set by code outside of this
 911          * work we don't need to worry about any other races.
 912          */
 913         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 914                 DRM_DEBUG_DRIVER("resetting chip\n");
 915                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
 916                                    reset_event);
 917
 918                 ret = i915_reset(dev);
 919
 920                 if (ret == 0) {
 921                         /*
 922                          * After all the gem state is reset, increment the reset
 923                          * counter and wake up everyone waiting for the reset to
 924                          * complete.
 925                          *
 926                          * Since unlock operations are a one-sided barrier only,
 927                          * we need to insert a barrier here to order any seqno
 928                          * updates before
 929                          * the counter increment.
 930                          */
 931                         smp_mb__before_atomic_inc();
 932                         atomic_inc(&dev_priv->gpu_error.reset_counter);
 933
 934                         kobject_uevent_env(&dev->primary->kdev.kobj,
 935                                            KOBJ_CHANGE, reset_done_event);
 936                 } else {
 937                         atomic_set(&error->reset_counter, I915_WEDGED);
 938                 }
 939
 940                 for_each_ring(ring, dev_priv, i)
 941                         wake_up_all(&ring->irq_queue);
 942
 943                 intel_display_handle_reset(dev);
 944
 945                 wake_up_all(&dev_priv->gpu_error.reset_queue);
 946         }
 947 }
 948
 949 /* NB: please notice the memset */
 950 static void i915_get_extra_instdone(struct drm_device *dev,
 951                                     uint32_t *instdone)
 952 {
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 955
 956         switch(INTEL_INFO(dev)->gen) {
 957         case 2:
 958         case 3:
 959                 instdone[0] = I915_READ(INSTDONE);
 960                 break;
 961         case 4:
 962         case 5:
 963         case 6:
 964                 instdone[0] = I915_READ(INSTDONE_I965);
 965                 instdone[1] = I915_READ(INSTDONE1);
 966                 break;
 967         default:
 968                 WARN_ONCE(1, "Unsupported platform\n");
 969         case 7:
 970                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 971                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 972                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 973                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 974                 break;
 975         }
 976 }
 977
 978 #ifdef CONFIG_DEBUG_FS
 979 static struct drm_i915_error_object *
 980 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
 981                                struct drm_i915_gem_object *src,
 982                                const int num_pages)
 983 {
 984         struct drm_i915_error_object *dst;
 985         int i;
 986         u32 reloc_offset;
 987
 988         if (src == NULL || src->pages == NULL)
 989                 return NULL;
 990
 991         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
 992         if (dst == NULL)
 993                 return NULL;
 994
 995         reloc_offset = src->gtt_offset;
 996         for (i = 0; i < num_pages; i++) {
 997                 unsigned long flags;
 998                 void *d;
 999
1000                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1001                 if (d == NULL)
1002                         goto unwind;
1003
1004                 local_irq_save(flags);
1005                 if (reloc_offset < dev_priv->gtt.mappable_end &&
1006                     src->has_global_gtt_mapping) {
1007                         void __iomem *s;
1008
1009                         /* Simply ignore tiling or any overlapping fence.
1010                          * It's part of the error state, and this hopefully
1011                          * captures what the GPU read.
1012                          */
1013
1014                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1015                                                      reloc_offset);
1016                         memcpy_fromio(d, s, PAGE_SIZE);
1017                         io_mapping_unmap_atomic(s);
1018                 } else if (src->stolen) {
1019                         unsigned long offset;
1020
1021                         offset = dev_priv->mm.stolen_base;
1022                         offset += src->stolen->start;
1023                         offset += i << PAGE_SHIFT;
1024
1025                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1026                 } else {
1027                         struct page *page;
1028                         void *s;
1029
1030                         page = i915_gem_object_get_page(src, i);
1031
1032                         drm_clflush_pages(&page, 1);
1033
1034                         s = kmap_atomic(page);
1035                         memcpy(d, s, PAGE_SIZE);
1036                         kunmap_atomic(s);
1037
1038                         drm_clflush_pages(&page, 1);
1039                 }
1040                 local_irq_restore(flags);
1041
1042                 dst->pages[i] = d;
1043
1044                 reloc_offset += PAGE_SIZE;
1045         }
1046         dst->page_count = num_pages;
1047         dst->gtt_offset = src->gtt_offset;
1048
1049         return dst;
1050
1051 unwind:
1052         while (i--)
1053                 kfree(dst->pages[i]);
1054         kfree(dst);
1055         return NULL;
1056 }
1057 #define i915_error_object_create(dev_priv, src) \
1058         i915_error_object_create_sized((dev_priv), (src), \
1059                                        (src)->base.size>>PAGE_SHIFT)
1060
1061 static void
1062 i915_error_object_free(struct drm_i915_error_object *obj)
1063 {
1064         int page;
1065
1066         if (obj == NULL)
1067                 return;
1068
1069         for (page = 0; page < obj->page_count; page++)
1070                 kfree(obj->pages[page]);
1071
1072         kfree(obj);
1073 }
1074
1075 void
1076 i915_error_state_free(struct kref *error_ref)
1077 {
1078         struct drm_i915_error_state *error = container_of(error_ref,
1079                                                           typeof(*error), ref);
1080         int i;
1081
1082         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1083                 i915_error_object_free(error->ring[i].batchbuffer);
1084                 i915_error_object_free(error->ring[i].ringbuffer);
1085                 kfree(error->ring[i].requests);
1086         }
1087
1088         kfree(error->active_bo);
1089         kfree(error->overlay);
1090         kfree(error);
1091 }
1092 static void capture_bo(struct drm_i915_error_buffer *err,
1093                        struct drm_i915_gem_object *obj)
1094 {
1095         err->size = obj->base.size;
1096         err->name = obj->base.name;
1097         err->rseqno = obj->last_read_seqno;
1098         err->wseqno = obj->last_write_seqno;
1099         err->gtt_offset = obj->gtt_offset;
1100         err->read_domains = obj->base.read_domains;
1101         err->write_domain = obj->base.write_domain;
1102         err->fence_reg = obj->fence_reg;
1103         err->pinned = 0;
1104         if (obj->pin_count > 0)
1105                 err->pinned = 1;
1106         if (obj->user_pin_count > 0)
1107                 err->pinned = -1;
1108         err->tiling = obj->tiling_mode;
1109         err->dirty = obj->dirty;
1110         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1111         err->ring = obj->ring ? obj->ring->id : -1;
1112         err->cache_level = obj->cache_level;
1113 }
1114
1115 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1116                              int count, struct list_head *head)
1117 {
1118         struct drm_i915_gem_object *obj;
1119         int i = 0;
1120
1121         list_for_each_entry(obj, head, mm_list) {
1122                 capture_bo(err++, obj);
1123                 if (++i == count)
1124                         break;
1125         }
1126
1127         return i;
1128 }
1129
1130 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1131                              int count, struct list_head *head)
1132 {
1133         struct drm_i915_gem_object *obj;
1134         int i = 0;
1135
1136         list_for_each_entry(obj, head, gtt_list) {
1137                 if (obj->pin_count == 0)
1138                         continue;
1139
1140                 capture_bo(err++, obj);
1141                 if (++i == count)
1142                         break;
1143         }
1144
1145         return i;
1146 }
1147
1148 static void i915_gem_record_fences(struct drm_device *dev,
1149                                    struct drm_i915_error_state *error)
1150 {
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         int i;
1153
1154         /* Fences */
1155         switch (INTEL_INFO(dev)->gen) {
1156         case 7:
1157         case 6:
1158                 for (i = 0; i < 16; i++)
1159                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1160                 break;
1161         case 5:
1162         case 4:
1163                 for (i = 0; i < 16; i++)
1164                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1165                 break;
1166         case 3:
1167                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1168                         for (i = 0; i < 8; i++)
1169                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1170         case 2:
1171                 for (i = 0; i < 8; i++)
1172                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1173                 break;
1174
1175         default:
1176                 BUG();
1177         }
1178 }
1179
1180 static struct drm_i915_error_object *
1181 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1182                              struct intel_ring_buffer *ring)
1183 {
1184         struct drm_i915_gem_object *obj;
1185         u32 seqno;
1186
1187         if (!ring->get_seqno)
1188                 return NULL;
1189
1190         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1191                 u32 acthd = I915_READ(ACTHD);
1192
1193                 if (WARN_ON(ring->id != RCS))
1194                         return NULL;
1195
1196                 obj = ring->private;
1197                 if (acthd >= obj->gtt_offset &&
1198                     acthd < obj->gtt_offset + obj->base.size)
1199                         return i915_error_object_create(dev_priv, obj);
1200         }
1201
1202         seqno = ring->get_seqno(ring, false);
1203         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1204                 if (obj->ring != ring)
1205                         continue;
1206
1207                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1208                         continue;
1209
1210                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1211                         continue;
1212
1213                 /* We need to copy these to an anonymous buffer as the simplest
1214                  * method to avoid being overwritten by userspace.
1215                  */
1216                 return i915_error_object_create(dev_priv, obj);
1217         }
1218
1219         return NULL;
1220 }
1221
1222 static void i915_record_ring_state(struct drm_device *dev,
1223                                    struct drm_i915_error_state *error,
1224                                    struct intel_ring_buffer *ring)
1225 {
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227
1228         if (INTEL_INFO(dev)->gen >= 6) {
1229                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1230                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1231                 error->semaphore_mboxes[ring->id][0]
1232                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1233                 error->semaphore_mboxes[ring->id][1]
1234                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1235                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1236                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1237         }
1238
1239         if (INTEL_INFO(dev)->gen >= 4) {
1240                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1241                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1242                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1243                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1244                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1245                 if (ring->id == RCS)
1246                         error->bbaddr = I915_READ64(BB_ADDR);
1247         } else {
1248                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1249                 error->ipeir[ring->id] = I915_READ(IPEIR);
1250                 error->ipehr[ring->id] = I915_READ(IPEHR);
1251                 error->instdone[ring->id] = I915_READ(INSTDONE);
1252         }
1253
1254         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1255         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1256         error->seqno[ring->id] = ring->get_seqno(ring, false);
1257         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1258         error->head[ring->id] = I915_READ_HEAD(ring);
1259         error->tail[ring->id] = I915_READ_TAIL(ring);
1260         error->ctl[ring->id] = I915_READ_CTL(ring);
1261
1262         error->cpu_ring_head[ring->id] = ring->head;
1263         error->cpu_ring_tail[ring->id] = ring->tail;
1264 }
1265
1266
1267 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1268                                            struct drm_i915_error_state *error,
1269                                            struct drm_i915_error_ring *ering)
1270 {
1271         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1272         struct drm_i915_gem_object *obj;
1273
1274         /* Currently render ring is the only HW context user */
1275         if (ring->id != RCS || !error->ccid)
1276                 return;
1277
1278         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1279                 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1280                         ering->ctx = i915_error_object_create_sized(dev_priv,
1281                                                                     obj, 1);
1282                 }
1283         }
1284 }
1285
1286 static void i915_gem_record_rings(struct drm_device *dev,
1287                                   struct drm_i915_error_state *error)
1288 {
1289         struct drm_i915_private *dev_priv = dev->dev_private;
1290         struct intel_ring_buffer *ring;
1291         struct drm_i915_gem_request *request;
1292         int i, count;
1293
1294         for_each_ring(ring, dev_priv, i) {
1295                 i915_record_ring_state(dev, error, ring);
1296
1297                 error->ring[i].batchbuffer =
1298                         i915_error_first_batchbuffer(dev_priv, ring);
1299
1300                 error->ring[i].ringbuffer =
1301                         i915_error_object_create(dev_priv, ring->obj);
1302
1303
1304                 i915_gem_record_active_context(ring, error, &error->ring[i]);
1305
1306                 count = 0;
1307                 list_for_each_entry(request, &ring->request_list, list)
1308                         count++;
1309
1310                 error->ring[i].num_requests = count;
1311                 error->ring[i].requests =
1312                         kmalloc(count*sizeof(struct drm_i915_error_request),
1313                                 GFP_ATOMIC);
1314                 if (error->ring[i].requests == NULL) {
1315                         error->ring[i].num_requests = 0;
1316                         continue;
1317                 }
1318
1319                 count = 0;
1320                 list_for_each_entry(request, &ring->request_list, list) {
1321                         struct drm_i915_error_request *erq;
1322
1323                         erq = &error->ring[i].requests[count++];
1324                         erq->seqno = request->seqno;
1325                         erq->jiffies = request->emitted_jiffies;
1326                         erq->tail = request->tail;
1327                 }
1328         }
1329 }
1330
1331 /**
1332  * i915_capture_error_state - capture an error record for later analysis
1333  * @dev: drm device
1334  *
1335  * Should be called when an error is detected (either a hang or an error
1336  * interrupt) to capture error state from the time of the error.  Fills
1337  * out a structure which becomes available in debugfs for user level tools
1338  * to pick up.
1339  */
1340 static void i915_capture_error_state(struct drm_device *dev)
1341 {
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         struct drm_i915_gem_object *obj;
1344         struct drm_i915_error_state *error;
1345         unsigned long flags;
1346         int i, pipe;
1347
1348         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1349         error = dev_priv->gpu_error.first_error;
1350         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1351         if (error)
1352                 return;
1353
1354         /* Account for pipe specific data like PIPE*STAT */
1355         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1356         if (!error) {
1357                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1358                 return;
1359         }
1360
1361         DRM_INFO("capturing error event; look for more information in "
1362                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1363                  dev->primary->index);
1364
1365         kref_init(&error->ref);
1366         error->eir = I915_READ(EIR);
1367         error->pgtbl_er = I915_READ(PGTBL_ER);
1368         if (HAS_HW_CONTEXTS(dev))
1369                 error->ccid = I915_READ(CCID);
1370
1371         if (HAS_PCH_SPLIT(dev))
1372                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1373         else if (IS_VALLEYVIEW(dev))
1374                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1375         else if (IS_GEN2(dev))
1376                 error->ier = I915_READ16(IER);
1377         else
1378                 error->ier = I915_READ(IER);
1379
1380         if (INTEL_INFO(dev)->gen >= 6)
1381                 error->derrmr = I915_READ(DERRMR);
1382
1383         if (IS_VALLEYVIEW(dev))
1384                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1385         else if (INTEL_INFO(dev)->gen >= 7)
1386                 error->forcewake = I915_READ(FORCEWAKE_MT);
1387         else if (INTEL_INFO(dev)->gen == 6)
1388                 error->forcewake = I915_READ(FORCEWAKE);
1389
1390         if (!HAS_PCH_SPLIT(dev))
1391                 for_each_pipe(pipe)
1392                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1393
1394         if (INTEL_INFO(dev)->gen >= 6) {
1395                 error->error = I915_READ(ERROR_GEN6);
1396                 error->done_reg = I915_READ(DONE_REG);
1397         }
1398
1399         if (INTEL_INFO(dev)->gen == 7)
1400                 error->err_int = I915_READ(GEN7_ERR_INT);
1401
1402         i915_get_extra_instdone(dev, error->extra_instdone);
1403
1404         i915_gem_record_fences(dev, error);
1405         i915_gem_record_rings(dev, error);
1406
1407         /* Record buffers on the active and pinned lists. */
1408         error->active_bo = NULL;
1409         error->pinned_bo = NULL;
1410
1411         i = 0;
1412         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1413                 i++;
1414         error->active_bo_count = i;
1415         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1416                 if (obj->pin_count)
1417                         i++;
1418         error->pinned_bo_count = i - error->active_bo_count;
1419
1420         error->active_bo = NULL;
1421         error->pinned_bo = NULL;
1422         if (i) {
1423                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1424                                            GFP_ATOMIC);
1425                 if (error->active_bo)
1426                         error->pinned_bo =
1427                                 error->active_bo + error->active_bo_count;
1428         }
1429
1430         if (error->active_bo)
1431                 error->active_bo_count =
1432                         capture_active_bo(error->active_bo,
1433                                           error->active_bo_count,
1434                                           &dev_priv->mm.active_list);
1435
1436         if (error->pinned_bo)
1437                 error->pinned_bo_count =
1438                         capture_pinned_bo(error->pinned_bo,
1439                                           error->pinned_bo_count,
1440                                           &dev_priv->mm.bound_list);
1441
1442         do_gettimeofday(&error->time);
1443
1444         error->overlay = intel_overlay_capture_error_state(dev);
1445         error->display = intel_display_capture_error_state(dev);
1446
1447         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1448         if (dev_priv->gpu_error.first_error == NULL) {
1449                 dev_priv->gpu_error.first_error = error;
1450                 error = NULL;
1451         }
1452         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1453
1454         if (error)
1455                 i915_error_state_free(&error->ref);
1456 }
1457
1458 void i915_destroy_error_state(struct drm_device *dev)
1459 {
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461         struct drm_i915_error_state *error;
1462         unsigned long flags;
1463
1464         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1465         error = dev_priv->gpu_error.first_error;
1466         dev_priv->gpu_error.first_error = NULL;
1467         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1468
1469         if (error)
1470                 kref_put(&error->ref, i915_error_state_free);
1471 }
1472 #else
1473 #define i915_capture_error_state(x)
1474 #endif
1475
1476 static void i915_report_and_clear_eir(struct drm_device *dev)
1477 {
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479         uint32_t instdone[I915_NUM_INSTDONE_REG];
1480         u32 eir = I915_READ(EIR);
1481         int pipe, i;
1482
1483         if (!eir)
1484                 return;
1485
1486         pr_err("render error detected, EIR: 0x%08x\n", eir);
1487
1488         i915_get_extra_instdone(dev, instdone);
1489
1490         if (IS_G4X(dev)) {
1491                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1492                         u32 ipeir = I915_READ(IPEIR_I965);
1493
1494                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1495                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1496                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1497                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1498                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1499                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1500                         I915_WRITE(IPEIR_I965, ipeir);
1501                         POSTING_READ(IPEIR_I965);
1502                 }
1503                 if (eir & GM45_ERROR_PAGE_TABLE) {
1504                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1505                         pr_err("page table error\n");
1506                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1507                         I915_WRITE(PGTBL_ER, pgtbl_err);
1508                         POSTING_READ(PGTBL_ER);
1509                 }
1510         }
1511
1512         if (!IS_GEN2(dev)) {
1513                 if (eir & I915_ERROR_PAGE_TABLE) {
1514                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1515                         pr_err("page table error\n");
1516                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1517                         I915_WRITE(PGTBL_ER, pgtbl_err);
1518                         POSTING_READ(PGTBL_ER);
1519                 }
1520         }
1521
1522         if (eir & I915_ERROR_MEMORY_REFRESH) {
1523                 pr_err("memory refresh error:\n");
1524                 for_each_pipe(pipe)
1525                         pr_err("pipe %c stat: 0x%08x\n",
1526                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1527                 /* pipestat has already been acked */
1528         }
1529         if (eir & I915_ERROR_INSTRUCTION) {
1530                 pr_err("instruction error\n");
1531                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1532                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1533                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1534                 if (INTEL_INFO(dev)->gen < 4) {
1535                         u32 ipeir = I915_READ(IPEIR);
1536
1537                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1538                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1539                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1540                         I915_WRITE(IPEIR, ipeir);
1541                         POSTING_READ(IPEIR);
1542                 } else {
1543                         u32 ipeir = I915_READ(IPEIR_I965);
1544
1545                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1546                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1547                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1548                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1549                         I915_WRITE(IPEIR_I965, ipeir);
1550                         POSTING_READ(IPEIR_I965);
1551                 }
1552         }
1553
1554         I915_WRITE(EIR, eir);
1555         POSTING_READ(EIR);
1556         eir = I915_READ(EIR);
1557         if (eir) {
1558                 /*
1559                  * some errors might have become stuck,
1560                  * mask them.
1561                  */
1562                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1563                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1564                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1565         }
1566 }
1567
1568 /**
1569  * i915_handle_error - handle an error interrupt
1570  * @dev: drm device
1571  *
1572  * Do some basic checking of regsiter state at error interrupt time and
1573  * dump it to the syslog.  Also call i915_capture_error_state() to make
1574  * sure we get a record and make it available in debugfs.  Fire a uevent
1575  * so userspace knows something bad happened (should trigger collection
1576  * of a ring dump etc.).
1577  */
1578 void i915_handle_error(struct drm_device *dev, bool wedged)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         struct intel_ring_buffer *ring;
1582         int i;
1583
1584         i915_capture_error_state(dev);
1585         i915_report_and_clear_eir(dev);
1586
1587         if (wedged) {
1588                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1589                                 &dev_priv->gpu_error.reset_counter);
1590
1591                 /*
1592                  * Wakeup waiting processes so that the reset work item
1593                  * doesn't deadlock trying to grab various locks.
1594                  */
1595                 for_each_ring(ring, dev_priv, i)
1596                         wake_up_all(&ring->irq_queue);
1597         }
1598
1599         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1600 }
1601
1602 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1603 {
1604         drm_i915_private_t *dev_priv = dev->dev_private;
1605         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1607         struct drm_i915_gem_object *obj;
1608         struct intel_unpin_work *work;
1609         unsigned long flags;
1610         bool stall_detected;
1611
1612         /* Ignore early vblank irqs */
1613         if (intel_crtc == NULL)
1614                 return;
1615
1616         spin_lock_irqsave(&dev->event_lock, flags);
1617         work = intel_crtc->unpin_work;
1618
1619         if (work == NULL ||
1620             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1621             !work->enable_stall_check) {
1622                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1623                 spin_unlock_irqrestore(&dev->event_lock, flags);
1624                 return;
1625         }
1626
1627         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1628         obj = work->pending_flip_obj;
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 int dspsurf = DSPSURF(intel_crtc->plane);
1631                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1632                                         obj->gtt_offset;
1633         } else {
1634                 int dspaddr = DSPADDR(intel_crtc->plane);
1635                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1636                                                         crtc->y * crtc->fb->pitches[0] +
1637                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1638         }
1639
1640         spin_unlock_irqrestore(&dev->event_lock, flags);
1641
1642         if (stall_detected) {
1643                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1644                 intel_prepare_page_flip(dev, intel_crtc->plane);
1645         }
1646 }
1647
1648 /* Called from drm generic code, passed 'crtc' which
1649  * we use as a pipe index
1650  */
1651 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1652 {
1653         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1654         unsigned long irqflags;
1655
1656         if (!i915_pipe_enabled(dev, pipe))
1657                 return -EINVAL;
1658
1659         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1660         if (INTEL_INFO(dev)->gen >= 4)
1661                 i915_enable_pipestat(dev_priv, pipe,
1662                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1663         else
1664                 i915_enable_pipestat(dev_priv, pipe,
1665                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1666
1667         /* maintain vblank delivery even in deep C-states */
1668         if (dev_priv->info->gen == 3)
1669                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1670         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1671
1672         return 0;
1673 }
1674
1675 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1676 {
1677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1678         unsigned long irqflags;
1679
1680         if (!i915_pipe_enabled(dev, pipe))
1681                 return -EINVAL;
1682
1683         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1684         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1685                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1686         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1687
1688         return 0;
1689 }
1690
1691 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1692 {
1693         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1694         unsigned long irqflags;
1695
1696         if (!i915_pipe_enabled(dev, pipe))
1697                 return -EINVAL;
1698
1699         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1700         ironlake_enable_display_irq(dev_priv,
1701                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1702         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1703
1704         return 0;
1705 }
1706
1707 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1708 {
1709         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1710         unsigned long irqflags;
1711         u32 imr;
1712
1713         if (!i915_pipe_enabled(dev, pipe))
1714                 return -EINVAL;
1715
1716         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1717         imr = I915_READ(VLV_IMR);
1718         if (pipe == 0)
1719                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1720         else
1721                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1722         I915_WRITE(VLV_IMR, imr);
1723         i915_enable_pipestat(dev_priv, pipe,
1724                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1725         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1726
1727         return 0;
1728 }
1729
1730 /* Called from drm generic code, passed 'crtc' which
1731  * we use as a pipe index
1732  */
1733 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1734 {
1735         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1736         unsigned long irqflags;
1737
1738         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1739         if (dev_priv->info->gen == 3)
1740                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1741
1742         i915_disable_pipestat(dev_priv, pipe,
1743                               PIPE_VBLANK_INTERRUPT_ENABLE |
1744                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1745         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1746 }
1747
1748 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1749 {
1750         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1751         unsigned long irqflags;
1752
1753         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1754         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1755                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1756         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1757 }
1758
1759 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1760 {
1761         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1762         unsigned long irqflags;
1763
1764         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1765         ironlake_disable_display_irq(dev_priv,
1766                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1767         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1768 }
1769
1770 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1771 {
1772         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1773         unsigned long irqflags;
1774         u32 imr;
1775
1776         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1777         i915_disable_pipestat(dev_priv, pipe,
1778                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1779         imr = I915_READ(VLV_IMR);
1780         if (pipe == 0)
1781                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1782         else
1783                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1784         I915_WRITE(VLV_IMR, imr);
1785         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1786 }
1787
1788 static u32
1789 ring_last_seqno(struct intel_ring_buffer *ring)
1790 {
1791         return list_entry(ring->request_list.prev,
1792                           struct drm_i915_gem_request, list)->seqno;
1793 }
1794
1795 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1796 {
1797         if (list_empty(&ring->request_list) ||
1798             i915_seqno_passed(ring->get_seqno(ring, false),
1799                               ring_last_seqno(ring))) {
1800                 /* Issue a wake-up to catch stuck h/w. */
1801                 if (waitqueue_active(&ring->irq_queue)) {
1802                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1803                                   ring->name);
1804                         wake_up_all(&ring->irq_queue);
1805                         *err = true;
1806                 }
1807                 return true;
1808         }
1809         return false;
1810 }
1811
1812 static bool semaphore_passed(struct intel_ring_buffer *ring)
1813 {
1814         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1815         u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1816         struct intel_ring_buffer *signaller;
1817         u32 cmd, ipehr, acthd_min;
1818
1819         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1820         if ((ipehr & ~(0x3 << 16)) !=
1821             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1822                 return false;
1823
1824         /* ACTHD is likely pointing to the dword after the actual command,
1825          * so scan backwards until we find the MBOX.
1826          */
1827         acthd_min = max((int)acthd - 3 * 4, 0);
1828         do {
1829                 cmd = ioread32(ring->virtual_start + acthd);
1830                 if (cmd == ipehr)
1831                         break;
1832
1833                 acthd -= 4;
1834                 if (acthd < acthd_min)
1835                         return false;
1836         } while (1);
1837
1838         signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1839         return i915_seqno_passed(signaller->get_seqno(signaller, false),
1840                                  ioread32(ring->virtual_start+acthd+4)+1);
1841 }
1842
1843 static bool kick_ring(struct intel_ring_buffer *ring)
1844 {
1845         struct drm_device *dev = ring->dev;
1846         struct drm_i915_private *dev_priv = dev->dev_private;
1847         u32 tmp = I915_READ_CTL(ring);
1848         if (tmp & RING_WAIT) {
1849                 DRM_ERROR("Kicking stuck wait on %s\n",
1850                           ring->name);
1851                 I915_WRITE_CTL(ring, tmp);
1852                 return true;
1853         }
1854
1855         if (INTEL_INFO(dev)->gen >= 6 &&
1856             tmp & RING_WAIT_SEMAPHORE &&
1857             semaphore_passed(ring)) {
1858                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1859                           ring->name);
1860                 I915_WRITE_CTL(ring, tmp);
1861                 return true;
1862         }
1863         return false;
1864 }
1865
1866 static bool i915_hangcheck_hung(struct drm_device *dev)
1867 {
1868         drm_i915_private_t *dev_priv = dev->dev_private;
1869
1870         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1871                 bool hung = true;
1872
1873                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1874                 i915_handle_error(dev, true);
1875
1876                 if (!IS_GEN2(dev)) {
1877                         struct intel_ring_buffer *ring;
1878                         int i;
1879
1880                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1881                          * If so we can simply poke the RB_WAIT bit
1882                          * and break the hang. This should work on
1883                          * all but the second generation chipsets.
1884                          */
1885                         for_each_ring(ring, dev_priv, i)
1886                                 hung &= !kick_ring(ring);
1887                 }
1888
1889                 return hung;
1890         }
1891
1892         return false;
1893 }
1894
1895 /**
1896  * This is called when the chip hasn't reported back with completed
1897  * batchbuffers in a long time. The first time this is called we simply record
1898  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1899  * again, we assume the chip is wedged and try to fix it.
1900  */
1901 void i915_hangcheck_elapsed(unsigned long data)
1902 {
1903         struct drm_device *dev = (struct drm_device *)data;
1904         drm_i915_private_t *dev_priv = dev->dev_private;
1905         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1906         struct intel_ring_buffer *ring;
1907         bool err = false, idle;
1908         int i;
1909
1910         if (!i915_enable_hangcheck)
1911                 return;
1912
1913         memset(acthd, 0, sizeof(acthd));
1914         idle = true;
1915         for_each_ring(ring, dev_priv, i) {
1916             idle &= i915_hangcheck_ring_idle(ring, &err);
1917             acthd[i] = intel_ring_get_active_head(ring);
1918         }
1919
1920         /* If all work is done then ACTHD clearly hasn't advanced. */
1921         if (idle) {
1922                 if (err) {
1923                         if (i915_hangcheck_hung(dev))
1924                                 return;
1925
1926                         goto repeat;
1927                 }
1928
1929                 dev_priv->gpu_error.hangcheck_count = 0;
1930                 return;
1931         }
1932
1933         i915_get_extra_instdone(dev, instdone);
1934         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1935                    sizeof(acthd)) == 0 &&
1936             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1937                    sizeof(instdone)) == 0) {
1938                 if (i915_hangcheck_hung(dev))
1939                         return;
1940         } else {
1941                 dev_priv->gpu_error.hangcheck_count = 0;
1942
1943                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1944                        sizeof(acthd));
1945                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1946                        sizeof(instdone));
1947         }
1948
1949 repeat:
1950         /* Reset timer case chip hangs without another request being added */
1951         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1952                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1953 }
1954
1955 /* drm_dma.h hooks
1956 */
1957 static void ironlake_irq_preinstall(struct drm_device *dev)
1958 {
1959         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1960
1961         atomic_set(&dev_priv->irq_received, 0);
1962
1963         I915_WRITE(HWSTAM, 0xeffe);
1964
1965         /* XXX hotplug from PCH */
1966
1967         I915_WRITE(DEIMR, 0xffffffff);
1968         I915_WRITE(DEIER, 0x0);
1969         POSTING_READ(DEIER);
1970
1971         /* and GT */
1972         I915_WRITE(GTIMR, 0xffffffff);
1973         I915_WRITE(GTIER, 0x0);
1974         POSTING_READ(GTIER);
1975
1976         /* south display irq */
1977         I915_WRITE(SDEIMR, 0xffffffff);
1978         I915_WRITE(SDEIER, 0x0);
1979         POSTING_READ(SDEIER);
1980 }
1981
1982 static void valleyview_irq_preinstall(struct drm_device *dev)
1983 {
1984         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1985         int pipe;
1986
1987         atomic_set(&dev_priv->irq_received, 0);
1988
1989         /* VLV magic */
1990         I915_WRITE(VLV_IMR, 0);
1991         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1992         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1993         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1994
1995         /* and GT */
1996         I915_WRITE(GTIIR, I915_READ(GTIIR));
1997         I915_WRITE(GTIIR, I915_READ(GTIIR));
1998         I915_WRITE(GTIMR, 0xffffffff);
1999         I915_WRITE(GTIER, 0x0);
2000         POSTING_READ(GTIER);
2001
2002         I915_WRITE(DPINVGTT, 0xff);
2003
2004         I915_WRITE(PORT_HOTPLUG_EN, 0);
2005         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2006         for_each_pipe(pipe)
2007                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2008         I915_WRITE(VLV_IIR, 0xffffffff);
2009         I915_WRITE(VLV_IMR, 0xffffffff);
2010         I915_WRITE(VLV_IER, 0x0);
2011         POSTING_READ(VLV_IER);
2012 }
2013
2014 /*
2015  * Enable digital hotplug on the PCH, and configure the DP short pulse
2016  * duration to 2ms (which is the minimum in the Display Port spec)
2017  *
2018  * This register is the same on all known PCH chips.
2019  */
2020
2021 static void ibx_enable_hotplug(struct drm_device *dev)
2022 {
2023         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2024         u32     hotplug;
2025
2026         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2027         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2028         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2029         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2030         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2031         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2032 }
2033
2034 static void ibx_irq_postinstall(struct drm_device *dev)
2035 {
2036         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2037         u32 mask;
2038
2039         if (HAS_PCH_IBX(dev))
2040                 mask = SDE_HOTPLUG_MASK |
2041                        SDE_GMBUS |
2042                        SDE_AUX_MASK;
2043         else
2044                 mask = SDE_HOTPLUG_MASK_CPT |
2045                        SDE_GMBUS_CPT |
2046                        SDE_AUX_MASK_CPT;
2047
2048         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2049         I915_WRITE(SDEIMR, ~mask);
2050         I915_WRITE(SDEIER, mask);
2051         POSTING_READ(SDEIER);
2052
2053         ibx_enable_hotplug(dev);
2054 }
2055
2056 static int ironlake_irq_postinstall(struct drm_device *dev)
2057 {
2058         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2059         /* enable kind of interrupts always enabled */
2060         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2061                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2062                            DE_AUX_CHANNEL_A;
2063         u32 render_irqs;
2064
2065         dev_priv->irq_mask = ~display_mask;
2066
2067         /* should always can generate irq */
2068         I915_WRITE(DEIIR, I915_READ(DEIIR));
2069         I915_WRITE(DEIMR, dev_priv->irq_mask);
2070         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2071         POSTING_READ(DEIER);
2072
2073         dev_priv->gt_irq_mask = ~0;
2074
2075         I915_WRITE(GTIIR, I915_READ(GTIIR));
2076         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2077
2078         if (IS_GEN6(dev))
2079                 render_irqs =
2080                         GT_USER_INTERRUPT |
2081                         GEN6_BSD_USER_INTERRUPT |
2082                         GEN6_BLITTER_USER_INTERRUPT;
2083         else
2084                 render_irqs =
2085                         GT_USER_INTERRUPT |
2086                         GT_PIPE_NOTIFY |
2087                         GT_BSD_USER_INTERRUPT;
2088         I915_WRITE(GTIER, render_irqs);
2089         POSTING_READ(GTIER);
2090
2091         ibx_irq_postinstall(dev);
2092
2093         if (IS_IRONLAKE_M(dev)) {
2094                 /* Clear & enable PCU event interrupts */
2095                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2096                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2097                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int ivybridge_irq_postinstall(struct drm_device *dev)
2104 {
2105         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2106         /* enable kind of interrupts always enabled */
2107         u32 display_mask =
2108                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2109                 DE_PLANEC_FLIP_DONE_IVB |
2110                 DE_PLANEB_FLIP_DONE_IVB |
2111                 DE_PLANEA_FLIP_DONE_IVB |
2112                 DE_AUX_CHANNEL_A_IVB;
2113         u32 render_irqs;
2114
2115         dev_priv->irq_mask = ~display_mask;
2116
2117         /* should always can generate irq */
2118         I915_WRITE(DEIIR, I915_READ(DEIIR));
2119         I915_WRITE(DEIMR, dev_priv->irq_mask);
2120         I915_WRITE(DEIER,
2121                    display_mask |
2122                    DE_PIPEC_VBLANK_IVB |
2123                    DE_PIPEB_VBLANK_IVB |
2124                    DE_PIPEA_VBLANK_IVB);
2125         POSTING_READ(DEIER);
2126
2127         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2128
2129         I915_WRITE(GTIIR, I915_READ(GTIIR));
2130         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2131
2132         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2133                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2134         I915_WRITE(GTIER, render_irqs);
2135         POSTING_READ(GTIER);
2136
2137         ibx_irq_postinstall(dev);
2138
2139         return 0;
2140 }
2141
2142 static int valleyview_irq_postinstall(struct drm_device *dev)
2143 {
2144         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2145         u32 enable_mask;
2146         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2147         u32 render_irqs;
2148         u16 msid;
2149
2150         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2151         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2152                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2153                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2154                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2155
2156         /*
2157          *Leave vblank interrupts masked initially.  enable/disable will
2158          * toggle them based on usage.
2159          */
2160         dev_priv->irq_mask = (~enable_mask) |
2161                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2162                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2163
2164         /* Hack for broken MSIs on VLV */
2165         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2166         pci_read_config_word(dev->pdev, 0x98, &msid);
2167         msid &= 0xff; /* mask out delivery bits */
2168         msid |= (1<<14);
2169         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2170
2171         I915_WRITE(PORT_HOTPLUG_EN, 0);
2172         POSTING_READ(PORT_HOTPLUG_EN);
2173
2174         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2175         I915_WRITE(VLV_IER, enable_mask);
2176         I915_WRITE(VLV_IIR, 0xffffffff);
2177         I915_WRITE(PIPESTAT(0), 0xffff);
2178         I915_WRITE(PIPESTAT(1), 0xffff);
2179         POSTING_READ(VLV_IER);
2180
2181         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2182         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2183         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2184
2185         I915_WRITE(VLV_IIR, 0xffffffff);
2186         I915_WRITE(VLV_IIR, 0xffffffff);
2187
2188         I915_WRITE(GTIIR, I915_READ(GTIIR));
2189         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2190
2191         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2192                 GEN6_BLITTER_USER_INTERRUPT;
2193         I915_WRITE(GTIER, render_irqs);
2194         POSTING_READ(GTIER);
2195
2196         /* ack & enable invalid PTE error interrupts */
2197 #if 0 /* FIXME: add support to irq handler for checking these bits */
2198         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2199         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2200 #endif
2201
2202         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2203
2204         return 0;
2205 }
2206
2207 static void valleyview_irq_uninstall(struct drm_device *dev)
2208 {
2209         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2210         int pipe;
2211
2212         if (!dev_priv)
2213                 return;
2214
2215         for_each_pipe(pipe)
2216                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2217
2218         I915_WRITE(HWSTAM, 0xffffffff);
2219         I915_WRITE(PORT_HOTPLUG_EN, 0);
2220         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2221         for_each_pipe(pipe)
2222                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2223         I915_WRITE(VLV_IIR, 0xffffffff);
2224         I915_WRITE(VLV_IMR, 0xffffffff);
2225         I915_WRITE(VLV_IER, 0x0);
2226         POSTING_READ(VLV_IER);
2227 }
2228
2229 static void ironlake_irq_uninstall(struct drm_device *dev)
2230 {
2231         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2232
2233         if (!dev_priv)
2234                 return;
2235
2236         I915_WRITE(HWSTAM, 0xffffffff);
2237
2238         I915_WRITE(DEIMR, 0xffffffff);
2239         I915_WRITE(DEIER, 0x0);
2240         I915_WRITE(DEIIR, I915_READ(DEIIR));
2241
2242         I915_WRITE(GTIMR, 0xffffffff);
2243         I915_WRITE(GTIER, 0x0);
2244         I915_WRITE(GTIIR, I915_READ(GTIIR));
2245
2246         I915_WRITE(SDEIMR, 0xffffffff);
2247         I915_WRITE(SDEIER, 0x0);
2248         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2249 }
2250
2251 static void i8xx_irq_preinstall(struct drm_device * dev)
2252 {
2253         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2254         int pipe;
2255
2256         atomic_set(&dev_priv->irq_received, 0);
2257
2258         for_each_pipe(pipe)
2259                 I915_WRITE(PIPESTAT(pipe), 0);
2260         I915_WRITE16(IMR, 0xffff);
2261         I915_WRITE16(IER, 0x0);
2262         POSTING_READ16(IER);
2263 }
2264
2265 static int i8xx_irq_postinstall(struct drm_device *dev)
2266 {
2267         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2268
2269         I915_WRITE16(EMR,
2270                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2271
2272         /* Unmask the interrupts that we always want on. */
2273         dev_priv->irq_mask =
2274                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2275                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2276                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2277                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2278                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2279         I915_WRITE16(IMR, dev_priv->irq_mask);
2280
2281         I915_WRITE16(IER,
2282                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2283                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2284                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2285                      I915_USER_INTERRUPT);
2286         POSTING_READ16(IER);
2287
2288         return 0;
2289 }
2290
2291 /*
2292  * Returns true when a page flip has completed.
2293  */
2294 static bool i8xx_handle_vblank(struct drm_device *dev,
2295                                int pipe, u16 iir)
2296 {
2297         drm_i915_private_t *dev_priv = dev->dev_private;
2298         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2299
2300         if (!drm_handle_vblank(dev, pipe))
2301                 return false;
2302
2303         if ((iir & flip_pending) == 0)
2304                 return false;
2305
2306         intel_prepare_page_flip(dev, pipe);
2307
2308         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2309          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2310          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2311          * the flip is completed (no longer pending). Since this doesn't raise
2312          * an interrupt per se, we watch for the change at vblank.
2313          */
2314         if (I915_READ16(ISR) & flip_pending)
2315                 return false;
2316
2317         intel_finish_page_flip(dev, pipe);
2318
2319         return true;
2320 }
2321
2322 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2323 {
2324         struct drm_device *dev = (struct drm_device *) arg;
2325         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2326         u16 iir, new_iir;
2327         u32 pipe_stats[2];
2328         unsigned long irqflags;
2329         int irq_received;
2330         int pipe;
2331         u16 flip_mask =
2332                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2333                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2334
2335         atomic_inc(&dev_priv->irq_received);
2336
2337         iir = I915_READ16(IIR);
2338         if (iir == 0)
2339                 return IRQ_NONE;
2340
2341         while (iir & ~flip_mask) {
2342                 /* Can't rely on pipestat interrupt bit in iir as it might
2343                  * have been cleared after the pipestat interrupt was received.
2344                  * It doesn't set the bit in iir again, but it still produces
2345                  * interrupts (for non-MSI).
2346                  */
2347                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2348                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2349                         i915_handle_error(dev, false);
2350
2351                 for_each_pipe(pipe) {
2352                         int reg = PIPESTAT(pipe);
2353                         pipe_stats[pipe] = I915_READ(reg);
2354
2355                         /*
2356                          * Clear the PIPE*STAT regs before the IIR
2357                          */
2358                         if (pipe_stats[pipe] & 0x8000ffff) {
2359                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2360                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2361                                                          pipe_name(pipe));
2362                                 I915_WRITE(reg, pipe_stats[pipe]);
2363                                 irq_received = 1;
2364                         }
2365                 }
2366                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2367
2368                 I915_WRITE16(IIR, iir & ~flip_mask);
2369                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2370
2371                 i915_update_dri1_breadcrumb(dev);
2372
2373                 if (iir & I915_USER_INTERRUPT)
2374                         notify_ring(dev, &dev_priv->ring[RCS]);
2375
2376                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2377                     i8xx_handle_vblank(dev, 0, iir))
2378                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2379
2380                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2381                     i8xx_handle_vblank(dev, 1, iir))
2382                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2383
2384                 iir = new_iir;
2385         }
2386
2387         return IRQ_HANDLED;
2388 }
2389
2390 static void i8xx_irq_uninstall(struct drm_device * dev)
2391 {
2392         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2393         int pipe;
2394
2395         for_each_pipe(pipe) {
2396                 /* Clear enable bits; then clear status bits */
2397                 I915_WRITE(PIPESTAT(pipe), 0);
2398                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2399         }
2400         I915_WRITE16(IMR, 0xffff);
2401         I915_WRITE16(IER, 0x0);
2402         I915_WRITE16(IIR, I915_READ16(IIR));
2403 }
2404
2405 static void i915_irq_preinstall(struct drm_device * dev)
2406 {
2407         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2408         int pipe;
2409
2410         atomic_set(&dev_priv->irq_received, 0);
2411
2412         if (I915_HAS_HOTPLUG(dev)) {
2413                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2414                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2415         }
2416
2417         I915_WRITE16(HWSTAM, 0xeffe);
2418         for_each_pipe(pipe)
2419                 I915_WRITE(PIPESTAT(pipe), 0);
2420         I915_WRITE(IMR, 0xffffffff);
2421         I915_WRITE(IER, 0x0);
2422         POSTING_READ(IER);
2423 }
2424
2425 static int i915_irq_postinstall(struct drm_device *dev)
2426 {
2427         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2428         u32 enable_mask;
2429
2430         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2431
2432         /* Unmask the interrupts that we always want on. */
2433         dev_priv->irq_mask =
2434                 ~(I915_ASLE_INTERRUPT |
2435                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2436                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2437                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2438                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2439                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2440
2441         enable_mask =
2442                 I915_ASLE_INTERRUPT |
2443                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2444                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2445                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2446                 I915_USER_INTERRUPT;
2447
2448         if (I915_HAS_HOTPLUG(dev)) {
2449                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2450                 POSTING_READ(PORT_HOTPLUG_EN);
2451
2452                 /* Enable in IER... */
2453                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2454                 /* and unmask in IMR */
2455                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2456         }
2457
2458         I915_WRITE(IMR, dev_priv->irq_mask);
2459         I915_WRITE(IER, enable_mask);
2460         POSTING_READ(IER);
2461
2462         intel_opregion_enable_asle(dev);
2463
2464         return 0;
2465 }
2466
2467 static void i915_hpd_irq_setup(struct drm_device *dev)
2468 {
2469         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2470         u32 hotplug_en;
2471
2472         if (I915_HAS_HOTPLUG(dev)) {
2473                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2474
2475                 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2476                         hotplug_en |= PORTB_HOTPLUG_INT_EN;
2477                 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2478                         hotplug_en |= PORTC_HOTPLUG_INT_EN;
2479                 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2480                         hotplug_en |= PORTD_HOTPLUG_INT_EN;
2481                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2482                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2483                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2484                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2485                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2486                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2487                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2488                 }
2489
2490                 /* Ignore TV since it's buggy */
2491
2492                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2493         }
2494 }
2495
2496 /*
2497  * Returns true when a page flip has completed.
2498  */
2499 static bool i915_handle_vblank(struct drm_device *dev,
2500                                int plane, int pipe, u32 iir)
2501 {
2502         drm_i915_private_t *dev_priv = dev->dev_private;
2503         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2504
2505         if (!drm_handle_vblank(dev, pipe))
2506                 return false;
2507
2508         if ((iir & flip_pending) == 0)
2509                 return false;
2510
2511         intel_prepare_page_flip(dev, plane);
2512
2513         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2514          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2515          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2516          * the flip is completed (no longer pending). Since this doesn't raise
2517          * an interrupt per se, we watch for the change at vblank.
2518          */
2519         if (I915_READ(ISR) & flip_pending)
2520                 return false;
2521
2522         intel_finish_page_flip(dev, pipe);
2523
2524         return true;
2525 }
2526
2527 static irqreturn_t i915_irq_handler(int irq, void *arg)
2528 {
2529         struct drm_device *dev = (struct drm_device *) arg;
2530         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2531         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2532         unsigned long irqflags;
2533         u32 flip_mask =
2534                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2535                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2536         int pipe, ret = IRQ_NONE;
2537
2538         atomic_inc(&dev_priv->irq_received);
2539
2540         iir = I915_READ(IIR);
2541         do {
2542                 bool irq_received = (iir & ~flip_mask) != 0;
2543                 bool blc_event = false;
2544
2545                 /* Can't rely on pipestat interrupt bit in iir as it might
2546                  * have been cleared after the pipestat interrupt was received.
2547                  * It doesn't set the bit in iir again, but it still produces
2548                  * interrupts (for non-MSI).
2549                  */
2550                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2551                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2552                         i915_handle_error(dev, false);
2553
2554                 for_each_pipe(pipe) {
2555                         int reg = PIPESTAT(pipe);
2556                         pipe_stats[pipe] = I915_READ(reg);
2557
2558                         /* Clear the PIPE*STAT regs before the IIR */
2559                         if (pipe_stats[pipe] & 0x8000ffff) {
2560                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2561                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2562                                                          pipe_name(pipe));
2563                                 I915_WRITE(reg, pipe_stats[pipe]);
2564                                 irq_received = true;
2565                         }
2566                 }
2567                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2568
2569                 if (!irq_received)
2570                         break;
2571
2572                 /* Consume port.  Then clear IIR or we'll miss events */
2573                 if ((I915_HAS_HOTPLUG(dev)) &&
2574                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2575                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2576
2577                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2578                                   hotplug_status);
2579                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2580                                 queue_work(dev_priv->wq,
2581                                            &dev_priv->hotplug_work);
2582
2583                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2584                         POSTING_READ(PORT_HOTPLUG_STAT);
2585                 }
2586
2587                 I915_WRITE(IIR, iir & ~flip_mask);
2588                 new_iir = I915_READ(IIR); /* Flush posted writes */
2589
2590                 if (iir & I915_USER_INTERRUPT)
2591                         notify_ring(dev, &dev_priv->ring[RCS]);
2592
2593                 for_each_pipe(pipe) {
2594                         int plane = pipe;
2595                         if (IS_MOBILE(dev))
2596                                 plane = !plane;
2597
2598                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2599                             i915_handle_vblank(dev, plane, pipe, iir))
2600                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2601
2602                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2603                                 blc_event = true;
2604                 }
2605
2606                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2607                         intel_opregion_asle_intr(dev);
2608
2609                 /* With MSI, interrupts are only generated when iir
2610                  * transitions from zero to nonzero.  If another bit got
2611                  * set while we were handling the existing iir bits, then
2612                  * we would never get another interrupt.
2613                  *
2614                  * This is fine on non-MSI as well, as if we hit this path
2615                  * we avoid exiting the interrupt handler only to generate
2616                  * another one.
2617                  *
2618                  * Note that for MSI this could cause a stray interrupt report
2619                  * if an interrupt landed in the time between writing IIR and
2620                  * the posting read.  This should be rare enough to never
2621                  * trigger the 99% of 100,000 interrupts test for disabling
2622                  * stray interrupts.
2623                  */
2624                 ret = IRQ_HANDLED;
2625                 iir = new_iir;
2626         } while (iir & ~flip_mask);
2627
2628         i915_update_dri1_breadcrumb(dev);
2629
2630         return ret;
2631 }
2632
2633 static void i915_irq_uninstall(struct drm_device * dev)
2634 {
2635         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2636         int pipe;
2637
2638         if (I915_HAS_HOTPLUG(dev)) {
2639                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2640                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2641         }
2642
2643         I915_WRITE16(HWSTAM, 0xffff);
2644         for_each_pipe(pipe) {
2645                 /* Clear enable bits; then clear status bits */
2646                 I915_WRITE(PIPESTAT(pipe), 0);
2647                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2648         }
2649         I915_WRITE(IMR, 0xffffffff);
2650         I915_WRITE(IER, 0x0);
2651
2652         I915_WRITE(IIR, I915_READ(IIR));
2653 }
2654
2655 static void i965_irq_preinstall(struct drm_device * dev)
2656 {
2657         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2658         int pipe;
2659
2660         atomic_set(&dev_priv->irq_received, 0);
2661
2662         I915_WRITE(PORT_HOTPLUG_EN, 0);
2663         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2664
2665         I915_WRITE(HWSTAM, 0xeffe);
2666         for_each_pipe(pipe)
2667                 I915_WRITE(PIPESTAT(pipe), 0);
2668         I915_WRITE(IMR, 0xffffffff);
2669         I915_WRITE(IER, 0x0);
2670         POSTING_READ(IER);
2671 }
2672
2673 static int i965_irq_postinstall(struct drm_device *dev)
2674 {
2675         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2676         u32 enable_mask;
2677         u32 error_mask;
2678
2679         /* Unmask the interrupts that we always want on. */
2680         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2681                                I915_DISPLAY_PORT_INTERRUPT |
2682                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2683                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2684                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2685                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2686                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2687
2688         enable_mask = ~dev_priv->irq_mask;
2689         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2690                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2691         enable_mask |= I915_USER_INTERRUPT;
2692
2693         if (IS_G4X(dev))
2694                 enable_mask |= I915_BSD_USER_INTERRUPT;
2695
2696         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2697
2698         /*
2699          * Enable some error detection, note the instruction error mask
2700          * bit is reserved, so we leave it masked.
2701          */
2702         if (IS_G4X(dev)) {
2703                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2704                                GM45_ERROR_MEM_PRIV |
2705                                GM45_ERROR_CP_PRIV |
2706                                I915_ERROR_MEMORY_REFRESH);
2707         } else {
2708                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2709                                I915_ERROR_MEMORY_REFRESH);
2710         }
2711         I915_WRITE(EMR, error_mask);
2712
2713         I915_WRITE(IMR, dev_priv->irq_mask);
2714         I915_WRITE(IER, enable_mask);
2715         POSTING_READ(IER);
2716
2717         I915_WRITE(PORT_HOTPLUG_EN, 0);
2718         POSTING_READ(PORT_HOTPLUG_EN);
2719
2720         intel_opregion_enable_asle(dev);
2721
2722         return 0;
2723 }
2724
2725 static void i965_hpd_irq_setup(struct drm_device *dev)
2726 {
2727         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2728         u32 hotplug_en;
2729
2730         /* Note HDMI and DP share hotplug bits */
2731         hotplug_en = 0;
2732         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2733                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2734         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2735                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2736         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2737                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2738         if (IS_G4X(dev)) {
2739                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2740                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2741                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2742                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2743         } else {
2744                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2745                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2746                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2747                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2748         }
2749         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2750                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2751
2752                 /* Programming the CRT detection parameters tends
2753                    to generate a spurious hotplug event about three
2754                    seconds later.  So just do it once.
2755                    */
2756                 if (IS_G4X(dev))
2757                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2758                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2759         }
2760
2761         /* Ignore TV since it's buggy */
2762
2763         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2764 }
2765
2766 static irqreturn_t i965_irq_handler(int irq, void *arg)
2767 {
2768         struct drm_device *dev = (struct drm_device *) arg;
2769         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2770         u32 iir, new_iir;
2771         u32 pipe_stats[I915_MAX_PIPES];
2772         unsigned long irqflags;
2773         int irq_received;
2774         int ret = IRQ_NONE, pipe;
2775         u32 flip_mask =
2776                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2777                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2778
2779         atomic_inc(&dev_priv->irq_received);
2780
2781         iir = I915_READ(IIR);
2782
2783         for (;;) {
2784                 bool blc_event = false;
2785
2786                 irq_received = (iir & ~flip_mask) != 0;
2787
2788                 /* Can't rely on pipestat interrupt bit in iir as it might
2789                  * have been cleared after the pipestat interrupt was received.
2790                  * It doesn't set the bit in iir again, but it still produces
2791                  * interrupts (for non-MSI).
2792                  */
2793                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2794                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2795                         i915_handle_error(dev, false);
2796
2797                 for_each_pipe(pipe) {
2798                         int reg = PIPESTAT(pipe);
2799                         pipe_stats[pipe] = I915_READ(reg);
2800
2801                         /*
2802                          * Clear the PIPE*STAT regs before the IIR
2803                          */
2804                         if (pipe_stats[pipe] & 0x8000ffff) {
2805                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2806                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2807                                                          pipe_name(pipe));
2808                                 I915_WRITE(reg, pipe_stats[pipe]);
2809                                 irq_received = 1;
2810                         }
2811                 }
2812                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2813
2814                 if (!irq_received)
2815                         break;
2816
2817                 ret = IRQ_HANDLED;
2818
2819                 /* Consume port.  Then clear IIR or we'll miss events */
2820                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2821                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2822
2823                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2824                                   hotplug_status);
2825                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2826                                 queue_work(dev_priv->wq,
2827                                            &dev_priv->hotplug_work);
2828
2829                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2830                         I915_READ(PORT_HOTPLUG_STAT);
2831                 }
2832
2833                 I915_WRITE(IIR, iir & ~flip_mask);
2834                 new_iir = I915_READ(IIR); /* Flush posted writes */
2835
2836                 if (iir & I915_USER_INTERRUPT)
2837                         notify_ring(dev, &dev_priv->ring[RCS]);
2838                 if (iir & I915_BSD_USER_INTERRUPT)
2839                         notify_ring(dev, &dev_priv->ring[VCS]);
2840
2841                 for_each_pipe(pipe) {
2842                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2843                             i915_handle_vblank(dev, pipe, pipe, iir))
2844                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2845
2846                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2847                                 blc_event = true;
2848                 }
2849
2850
2851                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2852                         intel_opregion_asle_intr(dev);
2853
2854                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2855                         gmbus_irq_handler(dev);
2856
2857                 /* With MSI, interrupts are only generated when iir
2858                  * transitions from zero to nonzero.  If another bit got
2859                  * set while we were handling the existing iir bits, then
2860                  * we would never get another interrupt.
2861                  *
2862                  * This is fine on non-MSI as well, as if we hit this path
2863                  * we avoid exiting the interrupt handler only to generate
2864                  * another one.
2865                  *
2866                  * Note that for MSI this could cause a stray interrupt report
2867                  * if an interrupt landed in the time between writing IIR and
2868                  * the posting read.  This should be rare enough to never
2869                  * trigger the 99% of 100,000 interrupts test for disabling
2870                  * stray interrupts.
2871                  */
2872                 iir = new_iir;
2873         }
2874
2875         i915_update_dri1_breadcrumb(dev);
2876
2877         return ret;
2878 }
2879
2880 static void i965_irq_uninstall(struct drm_device * dev)
2881 {
2882         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2883         int pipe;
2884
2885         if (!dev_priv)
2886                 return;
2887
2888         I915_WRITE(PORT_HOTPLUG_EN, 0);
2889         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2890
2891         I915_WRITE(HWSTAM, 0xffffffff);
2892         for_each_pipe(pipe)
2893                 I915_WRITE(PIPESTAT(pipe), 0);
2894         I915_WRITE(IMR, 0xffffffff);
2895         I915_WRITE(IER, 0x0);
2896
2897         for_each_pipe(pipe)
2898                 I915_WRITE(PIPESTAT(pipe),
2899                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2900         I915_WRITE(IIR, I915_READ(IIR));
2901 }
2902
2903 void intel_irq_init(struct drm_device *dev)
2904 {
2905         struct drm_i915_private *dev_priv = dev->dev_private;
2906
2907         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2908         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2909         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2910         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2911
2912         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2913                     i915_hangcheck_elapsed,
2914                     (unsigned long) dev);
2915
2916         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2917
2918         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2919         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2920         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2921                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2922                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2923         }
2924
2925         if (drm_core_check_feature(dev, DRIVER_MODESET))
2926                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2927         else
2928                 dev->driver->get_vblank_timestamp = NULL;
2929         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2930
2931         if (IS_VALLEYVIEW(dev)) {
2932                 dev->driver->irq_handler = valleyview_irq_handler;
2933                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2934                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2935                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2936                 dev->driver->enable_vblank = valleyview_enable_vblank;
2937                 dev->driver->disable_vblank = valleyview_disable_vblank;
2938                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2939         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2940                 /* Share pre & uninstall handlers with ILK/SNB */
2941                 dev->driver->irq_handler = ivybridge_irq_handler;
2942                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2943                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2944                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2945                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2946                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2947         } else if (HAS_PCH_SPLIT(dev)) {
2948                 dev->driver->irq_handler = ironlake_irq_handler;
2949                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2950                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2951                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2952                 dev->driver->enable_vblank = ironlake_enable_vblank;
2953                 dev->driver->disable_vblank = ironlake_disable_vblank;
2954         } else {
2955                 if (INTEL_INFO(dev)->gen == 2) {
2956                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2957                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2958                         dev->driver->irq_handler = i8xx_irq_handler;
2959                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2960                 } else if (INTEL_INFO(dev)->gen == 3) {
2961                         dev->driver->irq_preinstall = i915_irq_preinstall;
2962                         dev->driver->irq_postinstall = i915_irq_postinstall;
2963                         dev->driver->irq_uninstall = i915_irq_uninstall;
2964                         dev->driver->irq_handler = i915_irq_handler;
2965                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2966                 } else {
2967                         dev->driver->irq_preinstall = i965_irq_preinstall;
2968                         dev->driver->irq_postinstall = i965_irq_postinstall;
2969                         dev->driver->irq_uninstall = i965_irq_uninstall;
2970                         dev->driver->irq_handler = i965_irq_handler;
2971                         dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
2972                 }
2973                 dev->driver->enable_vblank = i915_enable_vblank;
2974                 dev->driver->disable_vblank = i915_disable_vblank;
2975         }
2976 }
2977
2978 void intel_hpd_init(struct drm_device *dev)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981
2982         if (dev_priv->display.hpd_irq_setup)
2983                 dev_priv->display.hpd_irq_setup(dev);
2984 }