drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pm.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pm.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pm.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pm.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pm.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pm.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pm.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         u32 reg = PIPESTAT(pipe);
 239         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 240
 241         assert_spin_locked(&dev_priv->irq_lock);
 242
 243         I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 244         POSTING_READ(reg);
 245 }
 246
 247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 248                                                  enum pipe pipe, bool enable)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 252                                           DE_PIPEB_FIFO_UNDERRUN;
 253
 254         if (enable)
 255                 ironlake_enable_display_irq(dev_priv, bit);
 256         else
 257                 ironlake_disable_display_irq(dev_priv, bit);
 258 }
 259
 260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 261                                                   enum pipe pipe, bool enable)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         if (enable) {
 265                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 266
 267                 if (!ivb_can_enable_err_int(dev))
 268                         return;
 269
 270                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 271         } else {
 272                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 273
 274                 /* Change the state _after_ we've read out the current one. */
 275                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 276
 277                 if (!was_enabled &&
 278                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 279                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 280                                       pipe_name(pipe));
 281                 }
 282         }
 283 }
 284
 285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 286                                                   enum pipe pipe, bool enable)
 287 {
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289
 290         assert_spin_locked(&dev_priv->irq_lock);
 291
 292         if (enable)
 293                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 294         else
 295                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 296         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 297         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 298 }
 299
 300 /**
 301  * ibx_display_interrupt_update - update SDEIMR
 302  * @dev_priv: driver private
 303  * @interrupt_mask: mask of interrupt bits to update
 304  * @enabled_irq_mask: mask of interrupt bits to enable
 305  */
 306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 307                                          uint32_t interrupt_mask,
 308                                          uint32_t enabled_irq_mask)
 309 {
 310         uint32_t sdeimr = I915_READ(SDEIMR);
 311         sdeimr &= ~interrupt_mask;
 312         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 313
 314         assert_spin_locked(&dev_priv->irq_lock);
 315
 316         if (dev_priv->pm.irqs_disabled &&
 317             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 318                 WARN(1, "IRQs disabled\n");
 319                 dev_priv->pm.regsave.sdeimr &= ~interrupt_mask;
 320                 dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask &
 321                                                  interrupt_mask);
 322                 return;
 323         }
 324
 325         I915_WRITE(SDEIMR, sdeimr);
 326         POSTING_READ(SDEIMR);
 327 }
 328 #define ibx_enable_display_interrupt(dev_priv, bits) \
 329         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 330 #define ibx_disable_display_interrupt(dev_priv, bits) \
 331         ibx_display_interrupt_update((dev_priv), (bits), 0)
 332
 333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 334                                             enum transcoder pch_transcoder,
 335                                             bool enable)
 336 {
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 339                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 340
 341         if (enable)
 342                 ibx_enable_display_interrupt(dev_priv, bit);
 343         else
 344                 ibx_disable_display_interrupt(dev_priv, bit);
 345 }
 346
 347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 348                                             enum transcoder pch_transcoder,
 349                                             bool enable)
 350 {
 351         struct drm_i915_private *dev_priv = dev->dev_private;
 352
 353         if (enable) {
 354                 I915_WRITE(SERR_INT,
 355                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 356
 357                 if (!cpt_can_enable_serr_int(dev))
 358                         return;
 359
 360                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 361         } else {
 362                 uint32_t tmp = I915_READ(SERR_INT);
 363                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 364
 365                 /* Change the state _after_ we've read out the current one. */
 366                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 367
 368                 if (!was_enabled &&
 369                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 370                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 371                                       transcoder_name(pch_transcoder));
 372                 }
 373         }
 374 }
 375
 376 /**
 377  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 378  * @dev: drm device
 379  * @pipe: pipe
 380  * @enable: true if we want to report FIFO underrun errors, false otherwise
 381  *
 382  * This function makes us disable or enable CPU fifo underruns for a specific
 383  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 384  * reporting for one pipe may also disable all the other CPU error interruts for
 385  * the other pipes, due to the fact that there's just one interrupt mask/enable
 386  * bit for all the pipes.
 387  *
 388  * Returns the previous state of underrun reporting.
 389  */
 390 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 391                                              enum pipe pipe, bool enable)
 392 {
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 396         bool ret;
 397
 398         assert_spin_locked(&dev_priv->irq_lock);
 399
 400         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 401
 402         if (enable == ret)
 403                 goto done;
 404
 405         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 406
 407         if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
 408                 i9xx_clear_fifo_underrun(dev, pipe);
 409         else if (IS_GEN5(dev) || IS_GEN6(dev))
 410                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 411         else if (IS_GEN7(dev))
 412                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 413         else if (IS_GEN8(dev))
 414                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 415
 416 done:
 417         return ret;
 418 }
 419
 420 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 421                                            enum pipe pipe, bool enable)
 422 {
 423         struct drm_i915_private *dev_priv = dev->dev_private;
 424         unsigned long flags;
 425         bool ret;
 426
 427         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 428         ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
 429         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 430
 431         return ret;
 432 }
 433
 434 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
 435                                                   enum pipe pipe)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 440
 441         return !intel_crtc->cpu_fifo_underrun_disabled;
 442 }
 443
 444 /**
 445  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 446  * @dev: drm device
 447  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 448  * @enable: true if we want to report FIFO underrun errors, false otherwise
 449  *
 450  * This function makes us disable or enable PCH fifo underruns for a specific
 451  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 452  * underrun reporting for one transcoder may also disable all the other PCH
 453  * error interruts for the other transcoders, due to the fact that there's just
 454  * one interrupt mask/enable bit for all the transcoders.
 455  *
 456  * Returns the previous state of underrun reporting.
 457  */
 458 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 459                                            enum transcoder pch_transcoder,
 460                                            bool enable)
 461 {
 462         struct drm_i915_private *dev_priv = dev->dev_private;
 463         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 465         unsigned long flags;
 466         bool ret;
 467
 468         /*
 469          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 470          * has only one pch transcoder A that all pipes can use. To avoid racy
 471          * pch transcoder -> pipe lookups from interrupt code simply store the
 472          * underrun statistics in crtc A. Since we never expose this anywhere
 473          * nor use it outside of the fifo underrun code here using the "wrong"
 474          * crtc on LPT won't cause issues.
 475          */
 476
 477         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 478
 479         ret = !intel_crtc->pch_fifo_underrun_disabled;
 480
 481         if (enable == ret)
 482                 goto done;
 483
 484         intel_crtc->pch_fifo_underrun_disabled = !enable;
 485
 486         if (HAS_PCH_IBX(dev))
 487                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 488         else
 489                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 490
 491 done:
 492         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 493         return ret;
 494 }
 495
 496
 497 static void
 498 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 499                        u32 enable_mask, u32 status_mask)
 500 {
 501         u32 reg = PIPESTAT(pipe);
 502         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 503
 504         assert_spin_locked(&dev_priv->irq_lock);
 505
 506         if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 507                          status_mask & ~PIPESTAT_INT_STATUS_MASK))
 508                 return;
 509
 510         if ((pipestat & enable_mask) == enable_mask)
 511                 return;
 512
 513         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 514
 515         /* Enable the interrupt, clear any pending status */
 516         pipestat |= enable_mask | status_mask;
 517         I915_WRITE(reg, pipestat);
 518         POSTING_READ(reg);
 519 }
 520
 521 static void
 522 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 523                         u32 enable_mask, u32 status_mask)
 524 {
 525         u32 reg = PIPESTAT(pipe);
 526         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 527
 528         assert_spin_locked(&dev_priv->irq_lock);
 529
 530         if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 531                          status_mask & ~PIPESTAT_INT_STATUS_MASK))
 532                 return;
 533
 534         if ((pipestat & enable_mask) == 0)
 535                 return;
 536
 537         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 538
 539         pipestat &= ~enable_mask;
 540         I915_WRITE(reg, pipestat);
 541         POSTING_READ(reg);
 542 }
 543
 544 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 545 {
 546         u32 enable_mask = status_mask << 16;
 547
 548         /*
 549          * On pipe A we don't support the PSR interrupt yet, on pipe B the
 550          * same bit MBZ.
 551          */
 552         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 553                 return 0;
 554
 555         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 556                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 557                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 558         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 559                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 560         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 561                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 562
 563         return enable_mask;
 564 }
 565
 566 void
 567 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 568                      u32 status_mask)
 569 {
 570         u32 enable_mask;
 571
 572         if (IS_VALLEYVIEW(dev_priv->dev))
 573                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 574                                                            status_mask);
 575         else
 576                 enable_mask = status_mask << 16;
 577         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 578 }
 579
 580 void
 581 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 582                       u32 status_mask)
 583 {
 584         u32 enable_mask;
 585
 586         if (IS_VALLEYVIEW(dev_priv->dev))
 587                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 588                                                            status_mask);
 589         else
 590                 enable_mask = status_mask << 16;
 591         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 592 }
 593
 594 /**
 595  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 596  */
 597 static void i915_enable_asle_pipestat(struct drm_device *dev)
 598 {
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         unsigned long irqflags;
 601
 602         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 603                 return;
 604
 605         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 606
 607         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 608         if (INTEL_INFO(dev)->gen >= 4)
 609                 i915_enable_pipestat(dev_priv, PIPE_A,
 610                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 611
 612         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 613 }
 614
 615 /**
 616  * i915_pipe_enabled - check if a pipe is enabled
 617  * @dev: DRM device
 618  * @pipe: pipe to check
 619  *
 620  * Reading certain registers when the pipe is disabled can hang the chip.
 621  * Use this routine to make sure the PLL is running and the pipe is active
 622  * before reading such registers if unsure.
 623  */
 624 static int
 625 i915_pipe_enabled(struct drm_device *dev, int pipe)
 626 {
 627         struct drm_i915_private *dev_priv = dev->dev_private;
 628
 629         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 630                 /* Locking is horribly broken here, but whatever. */
 631                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 632                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 633
 634                 return intel_crtc->active;
 635         } else {
 636                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 637         }
 638 }
 639
 640 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 641 {
 642         /* Gen2 doesn't have a hardware frame counter */
 643         return 0;
 644 }
 645
 646 /* Called from drm generic code, passed a 'crtc', which
 647  * we use as a pipe index
 648  */
 649 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 650 {
 651         struct drm_i915_private *dev_priv = dev->dev_private;
 652         unsigned long high_frame;
 653         unsigned long low_frame;
 654         u32 high1, high2, low, pixel, vbl_start;
 655
 656         if (!i915_pipe_enabled(dev, pipe)) {
 657                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 658                                 "pipe %c\n", pipe_name(pipe));
 659                 return 0;
 660         }
 661
 662         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 663                 struct intel_crtc *intel_crtc =
 664                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 665                 const struct drm_display_mode *mode =
 666                         &intel_crtc->config.adjusted_mode;
 667
 668                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 669         } else {
 670                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 671                 u32 htotal;
 672
 673                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 674                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 675
 676                 vbl_start *= htotal;
 677         }
 678
 679         high_frame = PIPEFRAME(pipe);
 680         low_frame = PIPEFRAMEPIXEL(pipe);
 681
 682         /*
 683          * High & low register fields aren't synchronized, so make sure
 684          * we get a low value that's stable across two reads of the high
 685          * register.
 686          */
 687         do {
 688                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 689                 low   = I915_READ(low_frame);
 690                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 691         } while (high1 != high2);
 692
 693         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 694         pixel = low & PIPE_PIXEL_MASK;
 695         low >>= PIPE_FRAME_LOW_SHIFT;
 696
 697         /*
 698          * The frame counter increments at beginning of active.
 699          * Cook up a vblank counter by also checking the pixel
 700          * counter against vblank start.
 701          */
 702         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 703 }
 704
 705 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 706 {
 707         struct drm_i915_private *dev_priv = dev->dev_private;
 708         int reg = PIPE_FRMCOUNT_GM45(pipe);
 709
 710         if (!i915_pipe_enabled(dev, pipe)) {
 711                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 712                                  "pipe %c\n", pipe_name(pipe));
 713                 return 0;
 714         }
 715
 716         return I915_READ(reg);
 717 }
 718
 719 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 720 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 721
 722 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725         uint32_t status;
 726         int reg;
 727
 728         if (INTEL_INFO(dev)->gen >= 8) {
 729                 status = GEN8_PIPE_VBLANK;
 730                 reg = GEN8_DE_PIPE_ISR(pipe);
 731         } else if (INTEL_INFO(dev)->gen >= 7) {
 732                 status = DE_PIPE_VBLANK_IVB(pipe);
 733                 reg = DEISR;
 734         } else {
 735                 status = DE_PIPE_VBLANK(pipe);
 736                 reg = DEISR;
 737         }
 738
 739         return __raw_i915_read32(dev_priv, reg) & status;
 740 }
 741
 742 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 743                                     unsigned int flags, int *vpos, int *hpos,
 744                                     ktime_t *stime, ktime_t *etime)
 745 {
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 749         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 750         int position;
 751         int vbl_start, vbl_end, htotal, vtotal;
 752         bool in_vbl = true;
 753         int ret = 0;
 754         unsigned long irqflags;
 755
 756         if (!intel_crtc->active) {
 757                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 758                                  "pipe %c\n", pipe_name(pipe));
 759                 return 0;
 760         }
 761
 762         htotal = mode->crtc_htotal;
 763         vtotal = mode->crtc_vtotal;
 764         vbl_start = mode->crtc_vblank_start;
 765         vbl_end = mode->crtc_vblank_end;
 766
 767         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 768                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 769                 vbl_end /= 2;
 770                 vtotal /= 2;
 771         }
 772
 773         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 774
 775         /*
 776          * Lock uncore.lock, as we will do multiple timing critical raw
 777          * register reads, potentially with preemption disabled, so the
 778          * following code must not block on uncore.lock.
 779          */
 780         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 781
 782         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 783
 784         /* Get optional system timestamp before query. */
 785         if (stime)
 786                 *stime = ktime_get();
 787
 788         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 789                 /* No obvious pixelcount register. Only query vertical
 790                  * scanout position from Display scan line register.
 791                  */
 792                 if (IS_GEN2(dev))
 793                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 794                 else
 795                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 796
 797                 if (HAS_DDI(dev)) {
 798                         /*
 799                          * On HSW HDMI outputs there seems to be a 2 line
 800                          * difference, whereas eDP has the normal 1 line
 801                          * difference that earlier platforms have. External
 802                          * DP is unknown. For now just check for the 2 line
 803                          * difference case on all output types on HSW+.
 804                          *
 805                          * This might misinterpret the scanline counter being
 806                          * one line too far along on eDP, but that's less
 807                          * dangerous than the alternative since that would lead
 808                          * the vblank timestamp code astray when it sees a
 809                          * scanline count before vblank_start during a vblank
 810                          * interrupt.
 811                          */
 812                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 813                         if ((in_vbl && (position == vbl_start - 2 ||
 814                                         position == vbl_start - 1)) ||
 815                             (!in_vbl && (position == vbl_end - 2 ||
 816                                          position == vbl_end - 1)))
 817                                 position = (position + 2) % vtotal;
 818                 } else if (HAS_PCH_SPLIT(dev)) {
 819                         /*
 820                          * The scanline counter increments at the leading edge
 821                          * of hsync, ie. it completely misses the active portion
 822                          * of the line. Fix up the counter at both edges of vblank
 823                          * to get a more accurate picture whether we're in vblank
 824                          * or not.
 825                          */
 826                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 827                         if ((in_vbl && position == vbl_start - 1) ||
 828                             (!in_vbl && position == vbl_end - 1))
 829                                 position = (position + 1) % vtotal;
 830                 } else {
 831                         /*
 832                          * ISR vblank status bits don't work the way we'd want
 833                          * them to work on non-PCH platforms (for
 834                          * ilk_pipe_in_vblank_locked()), and there doesn't
 835                          * appear any other way to determine if we're currently
 836                          * in vblank.
 837                          *
 838                          * Instead let's assume that we're already in vblank if
 839                          * we got called from the vblank interrupt and the
 840                          * scanline counter value indicates that we're on the
 841                          * line just prior to vblank start. This should result
 842                          * in the correct answer, unless the vblank interrupt
 843                          * delivery really got delayed for almost exactly one
 844                          * full frame/field.
 845                          */
 846                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 847                             position == vbl_start - 1) {
 848                                 position = (position + 1) % vtotal;
 849
 850                                 /* Signal this correction as "applied". */
 851                                 ret |= 0x8;
 852                         }
 853                 }
 854         } else {
 855                 /* Have access to pixelcount since start of frame.
 856                  * We can split this into vertical and horizontal
 857                  * scanout position.
 858                  */
 859                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 860
 861                 /* convert to pixel counts */
 862                 vbl_start *= htotal;
 863                 vbl_end *= htotal;
 864                 vtotal *= htotal;
 865         }
 866
 867         /* Get optional system timestamp after query. */
 868         if (etime)
 869                 *etime = ktime_get();
 870
 871         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 872
 873         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 874
 875         in_vbl = position >= vbl_start && position < vbl_end;
 876
 877         /*
 878          * While in vblank, position will be negative
 879          * counting up towards 0 at vbl_end. And outside
 880          * vblank, position will be positive counting
 881          * up since vbl_end.
 882          */
 883         if (position >= vbl_start)
 884                 position -= vbl_end;
 885         else
 886                 position += vtotal - vbl_end;
 887
 888         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 889                 *vpos = position;
 890                 *hpos = 0;
 891         } else {
 892                 *vpos = position / htotal;
 893                 *hpos = position - (*vpos * htotal);
 894         }
 895
 896         /* In vblank? */
 897         if (in_vbl)
 898                 ret |= DRM_SCANOUTPOS_INVBL;
 899
 900         return ret;
 901 }
 902
 903 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 904                               int *max_error,
 905                               struct timeval *vblank_time,
 906                               unsigned flags)
 907 {
 908         struct drm_crtc *crtc;
 909
 910         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 911                 DRM_ERROR("Invalid crtc %d\n", pipe);
 912                 return -EINVAL;
 913         }
 914
 915         /* Get drm_crtc to timestamp: */
 916         crtc = intel_get_crtc_for_pipe(dev, pipe);
 917         if (crtc == NULL) {
 918                 DRM_ERROR("Invalid crtc %d\n", pipe);
 919                 return -EINVAL;
 920         }
 921
 922         if (!crtc->enabled) {
 923                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 924                 return -EBUSY;
 925         }
 926
 927         /* Helper routine in DRM core does all the work: */
 928         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 929                                                      vblank_time, flags,
 930                                                      crtc,
 931                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 932 }
 933
 934 static bool intel_hpd_irq_event(struct drm_device *dev,
 935                                 struct drm_connector *connector)
 936 {
 937         enum drm_connector_status old_status;
 938
 939         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 940         old_status = connector->status;
 941
 942         connector->status = connector->funcs->detect(connector, false);
 943         if (old_status == connector->status)
 944                 return false;
 945
 946         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 947                       connector->base.id,
 948                       drm_get_connector_name(connector),
 949                       drm_get_connector_status_name(old_status),
 950                       drm_get_connector_status_name(connector->status));
 951
 952         return true;
 953 }
 954
 955 /*
 956  * Handle hotplug events outside the interrupt handler proper.
 957  */
 958 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 959
 960 static void i915_hotplug_work_func(struct work_struct *work)
 961 {
 962         struct drm_i915_private *dev_priv =
 963                 container_of(work, struct drm_i915_private, hotplug_work);
 964         struct drm_device *dev = dev_priv->dev;
 965         struct drm_mode_config *mode_config = &dev->mode_config;
 966         struct intel_connector *intel_connector;
 967         struct intel_encoder *intel_encoder;
 968         struct drm_connector *connector;
 969         unsigned long irqflags;
 970         bool hpd_disabled = false;
 971         bool changed = false;
 972         u32 hpd_event_bits;
 973
 974         /* HPD irq before everything is fully set up. */
 975         if (!dev_priv->enable_hotplug_processing)
 976                 return;
 977
 978         mutex_lock(&mode_config->mutex);
 979         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 980
 981         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 982
 983         hpd_event_bits = dev_priv->hpd_event_bits;
 984         dev_priv->hpd_event_bits = 0;
 985         list_for_each_entry(connector, &mode_config->connector_list, head) {
 986                 intel_connector = to_intel_connector(connector);
 987                 intel_encoder = intel_connector->encoder;
 988                 if (intel_encoder->hpd_pin > HPD_NONE &&
 989                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 990                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 991                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 992                                  "switching from hotplug detection to polling\n",
 993                                 drm_get_connector_name(connector));
 994                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 995                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 996                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 997                         hpd_disabled = true;
 998                 }
 999                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1000                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1001                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
1002                 }
1003         }
1004          /* if there were no outputs to poll, poll was disabled,
1005           * therefore make sure it's enabled when disabling HPD on
1006           * some connectors */
1007         if (hpd_disabled) {
1008                 drm_kms_helper_poll_enable(dev);
1009                 mod_timer(&dev_priv->hotplug_reenable_timer,
1010                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1011         }
1012
1013         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1014
1015         list_for_each_entry(connector, &mode_config->connector_list, head) {
1016                 intel_connector = to_intel_connector(connector);
1017                 intel_encoder = intel_connector->encoder;
1018                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1019                         if (intel_encoder->hot_plug)
1020                                 intel_encoder->hot_plug(intel_encoder);
1021                         if (intel_hpd_irq_event(dev, connector))
1022                                 changed = true;
1023                 }
1024         }
1025         mutex_unlock(&mode_config->mutex);
1026
1027         if (changed)
1028                 drm_kms_helper_hotplug_event(dev);
1029 }
1030
1031 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1032 {
1033         del_timer_sync(&dev_priv->hotplug_reenable_timer);
1034 }
1035
1036 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         u32 busy_up, busy_down, max_avg, min_avg;
1040         u8 new_delay;
1041
1042         spin_lock(&mchdev_lock);
1043
1044         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1045
1046         new_delay = dev_priv->ips.cur_delay;
1047
1048         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1049         busy_up = I915_READ(RCPREVBSYTUPAVG);
1050         busy_down = I915_READ(RCPREVBSYTDNAVG);
1051         max_avg = I915_READ(RCBMAXAVG);
1052         min_avg = I915_READ(RCBMINAVG);
1053
1054         /* Handle RCS change request from hw */
1055         if (busy_up > max_avg) {
1056                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1057                         new_delay = dev_priv->ips.cur_delay - 1;
1058                 if (new_delay < dev_priv->ips.max_delay)
1059                         new_delay = dev_priv->ips.max_delay;
1060         } else if (busy_down < min_avg) {
1061                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1062                         new_delay = dev_priv->ips.cur_delay + 1;
1063                 if (new_delay > dev_priv->ips.min_delay)
1064                         new_delay = dev_priv->ips.min_delay;
1065         }
1066
1067         if (ironlake_set_drps(dev, new_delay))
1068                 dev_priv->ips.cur_delay = new_delay;
1069
1070         spin_unlock(&mchdev_lock);
1071
1072         return;
1073 }
1074
1075 static void notify_ring(struct drm_device *dev,
1076                         struct intel_ring_buffer *ring)
1077 {
1078         if (ring->obj == NULL)
1079                 return;
1080
1081         trace_i915_gem_request_complete(ring);
1082
1083         wake_up_all(&ring->irq_queue);
1084         i915_queue_hangcheck(dev);
1085 }
1086
1087 static void gen6_pm_rps_work(struct work_struct *work)
1088 {
1089         struct drm_i915_private *dev_priv =
1090                 container_of(work, struct drm_i915_private, rps.work);
1091         u32 pm_iir;
1092         int new_delay, adj;
1093
1094         spin_lock_irq(&dev_priv->irq_lock);
1095         pm_iir = dev_priv->rps.pm_iir;
1096         dev_priv->rps.pm_iir = 0;
1097         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1098         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1099         spin_unlock_irq(&dev_priv->irq_lock);
1100
1101         /* Make sure we didn't queue anything we're not going to process. */
1102         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1103
1104         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1105                 return;
1106
1107         mutex_lock(&dev_priv->rps.hw_lock);
1108
1109         adj = dev_priv->rps.last_adj;
1110         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1111                 if (adj > 0)
1112                         adj *= 2;
1113                 else
1114                         adj = 1;
1115                 new_delay = dev_priv->rps.cur_freq + adj;
1116
1117                 /*
1118                  * For better performance, jump directly
1119                  * to RPe if we're below it.
1120                  */
1121                 if (new_delay < dev_priv->rps.efficient_freq)
1122                         new_delay = dev_priv->rps.efficient_freq;
1123         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1124                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1125                         new_delay = dev_priv->rps.efficient_freq;
1126                 else
1127                         new_delay = dev_priv->rps.min_freq_softlimit;
1128                 adj = 0;
1129         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1130                 if (adj < 0)
1131                         adj *= 2;
1132                 else
1133                         adj = -1;
1134                 new_delay = dev_priv->rps.cur_freq + adj;
1135         } else { /* unknown event */
1136                 new_delay = dev_priv->rps.cur_freq;
1137         }
1138
1139         /* sysfs frequency interfaces may have snuck in while servicing the
1140          * interrupt
1141          */
1142         new_delay = clamp_t(int, new_delay,
1143                             dev_priv->rps.min_freq_softlimit,
1144                             dev_priv->rps.max_freq_softlimit);
1145
1146         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1147
1148         if (IS_VALLEYVIEW(dev_priv->dev))
1149                 valleyview_set_rps(dev_priv->dev, new_delay);
1150         else
1151                 gen6_set_rps(dev_priv->dev, new_delay);
1152
1153         mutex_unlock(&dev_priv->rps.hw_lock);
1154 }
1155
1156
1157 /**
1158  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1159  * occurred.
1160  * @work: workqueue struct
1161  *
1162  * Doesn't actually do anything except notify userspace. As a consequence of
1163  * this event, userspace should try to remap the bad rows since statistically
1164  * it is likely the same row is more likely to go bad again.
1165  */
1166 static void ivybridge_parity_work(struct work_struct *work)
1167 {
1168         struct drm_i915_private *dev_priv =
1169                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1170         u32 error_status, row, bank, subbank;
1171         char *parity_event[6];
1172         uint32_t misccpctl;
1173         unsigned long flags;
1174         uint8_t slice = 0;
1175
1176         /* We must turn off DOP level clock gating to access the L3 registers.
1177          * In order to prevent a get/put style interface, acquire struct mutex
1178          * any time we access those registers.
1179          */
1180         mutex_lock(&dev_priv->dev->struct_mutex);
1181
1182         /* If we've screwed up tracking, just let the interrupt fire again */
1183         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1184                 goto out;
1185
1186         misccpctl = I915_READ(GEN7_MISCCPCTL);
1187         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1188         POSTING_READ(GEN7_MISCCPCTL);
1189
1190         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1191                 u32 reg;
1192
1193                 slice--;
1194                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1195                         break;
1196
1197                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1198
1199                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1200
1201                 error_status = I915_READ(reg);
1202                 row = GEN7_PARITY_ERROR_ROW(error_status);
1203                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1204                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1205
1206                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1207                 POSTING_READ(reg);
1208
1209                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1210                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1211                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1212                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1213                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1214                 parity_event[5] = NULL;
1215
1216                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1217                                    KOBJ_CHANGE, parity_event);
1218
1219                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1220                           slice, row, bank, subbank);
1221
1222                 kfree(parity_event[4]);
1223                 kfree(parity_event[3]);
1224                 kfree(parity_event[2]);
1225                 kfree(parity_event[1]);
1226         }
1227
1228         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1229
1230 out:
1231         WARN_ON(dev_priv->l3_parity.which_slice);
1232         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1233         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1234         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1235
1236         mutex_unlock(&dev_priv->dev->struct_mutex);
1237 }
1238
1239 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1240 {
1241         struct drm_i915_private *dev_priv = dev->dev_private;
1242
1243         if (!HAS_L3_DPF(dev))
1244                 return;
1245
1246         spin_lock(&dev_priv->irq_lock);
1247         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1248         spin_unlock(&dev_priv->irq_lock);
1249
1250         iir &= GT_PARITY_ERROR(dev);
1251         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1252                 dev_priv->l3_parity.which_slice |= 1 << 1;
1253
1254         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1255                 dev_priv->l3_parity.which_slice |= 1 << 0;
1256
1257         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1258 }
1259
1260 static void ilk_gt_irq_handler(struct drm_device *dev,
1261                                struct drm_i915_private *dev_priv,
1262                                u32 gt_iir)
1263 {
1264         if (gt_iir &
1265             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1266                 notify_ring(dev, &dev_priv->ring[RCS]);
1267         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1268                 notify_ring(dev, &dev_priv->ring[VCS]);
1269 }
1270
1271 static void snb_gt_irq_handler(struct drm_device *dev,
1272                                struct drm_i915_private *dev_priv,
1273                                u32 gt_iir)
1274 {
1275
1276         if (gt_iir &
1277             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1278                 notify_ring(dev, &dev_priv->ring[RCS]);
1279         if (gt_iir & GT_BSD_USER_INTERRUPT)
1280                 notify_ring(dev, &dev_priv->ring[VCS]);
1281         if (gt_iir & GT_BLT_USER_INTERRUPT)
1282                 notify_ring(dev, &dev_priv->ring[BCS]);
1283
1284         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1285                       GT_BSD_CS_ERROR_INTERRUPT |
1286                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1287                 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1288                                   gt_iir);
1289         }
1290
1291         if (gt_iir & GT_PARITY_ERROR(dev))
1292                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1293 }
1294
1295 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1296                                        struct drm_i915_private *dev_priv,
1297                                        u32 master_ctl)
1298 {
1299         u32 rcs, bcs, vcs;
1300         uint32_t tmp = 0;
1301         irqreturn_t ret = IRQ_NONE;
1302
1303         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1304                 tmp = I915_READ(GEN8_GT_IIR(0));
1305                 if (tmp) {
1306                         ret = IRQ_HANDLED;
1307                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1308                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1309                         if (rcs & GT_RENDER_USER_INTERRUPT)
1310                                 notify_ring(dev, &dev_priv->ring[RCS]);
1311                         if (bcs & GT_RENDER_USER_INTERRUPT)
1312                                 notify_ring(dev, &dev_priv->ring[BCS]);
1313                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1314                 } else
1315                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1316         }
1317
1318         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1319                 tmp = I915_READ(GEN8_GT_IIR(1));
1320                 if (tmp) {
1321                         ret = IRQ_HANDLED;
1322                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1323                         if (vcs & GT_RENDER_USER_INTERRUPT)
1324                                 notify_ring(dev, &dev_priv->ring[VCS]);
1325                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1326                 } else
1327                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1328         }
1329
1330         if (master_ctl & GEN8_GT_VECS_IRQ) {
1331                 tmp = I915_READ(GEN8_GT_IIR(3));
1332                 if (tmp) {
1333                         ret = IRQ_HANDLED;
1334                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1335                         if (vcs & GT_RENDER_USER_INTERRUPT)
1336                                 notify_ring(dev, &dev_priv->ring[VECS]);
1337                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1338                 } else
1339                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1340         }
1341
1342         return ret;
1343 }
1344
1345 #define HPD_STORM_DETECT_PERIOD 1000
1346 #define HPD_STORM_THRESHOLD 5
1347
1348 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1349                                          u32 hotplug_trigger,
1350                                          const u32 *hpd)
1351 {
1352         struct drm_i915_private *dev_priv = dev->dev_private;
1353         int i;
1354         bool storm_detected = false;
1355
1356         if (!hotplug_trigger)
1357                 return;
1358
1359         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1360                           hotplug_trigger);
1361
1362         spin_lock(&dev_priv->irq_lock);
1363         for (i = 1; i < HPD_NUM_PINS; i++) {
1364
1365                 WARN_ONCE(hpd[i] & hotplug_trigger &&
1366                           dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1367                           "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1368                           hotplug_trigger, i, hpd[i]);
1369
1370                 if (!(hpd[i] & hotplug_trigger) ||
1371                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1372                         continue;
1373
1374                 dev_priv->hpd_event_bits |= (1 << i);
1375                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1376                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1377                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1378                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1379                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1380                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1381                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1382                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1383                         dev_priv->hpd_event_bits &= ~(1 << i);
1384                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1385                         storm_detected = true;
1386                 } else {
1387                         dev_priv->hpd_stats[i].hpd_cnt++;
1388                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1389                                       dev_priv->hpd_stats[i].hpd_cnt);
1390                 }
1391         }
1392
1393         if (storm_detected)
1394                 dev_priv->display.hpd_irq_setup(dev);
1395         spin_unlock(&dev_priv->irq_lock);
1396
1397         /*
1398          * Our hotplug handler can grab modeset locks (by calling down into the
1399          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1400          * queue for otherwise the flush_work in the pageflip code will
1401          * deadlock.
1402          */
1403         schedule_work(&dev_priv->hotplug_work);
1404 }
1405
1406 static void gmbus_irq_handler(struct drm_device *dev)
1407 {
1408         struct drm_i915_private *dev_priv = dev->dev_private;
1409
1410         wake_up_all(&dev_priv->gmbus_wait_queue);
1411 }
1412
1413 static void dp_aux_irq_handler(struct drm_device *dev)
1414 {
1415         struct drm_i915_private *dev_priv = dev->dev_private;
1416
1417         wake_up_all(&dev_priv->gmbus_wait_queue);
1418 }
1419
1420 #if defined(CONFIG_DEBUG_FS)
1421 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1422                                          uint32_t crc0, uint32_t crc1,
1423                                          uint32_t crc2, uint32_t crc3,
1424                                          uint32_t crc4)
1425 {
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1428         struct intel_pipe_crc_entry *entry;
1429         int head, tail;
1430
1431         spin_lock(&pipe_crc->lock);
1432
1433         if (!pipe_crc->entries) {
1434                 spin_unlock(&pipe_crc->lock);
1435                 DRM_ERROR("spurious interrupt\n");
1436                 return;
1437         }
1438
1439         head = pipe_crc->head;
1440         tail = pipe_crc->tail;
1441
1442         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1443                 spin_unlock(&pipe_crc->lock);
1444                 DRM_ERROR("CRC buffer overflowing\n");
1445                 return;
1446         }
1447
1448         entry = &pipe_crc->entries[head];
1449
1450         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1451         entry->crc[0] = crc0;
1452         entry->crc[1] = crc1;
1453         entry->crc[2] = crc2;
1454         entry->crc[3] = crc3;
1455         entry->crc[4] = crc4;
1456
1457         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1458         pipe_crc->head = head;
1459
1460         spin_unlock(&pipe_crc->lock);
1461
1462         wake_up_interruptible(&pipe_crc->wq);
1463 }
1464 #else
1465 static inline void
1466 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1467                              uint32_t crc0, uint32_t crc1,
1468                              uint32_t crc2, uint32_t crc3,
1469                              uint32_t crc4) {}
1470 #endif
1471
1472
1473 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1474 {
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476
1477         display_pipe_crc_irq_handler(dev, pipe,
1478                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1479                                      0, 0, 0, 0);
1480 }
1481
1482 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1483 {
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485
1486         display_pipe_crc_irq_handler(dev, pipe,
1487                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1488                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1489                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1490                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1491                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1492 }
1493
1494 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1495 {
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         uint32_t res1, res2;
1498
1499         if (INTEL_INFO(dev)->gen >= 3)
1500                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1501         else
1502                 res1 = 0;
1503
1504         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1505                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1506         else
1507                 res2 = 0;
1508
1509         display_pipe_crc_irq_handler(dev, pipe,
1510                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1511                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1512                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1513                                      res1, res2);
1514 }
1515
1516 /* The RPS events need forcewake, so we add them to a work queue and mask their
1517  * IMR bits until the work is done. Other interrupts can be processed without
1518  * the work queue. */
1519 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1520 {
1521         if (pm_iir & dev_priv->pm_rps_events) {
1522                 spin_lock(&dev_priv->irq_lock);
1523                 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1524                 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1525                 spin_unlock(&dev_priv->irq_lock);
1526
1527                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1528         }
1529
1530         if (HAS_VEBOX(dev_priv->dev)) {
1531                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1532                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1533
1534                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1535                         i915_handle_error(dev_priv->dev, false,
1536                                           "VEBOX CS error interrupt 0x%08x",
1537                                           pm_iir);
1538                 }
1539         }
1540 }
1541
1542 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1543 {
1544         struct drm_i915_private *dev_priv = dev->dev_private;
1545         u32 pipe_stats[I915_MAX_PIPES] = { };
1546         int pipe;
1547
1548         spin_lock(&dev_priv->irq_lock);
1549         for_each_pipe(pipe) {
1550                 int reg;
1551                 u32 mask, iir_bit = 0;
1552
1553                 /*
1554                  * PIPESTAT bits get signalled even when the interrupt is
1555                  * disabled with the mask bits, and some of the status bits do
1556                  * not generate interrupts at all (like the underrun bit). Hence
1557                  * we need to be careful that we only handle what we want to
1558                  * handle.
1559                  */
1560                 mask = 0;
1561                 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1562                         mask |= PIPE_FIFO_UNDERRUN_STATUS;
1563
1564                 switch (pipe) {
1565                 case PIPE_A:
1566                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1567                         break;
1568                 case PIPE_B:
1569                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1570                         break;
1571                 }
1572                 if (iir & iir_bit)
1573                         mask |= dev_priv->pipestat_irq_mask[pipe];
1574
1575                 if (!mask)
1576                         continue;
1577
1578                 reg = PIPESTAT(pipe);
1579                 mask |= PIPESTAT_INT_ENABLE_MASK;
1580                 pipe_stats[pipe] = I915_READ(reg) & mask;
1581
1582                 /*
1583                  * Clear the PIPE*STAT regs before the IIR
1584                  */
1585                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1586                                         PIPESTAT_INT_STATUS_MASK))
1587                         I915_WRITE(reg, pipe_stats[pipe]);
1588         }
1589         spin_unlock(&dev_priv->irq_lock);
1590
1591         for_each_pipe(pipe) {
1592                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1593                         drm_handle_vblank(dev, pipe);
1594
1595                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1596                         intel_prepare_page_flip(dev, pipe);
1597                         intel_finish_page_flip(dev, pipe);
1598                 }
1599
1600                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1601                         i9xx_pipe_crc_irq_handler(dev, pipe);
1602
1603                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1604                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1605                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1606         }
1607
1608         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1609                 gmbus_irq_handler(dev);
1610 }
1611
1612 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1613 {
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1616
1617         if (IS_G4X(dev)) {
1618                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1619
1620                 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1621         } else {
1622                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1623
1624                 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1625         }
1626
1627         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1628             hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1629                 dp_aux_irq_handler(dev);
1630
1631         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1632         /*
1633          * Make sure hotplug status is cleared before we clear IIR, or else we
1634          * may miss hotplug events.
1635          */
1636         POSTING_READ(PORT_HOTPLUG_STAT);
1637 }
1638
1639 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1640 {
1641         struct drm_device *dev = (struct drm_device *) arg;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         u32 iir, gt_iir, pm_iir;
1644         irqreturn_t ret = IRQ_NONE;
1645
1646         while (true) {
1647                 iir = I915_READ(VLV_IIR);
1648                 gt_iir = I915_READ(GTIIR);
1649                 pm_iir = I915_READ(GEN6_PMIIR);
1650
1651                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1652                         goto out;
1653
1654                 ret = IRQ_HANDLED;
1655
1656                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1657
1658                 valleyview_pipestat_irq_handler(dev, iir);
1659
1660                 /* Consume port.  Then clear IIR or we'll miss events */
1661                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1662                         i9xx_hpd_irq_handler(dev);
1663
1664                 if (pm_iir)
1665                         gen6_rps_irq_handler(dev_priv, pm_iir);
1666
1667                 I915_WRITE(GTIIR, gt_iir);
1668                 I915_WRITE(GEN6_PMIIR, pm_iir);
1669                 I915_WRITE(VLV_IIR, iir);
1670         }
1671
1672 out:
1673         return ret;
1674 }
1675
1676 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1677 {
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         int pipe;
1680         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1681
1682         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1683
1684         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1685                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1686                                SDE_AUDIO_POWER_SHIFT);
1687                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1688                                  port_name(port));
1689         }
1690
1691         if (pch_iir & SDE_AUX_MASK)
1692                 dp_aux_irq_handler(dev);
1693
1694         if (pch_iir & SDE_GMBUS)
1695                 gmbus_irq_handler(dev);
1696
1697         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1698                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1699
1700         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1701                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1702
1703         if (pch_iir & SDE_POISON)
1704                 DRM_ERROR("PCH poison interrupt\n");
1705
1706         if (pch_iir & SDE_FDI_MASK)
1707                 for_each_pipe(pipe)
1708                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1709                                          pipe_name(pipe),
1710                                          I915_READ(FDI_RX_IIR(pipe)));
1711
1712         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1713                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1714
1715         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1716                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1717
1718         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1719                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1720                                                           false))
1721                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1722
1723         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1724                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1725                                                           false))
1726                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1727 }
1728
1729 static void ivb_err_int_handler(struct drm_device *dev)
1730 {
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         u32 err_int = I915_READ(GEN7_ERR_INT);
1733         enum pipe pipe;
1734
1735         if (err_int & ERR_INT_POISON)
1736                 DRM_ERROR("Poison interrupt\n");
1737
1738         for_each_pipe(pipe) {
1739                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1740                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1741                                                                   false))
1742                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1743                                           pipe_name(pipe));
1744                 }
1745
1746                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1747                         if (IS_IVYBRIDGE(dev))
1748                                 ivb_pipe_crc_irq_handler(dev, pipe);
1749                         else
1750                                 hsw_pipe_crc_irq_handler(dev, pipe);
1751                 }
1752         }
1753
1754         I915_WRITE(GEN7_ERR_INT, err_int);
1755 }
1756
1757 static void cpt_serr_int_handler(struct drm_device *dev)
1758 {
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         u32 serr_int = I915_READ(SERR_INT);
1761
1762         if (serr_int & SERR_INT_POISON)
1763                 DRM_ERROR("PCH poison interrupt\n");
1764
1765         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1766                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1767                                                           false))
1768                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1769
1770         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1771                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1772                                                           false))
1773                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1774
1775         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1776                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1777                                                           false))
1778                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
1779
1780         I915_WRITE(SERR_INT, serr_int);
1781 }
1782
1783 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1784 {
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786         int pipe;
1787         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1788
1789         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1790
1791         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1792                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1793                                SDE_AUDIO_POWER_SHIFT_CPT);
1794                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1795                                  port_name(port));
1796         }
1797
1798         if (pch_iir & SDE_AUX_MASK_CPT)
1799                 dp_aux_irq_handler(dev);
1800
1801         if (pch_iir & SDE_GMBUS_CPT)
1802                 gmbus_irq_handler(dev);
1803
1804         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1805                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1806
1807         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1808                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1809
1810         if (pch_iir & SDE_FDI_MASK_CPT)
1811                 for_each_pipe(pipe)
1812                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1813                                          pipe_name(pipe),
1814                                          I915_READ(FDI_RX_IIR(pipe)));
1815
1816         if (pch_iir & SDE_ERROR_CPT)
1817                 cpt_serr_int_handler(dev);
1818 }
1819
1820 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1821 {
1822         struct drm_i915_private *dev_priv = dev->dev_private;
1823         enum pipe pipe;
1824
1825         if (de_iir & DE_AUX_CHANNEL_A)
1826                 dp_aux_irq_handler(dev);
1827
1828         if (de_iir & DE_GSE)
1829                 intel_opregion_asle_intr(dev);
1830
1831         if (de_iir & DE_POISON)
1832                 DRM_ERROR("Poison interrupt\n");
1833
1834         for_each_pipe(pipe) {
1835                 if (de_iir & DE_PIPE_VBLANK(pipe))
1836                         drm_handle_vblank(dev, pipe);
1837
1838                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1839                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1840                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1841                                           pipe_name(pipe));
1842
1843                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1844                         i9xx_pipe_crc_irq_handler(dev, pipe);
1845
1846                 /* plane/pipes map 1:1 on ilk+ */
1847                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1848                         intel_prepare_page_flip(dev, pipe);
1849                         intel_finish_page_flip_plane(dev, pipe);
1850                 }
1851         }
1852
1853         /* check event from PCH */
1854         if (de_iir & DE_PCH_EVENT) {
1855                 u32 pch_iir = I915_READ(SDEIIR);
1856
1857                 if (HAS_PCH_CPT(dev))
1858                         cpt_irq_handler(dev, pch_iir);
1859                 else
1860                         ibx_irq_handler(dev, pch_iir);
1861
1862                 /* should clear PCH hotplug event before clear CPU irq */
1863                 I915_WRITE(SDEIIR, pch_iir);
1864         }
1865
1866         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1867                 ironlake_rps_change_irq_handler(dev);
1868 }
1869
1870 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1871 {
1872         struct drm_i915_private *dev_priv = dev->dev_private;
1873         enum pipe pipe;
1874
1875         if (de_iir & DE_ERR_INT_IVB)
1876                 ivb_err_int_handler(dev);
1877
1878         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1879                 dp_aux_irq_handler(dev);
1880
1881         if (de_iir & DE_GSE_IVB)
1882                 intel_opregion_asle_intr(dev);
1883
1884         for_each_pipe(pipe) {
1885                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1886                         drm_handle_vblank(dev, pipe);
1887
1888                 /* plane/pipes map 1:1 on ilk+ */
1889                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1890                         intel_prepare_page_flip(dev, pipe);
1891                         intel_finish_page_flip_plane(dev, pipe);
1892                 }
1893         }
1894
1895         /* check event from PCH */
1896         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1897                 u32 pch_iir = I915_READ(SDEIIR);
1898
1899                 cpt_irq_handler(dev, pch_iir);
1900
1901                 /* clear PCH hotplug event before clear CPU irq */
1902                 I915_WRITE(SDEIIR, pch_iir);
1903         }
1904 }
1905
1906 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1907 {
1908         struct drm_device *dev = (struct drm_device *) arg;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1911         irqreturn_t ret = IRQ_NONE;
1912
1913         /* We get interrupts on unclaimed registers, so check for this before we
1914          * do any I915_{READ,WRITE}. */
1915         intel_uncore_check_errors(dev);
1916
1917         /* disable master interrupt before clearing iir  */
1918         de_ier = I915_READ(DEIER);
1919         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1920         POSTING_READ(DEIER);
1921
1922         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1923          * interrupts will will be stored on its back queue, and then we'll be
1924          * able to process them after we restore SDEIER (as soon as we restore
1925          * it, we'll get an interrupt if SDEIIR still has something to process
1926          * due to its back queue). */
1927         if (!HAS_PCH_NOP(dev)) {
1928                 sde_ier = I915_READ(SDEIER);
1929                 I915_WRITE(SDEIER, 0);
1930                 POSTING_READ(SDEIER);
1931         }
1932
1933         gt_iir = I915_READ(GTIIR);
1934         if (gt_iir) {
1935                 if (INTEL_INFO(dev)->gen >= 6)
1936                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1937                 else
1938                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1939                 I915_WRITE(GTIIR, gt_iir);
1940                 ret = IRQ_HANDLED;
1941         }
1942
1943         de_iir = I915_READ(DEIIR);
1944         if (de_iir) {
1945                 if (INTEL_INFO(dev)->gen >= 7)
1946                         ivb_display_irq_handler(dev, de_iir);
1947                 else
1948                         ilk_display_irq_handler(dev, de_iir);
1949                 I915_WRITE(DEIIR, de_iir);
1950                 ret = IRQ_HANDLED;
1951         }
1952
1953         if (INTEL_INFO(dev)->gen >= 6) {
1954                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1955                 if (pm_iir) {
1956                         gen6_rps_irq_handler(dev_priv, pm_iir);
1957                         I915_WRITE(GEN6_PMIIR, pm_iir);
1958                         ret = IRQ_HANDLED;
1959                 }
1960         }
1961
1962         I915_WRITE(DEIER, de_ier);
1963         POSTING_READ(DEIER);
1964         if (!HAS_PCH_NOP(dev)) {
1965                 I915_WRITE(SDEIER, sde_ier);
1966                 POSTING_READ(SDEIER);
1967         }
1968
1969         return ret;
1970 }
1971
1972 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1973 {
1974         struct drm_device *dev = arg;
1975         struct drm_i915_private *dev_priv = dev->dev_private;
1976         u32 master_ctl;
1977         irqreturn_t ret = IRQ_NONE;
1978         uint32_t tmp = 0;
1979         enum pipe pipe;
1980
1981         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1982         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1983         if (!master_ctl)
1984                 return IRQ_NONE;
1985
1986         I915_WRITE(GEN8_MASTER_IRQ, 0);
1987         POSTING_READ(GEN8_MASTER_IRQ);
1988
1989         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1990
1991         if (master_ctl & GEN8_DE_MISC_IRQ) {
1992                 tmp = I915_READ(GEN8_DE_MISC_IIR);
1993                 if (tmp & GEN8_DE_MISC_GSE)
1994                         intel_opregion_asle_intr(dev);
1995                 else if (tmp)
1996                         DRM_ERROR("Unexpected DE Misc interrupt\n");
1997                 else
1998                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1999
2000                 if (tmp) {
2001                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2002                         ret = IRQ_HANDLED;
2003                 }
2004         }
2005
2006         if (master_ctl & GEN8_DE_PORT_IRQ) {
2007                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2008                 if (tmp & GEN8_AUX_CHANNEL_A)
2009                         dp_aux_irq_handler(dev);
2010                 else if (tmp)
2011                         DRM_ERROR("Unexpected DE Port interrupt\n");
2012                 else
2013                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2014
2015                 if (tmp) {
2016                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2017                         ret = IRQ_HANDLED;
2018                 }
2019         }
2020
2021         for_each_pipe(pipe) {
2022                 uint32_t pipe_iir;
2023
2024                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2025                         continue;
2026
2027                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2028                 if (pipe_iir & GEN8_PIPE_VBLANK)
2029                         drm_handle_vblank(dev, pipe);
2030
2031                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2032                         intel_prepare_page_flip(dev, pipe);
2033                         intel_finish_page_flip_plane(dev, pipe);
2034                 }
2035
2036                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2037                         hsw_pipe_crc_irq_handler(dev, pipe);
2038
2039                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2040                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2041                                                                   false))
2042                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2043                                           pipe_name(pipe));
2044                 }
2045
2046                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2047                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2048                                   pipe_name(pipe),
2049                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2050                 }
2051
2052                 if (pipe_iir) {
2053                         ret = IRQ_HANDLED;
2054                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2055                 } else
2056                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2057         }
2058
2059         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2060                 /*
2061                  * FIXME(BDW): Assume for now that the new interrupt handling
2062                  * scheme also closed the SDE interrupt handling race we've seen
2063                  * on older pch-split platforms. But this needs testing.
2064                  */
2065                 u32 pch_iir = I915_READ(SDEIIR);
2066
2067                 cpt_irq_handler(dev, pch_iir);
2068
2069                 if (pch_iir) {
2070                         I915_WRITE(SDEIIR, pch_iir);
2071                         ret = IRQ_HANDLED;
2072                 }
2073         }
2074
2075         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2076         POSTING_READ(GEN8_MASTER_IRQ);
2077
2078         return ret;
2079 }
2080
2081 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2082                                bool reset_completed)
2083 {
2084         struct intel_ring_buffer *ring;
2085         int i;
2086
2087         /*
2088          * Notify all waiters for GPU completion events that reset state has
2089          * been changed, and that they need to restart their wait after
2090          * checking for potential errors (and bail out to drop locks if there is
2091          * a gpu reset pending so that i915_error_work_func can acquire them).
2092          */
2093
2094         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2095         for_each_ring(ring, dev_priv, i)
2096                 wake_up_all(&ring->irq_queue);
2097
2098         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2099         wake_up_all(&dev_priv->pending_flip_queue);
2100
2101         /*
2102          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2103          * reset state is cleared.
2104          */
2105         if (reset_completed)
2106                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2107 }
2108
2109 /**
2110  * i915_error_work_func - do process context error handling work
2111  * @work: work struct
2112  *
2113  * Fire an error uevent so userspace can see that a hang or error
2114  * was detected.
2115  */
2116 static void i915_error_work_func(struct work_struct *work)
2117 {
2118         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2119                                                     work);
2120         struct drm_i915_private *dev_priv =
2121                 container_of(error, struct drm_i915_private, gpu_error);
2122         struct drm_device *dev = dev_priv->dev;
2123         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2124         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2125         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2126         int ret;
2127
2128         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2129
2130         /*
2131          * Note that there's only one work item which does gpu resets, so we
2132          * need not worry about concurrent gpu resets potentially incrementing
2133          * error->reset_counter twice. We only need to take care of another
2134          * racing irq/hangcheck declaring the gpu dead for a second time. A
2135          * quick check for that is good enough: schedule_work ensures the
2136          * correct ordering between hang detection and this work item, and since
2137          * the reset in-progress bit is only ever set by code outside of this
2138          * work we don't need to worry about any other races.
2139          */
2140         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2141                 DRM_DEBUG_DRIVER("resetting chip\n");
2142                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2143                                    reset_event);
2144
2145                 /*
2146                  * All state reset _must_ be completed before we update the
2147                  * reset counter, for otherwise waiters might miss the reset
2148                  * pending state and not properly drop locks, resulting in
2149                  * deadlocks with the reset work.
2150                  */
2151                 ret = i915_reset(dev);
2152
2153                 intel_display_handle_reset(dev);
2154
2155                 if (ret == 0) {
2156                         /*
2157                          * After all the gem state is reset, increment the reset
2158                          * counter and wake up everyone waiting for the reset to
2159                          * complete.
2160                          *
2161                          * Since unlock operations are a one-sided barrier only,
2162                          * we need to insert a barrier here to order any seqno
2163                          * updates before
2164                          * the counter increment.
2165                          */
2166                         smp_mb__before_atomic_inc();
2167                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2168
2169                         kobject_uevent_env(&dev->primary->kdev->kobj,
2170                                            KOBJ_CHANGE, reset_done_event);
2171                 } else {
2172                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2173                 }
2174
2175                 /*
2176                  * Note: The wake_up also serves as a memory barrier so that
2177                  * waiters see the update value of the reset counter atomic_t.
2178                  */
2179                 i915_error_wake_up(dev_priv, true);
2180         }
2181 }
2182
2183 static void i915_report_and_clear_eir(struct drm_device *dev)
2184 {
2185         struct drm_i915_private *dev_priv = dev->dev_private;
2186         uint32_t instdone[I915_NUM_INSTDONE_REG];
2187         u32 eir = I915_READ(EIR);
2188         int pipe, i;
2189
2190         if (!eir)
2191                 return;
2192
2193         pr_err("render error detected, EIR: 0x%08x\n", eir);
2194
2195         i915_get_extra_instdone(dev, instdone);
2196
2197         if (IS_G4X(dev)) {
2198                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2199                         u32 ipeir = I915_READ(IPEIR_I965);
2200
2201                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2202                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2203                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2204                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2205                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2206                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2207                         I915_WRITE(IPEIR_I965, ipeir);
2208                         POSTING_READ(IPEIR_I965);
2209                 }
2210                 if (eir & GM45_ERROR_PAGE_TABLE) {
2211                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2212                         pr_err("page table error\n");
2213                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2214                         I915_WRITE(PGTBL_ER, pgtbl_err);
2215                         POSTING_READ(PGTBL_ER);
2216                 }
2217         }
2218
2219         if (!IS_GEN2(dev)) {
2220                 if (eir & I915_ERROR_PAGE_TABLE) {
2221                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2222                         pr_err("page table error\n");
2223                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2224                         I915_WRITE(PGTBL_ER, pgtbl_err);
2225                         POSTING_READ(PGTBL_ER);
2226                 }
2227         }
2228
2229         if (eir & I915_ERROR_MEMORY_REFRESH) {
2230                 pr_err("memory refresh error:\n");
2231                 for_each_pipe(pipe)
2232                         pr_err("pipe %c stat: 0x%08x\n",
2233                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2234                 /* pipestat has already been acked */
2235         }
2236         if (eir & I915_ERROR_INSTRUCTION) {
2237                 pr_err("instruction error\n");
2238                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2239                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2240                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2241                 if (INTEL_INFO(dev)->gen < 4) {
2242                         u32 ipeir = I915_READ(IPEIR);
2243
2244                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2245                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2246                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2247                         I915_WRITE(IPEIR, ipeir);
2248                         POSTING_READ(IPEIR);
2249                 } else {
2250                         u32 ipeir = I915_READ(IPEIR_I965);
2251
2252                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2253                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2254                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2255                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2256                         I915_WRITE(IPEIR_I965, ipeir);
2257                         POSTING_READ(IPEIR_I965);
2258                 }
2259         }
2260
2261         I915_WRITE(EIR, eir);
2262         POSTING_READ(EIR);
2263         eir = I915_READ(EIR);
2264         if (eir) {
2265                 /*
2266                  * some errors might have become stuck,
2267                  * mask them.
2268                  */
2269                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2270                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2271                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2272         }
2273 }
2274
2275 /**
2276  * i915_handle_error - handle an error interrupt
2277  * @dev: drm device
2278  *
2279  * Do some basic checking of regsiter state at error interrupt time and
2280  * dump it to the syslog.  Also call i915_capture_error_state() to make
2281  * sure we get a record and make it available in debugfs.  Fire a uevent
2282  * so userspace knows something bad happened (should trigger collection
2283  * of a ring dump etc.).
2284  */
2285 void i915_handle_error(struct drm_device *dev, bool wedged,
2286                        const char *fmt, ...)
2287 {
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         va_list args;
2290         char error_msg[80];
2291
2292         va_start(args, fmt);
2293         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2294         va_end(args);
2295
2296         i915_capture_error_state(dev, wedged, error_msg);
2297         i915_report_and_clear_eir(dev);
2298
2299         if (wedged) {
2300                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2301                                 &dev_priv->gpu_error.reset_counter);
2302
2303                 /*
2304                  * Wakeup waiting processes so that the reset work function
2305                  * i915_error_work_func doesn't deadlock trying to grab various
2306                  * locks. By bumping the reset counter first, the woken
2307                  * processes will see a reset in progress and back off,
2308                  * releasing their locks and then wait for the reset completion.
2309                  * We must do this for _all_ gpu waiters that might hold locks
2310                  * that the reset work needs to acquire.
2311                  *
2312                  * Note: The wake_up serves as the required memory barrier to
2313                  * ensure that the waiters see the updated value of the reset
2314                  * counter atomic_t.
2315                  */
2316                 i915_error_wake_up(dev_priv, false);
2317         }
2318
2319         /*
2320          * Our reset work can grab modeset locks (since it needs to reset the
2321          * state of outstanding pagelips). Hence it must not be run on our own
2322          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2323          * code will deadlock.
2324          */
2325         schedule_work(&dev_priv->gpu_error.work);
2326 }
2327
2328 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2329 {
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333         struct drm_i915_gem_object *obj;
2334         struct intel_unpin_work *work;
2335         unsigned long flags;
2336         bool stall_detected;
2337
2338         /* Ignore early vblank irqs */
2339         if (intel_crtc == NULL)
2340                 return;
2341
2342         spin_lock_irqsave(&dev->event_lock, flags);
2343         work = intel_crtc->unpin_work;
2344
2345         if (work == NULL ||
2346             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2347             !work->enable_stall_check) {
2348                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2349                 spin_unlock_irqrestore(&dev->event_lock, flags);
2350                 return;
2351         }
2352
2353         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2354         obj = work->pending_flip_obj;
2355         if (INTEL_INFO(dev)->gen >= 4) {
2356                 int dspsurf = DSPSURF(intel_crtc->plane);
2357                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2358                                         i915_gem_obj_ggtt_offset(obj);
2359         } else {
2360                 int dspaddr = DSPADDR(intel_crtc->plane);
2361                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2362                                                         crtc->y * crtc->fb->pitches[0] +
2363                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2364         }
2365
2366         spin_unlock_irqrestore(&dev->event_lock, flags);
2367
2368         if (stall_detected) {
2369                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2370                 intel_prepare_page_flip(dev, intel_crtc->plane);
2371         }
2372 }
2373
2374 /* Called from drm generic code, passed 'crtc' which
2375  * we use as a pipe index
2376  */
2377 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         unsigned long irqflags;
2381
2382         if (!i915_pipe_enabled(dev, pipe))
2383                 return -EINVAL;
2384
2385         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2386         if (INTEL_INFO(dev)->gen >= 4)
2387                 i915_enable_pipestat(dev_priv, pipe,
2388                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2389         else
2390                 i915_enable_pipestat(dev_priv, pipe,
2391                                      PIPE_VBLANK_INTERRUPT_STATUS);
2392
2393         /* maintain vblank delivery even in deep C-states */
2394         if (INTEL_INFO(dev)->gen == 3)
2395                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2396         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2397
2398         return 0;
2399 }
2400
2401 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2402 {
2403         struct drm_i915_private *dev_priv = dev->dev_private;
2404         unsigned long irqflags;
2405         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2406                                                      DE_PIPE_VBLANK(pipe);
2407
2408         if (!i915_pipe_enabled(dev, pipe))
2409                 return -EINVAL;
2410
2411         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2412         ironlake_enable_display_irq(dev_priv, bit);
2413         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2414
2415         return 0;
2416 }
2417
2418 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2419 {
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         unsigned long irqflags;
2422
2423         if (!i915_pipe_enabled(dev, pipe))
2424                 return -EINVAL;
2425
2426         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2427         i915_enable_pipestat(dev_priv, pipe,
2428                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2429         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2430
2431         return 0;
2432 }
2433
2434 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2435 {
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         unsigned long irqflags;
2438
2439         if (!i915_pipe_enabled(dev, pipe))
2440                 return -EINVAL;
2441
2442         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2443         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2444         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2445         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2446         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2447         return 0;
2448 }
2449
2450 /* Called from drm generic code, passed 'crtc' which
2451  * we use as a pipe index
2452  */
2453 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2454 {
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         unsigned long irqflags;
2457
2458         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2459         if (INTEL_INFO(dev)->gen == 3)
2460                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2461
2462         i915_disable_pipestat(dev_priv, pipe,
2463                               PIPE_VBLANK_INTERRUPT_STATUS |
2464                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2465         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2466 }
2467
2468 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2469 {
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         unsigned long irqflags;
2472         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2473                                                      DE_PIPE_VBLANK(pipe);
2474
2475         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2476         ironlake_disable_display_irq(dev_priv, bit);
2477         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2478 }
2479
2480 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2481 {
2482         struct drm_i915_private *dev_priv = dev->dev_private;
2483         unsigned long irqflags;
2484
2485         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2486         i915_disable_pipestat(dev_priv, pipe,
2487                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2488         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2489 }
2490
2491 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2492 {
2493         struct drm_i915_private *dev_priv = dev->dev_private;
2494         unsigned long irqflags;
2495
2496         if (!i915_pipe_enabled(dev, pipe))
2497                 return;
2498
2499         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2500         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2501         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2502         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2503         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2504 }
2505
2506 static u32
2507 ring_last_seqno(struct intel_ring_buffer *ring)
2508 {
2509         return list_entry(ring->request_list.prev,
2510                           struct drm_i915_gem_request, list)->seqno;
2511 }
2512
2513 static bool
2514 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2515 {
2516         return (list_empty(&ring->request_list) ||
2517                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2518 }
2519
2520 static bool
2521 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2522 {
2523         if (INTEL_INFO(dev)->gen >= 8) {
2524                 /*
2525                  * FIXME: gen8 semaphore support - currently we don't emit
2526                  * semaphores on bdw anyway, but this needs to be addressed when
2527                  * we merge that code.
2528                  */
2529                 return false;
2530         } else {
2531                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2532                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2533                                  MI_SEMAPHORE_REGISTER);
2534         }
2535 }
2536
2537 static struct intel_ring_buffer *
2538 semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
2539 {
2540         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2541         struct intel_ring_buffer *signaller;
2542         int i;
2543
2544         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2545                 /*
2546                  * FIXME: gen8 semaphore support - currently we don't emit
2547                  * semaphores on bdw anyway, but this needs to be addressed when
2548                  * we merge that code.
2549                  */
2550                 return NULL;
2551         } else {
2552                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2553
2554                 for_each_ring(signaller, dev_priv, i) {
2555                         if(ring == signaller)
2556                                 continue;
2557
2558                         if (sync_bits ==
2559                             signaller->semaphore_register[ring->id])
2560                                 return signaller;
2561                 }
2562         }
2563
2564         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2565                   ring->id, ipehr);
2566
2567         return NULL;
2568 }
2569
2570 static struct intel_ring_buffer *
2571 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2572 {
2573         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2574         u32 cmd, ipehr, head;
2575         int i;
2576
2577         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2578         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2579                 return NULL;
2580
2581         /*
2582          * HEAD is likely pointing to the dword after the actual command,
2583          * so scan backwards until we find the MBOX. But limit it to just 3
2584          * dwords. Note that we don't care about ACTHD here since that might
2585          * point at at batch, and semaphores are always emitted into the
2586          * ringbuffer itself.
2587          */
2588         head = I915_READ_HEAD(ring) & HEAD_ADDR;
2589
2590         for (i = 4; i; --i) {
2591                 /*
2592                  * Be paranoid and presume the hw has gone off into the wild -
2593                  * our ring is smaller than what the hardware (and hence
2594                  * HEAD_ADDR) allows. Also handles wrap-around.
2595                  */
2596                 head &= ring->size - 1;
2597
2598                 /* This here seems to blow up */
2599                 cmd = ioread32(ring->virtual_start + head);
2600                 if (cmd == ipehr)
2601                         break;
2602
2603                 head -= 4;
2604         }
2605
2606         if (!i)
2607                 return NULL;
2608
2609         *seqno = ioread32(ring->virtual_start + head + 4) + 1;
2610         return semaphore_wait_to_signaller_ring(ring, ipehr);
2611 }
2612
2613 static int semaphore_passed(struct intel_ring_buffer *ring)
2614 {
2615         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2616         struct intel_ring_buffer *signaller;
2617         u32 seqno, ctl;
2618
2619         ring->hangcheck.deadlock = true;
2620
2621         signaller = semaphore_waits_for(ring, &seqno);
2622         if (signaller == NULL || signaller->hangcheck.deadlock)
2623                 return -1;
2624
2625         /* cursory check for an unkickable deadlock */
2626         ctl = I915_READ_CTL(signaller);
2627         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2628                 return -1;
2629
2630         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2631 }
2632
2633 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2634 {
2635         struct intel_ring_buffer *ring;
2636         int i;
2637
2638         for_each_ring(ring, dev_priv, i)
2639                 ring->hangcheck.deadlock = false;
2640 }
2641
2642 static enum intel_ring_hangcheck_action
2643 ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
2644 {
2645         struct drm_device *dev = ring->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         u32 tmp;
2648
2649         if (ring->hangcheck.acthd != acthd)
2650                 return HANGCHECK_ACTIVE;
2651
2652         if (IS_GEN2(dev))
2653                 return HANGCHECK_HUNG;
2654
2655         /* Is the chip hanging on a WAIT_FOR_EVENT?
2656          * If so we can simply poke the RB_WAIT bit
2657          * and break the hang. This should work on
2658          * all but the second generation chipsets.
2659          */
2660         tmp = I915_READ_CTL(ring);
2661         if (tmp & RING_WAIT) {
2662                 i915_handle_error(dev, false,
2663                                   "Kicking stuck wait on %s",
2664                                   ring->name);
2665                 I915_WRITE_CTL(ring, tmp);
2666                 return HANGCHECK_KICK;
2667         }
2668
2669         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2670                 switch (semaphore_passed(ring)) {
2671                 default:
2672                         return HANGCHECK_HUNG;
2673                 case 1:
2674                         i915_handle_error(dev, false,
2675                                           "Kicking stuck semaphore on %s",
2676                                           ring->name);
2677                         I915_WRITE_CTL(ring, tmp);
2678                         return HANGCHECK_KICK;
2679                 case 0:
2680                         return HANGCHECK_WAIT;
2681                 }
2682         }
2683
2684         return HANGCHECK_HUNG;
2685 }
2686
2687 /**
2688  * This is called when the chip hasn't reported back with completed
2689  * batchbuffers in a long time. We keep track per ring seqno progress and
2690  * if there are no progress, hangcheck score for that ring is increased.
2691  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2692  * we kick the ring. If we see no progress on three subsequent calls
2693  * we assume chip is wedged and try to fix it by resetting the chip.
2694  */
2695 static void i915_hangcheck_elapsed(unsigned long data)
2696 {
2697         struct drm_device *dev = (struct drm_device *)data;
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct intel_ring_buffer *ring;
2700         int i;
2701         int busy_count = 0, rings_hung = 0;
2702         bool stuck[I915_NUM_RINGS] = { 0 };
2703 #define BUSY 1
2704 #define KICK 5
2705 #define HUNG 20
2706
2707         if (!i915.enable_hangcheck)
2708                 return;
2709
2710         for_each_ring(ring, dev_priv, i) {
2711                 u64 acthd;
2712                 u32 seqno;
2713                 bool busy = true;
2714
2715                 semaphore_clear_deadlocks(dev_priv);
2716
2717                 seqno = ring->get_seqno(ring, false);
2718                 acthd = intel_ring_get_active_head(ring);
2719
2720                 if (ring->hangcheck.seqno == seqno) {
2721                         if (ring_idle(ring, seqno)) {
2722                                 ring->hangcheck.action = HANGCHECK_IDLE;
2723
2724                                 if (waitqueue_active(&ring->irq_queue)) {
2725                                         /* Issue a wake-up to catch stuck h/w. */
2726                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2727                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2728                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2729                                                                   ring->name);
2730                                                 else
2731                                                         DRM_INFO("Fake missed irq on %s\n",
2732                                                                  ring->name);
2733                                                 wake_up_all(&ring->irq_queue);
2734                                         }
2735                                         /* Safeguard against driver failure */
2736                                         ring->hangcheck.score += BUSY;
2737                                 } else
2738                                         busy = false;
2739                         } else {
2740                                 /* We always increment the hangcheck score
2741                                  * if the ring is busy and still processing
2742                                  * the same request, so that no single request
2743                                  * can run indefinitely (such as a chain of
2744                                  * batches). The only time we do not increment
2745                                  * the hangcheck score on this ring, if this
2746                                  * ring is in a legitimate wait for another
2747                                  * ring. In that case the waiting ring is a
2748                                  * victim and we want to be sure we catch the
2749                                  * right culprit. Then every time we do kick
2750                                  * the ring, add a small increment to the
2751                                  * score so that we can catch a batch that is
2752                                  * being repeatedly kicked and so responsible
2753                                  * for stalling the machine.
2754                                  */
2755                                 ring->hangcheck.action = ring_stuck(ring,
2756                                                                     acthd);
2757
2758                                 switch (ring->hangcheck.action) {
2759                                 case HANGCHECK_IDLE:
2760                                 case HANGCHECK_WAIT:
2761                                         break;
2762                                 case HANGCHECK_ACTIVE:
2763                                         ring->hangcheck.score += BUSY;
2764                                         break;
2765                                 case HANGCHECK_KICK:
2766                                         ring->hangcheck.score += KICK;
2767                                         break;
2768                                 case HANGCHECK_HUNG:
2769                                         ring->hangcheck.score += HUNG;
2770                                         stuck[i] = true;
2771                                         break;
2772                                 }
2773                         }
2774                 } else {
2775                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2776
2777                         /* Gradually reduce the count so that we catch DoS
2778                          * attempts across multiple batches.
2779                          */
2780                         if (ring->hangcheck.score > 0)
2781                                 ring->hangcheck.score--;
2782                 }
2783
2784                 ring->hangcheck.seqno = seqno;
2785                 ring->hangcheck.acthd = acthd;
2786                 busy_count += busy;
2787         }
2788
2789         for_each_ring(ring, dev_priv, i) {
2790                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2791                         DRM_INFO("%s on %s\n",
2792                                  stuck[i] ? "stuck" : "no progress",
2793                                  ring->name);
2794                         rings_hung++;
2795                 }
2796         }
2797
2798         if (rings_hung)
2799                 return i915_handle_error(dev, true, "Ring hung");
2800
2801         if (busy_count)
2802                 /* Reset timer case chip hangs without another request
2803                  * being added */
2804                 i915_queue_hangcheck(dev);
2805 }
2806
2807 void i915_queue_hangcheck(struct drm_device *dev)
2808 {
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         if (!i915.enable_hangcheck)
2811                 return;
2812
2813         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2814                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2815 }
2816
2817 static void ibx_irq_preinstall(struct drm_device *dev)
2818 {
2819         struct drm_i915_private *dev_priv = dev->dev_private;
2820
2821         if (HAS_PCH_NOP(dev))
2822                 return;
2823
2824         /* south display irq */
2825         I915_WRITE(SDEIMR, 0xffffffff);
2826         /*
2827          * SDEIER is also touched by the interrupt handler to work around missed
2828          * PCH interrupts. Hence we can't update it after the interrupt handler
2829          * is enabled - instead we unconditionally enable all PCH interrupt
2830          * sources here, but then only unmask them as needed with SDEIMR.
2831          */
2832         I915_WRITE(SDEIER, 0xffffffff);
2833         POSTING_READ(SDEIER);
2834 }
2835
2836 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2837 {
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839
2840         /* and GT */
2841         I915_WRITE(GTIMR, 0xffffffff);
2842         I915_WRITE(GTIER, 0x0);
2843         POSTING_READ(GTIER);
2844
2845         if (INTEL_INFO(dev)->gen >= 6) {
2846                 /* and PM */
2847                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2848                 I915_WRITE(GEN6_PMIER, 0x0);
2849                 POSTING_READ(GEN6_PMIER);
2850         }
2851 }
2852
2853 /* drm_dma.h hooks
2854 */
2855 static void ironlake_irq_preinstall(struct drm_device *dev)
2856 {
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858
2859         I915_WRITE(HWSTAM, 0xeffe);
2860
2861         I915_WRITE(DEIMR, 0xffffffff);
2862         I915_WRITE(DEIER, 0x0);
2863         POSTING_READ(DEIER);
2864
2865         gen5_gt_irq_preinstall(dev);
2866
2867         ibx_irq_preinstall(dev);
2868 }
2869
2870 static void valleyview_irq_preinstall(struct drm_device *dev)
2871 {
2872         struct drm_i915_private *dev_priv = dev->dev_private;
2873         int pipe;
2874
2875         /* VLV magic */
2876         I915_WRITE(VLV_IMR, 0);
2877         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2878         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2879         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2880
2881         /* and GT */
2882         I915_WRITE(GTIIR, I915_READ(GTIIR));
2883         I915_WRITE(GTIIR, I915_READ(GTIIR));
2884
2885         gen5_gt_irq_preinstall(dev);
2886
2887         I915_WRITE(DPINVGTT, 0xff);
2888
2889         I915_WRITE(PORT_HOTPLUG_EN, 0);
2890         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2891         for_each_pipe(pipe)
2892                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2893         I915_WRITE(VLV_IIR, 0xffffffff);
2894         I915_WRITE(VLV_IMR, 0xffffffff);
2895         I915_WRITE(VLV_IER, 0x0);
2896         POSTING_READ(VLV_IER);
2897 }
2898
2899 static void gen8_irq_preinstall(struct drm_device *dev)
2900 {
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         int pipe;
2903
2904         I915_WRITE(GEN8_MASTER_IRQ, 0);
2905         POSTING_READ(GEN8_MASTER_IRQ);
2906
2907         /* IIR can theoretically queue up two events. Be paranoid */
2908 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2909                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2910                 POSTING_READ(GEN8_##type##_IMR(which)); \
2911                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2912                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2913                 POSTING_READ(GEN8_##type##_IIR(which)); \
2914                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2915         } while (0)
2916
2917 #define GEN8_IRQ_INIT(type) do { \
2918                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2919                 POSTING_READ(GEN8_##type##_IMR); \
2920                 I915_WRITE(GEN8_##type##_IER, 0); \
2921                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2922                 POSTING_READ(GEN8_##type##_IIR); \
2923                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2924         } while (0)
2925
2926         GEN8_IRQ_INIT_NDX(GT, 0);
2927         GEN8_IRQ_INIT_NDX(GT, 1);
2928         GEN8_IRQ_INIT_NDX(GT, 2);
2929         GEN8_IRQ_INIT_NDX(GT, 3);
2930
2931         for_each_pipe(pipe) {
2932                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2933         }
2934
2935         GEN8_IRQ_INIT(DE_PORT);
2936         GEN8_IRQ_INIT(DE_MISC);
2937         GEN8_IRQ_INIT(PCU);
2938 #undef GEN8_IRQ_INIT
2939 #undef GEN8_IRQ_INIT_NDX
2940
2941         POSTING_READ(GEN8_PCU_IIR);
2942
2943         ibx_irq_preinstall(dev);
2944 }
2945
2946 static void ibx_hpd_irq_setup(struct drm_device *dev)
2947 {
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         struct drm_mode_config *mode_config = &dev->mode_config;
2950         struct intel_encoder *intel_encoder;
2951         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2952
2953         if (HAS_PCH_IBX(dev)) {
2954                 hotplug_irqs = SDE_HOTPLUG_MASK;
2955                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2956                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2957                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2958         } else {
2959                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2960                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2961                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2962                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2963         }
2964
2965         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2966
2967         /*
2968          * Enable digital hotplug on the PCH, and configure the DP short pulse
2969          * duration to 2ms (which is the minimum in the Display Port spec)
2970          *
2971          * This register is the same on all known PCH chips.
2972          */
2973         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2974         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2975         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2976         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2977         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2978         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2979 }
2980
2981 static void ibx_irq_postinstall(struct drm_device *dev)
2982 {
2983         struct drm_i915_private *dev_priv = dev->dev_private;
2984         u32 mask;
2985
2986         if (HAS_PCH_NOP(dev))
2987                 return;
2988
2989         if (HAS_PCH_IBX(dev)) {
2990                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
2991         } else {
2992                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2993
2994                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2995         }
2996
2997         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2998         I915_WRITE(SDEIMR, ~mask);
2999 }
3000
3001 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         u32 pm_irqs, gt_irqs;
3005
3006         pm_irqs = gt_irqs = 0;
3007
3008         dev_priv->gt_irq_mask = ~0;
3009         if (HAS_L3_DPF(dev)) {
3010                 /* L3 parity interrupt is always unmasked. */
3011                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3012                 gt_irqs |= GT_PARITY_ERROR(dev);
3013         }
3014
3015         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3016         if (IS_GEN5(dev)) {
3017                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3018                            ILK_BSD_USER_INTERRUPT;
3019         } else {
3020                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3021         }
3022
3023         I915_WRITE(GTIIR, I915_READ(GTIIR));
3024         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3025         I915_WRITE(GTIER, gt_irqs);
3026         POSTING_READ(GTIER);
3027
3028         if (INTEL_INFO(dev)->gen >= 6) {
3029                 pm_irqs |= dev_priv->pm_rps_events;
3030
3031                 if (HAS_VEBOX(dev))
3032                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3033
3034                 dev_priv->pm_irq_mask = 0xffffffff;
3035                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3036                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
3037                 I915_WRITE(GEN6_PMIER, pm_irqs);
3038                 POSTING_READ(GEN6_PMIER);
3039         }
3040 }
3041
3042 static int ironlake_irq_postinstall(struct drm_device *dev)
3043 {
3044         unsigned long irqflags;
3045         struct drm_i915_private *dev_priv = dev->dev_private;
3046         u32 display_mask, extra_mask;
3047
3048         if (INTEL_INFO(dev)->gen >= 7) {
3049                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3050                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3051                                 DE_PLANEB_FLIP_DONE_IVB |
3052                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3053                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3054                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3055
3056                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3057         } else {
3058                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3059                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3060                                 DE_AUX_CHANNEL_A |
3061                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3062                                 DE_POISON);
3063                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3064                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3065         }
3066
3067         dev_priv->irq_mask = ~display_mask;
3068
3069         /* should always can generate irq */
3070         I915_WRITE(DEIIR, I915_READ(DEIIR));
3071         I915_WRITE(DEIMR, dev_priv->irq_mask);
3072         I915_WRITE(DEIER, display_mask | extra_mask);
3073         POSTING_READ(DEIER);
3074
3075         gen5_gt_irq_postinstall(dev);
3076
3077         ibx_irq_postinstall(dev);
3078
3079         if (IS_IRONLAKE_M(dev)) {
3080                 /* Enable PCU event interrupts
3081                  *
3082                  * spinlocking not required here for correctness since interrupt
3083                  * setup is guaranteed to run in single-threaded context. But we
3084                  * need it to make the assert_spin_locked happy. */
3085                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3086                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3087                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3088         }
3089
3090         return 0;
3091 }
3092
3093 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3094 {
3095         u32 pipestat_mask;
3096         u32 iir_mask;
3097
3098         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3099                         PIPE_FIFO_UNDERRUN_STATUS;
3100
3101         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3102         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3103         POSTING_READ(PIPESTAT(PIPE_A));
3104
3105         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3106                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3107
3108         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3109                                                PIPE_GMBUS_INTERRUPT_STATUS);
3110         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3111
3112         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3113                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3114                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3115         dev_priv->irq_mask &= ~iir_mask;
3116
3117         I915_WRITE(VLV_IIR, iir_mask);
3118         I915_WRITE(VLV_IIR, iir_mask);
3119         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3120         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3121         POSTING_READ(VLV_IER);
3122 }
3123
3124 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3125 {
3126         u32 pipestat_mask;
3127         u32 iir_mask;
3128
3129         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3130                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3131                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3132
3133         dev_priv->irq_mask |= iir_mask;
3134         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3135         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3136         I915_WRITE(VLV_IIR, iir_mask);
3137         I915_WRITE(VLV_IIR, iir_mask);
3138         POSTING_READ(VLV_IIR);
3139
3140         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3141                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3142
3143         i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3144                                                 PIPE_GMBUS_INTERRUPT_STATUS);
3145         i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3146
3147         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3148                         PIPE_FIFO_UNDERRUN_STATUS;
3149         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3150         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3151         POSTING_READ(PIPESTAT(PIPE_A));
3152 }
3153
3154 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3155 {
3156         assert_spin_locked(&dev_priv->irq_lock);
3157
3158         if (dev_priv->display_irqs_enabled)
3159                 return;
3160
3161         dev_priv->display_irqs_enabled = true;
3162
3163         if (dev_priv->dev->irq_enabled)
3164                 valleyview_display_irqs_install(dev_priv);
3165 }
3166
3167 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3168 {
3169         assert_spin_locked(&dev_priv->irq_lock);
3170
3171         if (!dev_priv->display_irqs_enabled)
3172                 return;
3173
3174         dev_priv->display_irqs_enabled = false;
3175
3176         if (dev_priv->dev->irq_enabled)
3177                 valleyview_display_irqs_uninstall(dev_priv);
3178 }
3179
3180 static int valleyview_irq_postinstall(struct drm_device *dev)
3181 {
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         unsigned long irqflags;
3184
3185         dev_priv->irq_mask = ~0;
3186
3187         I915_WRITE(PORT_HOTPLUG_EN, 0);
3188         POSTING_READ(PORT_HOTPLUG_EN);
3189
3190         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3191         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3192         I915_WRITE(VLV_IIR, 0xffffffff);
3193         POSTING_READ(VLV_IER);
3194
3195         /* Interrupt setup is already guaranteed to be single-threaded, this is
3196          * just to make the assert_spin_locked check happy. */
3197         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3198         if (dev_priv->display_irqs_enabled)
3199                 valleyview_display_irqs_install(dev_priv);
3200         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3201
3202         I915_WRITE(VLV_IIR, 0xffffffff);
3203         I915_WRITE(VLV_IIR, 0xffffffff);
3204
3205         gen5_gt_irq_postinstall(dev);
3206
3207         /* ack & enable invalid PTE error interrupts */
3208 #if 0 /* FIXME: add support to irq handler for checking these bits */
3209         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3210         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3211 #endif
3212
3213         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3214
3215         return 0;
3216 }
3217
3218 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3219 {
3220         int i;
3221
3222         /* These are interrupts we'll toggle with the ring mask register */
3223         uint32_t gt_interrupts[] = {
3224                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3225                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3226                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3227                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3228                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3229                 0,
3230                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3231                 };
3232
3233         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
3234                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
3235                 if (tmp)
3236                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3237                                   i, tmp);
3238                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
3239                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
3240         }
3241         POSTING_READ(GEN8_GT_IER(0));
3242 }
3243
3244 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3245 {
3246         struct drm_device *dev = dev_priv->dev;
3247         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3248                 GEN8_PIPE_CDCLK_CRC_DONE |
3249                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3250         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3251                 GEN8_PIPE_FIFO_UNDERRUN;
3252         int pipe;
3253         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3254         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3255         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3256
3257         for_each_pipe(pipe) {
3258                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3259                 if (tmp)
3260                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3261                                   pipe, tmp);
3262                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3263                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3264         }
3265         POSTING_READ(GEN8_DE_PIPE_ISR(0));
3266
3267         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3268         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3269         POSTING_READ(GEN8_DE_PORT_IER);
3270 }
3271
3272 static int gen8_irq_postinstall(struct drm_device *dev)
3273 {
3274         struct drm_i915_private *dev_priv = dev->dev_private;
3275
3276         gen8_gt_irq_postinstall(dev_priv);
3277         gen8_de_irq_postinstall(dev_priv);
3278
3279         ibx_irq_postinstall(dev);
3280
3281         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3282         POSTING_READ(GEN8_MASTER_IRQ);
3283
3284         return 0;
3285 }
3286
3287 static void gen8_irq_uninstall(struct drm_device *dev)
3288 {
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290         int pipe;
3291
3292         if (!dev_priv)
3293                 return;
3294
3295         I915_WRITE(GEN8_MASTER_IRQ, 0);
3296
3297 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3298                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3299                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3300                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3301         } while (0)
3302
3303 #define GEN8_IRQ_FINI(type) do { \
3304                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3305                 I915_WRITE(GEN8_##type##_IER, 0); \
3306                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3307         } while (0)
3308
3309         GEN8_IRQ_FINI_NDX(GT, 0);
3310         GEN8_IRQ_FINI_NDX(GT, 1);
3311         GEN8_IRQ_FINI_NDX(GT, 2);
3312         GEN8_IRQ_FINI_NDX(GT, 3);
3313
3314         for_each_pipe(pipe) {
3315                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3316         }
3317
3318         GEN8_IRQ_FINI(DE_PORT);
3319         GEN8_IRQ_FINI(DE_MISC);
3320         GEN8_IRQ_FINI(PCU);
3321 #undef GEN8_IRQ_FINI
3322 #undef GEN8_IRQ_FINI_NDX
3323
3324         POSTING_READ(GEN8_PCU_IIR);
3325 }
3326
3327 static void valleyview_irq_uninstall(struct drm_device *dev)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         unsigned long irqflags;
3331         int pipe;
3332
3333         if (!dev_priv)
3334                 return;
3335
3336         intel_hpd_irq_uninstall(dev_priv);
3337
3338         for_each_pipe(pipe)
3339                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3340
3341         I915_WRITE(HWSTAM, 0xffffffff);
3342         I915_WRITE(PORT_HOTPLUG_EN, 0);
3343         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3344
3345         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3346         if (dev_priv->display_irqs_enabled)
3347                 valleyview_display_irqs_uninstall(dev_priv);
3348         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3349
3350         dev_priv->irq_mask = 0;
3351
3352         I915_WRITE(VLV_IIR, 0xffffffff);
3353         I915_WRITE(VLV_IMR, 0xffffffff);
3354         I915_WRITE(VLV_IER, 0x0);
3355         POSTING_READ(VLV_IER);
3356 }
3357
3358 static void ironlake_irq_uninstall(struct drm_device *dev)
3359 {
3360         struct drm_i915_private *dev_priv = dev->dev_private;
3361
3362         if (!dev_priv)
3363                 return;
3364
3365         intel_hpd_irq_uninstall(dev_priv);
3366
3367         I915_WRITE(HWSTAM, 0xffffffff);
3368
3369         I915_WRITE(DEIMR, 0xffffffff);
3370         I915_WRITE(DEIER, 0x0);
3371         I915_WRITE(DEIIR, I915_READ(DEIIR));
3372         if (IS_GEN7(dev))
3373                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3374
3375         I915_WRITE(GTIMR, 0xffffffff);
3376         I915_WRITE(GTIER, 0x0);
3377         I915_WRITE(GTIIR, I915_READ(GTIIR));
3378
3379         if (HAS_PCH_NOP(dev))
3380                 return;
3381
3382         I915_WRITE(SDEIMR, 0xffffffff);
3383         I915_WRITE(SDEIER, 0x0);
3384         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3385         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3386                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3387 }
3388
3389 static void i8xx_irq_preinstall(struct drm_device * dev)
3390 {
3391         struct drm_i915_private *dev_priv = dev->dev_private;
3392         int pipe;
3393
3394         for_each_pipe(pipe)
3395                 I915_WRITE(PIPESTAT(pipe), 0);
3396         I915_WRITE16(IMR, 0xffff);
3397         I915_WRITE16(IER, 0x0);
3398         POSTING_READ16(IER);
3399 }
3400
3401 static int i8xx_irq_postinstall(struct drm_device *dev)
3402 {
3403         struct drm_i915_private *dev_priv = dev->dev_private;
3404         unsigned long irqflags;
3405
3406         I915_WRITE16(EMR,
3407                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3408
3409         /* Unmask the interrupts that we always want on. */
3410         dev_priv->irq_mask =
3411                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3412                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3413                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3414                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3415                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3416         I915_WRITE16(IMR, dev_priv->irq_mask);
3417
3418         I915_WRITE16(IER,
3419                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3420                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3421                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3422                      I915_USER_INTERRUPT);
3423         POSTING_READ16(IER);
3424
3425         /* Interrupt setup is already guaranteed to be single-threaded, this is
3426          * just to make the assert_spin_locked check happy. */
3427         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3428         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3429         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3430         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3431
3432         return 0;
3433 }
3434
3435 /*
3436  * Returns true when a page flip has completed.
3437  */
3438 static bool i8xx_handle_vblank(struct drm_device *dev,
3439                                int plane, int pipe, u32 iir)
3440 {
3441         struct drm_i915_private *dev_priv = dev->dev_private;
3442         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3443
3444         if (!drm_handle_vblank(dev, pipe))
3445                 return false;
3446
3447         if ((iir & flip_pending) == 0)
3448                 return false;
3449
3450         intel_prepare_page_flip(dev, plane);
3451
3452         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3453          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3454          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3455          * the flip is completed (no longer pending). Since this doesn't raise
3456          * an interrupt per se, we watch for the change at vblank.
3457          */
3458         if (I915_READ16(ISR) & flip_pending)
3459                 return false;
3460
3461         intel_finish_page_flip(dev, pipe);
3462
3463         return true;
3464 }
3465
3466 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3467 {
3468         struct drm_device *dev = (struct drm_device *) arg;
3469         struct drm_i915_private *dev_priv = dev->dev_private;
3470         u16 iir, new_iir;
3471         u32 pipe_stats[2];
3472         unsigned long irqflags;
3473         int pipe;
3474         u16 flip_mask =
3475                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3476                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3477
3478         iir = I915_READ16(IIR);
3479         if (iir == 0)
3480                 return IRQ_NONE;
3481
3482         while (iir & ~flip_mask) {
3483                 /* Can't rely on pipestat interrupt bit in iir as it might
3484                  * have been cleared after the pipestat interrupt was received.
3485                  * It doesn't set the bit in iir again, but it still produces
3486                  * interrupts (for non-MSI).
3487                  */
3488                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3489                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3490                         i915_handle_error(dev, false,
3491                                           "Command parser error, iir 0x%08x",
3492                                           iir);
3493
3494                 for_each_pipe(pipe) {
3495                         int reg = PIPESTAT(pipe);
3496                         pipe_stats[pipe] = I915_READ(reg);
3497
3498                         /*
3499                          * Clear the PIPE*STAT regs before the IIR
3500                          */
3501                         if (pipe_stats[pipe] & 0x8000ffff)
3502                                 I915_WRITE(reg, pipe_stats[pipe]);
3503                 }
3504                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3505
3506                 I915_WRITE16(IIR, iir & ~flip_mask);
3507                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3508
3509                 i915_update_dri1_breadcrumb(dev);
3510
3511                 if (iir & I915_USER_INTERRUPT)
3512                         notify_ring(dev, &dev_priv->ring[RCS]);
3513
3514                 for_each_pipe(pipe) {
3515                         int plane = pipe;
3516                         if (HAS_FBC(dev))
3517                                 plane = !plane;
3518
3519                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3520                             i8xx_handle_vblank(dev, plane, pipe, iir))
3521                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3522
3523                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3524                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3525
3526                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3527                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3528                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3529                 }
3530
3531                 iir = new_iir;
3532         }
3533
3534         return IRQ_HANDLED;
3535 }
3536
3537 static void i8xx_irq_uninstall(struct drm_device * dev)
3538 {
3539         struct drm_i915_private *dev_priv = dev->dev_private;
3540         int pipe;
3541
3542         for_each_pipe(pipe) {
3543                 /* Clear enable bits; then clear status bits */
3544                 I915_WRITE(PIPESTAT(pipe), 0);
3545                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3546         }
3547         I915_WRITE16(IMR, 0xffff);
3548         I915_WRITE16(IER, 0x0);
3549         I915_WRITE16(IIR, I915_READ16(IIR));
3550 }
3551
3552 static void i915_irq_preinstall(struct drm_device * dev)
3553 {
3554         struct drm_i915_private *dev_priv = dev->dev_private;
3555         int pipe;
3556
3557         if (I915_HAS_HOTPLUG(dev)) {
3558                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3559                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3560         }
3561
3562         I915_WRITE16(HWSTAM, 0xeffe);
3563         for_each_pipe(pipe)
3564                 I915_WRITE(PIPESTAT(pipe), 0);
3565         I915_WRITE(IMR, 0xffffffff);
3566         I915_WRITE(IER, 0x0);
3567         POSTING_READ(IER);
3568 }
3569
3570 static int i915_irq_postinstall(struct drm_device *dev)
3571 {
3572         struct drm_i915_private *dev_priv = dev->dev_private;
3573         u32 enable_mask;
3574         unsigned long irqflags;
3575
3576         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3577
3578         /* Unmask the interrupts that we always want on. */
3579         dev_priv->irq_mask =
3580                 ~(I915_ASLE_INTERRUPT |
3581                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3582                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3583                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3584                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3585                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3586
3587         enable_mask =
3588                 I915_ASLE_INTERRUPT |
3589                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3590                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3591                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3592                 I915_USER_INTERRUPT;
3593
3594         if (I915_HAS_HOTPLUG(dev)) {
3595                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3596                 POSTING_READ(PORT_HOTPLUG_EN);
3597
3598                 /* Enable in IER... */
3599                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3600                 /* and unmask in IMR */
3601                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3602         }
3603
3604         I915_WRITE(IMR, dev_priv->irq_mask);
3605         I915_WRITE(IER, enable_mask);
3606         POSTING_READ(IER);
3607
3608         i915_enable_asle_pipestat(dev);
3609
3610         /* Interrupt setup is already guaranteed to be single-threaded, this is
3611          * just to make the assert_spin_locked check happy. */
3612         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3613         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3614         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3615         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3616
3617         return 0;
3618 }
3619
3620 /*
3621  * Returns true when a page flip has completed.
3622  */
3623 static bool i915_handle_vblank(struct drm_device *dev,
3624                                int plane, int pipe, u32 iir)
3625 {
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3628
3629         if (!drm_handle_vblank(dev, pipe))
3630                 return false;
3631
3632         if ((iir & flip_pending) == 0)
3633                 return false;
3634
3635         intel_prepare_page_flip(dev, plane);
3636
3637         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3638          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3639          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3640          * the flip is completed (no longer pending). Since this doesn't raise
3641          * an interrupt per se, we watch for the change at vblank.
3642          */
3643         if (I915_READ(ISR) & flip_pending)
3644                 return false;
3645
3646         intel_finish_page_flip(dev, pipe);
3647
3648         return true;
3649 }
3650
3651 static irqreturn_t i915_irq_handler(int irq, void *arg)
3652 {
3653         struct drm_device *dev = (struct drm_device *) arg;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3656         unsigned long irqflags;
3657         u32 flip_mask =
3658                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3659                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3660         int pipe, ret = IRQ_NONE;
3661
3662         iir = I915_READ(IIR);
3663         do {
3664                 bool irq_received = (iir & ~flip_mask) != 0;
3665                 bool blc_event = false;
3666
3667                 /* Can't rely on pipestat interrupt bit in iir as it might
3668                  * have been cleared after the pipestat interrupt was received.
3669                  * It doesn't set the bit in iir again, but it still produces
3670                  * interrupts (for non-MSI).
3671                  */
3672                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3673                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3674                         i915_handle_error(dev, false,
3675                                           "Command parser error, iir 0x%08x",
3676                                           iir);
3677
3678                 for_each_pipe(pipe) {
3679                         int reg = PIPESTAT(pipe);
3680                         pipe_stats[pipe] = I915_READ(reg);
3681
3682                         /* Clear the PIPE*STAT regs before the IIR */
3683                         if (pipe_stats[pipe] & 0x8000ffff) {
3684                                 I915_WRITE(reg, pipe_stats[pipe]);
3685                                 irq_received = true;
3686                         }
3687                 }
3688                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3689
3690                 if (!irq_received)
3691                         break;
3692
3693                 /* Consume port.  Then clear IIR or we'll miss events */
3694                 if (I915_HAS_HOTPLUG(dev) &&
3695                     iir & I915_DISPLAY_PORT_INTERRUPT)
3696                         i9xx_hpd_irq_handler(dev);
3697
3698                 I915_WRITE(IIR, iir & ~flip_mask);
3699                 new_iir = I915_READ(IIR); /* Flush posted writes */
3700
3701                 if (iir & I915_USER_INTERRUPT)
3702                         notify_ring(dev, &dev_priv->ring[RCS]);
3703
3704                 for_each_pipe(pipe) {
3705                         int plane = pipe;
3706                         if (HAS_FBC(dev))
3707                                 plane = !plane;
3708
3709                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3710                             i915_handle_vblank(dev, plane, pipe, iir))
3711                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3712
3713                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3714                                 blc_event = true;
3715
3716                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3717                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3718
3719                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3720                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3721                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3722                 }
3723
3724                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3725                         intel_opregion_asle_intr(dev);
3726
3727                 /* With MSI, interrupts are only generated when iir
3728                  * transitions from zero to nonzero.  If another bit got
3729                  * set while we were handling the existing iir bits, then
3730                  * we would never get another interrupt.
3731                  *
3732                  * This is fine on non-MSI as well, as if we hit this path
3733                  * we avoid exiting the interrupt handler only to generate
3734                  * another one.
3735                  *
3736                  * Note that for MSI this could cause a stray interrupt report
3737                  * if an interrupt landed in the time between writing IIR and
3738                  * the posting read.  This should be rare enough to never
3739                  * trigger the 99% of 100,000 interrupts test for disabling
3740                  * stray interrupts.
3741                  */
3742                 ret = IRQ_HANDLED;
3743                 iir = new_iir;
3744         } while (iir & ~flip_mask);
3745
3746         i915_update_dri1_breadcrumb(dev);
3747
3748         return ret;
3749 }
3750
3751 static void i915_irq_uninstall(struct drm_device * dev)
3752 {
3753         struct drm_i915_private *dev_priv = dev->dev_private;
3754         int pipe;
3755
3756         intel_hpd_irq_uninstall(dev_priv);
3757
3758         if (I915_HAS_HOTPLUG(dev)) {
3759                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3760                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3761         }
3762
3763         I915_WRITE16(HWSTAM, 0xffff);
3764         for_each_pipe(pipe) {
3765                 /* Clear enable bits; then clear status bits */
3766                 I915_WRITE(PIPESTAT(pipe), 0);
3767                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3768         }
3769         I915_WRITE(IMR, 0xffffffff);
3770         I915_WRITE(IER, 0x0);
3771
3772         I915_WRITE(IIR, I915_READ(IIR));
3773 }
3774
3775 static void i965_irq_preinstall(struct drm_device * dev)
3776 {
3777         struct drm_i915_private *dev_priv = dev->dev_private;
3778         int pipe;
3779
3780         I915_WRITE(PORT_HOTPLUG_EN, 0);
3781         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3782
3783         I915_WRITE(HWSTAM, 0xeffe);
3784         for_each_pipe(pipe)
3785                 I915_WRITE(PIPESTAT(pipe), 0);
3786         I915_WRITE(IMR, 0xffffffff);
3787         I915_WRITE(IER, 0x0);
3788         POSTING_READ(IER);
3789 }
3790
3791 static int i965_irq_postinstall(struct drm_device *dev)
3792 {
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         u32 enable_mask;
3795         u32 error_mask;
3796         unsigned long irqflags;
3797
3798         /* Unmask the interrupts that we always want on. */
3799         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3800                                I915_DISPLAY_PORT_INTERRUPT |
3801                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3802                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3803                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3804                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3805                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3806
3807         enable_mask = ~dev_priv->irq_mask;
3808         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3809                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3810         enable_mask |= I915_USER_INTERRUPT;
3811
3812         if (IS_G4X(dev))
3813                 enable_mask |= I915_BSD_USER_INTERRUPT;
3814
3815         /* Interrupt setup is already guaranteed to be single-threaded, this is
3816          * just to make the assert_spin_locked check happy. */
3817         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3818         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3819         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3820         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3821         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3822
3823         /*
3824          * Enable some error detection, note the instruction error mask
3825          * bit is reserved, so we leave it masked.
3826          */
3827         if (IS_G4X(dev)) {
3828                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3829                                GM45_ERROR_MEM_PRIV |
3830                                GM45_ERROR_CP_PRIV |
3831                                I915_ERROR_MEMORY_REFRESH);
3832         } else {
3833                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3834                                I915_ERROR_MEMORY_REFRESH);
3835         }
3836         I915_WRITE(EMR, error_mask);
3837
3838         I915_WRITE(IMR, dev_priv->irq_mask);
3839         I915_WRITE(IER, enable_mask);
3840         POSTING_READ(IER);
3841
3842         I915_WRITE(PORT_HOTPLUG_EN, 0);
3843         POSTING_READ(PORT_HOTPLUG_EN);
3844
3845         i915_enable_asle_pipestat(dev);
3846
3847         return 0;
3848 }
3849
3850 static void i915_hpd_irq_setup(struct drm_device *dev)
3851 {
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         struct drm_mode_config *mode_config = &dev->mode_config;
3854         struct intel_encoder *intel_encoder;
3855         u32 hotplug_en;
3856
3857         assert_spin_locked(&dev_priv->irq_lock);
3858
3859         if (I915_HAS_HOTPLUG(dev)) {
3860                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3861                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3862                 /* Note HDMI and DP share hotplug bits */
3863                 /* enable bits are the same for all generations */
3864                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3865                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3866                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3867                 /* Programming the CRT detection parameters tends
3868                    to generate a spurious hotplug event about three
3869                    seconds later.  So just do it once.
3870                 */
3871                 if (IS_G4X(dev))
3872                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3873                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3874                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3875
3876                 /* Ignore TV since it's buggy */
3877                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3878         }
3879 }
3880
3881 static irqreturn_t i965_irq_handler(int irq, void *arg)
3882 {
3883         struct drm_device *dev = (struct drm_device *) arg;
3884         struct drm_i915_private *dev_priv = dev->dev_private;
3885         u32 iir, new_iir;
3886         u32 pipe_stats[I915_MAX_PIPES];
3887         unsigned long irqflags;
3888         int ret = IRQ_NONE, pipe;
3889         u32 flip_mask =
3890                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3891                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3892
3893         iir = I915_READ(IIR);
3894
3895         for (;;) {
3896                 bool irq_received = (iir & ~flip_mask) != 0;
3897                 bool blc_event = false;
3898
3899                 /* Can't rely on pipestat interrupt bit in iir as it might
3900                  * have been cleared after the pipestat interrupt was received.
3901                  * It doesn't set the bit in iir again, but it still produces
3902                  * interrupts (for non-MSI).
3903                  */
3904                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3905                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3906                         i915_handle_error(dev, false,
3907                                           "Command parser error, iir 0x%08x",
3908                                           iir);
3909
3910                 for_each_pipe(pipe) {
3911                         int reg = PIPESTAT(pipe);
3912                         pipe_stats[pipe] = I915_READ(reg);
3913
3914                         /*
3915                          * Clear the PIPE*STAT regs before the IIR
3916                          */
3917                         if (pipe_stats[pipe] & 0x8000ffff) {
3918                                 I915_WRITE(reg, pipe_stats[pipe]);
3919                                 irq_received = true;
3920                         }
3921                 }
3922                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3923
3924                 if (!irq_received)
3925                         break;
3926
3927                 ret = IRQ_HANDLED;
3928
3929                 /* Consume port.  Then clear IIR or we'll miss events */
3930                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3931                         i9xx_hpd_irq_handler(dev);
3932
3933                 I915_WRITE(IIR, iir & ~flip_mask);
3934                 new_iir = I915_READ(IIR); /* Flush posted writes */
3935
3936                 if (iir & I915_USER_INTERRUPT)
3937                         notify_ring(dev, &dev_priv->ring[RCS]);
3938                 if (iir & I915_BSD_USER_INTERRUPT)
3939                         notify_ring(dev, &dev_priv->ring[VCS]);
3940
3941                 for_each_pipe(pipe) {
3942                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3943                             i915_handle_vblank(dev, pipe, pipe, iir))
3944                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3945
3946                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3947                                 blc_event = true;
3948
3949                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3950                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3951
3952                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3953                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3954                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3955                 }
3956
3957                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3958                         intel_opregion_asle_intr(dev);
3959
3960                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3961                         gmbus_irq_handler(dev);
3962
3963                 /* With MSI, interrupts are only generated when iir
3964                  * transitions from zero to nonzero.  If another bit got
3965                  * set while we were handling the existing iir bits, then
3966                  * we would never get another interrupt.
3967                  *
3968                  * This is fine on non-MSI as well, as if we hit this path
3969                  * we avoid exiting the interrupt handler only to generate
3970                  * another one.
3971                  *
3972                  * Note that for MSI this could cause a stray interrupt report
3973                  * if an interrupt landed in the time between writing IIR and
3974                  * the posting read.  This should be rare enough to never
3975                  * trigger the 99% of 100,000 interrupts test for disabling
3976                  * stray interrupts.
3977                  */
3978                 iir = new_iir;
3979         }
3980
3981         i915_update_dri1_breadcrumb(dev);
3982
3983         return ret;
3984 }
3985
3986 static void i965_irq_uninstall(struct drm_device * dev)
3987 {
3988         struct drm_i915_private *dev_priv = dev->dev_private;
3989         int pipe;
3990
3991         if (!dev_priv)
3992                 return;
3993
3994         intel_hpd_irq_uninstall(dev_priv);
3995
3996         I915_WRITE(PORT_HOTPLUG_EN, 0);
3997         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3998
3999         I915_WRITE(HWSTAM, 0xffffffff);
4000         for_each_pipe(pipe)
4001                 I915_WRITE(PIPESTAT(pipe), 0);
4002         I915_WRITE(IMR, 0xffffffff);
4003         I915_WRITE(IER, 0x0);
4004
4005         for_each_pipe(pipe)
4006                 I915_WRITE(PIPESTAT(pipe),
4007                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4008         I915_WRITE(IIR, I915_READ(IIR));
4009 }
4010
4011 static void intel_hpd_irq_reenable(unsigned long data)
4012 {
4013         struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4014         struct drm_device *dev = dev_priv->dev;
4015         struct drm_mode_config *mode_config = &dev->mode_config;
4016         unsigned long irqflags;
4017         int i;
4018
4019         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4020         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4021                 struct drm_connector *connector;
4022
4023                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4024                         continue;
4025
4026                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4027
4028                 list_for_each_entry(connector, &mode_config->connector_list, head) {
4029                         struct intel_connector *intel_connector = to_intel_connector(connector);
4030
4031                         if (intel_connector->encoder->hpd_pin == i) {
4032                                 if (connector->polled != intel_connector->polled)
4033                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4034                                                          drm_get_connector_name(connector));
4035                                 connector->polled = intel_connector->polled;
4036                                 if (!connector->polled)
4037                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4038                         }
4039                 }
4040         }
4041         if (dev_priv->display.hpd_irq_setup)
4042                 dev_priv->display.hpd_irq_setup(dev);
4043         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4044 }
4045
4046 void intel_irq_init(struct drm_device *dev)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049
4050         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4051         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4052         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4053         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4054
4055         /* Let's track the enabled rps events */
4056         dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4057
4058         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4059                     i915_hangcheck_elapsed,
4060                     (unsigned long) dev);
4061         setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4062                     (unsigned long) dev_priv);
4063
4064         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4065
4066         if (IS_GEN2(dev)) {
4067                 dev->max_vblank_count = 0;
4068                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4069         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4070                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4071                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4072         } else {
4073                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4074                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4075         }
4076
4077         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4078                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4079                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4080         }
4081
4082         if (IS_VALLEYVIEW(dev)) {
4083                 dev->driver->irq_handler = valleyview_irq_handler;
4084                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4085                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4086                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4087                 dev->driver->enable_vblank = valleyview_enable_vblank;
4088                 dev->driver->disable_vblank = valleyview_disable_vblank;
4089                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4090         } else if (IS_GEN8(dev)) {
4091                 dev->driver->irq_handler = gen8_irq_handler;
4092                 dev->driver->irq_preinstall = gen8_irq_preinstall;
4093                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4094                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4095                 dev->driver->enable_vblank = gen8_enable_vblank;
4096                 dev->driver->disable_vblank = gen8_disable_vblank;
4097                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4098         } else if (HAS_PCH_SPLIT(dev)) {
4099                 dev->driver->irq_handler = ironlake_irq_handler;
4100                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4101                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4102                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4103                 dev->driver->enable_vblank = ironlake_enable_vblank;
4104                 dev->driver->disable_vblank = ironlake_disable_vblank;
4105                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4106         } else {
4107                 if (INTEL_INFO(dev)->gen == 2) {
4108                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4109                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4110                         dev->driver->irq_handler = i8xx_irq_handler;
4111                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4112                 } else if (INTEL_INFO(dev)->gen == 3) {
4113                         dev->driver->irq_preinstall = i915_irq_preinstall;
4114                         dev->driver->irq_postinstall = i915_irq_postinstall;
4115                         dev->driver->irq_uninstall = i915_irq_uninstall;
4116                         dev->driver->irq_handler = i915_irq_handler;
4117                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4118                 } else {
4119                         dev->driver->irq_preinstall = i965_irq_preinstall;
4120                         dev->driver->irq_postinstall = i965_irq_postinstall;
4121                         dev->driver->irq_uninstall = i965_irq_uninstall;
4122                         dev->driver->irq_handler = i965_irq_handler;
4123                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4124                 }
4125                 dev->driver->enable_vblank = i915_enable_vblank;
4126                 dev->driver->disable_vblank = i915_disable_vblank;
4127         }
4128 }
4129
4130 void intel_hpd_init(struct drm_device *dev)
4131 {
4132         struct drm_i915_private *dev_priv = dev->dev_private;
4133         struct drm_mode_config *mode_config = &dev->mode_config;
4134         struct drm_connector *connector;
4135         unsigned long irqflags;
4136         int i;
4137
4138         for (i = 1; i < HPD_NUM_PINS; i++) {
4139                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4140                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4141         }
4142         list_for_each_entry(connector, &mode_config->connector_list, head) {
4143                 struct intel_connector *intel_connector = to_intel_connector(connector);
4144                 connector->polled = intel_connector->polled;
4145                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4146                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4147         }
4148
4149         /* Interrupt setup is already guaranteed to be single-threaded, this is
4150          * just to make the assert_spin_locked checks happy. */
4151         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4152         if (dev_priv->display.hpd_irq_setup)
4153                 dev_priv->display.hpd_irq_setup(dev);
4154         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4155 }
4156
4157 /* Disable interrupts so we can allow runtime PM. */
4158 void hsw_runtime_pm_disable_interrupts(struct drm_device *dev)
4159 {
4160         struct drm_i915_private *dev_priv = dev->dev_private;
4161         unsigned long irqflags;
4162
4163         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4164
4165         dev_priv->pm.regsave.deimr = I915_READ(DEIMR);
4166         dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR);
4167         dev_priv->pm.regsave.gtimr = I915_READ(GTIMR);
4168         dev_priv->pm.regsave.gtier = I915_READ(GTIER);
4169         dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
4170
4171         ironlake_disable_display_irq(dev_priv, 0xffffffff);
4172         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4173         ilk_disable_gt_irq(dev_priv, 0xffffffff);
4174         snb_disable_pm_irq(dev_priv, 0xffffffff);
4175
4176         dev_priv->pm.irqs_disabled = true;
4177
4178         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4179 }
4180
4181 /* Restore interrupts so we can recover from runtime PM. */
4182 void hsw_runtime_pm_restore_interrupts(struct drm_device *dev)
4183 {
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         unsigned long irqflags;
4186         uint32_t val;
4187
4188         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4189
4190         val = I915_READ(DEIMR);
4191         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
4192
4193         val = I915_READ(SDEIMR);
4194         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
4195
4196         val = I915_READ(GTIMR);
4197         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
4198
4199         val = I915_READ(GEN6_PMIMR);
4200         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4201
4202         dev_priv->pm.irqs_disabled = false;
4203
4204         ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr);
4205         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr);
4206         ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr);
4207         snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr);
4208         I915_WRITE(GTIER, dev_priv->pm.regsave.gtier);
4209
4210         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4211 }